Semiconductor structure manufacturing methods and semiconductor structures

Abstract

This invention provides a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate; forming a lower dielectric layer; forming a first lower conductive pillar, a second lower conductive pillar, and a third lower conductive pillar; wherein the first lower conductive pillar is located in an array region, the second lower conductive pillar is located in a peripheral region, and the third lower conductive pillar is located in a core region; forming an upper dielectric layer, wherein the upper dielectric layer exposes the top surfaces of the first lower conductive pillar, the second lower conductive pillar, and a portion of the top surface of the third lower conductive pillar; forming a first upper conductive pillar, a second upper conductive pillar, and a third upper conductive pillar within the upper dielectric layer; wherein the third upper conductive pillar and the third lower conductive pillar constitute a third conductive pillar; and the top surface area of ​​the third lower conductive pillar is larger than the top surface area of ​​the third upper conductive pillar. This invention can optimize the semiconductor structure manufacturing process and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Technology

[0002] With the development of semiconductor technology, the process nodes of semiconductor structures are constantly shrinking, leading to increasingly higher integration levels. Increased integration levels bring several benefits: First, it increases the functionality of the semiconductor structure; second, according to Moore's Law, increased integration levels directly result in lower costs; and third, it reduces the overall supply voltage of the semiconductor structure, thereby reducing power consumption.

[0003] In pursuit of smaller process nodes, the manufacturing process and performance of semiconductor structures need further improvement. Summary of the Invention

[0004] This invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, in order to optimize the manufacturing process of the semiconductor structure and improve its performance.

[0005] This invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a lower dielectric layer on the substrate; forming a first lower conductive pillar, a second lower conductive pillar, and a third lower conductive pillar within the lower dielectric layer; wherein the first lower conductive pillar is located in an array region, the second lower conductive pillar is located in a peripheral region, and the third lower conductive pillar is located in a core region; forming an upper dielectric layer on the lower dielectric layer, wherein the upper dielectric layer exposes the top surfaces of the first lower conductive pillar, the second lower conductive pillar, and a portion of the top surface of the third lower conductive pillar; and forming a first upper conductive pillar, a second upper conductive pillar, and a third upper conductive pillar within the upper dielectric layer; wherein the first upper conductive pillar and the first lower conductive pillar constitute a first conductive pillar; the second upper conductive pillar and the second lower conductive pillar constitute a second conductive pillar; and the third upper conductive pillar and the third lower conductive pillar constitute a third conductive pillar; and the top surface area of ​​the third lower conductive pillar is larger than the top surface area of ​​the third upper conductive pillar.

[0006] In addition, the orthographic projection of the top surface of the third upper conductive post onto the top surface of the third lower conductive post falls within the top surface of the third lower conductive post.

[0007] In addition, the top surface of the third upper conductive post, when projected onto the top surface of the third lower conductive post, together with the top surface of the third lower conductive post, forms a ring-shaped pattern.

[0008] In addition, in a direction parallel to the top surface of the substrate, the cross-sectional shape of the third upper conductive post and the third lower conductive post is rectangular; one side wall of the third upper conductive post is directly opposite to one side wall of the third lower conductive post; or, the two side walls of the third upper conductive post are directly opposite to the two side walls of the third lower conductive post; or, the three side walls of the third upper conductive post are directly opposite to the three side walls of the third lower conductive post.

[0009] In addition, the ratio of the top surface area of ​​the third upper conductive pillar to the top surface area of ​​the third lower conductive pillar is less than 4 / 5.

[0010] In addition, in the direction perpendicular to the top surface of the substrate, the ratio of the thickness of the upper dielectric layer to the thickness of the lower dielectric layer ranges from 3 / 5 to 2 / 5.

[0011] In addition, the substrate has multiple active regions, which are electrically connected to the first conductive post, the second conductive post and the third conductive post, respectively.

[0012] In addition, the core region has a gate in the substrate, and the gate is electrically connected to the third conductive post.

[0013] In addition, the orthographic projection of the first upper conductive post onto the top surface of the first lower conductive post coincides with the top surface of the first lower conductive post, and the orthographic projection of the second upper conductive post onto the top surface of the second lower conductive post coincides with the top surface of the second lower conductive post.

[0014] In addition, the material of the third upper conductive post is the same as the material of the third lower conductive post.

[0015] In addition, the conductivity of the material of the third upper conductive pillar is greater than that of the material of the third lower conductive pillar.

[0016] In addition, the step of forming the upper dielectric layer includes: forming an initial upper dielectric layer covering the lower dielectric layer, the first lower conductive pillar, the second lower conductive pillar and the third lower conductive pillar; and performing patterning processing on the initial upper dielectric layer to form the upper dielectric layer.

[0017] In addition, the step of forming the lower dielectric layer includes: forming an initial lower dielectric layer covering the substrate; and performing patterning processing on the initial lower dielectric layer to form the lower dielectric layer.

[0018] This invention also provides a semiconductor structure, comprising: a substrate having a lower dielectric layer thereon; a first lower conductive pillar, a second lower conductive pillar, and a third lower conductive pillar located within the lower dielectric layer; the first lower conductive pillar being located in the array region, the second lower conductive pillar being located in the peripheral region, and the third lower conductive pillar being located in the core region; an upper dielectric layer located on the lower dielectric layer, the upper dielectric layer exposing the top surfaces of the first lower conductive pillar, the second lower conductive pillar, and a portion of the top surface of the third lower conductive pillar; and a first upper conductive pillar, a second upper conductive pillar, and a third upper conductive pillar located within the upper dielectric layer; wherein the first upper conductive pillar and the first lower conductive pillar constitute a first conductive pillar; the second upper conductive pillar and the second lower conductive pillar constitute a second conductive pillar; the third upper conductive pillar and the third lower conductive pillar constitute a third conductive pillar; and the top surface area of ​​the third lower conductive pillar is larger than the top surface area of ​​the third upper conductive pillar.

[0019] In addition, in the direction perpendicular to the top surface of the substrate, the ratio of the thickness of the third upper conductive post to the thickness of the second lower conductive post ranges from 3 / 5 to 2 / 5.

[0020] The technical solution provided by the embodiments of the present invention has at least the following advantages:

[0021] In this embodiment of the invention, a first lower conductive pillar, a second lower conductive pillar, and a third lower conductive pillar are formed within a lower dielectric layer; an upper dielectric layer is formed, exposing the top surfaces of the first and second lower conductive pillars and a portion of the top surface of the third lower conductive pillar; and a first upper conductive pillar, a second upper conductive pillar, and a third upper conductive pillar are formed within the upper dielectric layer. This allows for the consideration of manufacturing processes for the array region, the peripheral region, and the core region, enabling the first and second upper conductive pillars to maintain their original dimensions while changing the size of the third upper conductive pillar. Furthermore, the top surface area of ​​the third lower conductive pillar is larger than that of the third upper conductive pillar, meaning the third lower conductive pillar has a larger size, which reduces its resistance and improves its electrical performance. Additionally, the exposed top surface area of ​​the third upper conductive pillar within the upper dielectric layer is smaller, reducing the probability of incorrect electrical connections between the third upper conductive pillar and other conductive structures.

[0022] Furthermore, the ratio of the top surface area of ​​the third upper conductive post to the top surface area of ​​the third lower conductive post is less than 4 / 5. When the area ratio is within the above range, the probability of incorrect electrical connection of the third upper conductive post can be reduced, and the resistance of the third lower conductive post can also be reduced. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0024] Figures 1-11 The diagram shows the structural schematics corresponding to each step in the semiconductor structure manufacturing method provided in the embodiments of the present invention. Detailed Implementation

[0025] Semiconductor structures typically consist of an array region, a peripheral region, and a core region. The core region is closely connected to the array region and has unique device structures such as word-line drivers. The peripheral region is used to ensure that the core region's functions are realized. When the size of a semiconductor structure is reduced, the size of all three regions must be continuously reduced. This results in the conductive pillars in the core region exhibiting high resistance, and the electrical performance of the core region cannot be effectively improved.

[0026] This invention provides a method for manufacturing a semiconductor structure, comprising: forming a first lower conductive pillar, a second lower conductive pillar, and a third lower conductive pillar within a lower dielectric layer; forming an upper dielectric layer on top of the lower dielectric layer, the upper dielectric layer exposing the top surfaces of the first lower conductive pillar, the second lower conductive pillar, and a portion of the top surface of the third lower conductive pillar; forming a first upper conductive pillar, a second upper conductive pillar, and a third upper conductive pillar within the upper dielectric layer; wherein the top surface area of ​​the third lower conductive pillar is larger than the top surface area of ​​the third upper conductive pillar. The larger size of the third lower conductive pillar can reduce resistance and improve electrical performance, while the upper dielectric layer exposing the smaller-sized third upper conductive pillar can prevent incorrect electrical connections between the third upper conductive pillar and other conductive structures. Furthermore, it is compatible with the manufacturing processes of the first, second, and third lower conductive pillars, allowing all three to be formed in the same process steps.

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0028] One embodiment of the present invention provides a method for manufacturing a semiconductor structure. Figures 1-11 The accompanying drawings are schematic diagrams of each step in the semiconductor structure manufacturing method provided in this embodiment. The following will provide a detailed description in conjunction with the accompanying drawings.

[0029] refer to Figure 1 The semiconductor structure includes an array region a, a peripheral region b, and a core region c. In this embodiment, the semiconductor structure can be a Dynamic Random Access Memory (DRAM). The array region a is suitable for forming structures such as transistors, word lines, and bit lines. The core region c is suitable for forming device structures such as word line drivers. The peripheral region b is used to ensure that the functions of the core region c are realized. A substrate 100 is provided. Specifically, the substrate 100 of the array region a, the peripheral region b, and the core region c each has a substrate 101, an isolation structure 103, and an active region 102. The substrate 101 can be made of a semiconductor material, such as an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon germanide, gallium arsenide, or indium gallium nitride, etc. The substrate 101 may also contain doped ions, such as boron or phosphorus. The isolation structure 103 is made of an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. The active region 102 is made of semiconductor material and also contains doped ions. Furthermore, the doping type of the active region 102 can be opposite to the doping type of the substrate 101.

[0030] Furthermore, in this embodiment, the substrate 100 of the core region c also has a gate (not shown), and the substrate 100 of the array region a also has a word line 104. The gate and the word line 104 can be made of the same material, such as tungsten. In other embodiments, the gate and the word line can also be made of different materials.

[0031] refer to Figures 1-2 A lower dielectric layer 110 is formed on the substrate 100. Multiple conductive pillars will subsequently be formed within the lower dielectric layer 110, which isolates the conductive pillars. In this embodiment, the lower dielectric layer 110 has a double-layer structure, including a first lower dielectric layer 111 and a second lower dielectric layer 112 stacked together. In other embodiments, the lower dielectric layer can also be a single-layer structure, or a structure with three or more layers. The material of the lower dielectric layer 110 is an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0032] The steps for forming the lower dielectric layer 110 include:

[0033] refer to Figure 1 An initial lower dielectric layer 160 is formed covering the substrate 100. The initial lower dielectric layer 160 includes a first initial lower dielectric layer 161 and a second initial lower dielectric layer 162 stacked together. In this embodiment, the first initial lower dielectric layer 161 and the second initial lower dielectric layer 162 can be formed by chemical vapor deposition.

[0034] In this embodiment, the initial lower dielectric layer 160 of the array region a also includes a bit line contact layer 141 and a bit line conductive layer 142. Further, the bit line contact layer 141 and the bit line conductive layer 142 can be formed on the substrate 100 first, and then the initial lower dielectric layer 160 covering the bit line contact layer 141 and the bit line conductive layer 142 can be formed.

[0035] refer to Figure 2 The initial lower dielectric layer 160 is patterned to form the lower dielectric layer 110. Specifically, the lower dielectric layer 110 is etched using a mask 200 to form a first via 113, a second via 114, and a third via 115 located within the lower dielectric layer 110. The first via 113 is located in array region a, the second via 114 is located in peripheral region b, and the third via 115 is located in core region c. That is, the first via 113, the second via 114, and the third via 115 are formed in the same step, thereby simplifying the manufacturing process.

[0036] The first through hole 113 is subsequently used to fill the first lower conductive post, the second through hole 114 is subsequently used to fill the second lower conductive post, and the third through hole 115 is subsequently used to fill the third lower conductive post.

[0037] refer to Figure 3 This forms a first lower conductive pillar 131, a second lower conductive pillar 132, and a third lower conductive pillar 133 within the lower dielectric layer 110; the first lower conductive pillar 131 is located in array region a, the second lower conductive pillar 132 is located in peripheral region b, and the third lower conductive pillar 133 is located in core region c. That is, it forms a filling of the first through-hole 113 (reference). Figure 2 The first lower conductive post 131 and the second through hole 114 are filled (reference). Figure 2 The second lower conductive post 132 and the filling of the third through hole 115 (see reference) Figure 2 The third lower conductive column 133.

[0038] The first lower conductive post 131 is electrically connected to the active region 102 in the array region a, the second lower conductive post 132 is electrically connected to the active region 102 in the peripheral region b, and the third lower conductive post 133 is electrically connected to the active region 102 and the gate in the core region c.

[0039] In this embodiment, the first lower conductive pillar 131, the second lower conductive pillar 132, and the third lower conductive pillar 133 are formed in the same step, thereby simplifying the manufacturing process. Specifically, the method for forming the first lower conductive pillar 131, the second lower conductive pillar 132, and the third lower conductive pillar 133 can be physical vapor deposition. In other embodiments, the method can also be chemical vapor deposition.

[0040] In this embodiment, the first lower conductive pillar 131, the second lower conductive pillar 132, and the third lower conductive pillar 133 are made of the same material, and all are conductive materials, such as tungsten, copper, gold, silver, or polycrystalline silicon. In other embodiments, the materials of the first lower conductive pillar, the second lower conductive pillar, and the third lower conductive pillar may be different.

[0041] In this embodiment, the first lower conductive post 131, the second lower conductive post 132, and the third lower conductive post 133 are cuboids. In other embodiments, the first lower conductive post, the second lower conductive post, and the third lower conductive post can also be cylindrical.

[0042] refer to Figures 4-5 An upper dielectric layer 120 is formed on the lower dielectric layer 110, exposing the top surfaces of the first lower conductive post 131, the second lower conductive post 132, and a portion of the top surface of the third lower conductive post 133. That is, the upper dielectric layer 120 exposes the entire top surface of the first and second lower conductive posts 131, while covering a portion of the top surface of the third lower conductive post 133.

[0043] In the direction perpendicular to the top surface of the substrate 100, the ratio of the thickness of the upper dielectric layer 120 to the thickness of the lower dielectric layer 110 ranges from 3 / 5 to 2 / 5, for example, it can be 1 / 2. When the thickness ratio of the two is within the above range, it is possible to make the third lower conductive pillar 133 and the subsequently formed third upper conductive pillar 143 (see reference) Figure 6 The third conductive post has a suitable thickness, which ensures that it has a low resistance and thus improves its electrical performance.

[0044] Specifically, refer to Figure 4 This forms an initial upper dielectric layer 121 covering the lower dielectric layer 110, the first lower conductive pillar 131, the second lower conductive pillar 132, and the third lower conductive pillar 133.

[0045] In this embodiment, the material of the initial upper dielectric layer 121 is the same as the material of the lower dielectric layer 110, for example, both can be silicon nitride. In other embodiments, the material of the initial upper dielectric layer 121 can be different from the material of the lower dielectric layer 110. In this embodiment, the initial upper dielectric layer 121 is formed by chemical vapor deposition.

[0046] refer to Figure 5 The initial upper dielectric layer 121 is patterned to form the upper dielectric layer 120. Specifically, a portion of the initial upper dielectric layer 121 is etched to expose the entire top surface of the first lower conductive pillar 131 and the second lower conductive pillar 132, and a portion of the top surface of the third lower conductive pillar 133.

[0047] refer to Figure 6A first upper conductive pillar 141, a second upper conductive pillar 142, and a third upper conductive pillar 143 are formed within the upper dielectric layer 120. The first upper conductive pillar 141 and the first lower conductive pillar 131 constitute the first conductive pillar 151; the second upper conductive pillar 142 and the second lower conductive pillar 132 constitute the second conductive pillar 152; the third upper conductive pillar 143 and the third lower conductive pillar 133 constitute the third conductive pillar 153; the top surface area of ​​the third lower conductive pillar 133 is larger than the top surface area of ​​the third upper conductive pillar 143.

[0048] In this embodiment, the first upper conductive post 141, the second upper conductive post 142, and the third upper conductive post 143 are formed in the same process step, thereby simplifying the production process.

[0049] The orthographic projection of the first upper conductive post 141 onto the top surface of the first lower conductive post 131 coincides with the top surface of the first lower conductive post 131, and the orthographic projection of the second upper conductive post 142 onto the top surface of the second lower conductive post 132 coincides with the top surface of the second lower conductive post 132. That is, the first upper conductive post 141 and the first lower conductive post 131 have the same shape and size, and the second upper conductive post 142 and the second lower conductive post 132 have the same shape and size.

[0050] In this embodiment, the orthographic projection of the top surface of the third upper conductive post 143 onto the top surface of the third lower conductive post 133 falls within the top surface of the third lower conductive post 133. At this time, the size of the third upper conductive post 143 is smaller than the size of the third lower conductive post 133, and the third upper conductive post 143 and the third lower conductive post 133 are directly opposite each other. When the third upper conductive post 143 and the third lower conductive post 133 are directly opposite each other, the contact area between them is the largest, and the contact resistance is the smallest.

[0051] The ratio of the top surface area of ​​the third upper conductive post 143 to the top surface area of ​​the third lower conductive post 133 is less than 4 / 5, for example, it can be 1 / 2, 1 / 3 or 1 / 4. When the area ratio is within the above range, the probability of incorrect electrical connection of the third upper conductive post 143 can be reduced, and the resistance of the third lower conductive post 133 can be further reduced.

[0052] The thickness ratio of the third upper conductive post 143 to the third lower conductive post 133 ranges from 3 / 5 to 2 / 5, for example, it can be 1 / 2. When the thickness ratio is within the above range, the third lower conductive post 133 can have a larger volume, and therefore, the third lower conductive post 133 has a smaller resistance.

[0053] In this embodiment, the material of the third upper conductive post 143 is the same as that of the third lower conductive post 133. When the two materials are the same, their affinity is greater and there are fewer defects at the interface. For example, the materials of both the third upper conductive post 143 and the third lower conductive post 133 can be copper.

[0054] In other embodiments, the materials of the third upper conductive pillar 143 and the third lower conductive pillar 133 can also be different. For example, the conductivity of the material of the third upper conductive pillar 143 may be greater than that of the material of the third lower conductive pillar 133. In one example, the material of the third upper conductive pillar 143 may be silver, and the material of the third lower conductive pillar 133 may be copper. Because the third upper conductive pillar 143 has a smaller volume, when the third upper conductive pillar 143 has a larger conductivity, the total resistance of the third upper conductive pillar 143 is smaller, which is beneficial to improving the electrical performance of the third conductive pillar 153.

[0055] The relative positions of the third upper conductive post 143 and the third lower conductive post 133 will be described in detail below.

[0056] First, it should be noted that since the third upper conductive post 143 and the third lower conductive post 133 in this embodiment are cuboids, their cross-sectional shapes are rectangular in the direction parallel to the top surface of the base 100. In other embodiments, since the third upper conductive post and the third lower conductive post can also be cylindrical, their cross-sectional shapes can be circular.

[0057] Reference Figure 6 and Figure 7 , Figure 7 for Figure 6 A top view of the central core area c; it should be noted that... Figure 7 The left or right area in the middle corresponds to Figure 6 The core area c is shown. Figure 7 The middle area in Figure 6 The third lower conductive pillar 133 in the middle region is electrically connected to the gate in the substrate 100 of the core region c. The orthographic projection of the top surface of the third upper conductive pillar 143 onto the top surface of the third lower conductive pillar 133 together with the top surface of the third lower conductive pillar 133 forms a ring-shaped pattern.

[0058] At this point, the length of the third lower conductive post 133 is greater than the length of the third upper conductive post 143, and the width of the third lower conductive post 133 is greater than the width of the third upper conductive post 143. That is, the area of ​​the top surface of the third lower conductive post 133 can be maximized, thereby further increasing and reducing the resistance of the third lower conductive post 133.

[0059] Furthermore, the central axis of the third upper conductive post 143 in a direction perpendicular to the top surface of the substrate 100 coincides with the central axis of the third lower conductive post 133 in a direction perpendicular to the top surface of the substrate 100. In other embodiments, the central axis of the third upper conductive post may not coincide with the center of the third lower conductive post.

[0060] In another example, refer to Figure 8 One sidewall of the third upper conductive post 143 is directly opposite to one sidewall of the third lower conductive post 133.

[0061] In another example, refer to Figures 9-10 The two sidewalls of the third upper conductive post 143 are directly opposite the two sidewalls of the third lower conductive post 133; further reference Figure 9 The two sidewalls of the third upper conductive post 143 are connected; Reference Figure 10 The two sidewalls of the third upper conductive post 143 are opposite sidewalls.

[0062] In another example, refer to Figure 11 The three sidewalls of the third upper conductive post 143 are directly opposite the three sidewalls of the third lower conductive post 133.

[0063] In the above examples, the relative positions of the third upper conductive post 143 and the third lower conductive post 133 are different, but the volume of the third upper conductive post 143 is smaller than that of the third lower conductive post 133, which means that the resistance of the third lower conductive post 133 can be reduced.

[0064] In summary, in this embodiment, a third upper conductive pillar 143 and a third lower conductive pillar 133 are formed, and the top surface area of ​​the third upper conductive pillar 143 is smaller than that of the third lower conductive pillar 133. This reduces the probability of a short circuit between the third upper conductive pillar 143 and other conductive structures, and also reduces the resistance of the third conductive pillar 153, thereby improving its electrical performance. Furthermore, the formation processes of the array region a and the peripheral region b are also considered during the formation of the third conductive pillar 153, thus optimizing the semiconductor structure manufacturing process.

[0065] Another embodiment of the present invention provides a semiconductor structure, which can be manufactured by the manufacturing method of the semiconductor structure provided in the previous embodiment. Figure 6 This is a schematic diagram of the semiconductor structure provided in this embodiment, with reference to... Figure 6The semiconductor structure includes: a substrate 100, on which a lower dielectric layer 110 is having been formed; a first lower conductive pillar 131, a second lower conductive pillar 132, and a third lower conductive pillar 133 located within the lower dielectric layer 110; the first lower conductive pillar 131 is located in array region a, the second lower conductive pillar 132 is located in peripheral region b, and the third lower conductive pillar 133 is located in core region c; and an upper dielectric layer 120 is located on the lower dielectric layer 110, the upper dielectric layer 120 exposing the top surfaces of the first lower conductive pillar 131, the second lower conductive pillar 132, and... A portion of the top surface of the third lower conductive pillar 133; the first upper conductive pillar 141, the second upper conductive pillar 142, and the third upper conductive pillar 143 located within the upper dielectric layer 120; wherein, the first upper conductive pillar 141 and the first lower conductive pillar 131 constitute the first conductive pillar 151; the second upper conductive pillar 142 and the second lower conductive pillar 132 constitute the second conductive pillar 152; the third upper conductive pillar 143 and the third lower conductive pillar 133 constitute the third conductive pillar 153; the top surface area of ​​the third lower conductive pillar 133 is larger than the top surface area of ​​the third upper conductive pillar 143. For the parts of this embodiment that are the same as or similar to the previous embodiment, please refer to the detailed description of the previous embodiment, which will not be repeated here.

[0066] The following explanation will be provided in conjunction with the accompanying drawings.

[0067] The substrates 100 of array region a, peripheral region b, and core region c each have a substrate 101, an isolation structure 103, and an active region 102. In this embodiment, the substrate 100 of core region c also has a gate, and the substrate 100 of array region a also has a word line 104.

[0068] The first conductive post 151 is electrically connected to the active region 102; the second conductive post 152 is electrically connected to the active region 102; and the third conductive post 153 is electrically connected to the gate or the active region 102.

[0069] The third conductive post 153 includes a third lower conductive post 133 and a third upper conductive post 143 stacked together. In this embodiment, the third upper conductive post 143 and the third lower conductive post 133 are cuboids; in other embodiments, they may also be cylindrical. In this embodiment, the orthographic projection of the top surface of the third upper conductive post 143 onto the top surface of the third lower conductive post 133 falls within the top surface of the third lower conductive post 133. At this time, the third upper conductive post 143 and the third lower conductive post 133 are directly opposite each other, and the contact area between them is maximized, resulting in minimum contact resistance.

[0070] The thickness ratio of the third upper conductive post 143 to the third lower conductive post 133 ranges from 3 / 5 to 2 / 5, for example, it can be 1 / 2. When the thickness ratio is within the above range, the third lower conductive post 133 can have a larger volume, and therefore, the third lower conductive post 133 has a smaller resistance.

[0071] In summary, the top surface area of ​​the third upper conductive post 143 is smaller than that of the third lower conductive post 133, which can reduce the probability of short circuit between the third upper conductive post 143 and other conductive structures, and also reduce the resistance of the third conductive post 153, thereby improving the electrical performance of the third conductive post 153.

[0072] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, said semiconductor structure comprising an array region, a peripheral region, and a core region, characterized in that, include: Provide a base; A lower dielectric layer is formed on the substrate; The underlying dielectric layer is etched using a photomask to form a first via, a second via, and a third via located in the underlying dielectric layer; A first lower conductive post is formed to fill the first through hole, a second lower conductive post is formed to fill the second through hole, and a third lower conductive post is formed to fill the third through hole. The first lower conductive post, the second lower conductive post, and the third lower conductive post are formed in the same step. The first lower conductive post is located in the array region, the second lower conductive post is located in the peripheral region, and the third lower conductive post is located in the core region; An upper dielectric layer is formed on the lower dielectric layer, the upper dielectric layer exposing the top surface of the first lower conductive pillar, the top surface of the second lower conductive pillar, and a portion of the top surface of the third lower conductive pillar; A first upper conductive pillar, a second upper conductive pillar, and a third upper conductive pillar are formed within the upper dielectric layer; wherein, the first upper conductive pillar and the first lower conductive pillar constitute a first conductive pillar; the second upper conductive pillar and the second lower conductive pillar constitute a second conductive pillar; the third upper conductive pillar and the third lower conductive pillar constitute a third conductive pillar; and the top surface area of ​​the third lower conductive pillar is larger than the top surface area of ​​the third upper conductive pillar.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The top surface of the third upper conductive post is projected onto the top surface of the third lower conductive post, and the projection of the top surface of the third upper conductive post falls within the top surface of the third lower conductive post.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The top surface of the third upper conductive post, when projected onto the top surface of the third lower conductive post, together with the top surface of the third lower conductive post, forms a ring-shaped pattern.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, In a direction parallel to the top surface of the substrate, the cross-sectional shape of the third upper conductive post and the third lower conductive post is rectangular; one sidewall of the third upper conductive post is directly opposite one sidewall of the third lower conductive post. Alternatively, the two sidewalls of the third upper conductive post are respectively opposite to the two sidewalls of the third lower conductive post; Alternatively, the three sidewalls of the third upper conductive post are respectively opposite to the three sidewalls of the third lower conductive post.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The ratio of the top surface area of ​​the third upper conductive pillar to the top surface area of ​​the third lower conductive pillar is less than 4 / 5.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, In the direction perpendicular to the top surface of the substrate, the ratio of the thickness of the upper dielectric layer to the thickness of the lower dielectric layer ranges from 3 / 5 to 2 / 5.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The substrate has multiple active regions, which are electrically connected to the first conductive post, the second conductive post, and the third conductive post, respectively.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The core region has a gate within its substrate, and the gate is electrically connected to the third conductive pillar.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The orthographic projection of the first upper conductive post onto the top surface of the first lower conductive post coincides with the top surface of the first lower conductive post, and the orthographic projection of the second upper conductive post onto the top surface of the second lower conductive post coincides with the top surface of the second lower conductive post.

10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The material of the third upper conductive pillar is the same as the material of the third lower conductive pillar.

11. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The conductivity of the material of the third upper conductive pillar is greater than that of the material of the third lower conductive pillar.

12. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming the upper dielectric layer includes: forming an initial upper dielectric layer covering the lower dielectric layer, the first lower conductive pillar, the second lower conductive pillar, and the third lower conductive pillar; and performing patterning processing on the initial upper dielectric layer to form the upper dielectric layer.

13. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming the lower dielectric layer includes: forming an initial lower dielectric layer covering the substrate; and patterning the initial lower dielectric layer to form the lower dielectric layer.

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