A handshake control method and system for a PMC and a CPU based on an SOC

Abstract

The application provides a handshake control method for a SOC-based PMC and a CPU, comprising the following steps: S1, before the SOC enters a standby mode, the CPU sends a deep sleep signal to the PMC, the deep sleep signal indicating that the CPU starts to enter sleep; S2, after receiving the deep sleep signal, the PMC sends a first handshake signal to the CPU in the next clock cycle, the first handshake signal being valid when the deep sleep signal is valid, and the CPU keeping sleep and not executing instructions; S3, after receiving the first handshake signal, the CPU sends a second handshake signal to the PMC, the second handshake signal being valid when the CPU informs the PMC that the CPU has entered a stationary mode before entering a sleep state, and then the PMC controls the SOC to enter the standby mode; and S4, when the first handshake signal is invalid, the CPU changes the second handshake signal to be invalid in the next clock cycle after seeing that the first handshake signal is invalid, and the PMC controls the SOC to exit the standby mode. Through the handshake between the CPU and the PMC, the application can prevent the CPU from running away or the SOC from running abnormally when an external wake-up source is asynchronous.

Description

[Technical Field]

[0001] This invention relates to the field of communication technology, and in particular to a handshake control method and system for PMC and CPU based on SOC. [Background Technology]

[0002] A System on Chip (SoC) is a microprocessor system that includes a CPU, memory modules, peripheral interfaces, buses, clock modules, etc., and can be widely used in automobiles, handheld electronic products, consumer electronics, and other products.

[0003] As technology advances, System-on-a-Chip (SoC) becomes increasingly complex, containing more and more modules, thus creating a demand for multi-level power supplies. To meet the challenge of low power consumption, a dedicated power management controller (PMC) is integrated within the SoC.

[0004] System-on-a-Chip (SoC) typically includes three modes: normal operation mode, standby mode, and shutdown mode. Low-power design is particularly important in standby mode. In standby mode, the power supply module (PMC) shuts down most modules, retaining only the external wake-up source, while the clock module retains a low-speed clock.

[0005] When an SOC enters standby mode, if it receives a wake-up signal from a wake-up source, the SOC must be able to respond to the wake-up source. However, since the external wake-up source is asynchronous in the SOC, it cannot be guaranteed that the wake-up source will send signals to the CPU and PMC components at the same time. Due to the inconsistent signal delay, the CPU may start first while the PMC state transition is delayed during the SOC's entry into standby mode. This inevitably leads to the possibility of the CPU running out of control or the SOC malfunctioning.

[0006] Therefore, it is necessary to provide a new handshake control method and system for PMC and CPU based on SOC to solve the above-mentioned technical problems. [Summary of the Invention]

[0007] The purpose of this invention is to provide a handshake control method and system for PMC and CPU based on SOC that can ensure the normal operation of CPU and SOC when the external wake-up source is asynchronous, so as to solve the problems in related technologies.

[0008] To achieve the above objectives, this invention provides a handshake control method between a System-on-a-Chip (SOC) PMC and a CPU. The handshake control method includes the following steps: S1, before the SOC enters standby mode, the CPU sends a deep sleep signal to the PMC, indicating that the CPU has entered sleep mode; S2, after receiving the deep sleep signal, the PMC sends a first handshake signal to the CPU in the next clock cycle. When the deep sleep signal is valid, the first handshake signal is valid, and the CPU remains asleep and does not execute instructions; S3, after receiving the first handshake signal, the CPU sends a second handshake signal to the PMC. When the second handshake signal is valid, it indicates that the CPU has informed the PMC that it has entered a static mode before entering sleep mode, and then the PMC controls the SOC to enter standby mode; S4, when the first handshake signal is invalid, after the CPU sees that the first handshake signal is invalid, the CPU will invalidate the second handshake signal in the next clock cycle, and the PMC controls the SOC to exit standby mode.

[0009] More preferably, in step S3, when a wake-up source appears in the standby mode of the SOC, the PMC generates an asynchronous wake-up signal, the PMC performs judgment and control, and in the next working clock cycle, the PMC sets the first handshake signal to invalid. After the CPU sees that the first handshake signal is invalid, the CPU sets the second handshake signal to invalid in the next working clock cycle, and the PMC controls the SOC to exit the standby mode.

[0010] More preferably, in step S2, when the PMC is in a state of waiting for the CPU to send the second handshake signal, a wake-up source appears after the asynchronous wake-up source is synchronized, and the CPU sees the wake-up source first, the PMC sees the wake-up source later, and the first handshake signal is valid. In the next working clock cycle, the CPU generates the second handshake signal to be valid and simultaneously invalidates the deep sleep signal. In the next working clock cycle, the PMC jumps to the normal working mode and invalidates the first handshake signal. After the CPU sees the first handshake signal invalid, it invalidates the second handshake signal in the next working clock cycle. The PMC controls the SOC to exit the standby mode.

[0011] More preferably, in step S2, when the PMC is waiting for the CPU to send the second handshake signal, a wake-up source appears after the asynchronous wake-up synchronization. The PMC sees the wake-up source first, and the CPU sees the wake-up source later. The first handshake signal is valid. The PMC jumps to the normal working mode in the next working clock cycle and invalidates the first handshake signal. The CPU receives the first handshake signal as invalid and also invalidates the second handshake signal in the next working clock cycle. The PMC controls the SOC to exit the standby mode.

[0012] More preferably, when CPU memory operations are involved, the process by which the PMC controls the SOC to enter standby mode includes: C1, the CPU sends a deep sleep command to the PMC; C2, the PMC receives the deep sleep command, sends a keep-sleep-not-execute command signal to the CPU, and the PMC enters a wait-to-keep-sleep state; C3, the PMC enters a CPU memory read request state; C4, when the CPU memory read request is completed, the PMC enters an isolation-enabled state; C5, the PMC enters standby mode, and the SOC enters standby mode.

[0013] More preferably, in step C3, when the PMC is in the CPU memory read request state, a wake-up source appears after asynchronous wake-up synchronization. After the PMC sees the wake-up source, the PMC switches to normal working state and releases the first handshake signal as invalid. The CPU sees the first handshake signal as invalid and sets the second handshake signal as invalid in the next working clock cycle. The PMC controls the SOC to exit standby mode.

[0014] More preferably, the SOC further includes Flash, and the low-power mode of the Flash is DPD or power-off mode. In step C5, when the low-power mode of the Flash is DPD mode, the PMC controls the enable signal of the Flash to be valid, the SOC is powered down, the PMC enters standby mode, and the SOC enters standby mode; when the low-power mode of the Flash is power-off mode, the PMC first resets the Flash, then the Flash is powered down, then the SOC is powered down, the PMC enters standby mode, and the SOC enters standby mode.

[0015] More preferably, in step C4, when the PMC is in the isolation enable enabled state, and the Flash's low-power mode is DPD mode and the PMC controls the Flash's enable signal to be invalid, or the Flash's low-power mode is power off mode and the Flash is resetting and has not yet lost power, a wake-up source appears after asynchronous wake-up synchronization. When the PMC sees the wake-up source, the PMC switches to normal working state and releases the first handshake signal as invalid. The CPU sees the first handshake signal as invalid and sets the second handshake signal as invalid in the next clock cycle. The PMC controls the SOC to exit standby mode.

[0016] More preferably, in step C4, when the PMC is in the isolation enable state, and the Flash's low-power mode is power off and the Flash has completed reset and power-down, a wake-up source appears after asynchronous wake-up synchronization. When the PMC sees the wake-up source, the PMC enters normal working state, controls the Flash to power on, then controls the Flash to reset and release, then the PMC releases the first handshake signal as invalid. The CPU sees the first handshake signal as invalid, sets the second handshake signal as invalid in the next working clock cycle, and the PMC controls the SOC to exit standby mode.

[0017] The present invention also provides a system that employs a handshake control method between a PMC and a CPU based on a SOC, wherein the PMC includes a control center, a bus, a synchronization unit, an analog unit interface, and a wake-up trigger source generation unit.

[0018] The technical effect of this invention is that the handshake control method between the CPU and PMC can effectively prevent the CPU from crashing or the SOC from malfunctioning when the external wake-up source is asynchronous. [Attached Image Description]

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0020] Figure 1 This is a framework diagram of the SOC of the present invention;

[0021] Figure 2 This is a framework diagram of the PMC of the present invention;

[0022] Figure 3This is a block diagram of the handshake operating system between the PMC and the CPU of the present invention;

[0023] Figure 4 This is a schematic diagram of the handshake between the PMC and the CPU in this invention;

[0024] Figure 5 This is a flowchart of the handshake control method between the PMC and the CPU of the present invention;

[0025] Figure 6 This is a timing diagram of Embodiment 1 of the present invention;

[0026] Figure 7 This is a timing diagram of Embodiment 2 of the present invention;

[0027] Figure 8 This is a timing diagram of Embodiment 3 of the present invention;

[0028] Figure 9 This is a timing diagram of Embodiment 4 of the present invention;

[0029] Figure 10 This is a timing diagram of Embodiment Six of the present invention.

Detailed Implementation Methods

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Please refer to Figure 1 As shown, the SOC includes a CPU, a power management controller (PMC), a CPU memory control unit, a CPU memory static storage unit, a system static storage unit, a flash memory unit, an analog unit, an external wake-up source, a clock, etc.

[0032] The power area of ​​a SOC includes a normally-on power area and a power-off power area. When the SOC is in standby mode, most modules in the power-off power area can be turned off, with only the low-speed clock and external wake-up source remaining.

[0033] An external wake-up source triggers an asynchronous wake-up signal through the SOC's ports, external pins, and normally open power supply area. After being synchronized by a clock, the asynchronous wake-up signal is sent to the PMC and CPU respectively.

[0034] When the SOC is in normal operating mode, all power supplies, operating clocks, and modules are in normal operating condition.

[0035] When the SOC is in standby mode, most of the digital circuits are powered off, with only the external wake-up source and low-speed clock remaining, and the Flash memory entering a low-power mode.

[0036] When the SOC is in shutdown mode, the core clock is turned off and the CPU stops; other clock sources can be determined by software.

[0037] In this embodiment, the frequency of the low-speed clock is 128kHz, and the frequency of the working clock (sirc_clk) is 8MHz, but it is not limited to these.

[0038] The SoC supports CPU memory operations, meaning that before entering standby mode, the SoC reads instructions from the CPU and stores them in the CPU's static memory. When exiting standby mode and powering on again, the SoC reloads the instructions from the CPU's static memory and writes them back to the CPU. Whether the SoC uses CPU memory operations can be controlled by software.

[0039] Flash memory's low-power modes include DPD (Deep Power Down) mode and power-off mode. Flash memory's low-power modes can be configured via software.

[0040] When the Flash's low-power mode is DPD mode, the Flash power is not completely turned off. When the Flash is woken up from DPD mode, the PMC does not need to power on or reset the Flash. The PMC needs to control the Flash's enable signal to be valid.

[0041] When the Flash's low-power mode is power-off, the Flash power can be turned off via a switch. When the Flash is woken up from power-off mode, the PMC needs to power on and reset the Flash.

[0042] like Figure 2 As shown, the PMC can control the power-on and power-off of the SOC, thereby achieving a low-power design. The PMC includes a control center, bus, synchronization unit, analog unit interface, and wake-up trigger source generation unit.

[0043] Specifically, the PMC can control the SOC to enter power-off mode / normal working mode / standby mode; the PMC can control the CPU memory static storage unit and system static storage unit to enter / exit low-power mode; the PMC can control the Flash to enter / exit low-power mode; the PMC can control the generation of Flash and SOC power-on reset signals; the PMC can control the generation of CPU memory read request signals and control the generation of reload CPU memory request signals; the PMC can control the SOC to terminate the standby mode process.

[0044] If there are no CPU memory operations, the process by which the PMC controls the SOC to enter standby mode includes:

[0045] A1, the CPU sends a deep sleep command to the PMC;

[0046] A2, PMC receives a deep sleep instruction, PMC sends a signal to CPU to keep the sleep instruction inactive, and PMC enters a wait-to-keep-sleep state (WAIT_HOLD);

[0047] A3, PMC enters the PMC isolation enable active state (ISO-ON);

[0048] A4. When the Flash's low-power mode is DPD mode, the PMC controls the Flash's enable signal to be valid, the SOC powers down, the PMC enters standby mode, and the SOC enters standby mode. When the Flash's low-power mode is power off mode, the PMC first resets the Flash, then the Flash powers down, then the SOC system powers down. In the next working clock cycle, the PMC enters standby mode, the working clock is turned off, the low-speed clock is retained, and the SOC enters standby mode.

[0049] If there are no CPU memory operations, the process by which the PMC controls the SOC to exit standby mode includes:

[0050] B1: When a wake-up source is detected, the SOC will be powered on again after approximately one low-speed clock cycle.

[0051] B2, the working clock starts, the PMC generates a power-on completion enable signal according to the timing sequence, and the PMC exits standby mode;

[0052] B3, PMC enters the PMC isolation enable invalid state (ISO-OFF). At the same time, if the Flash's low power mode is power off, the Flash starts to power on and the Flash resets and releases. If the Flash's low power mode is DPD mode, the PMC control Flash enable signal is disabled.

[0053] B4. When the SOC is powered on, the PMC enters normal operating state, and the SOC enters normal operating mode.

[0054] If CPU memory operations are involved, the process by which the PMC controls the SOC to enter standby mode includes:

[0055] C1, the CPU sends a deep sleep command to the PMC;

[0056] C2, PMC receives a deep sleep instruction, PMC sends a signal to CPU to keep the sleep instruction inactive, and PMC enters a wait-to-keep-sleep state (WAIT_HOLD);

[0057] C3, PMC enters CPU memory read request state (CPURD_REQ);

[0058] C4, when the CPU memory read request is completed, the PMC enters the isolation enable state (ISO-ON);

[0059] C5, when the Flash's low-power mode is DPD mode, the PMC controls the Flash's enable signal to be valid, the SOC powers down, the PMC enters standby mode, and the SOC enters standby mode; when the Flash's low-power mode is power off mode, the PMC first resets the Flash, then the Flash powers down, then the SOC powers down, the PMC enters standby mode, the operating clock is turned off, the low-speed clock is retained, and the SOC enters standby mode.

[0060] If CPU memory operations are involved, the process by which the PMC controls the SOC to exit standby mode includes:

[0061] D1: When a wake-up source is detected, the SOC is powered on again after approximately one low-speed clock cycle.

[0062] D2, the working clock starts, the PMC generates a power-on completion enable signal according to the timing sequence, and the PMC exits the standby mode;

[0063] D3, PMC enters CPU memory reload request state (CPURLD_REQ), and reloads data from the CPU memory static storage unit of the SOC to the CPU.

[0064] D4, PMC enters the isolation enable disabled state (ISO_OFF);

[0065] D5. When the Flash's low-power mode is DPD mode, the enable signal controlling the Flash is disabled by the PMC, the SOC powers on, the PMC enters normal operating mode, and the SOC exits standby mode. When the Flash's low-power mode is power-off mode, the Flash starts to power on, the Flash resets and releases, then the SOC powers on, the PMC enters normal operating mode, and the SOC exits standby mode. During the process of entering standby mode, if the SOC receives a wake-up signal from a wake-up source, the SOC must be able to respond to the wake-up source. However, since the external wake-up source is asynchronous in the SOC, the timing of the wake-up signal being sent to the CPU and PMC cannot be guaranteed to be consistent.

[0066] like Figure 3As shown, the wake-up source from the port is sent to the porta / portb / portc / portd / porte modules through the alon_pad_top module, generating a combination of porta_wakeup / portb_wakeup / portc_wakeup / portd_wakeup / porte_wakeup wake-up signals, which are then sent to the CPU and PMC respectively. The resetb input from the external pin is processed by alon_pad_top to generate the resetb_wakeup wake-up signal, which is then sent to the CPU and PMC respectively. The lpit / lptmr / cmp / wdg / rtc modules (internal modules in the normally open power area) generate lpit_wakeup / lptmr_wakeup / cmp_wakeup / wdg_wakeup / rtc_wakeup wake-up signals, which are then sent to the CPU and PMC respectively.

[0067] Due to layout and wiring issues, the arrival times of external wake-up sources from ports, external pins, and normally-on power supply areas are often inconsistent between the CPU and PMC. This can cause the CPU and PMC to receive external wake-up sources at different times, potentially leading to a situation where the CPU starts first while the PMC state transitions later during the SOC's entry into standby mode. This can inevitably result in the CPU running out of power or the SOC malfunctioning.

[0068] like Figure 4 , Figure 5 As shown, to address the issue of potential CPU crashes or SOC malfunctions caused by asynchronous external wake-up sources, this invention provides a handshake control method between the SOC-based PMC and CPU, comprising the following steps:

[0069] S1, Before the SOC enters standby mode, the CPU sends a deep sleep signal to the PMC. A valid deep sleep signal indicates that the CPU has started to enter sleep mode.

[0070] S2, after receiving the deep sleep signal, the PMC sends the first handshake signal to the CPU in the next working clock cycle. When the deep sleep signal is valid, the first handshake signal is valid, and the CPU remains in sleep and does not execute instructions.

[0071] S3, after receiving the first handshake signal, the CPU sends a second handshake signal to the PMC. When the second handshake signal is valid, it means that the CPU has informed the PMC that the CPU has entered the static mode before sleep mode, and then the PMC controls the SOC to enter the standby mode.

[0072] S4. When the first handshake signal is invalid, after the CPU sees that the first handshake signal is invalid, the CPU will make the second handshake signal invalid in the next clock cycle, and the PMC will control the SOC to exit the standby mode.

[0073] Specifically, when the CPU receives a wake-up source, it synchronizes the deep sleep signal for two clock cycles and then invalidates it in the third clock cycle. When the PMC receives a wake-up source, it invalidates the first handshake signal in the next clock cycle. After the CPU sees that the first handshake signal is invalid, it invalidates the second handshake signal in the next working clock cycle, and the handshake between the PMC and the CPU is completed.

[0074] Example 1

[0075] like Figure 6 As shown in this embodiment, after the SOC enters standby mode, a wake-up source appears.

[0076] After the SOC enters standby mode, if a wake-up source appears, the handshake control method between the PMC and the CPU includes the following steps:

[0077] S101, before the SOC enters standby mode, the CPU sends a deep sleep signal (core_deepsleep) to the PMC. If the deep sleep signal is valid, the CPU begins to enter sleep mode.

[0078] S102, after receiving the deep sleep signal, the PMC sends the first handshake signal (holdsleepn) to the CPU in the next clock cycle. If the first handshake signal is valid, the CPU will remain in sleep mode and will not execute any instructions.

[0079] S103, after receiving the first handshake signal, the CPU sends a second handshake signal (holdsleepn_ackn) to the PMC. If the second handshake signal is valid, it means that the CPU has informed the PMC that the CPU has entered the static mode before sleep. The CPU is reset, the working clock is turned off, the low-speed clock is retained, the deep sleep signal is set to invalid, and the SOC enters standby mode.

[0080] S104, a wake-up source appears. The CPU is in a reset state and cannot be woken up. The PMC generates a wake-up signal. The PMC judges and controls the next working clock cycle. The PMC sets the first handshake signal to invalid. After the CPU sees that the first handshake signal is invalid, the CPU sets the second handshake signal to invalid in the next working clock cycle. The handshake between the PMC and the CPU is completed.

[0081] S105, PMC controls SOC to exit standby mode.

[0082] In this embodiment, the deep sleep signal is active high, the first handshake signal is active low, and the second handshake signal is active low.

[0083] In this embodiment, when the SOC enters standby mode, a wake-up source appears. Through the handshake operation between the PMC and the CPU, it is ensured that the CPU will not hang when the external wake-up source is asynchronous, and the SOC can operate normally.

[0084] Example 2

[0085] like Figure 7 As shown in this embodiment, before the SOC enters standby mode, a wake-up source appears after asynchronous wake-up synchronization, and the CPU sees the wake-up source first, followed by the PMC.

[0086] The handshake control method between the PMC and the CPU includes the following steps:

[0087] S201: Before the SOC enters standby mode, the CPU sends a deep sleep signal to the PMC. If the deep sleep signal is valid, the CPU begins to enter sleep mode.

[0088] S202, after the PMC receives the deep sleep signal, it sends the first handshake signal to the CPU in the next working clock cycle. If the first handshake signal is valid, the CPU will remain in sleep mode and will not execute any instructions.

[0089] S203: The CPU sees the wake-up source first. In the next working clock cycle, the CPU sends the second handshake signal to the PMC and makes it valid, while setting the deep sleep signal to invalid.

[0090] S204, in the next working clock cycle, the PMC resumes normal operation and invalidates the first handshake signal;

[0091] S205, the CPU sees the first handshake signal as invalid, and in the next working clock cycle, it sets the second handshake signal to invalid, completing the handshake between the PMC and the CPU;

[0092] S206, PMC controls SOC to exit standby mode.

[0093] In this embodiment, the deep sleep signal is active high, the first handshake signal is active low, and the second handshake signal is active low.

[0094] In this embodiment, before the SOC enters standby mode, a wake-up source appears after the asynchronous wake-up synchronization. The CPU sees the wake-up source first, and the PMC sees it later. Through the handshake operation between the PMC and the CPU, it is ensured that the CPU will not hang when the external wake-up source is asynchronous, and the SOC can run normally.

[0095] Example 3

[0096] like Figure 8As shown in this embodiment, before the SOC enters standby mode, a wake-up source appears after asynchronous wake-up synchronization, and the PMC sees the wake-up source first, followed by the CPU.

[0097] The handshake control method between the PMC and the CPU includes the following steps:

[0098] S301: Before the SOC enters standby mode, the CPU sends a deep sleep signal to the PMC. If the deep sleep signal is valid, the CPU begins to enter sleep mode.

[0099] After receiving the deep sleep signal, the S302 PMC sends the first handshake signal to the CPU in the next working clock cycle. If the first handshake signal is valid, the CPU will remain in sleep mode and will not execute any instructions.

[0100] S303, PMC sees the wake-up source first, and in the next working clock cycle, PMC resumes normal operation and invalidates the first handshake signal;

[0101] S304, the CPU sees the first handshake signal as invalid, and in the next working clock cycle, it sets the second handshake signal to invalid, completing the handshake between the PMC and the CPU;

[0102] S305, PMC controls SOC to exit standby mode.

[0103] In this embodiment, the deep sleep signal is active high, the first handshake signal is active low, and the second handshake signal is active low.

[0104] In this embodiment, before the SOC enters standby mode, a wake-up source appears after the asynchronous wake-up synchronization. The PMC sees the wake-up source first, and the CPU sees the wake-up source later. Through the handshake operation between the PMC and the CPU, it is ensured that the CPU will not hang when the external wake-up source is asynchronous, and the SOC can run normally.

[0105] Example 4

[0106] like Figure 9 As shown in this embodiment, before the SOC enters standby mode, the CPU is performing a memory operation, that is, when the CPU reads instructions and stores them in the CPU memory static storage unit, a wake-up source appears after asynchronous wake-up synchronization.

[0107] The handshake control method between the PMC and the CPU includes the following steps:

[0108] S401: Before the SOC enters standby mode, the CPU sends a deep sleep signal to the PMC. If the deep sleep signal is valid, the CPU begins to enter sleep mode.

[0109] S402, after the PMC receives the deep sleep signal, it sends the first handshake signal to the CPU in the next working clock cycle. If the first handshake signal is valid, the CPU remains asleep and does not execute instructions. The PMC enters the CPU read request state (CPURD_REQ). At this time, a wake-up source appears.

[0110] S403, in the next working clock cycle, the PMC resumes normal operation and invalidates the first handshake signal;

[0111] S404, the CPU sees the first handshake signal as invalid, and in the next working clock cycle, it sets the second handshake signal to invalid, completing the handshake between the PMC and the CPU;

[0112] S405, PMC controls SOC to exit standby mode.

[0113] In this embodiment, the deep sleep signal is active high, the first handshake signal is active low, and the second handshake signal is active low.

[0114] In this embodiment, before the SOC enters standby mode, the CPU is performing a memory operation, that is, when the CPU reads instructions and stores them in the CPU memory static storage unit, a wake-up source appears after the asynchronous wake-up synchronization. Through the handshake operation between the PMC and the CPU, it is ensured that the CPU will not hang when the external wake-up source is asynchronous, and the SOC can run normally.

[0115] Example 5

[0116] In this embodiment, before the SOC enters standby mode, when the PMC is in the isolation enable active state (ISO_ON), ​​a wake-up source appears after asynchronous wake-up synchronization. The low power mode of the Flash is DPD mode and the Flash enable signal is invalid, or the low power mode of the Flash is power off mode, but the Flash is resetting and has not yet lost power.

[0117] The handshake control method between the PMC and the CPU includes the following steps:

[0118] S501: Before the SOC enters standby mode, the CPU sends a deep sleep signal to the PMC. If the deep sleep signal is valid, the CPU begins to enter sleep mode.

[0119] After receiving the deep sleep signal, the S502 PMC sends the first handshake signal to the CPU in the next working clock cycle. If the first handshake signal is valid, the CPU will remain in sleep mode and will not execute any instructions.

[0120] S503: After receiving the first handshake signal, the CPU sends a second handshake signal to the PMC. The second handshake signal is valid.

[0121] S504 When the PMC enters the isolation enable state, a wake-up source appears. In the next working clock cycle, the PMC resumes normal operation and invalidates the first handshake signal.

[0122] S505: When the CPU sees the first handshake signal as invalid, it sets the second handshake signal to invalid in the next working clock cycle, thus completing the handshake between the PMC and the CPU.

[0123] S506, PMC controls the SOC to exit standby mode.

[0124] In this embodiment, the deep sleep signal is active high, the first handshake signal is active low, and the second handshake signal is active low.

[0125] In this embodiment, before the SOC enters standby mode, when the PMC is in the isolation enable effective state, a wake-up source appears after the asynchronous wake-up synchronization. The Flash's low power mode is DPD mode and the Flash's enable signal is invalid, or the Flash's low power mode is power off mode and the Flash is resetting and has not yet lost power. Through the handshake operation between the PMC and the CPU, it is ensured that the CPU will not hang when the external wake-up source is asynchronous, and the SOC can operate normally.

[0126] Example 6

[0127] like Figure 10 As shown in this embodiment, before the SOC enters standby mode, when the PMC is in the isolation enable effective state (ISO_ON), ​​a wake-up source appears after asynchronous wake-up synchronization. The low power mode of the Flash is power off mode, and the Flash has completed reset and power-off.

[0128] The handshake control method between the PMC and the CPU includes the following steps:

[0129] S601: Before the SOC enters standby mode, the CPU sends a deep sleep signal to the PMC. If the deep sleep signal is valid, the CPU begins to enter sleep mode.

[0130] S602: After the PMC receives the deep sleep signal, it sends the first handshake signal to the CPU in the next working clock cycle. If the first handshake signal is valid, the CPU will remain in sleep mode and will not execute any instructions.

[0131] S603: After receiving the first handshake signal, the CPU sends a second handshake signal to the PMC. The second handshake signal is valid.

[0132] S604 When the PMC enters the isolation enable state, a wake-up source appears. In the next working clock cycle, the PMC resumes normal operation, controls the Flash to power on, then controls the Flash to reset and release, and then the PMC releases the first handshake signal as invalid.

[0133] S605: When the CPU sees the first handshake signal as invalid, it sets the second handshake signal to invalid in the next working clock cycle, thus completing the handshake between the PMC and the CPU.

[0134] S606, PMC controls SOC to exit standby mode.

[0135] In this embodiment, the deep sleep signal is active high, the first handshake signal is active low, and the second handshake signal is active low.

[0136] In this embodiment, before the SOC enters standby mode, when the PMC is in the isolation enable state, a wake-up source appears after the asynchronous wake-up synchronization. The low power mode of the Flash is power off mode, and the Flash has completed reset and power-down. Through the handshake operation between the PMC and the CPU, it is ensured that the CPU will not hang when the external wake-up source is asynchronous, and the SOC can run normally.

[0137] In summary, the present invention has the following beneficial effects: regardless of whether the SOC enters standby mode or not, and regardless of the state of the PMC, if an asynchronous wake-up signal occurs, the handshake control method between the PMC and the CPU can ensure that the CPU will not hang when the external wake-up source is asynchronous, and the SOC can operate normally.

[0138] The present invention also provides a system that employs the aforementioned handshake control method between the SOC-based PMC and the CPU.

[0139] The present invention has the following beneficial effects: regardless of whether the SOC enters standby mode or before standby mode, and under various states of the PMC, if an asynchronous wake-up signal appears, the handshake control method between the PMC and the CPU can ensure that the CPU will not hang when the external wake-up source is asynchronous, and the SOC can operate normally.

[0140] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A handshake control method between PMC and CPU based on SOC, characterized in that, The handshake control method includes the following steps: S1, before the SOC enters standby mode, the CPU sends a deep sleep signal to the PMC, the deep sleep signal indicating that the CPU has started to enter sleep mode; S2, after receiving the deep sleep signal, the PMC sends a first handshake signal to the CPU in the next clock cycle. When the deep sleep signal is valid, the first handshake signal is valid, and the CPU remains in sleep mode and does not execute instructions. S3, after receiving the first handshake signal, the CPU sends a second handshake signal to the PMC. When the second handshake signal is valid, it indicates that the CPU has informed the PMC that the CPU has entered the static mode before sleep mode, and then the PMC controls the SOC to enter the standby mode. S4, when the first handshake signal is invalid, after the CPU sees that the first handshake signal is invalid, the CPU will make the second handshake signal invalid in the next clock cycle, and the PMC will control the SOC to exit the standby mode.

2. The handshake control method between PMC and CPU based on SOC according to claim 1, characterized in that, In step S3, a wake-up source appears in the standby mode of the SOC. The PMC generates an asynchronous wake-up signal and performs judgment and control. In the next working clock cycle, the PMC invalidates the first handshake signal. After the CPU sees that the first handshake signal is invalid, the CPU invalidates the second handshake signal in the next working clock cycle. The PMC controls the SOC to exit the standby mode.

3. The handshake control method between PMC and CPU based on SOC according to claim 1, characterized in that, In step S2, when the PMC is waiting for the CPU to send the second handshake signal, a wake-up source appears after the asynchronous wake-up source is synchronized. The CPU sees the wake-up source first, and the PMC sees the wake-up source later. The first handshake signal is valid. In the next working clock cycle, the CPU generates a valid second handshake signal and simultaneously invalidates the deep sleep signal. In the next working clock cycle, the PMC jumps to the normal working mode and invalidates the first handshake signal. After the CPU sees the first handshake signal invalid, it invalidates the second handshake signal in the next working clock cycle. The PMC controls the SOC to exit the standby mode.

4. The handshake control method between PMC and CPU based on SOC according to claim 1, characterized in that, In step S2, when the PMC is waiting for the CPU to send the second handshake signal, a wake-up source appears after the asynchronous wake-up synchronization. The PMC sees the wake-up source first, and the CPU sees the wake-up source later. The first handshake signal is valid. The PMC jumps to normal working mode in the next working clock cycle and invalidates the first handshake signal. The CPU receives the invalid first handshake signal and also invalidates the second handshake signal in the next working clock cycle. The PMC controls the SOC to exit standby mode.

5. The handshake control method between PMC and CPU based on SOC according to claim 1, characterized in that, When CPU memory operations are involved, the process by which the PMC controls the SOC to enter standby mode includes: C1, the CPU sends a deep sleep command to the PMC; C2, the PMC receives the deep sleep instruction, the PMC sends a signal to the CPU to keep the sleep instruction inactive, and the PMC enters a waiting state to keep the sleep. C3, the PMC enters the CPU memory read request state; C4, when the CPU memory read request is completed, the PMC enters the isolation enable state; C5, the PMC enters standby mode, and the SOC enters standby mode.

6. The handshake control method between PMC and CPU based on SOC according to claim 5, characterized in that, In step C3, when the PMC is in the CPU memory read request state, a wake-up source appears after asynchronous wake-up synchronization. After seeing the wake-up source, the PMC switches to normal working state and releases the first handshake signal as invalid. The CPU sees that the first handshake signal is invalid and sets the second handshake signal to invalid in the next working clock cycle. The PMC controls the SOC to exit standby mode.

7. The handshake control method between PMC and CPU based on SOC according to claim 5, characterized in that, The SOC also includes Flash memory, which has a low-power mode of DPD or power-off mode. In step C5, when the Flash memory is in DPD mode, the PMC enables the Flash memory, the SOC is powered down, the PMC enters standby mode, and the SOC enters standby mode. When the Flash memory is in power-off mode, the PMC first resets the Flash memory, then the Flash memory is powered down, then the SOC is powered down, the PMC enters standby mode, and the SOC enters standby mode.

8. The handshake control method between PMC and CPU based on SOC according to claim 7, characterized in that, In step C4, when the PMC is in the isolation enable enabled state, and the Flash's low-power mode is DPD mode and the PMC controls the Flash's enable signal to be invalid, or when the Flash's low-power mode is power off mode and the Flash is resetting and has not yet lost power, a wake-up source appears after asynchronous wake-up synchronization. When the PMC sees the wake-up source, the PMC switches to normal working state and releases the first handshake signal as invalid. The CPU sees the first handshake signal as invalid and sets the second handshake signal as invalid in the next clock cycle. The PMC controls the SOC to exit standby mode.

9. The handshake control method between PMC and CPU based on SOC according to claim 7, characterized in that, In step C4, when the PMC is in the isolation enable state, and the Flash is in power-off mode and has completed reset and power-down, a wake-up source appears after asynchronous wake-up synchronization. When the PMC sees the wake-up source, the PMC enters normal working state, controls the Flash to power on, then controls the Flash to reset and release, and then the PMC releases the first handshake signal as invalid. The CPU sees the first handshake signal as invalid and sets the second handshake signal as invalid in the next working clock cycle. The PMC controls the SOC to exit standby mode.

10. A system employing any one of the SOC-based PMC and CPU handshake control methods as described in claims 1-9, characterized in that: The PMC includes a control center, a bus, a synchronization unit, an analog unit interface, and a wake-up trigger source generation unit.

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