A processor low-power consumption control method, system, device and storage medium

Abstract

The application belongs to the field of computer chips, and particularly relates to a processor low-power consumption control method, system, device and readable storage medium. The method comprises the following steps: constructing a mapping relationship or model based on the association relationship between the memory data in the memory and the working state of the extension node during execution; and determining the working state of the extension node according to the mapping relationship or model and the memory data read by the processor. Through the processor low-power consumption control method, the influence of the memory data loaded by the processor on the working state of the extension node is considered, and when the memory data capable of influencing the extension node is read by the processor, if the corresponding extension node is in a closed state, the corresponding extension node is turned on. The power consumption control scheme with clock cycle as granularity can be realized.

Description

Technical Field

[0001] This invention belongs to the field of computer chips, and specifically relates to a processor low-power control method, system, device, and readable storage medium. Background Technology

[0002] With the continuous advancement of semiconductor technology, the number of transistors per unit area is increasing, and computing performance is becoming more and more powerful. However, this also brings about higher power consumption and higher demands on power resources, requiring additional financial investment. Therefore, reducing chip power consumption has become one of the hottest topics in the chip industry.

[0003] However, traditional implementations typically employ power gating technology. Power gating refers to shutting off the power supply to a specific area of ​​the chip, effectively disconnecting the power supply to the logic circuits within that area. If a module is not operating for a period of time, its power supply can be turned off. After power failure, the design enters sleep mode, resulting in very low leakage power. Upon wake-up, to ensure the module quickly resumes its operating mode, it needs to maintain its state before power failure. Holding registers can be used to remember this state. In other words, controlling the function of corresponding modules within the chip through power gating is a relatively suitable power consumption control method.

[0004] Power gating technology requires the addition of holding registers, increasing chip area. Although holding registers consume less power than ordinary registers, they still consume some power. Power control requires software control software, and during use, switching operations need to be performed multiple clock cycles in advance, which affects the system's response speed. Power control requires pre-writing control software for specific application scenarios, resulting in poor versatility and an inability to achieve universal adaptability.

[0005] Therefore, an effective solution is urgently needed to address the above problems. Summary of the Invention

[0006] To address the above problems, this invention proposes a processor low-power control method, comprising:

[0007] A mapping relationship or model is constructed based on the association between the corresponding memory data in memory and the working state of the extended node during execution;

[0008] The working state of the extended node is determined based on the mapping relationship or model and the memory data read by the processor.

[0009] In some embodiments of the present invention, constructing a mapping relationship or model based on the association between the corresponding memory data in memory during execution and the working state of the extended node includes:

[0010] Monitor the memory read requests issued by the processor and record the memory address in memory corresponding to the memory read request;

[0011] Monitor the bus communication data between the processor and the expansion node, and determine whether the processor sends an access request to the expansion node after the memory data corresponding to the read request is loaded into the processor based on the bus communication.

[0012] In response to the processor issuing an access request to the corresponding extension node, a mapping relationship or model is established between the memory address and the extension node.

[0013] In some embodiments of the present invention, determining the working state of the extended node based on the mapping relationship or model and the memory data read by the processor includes:

[0014] Real-time monitoring of memory read requests issued by the processor, and determination of whether the memory address corresponding to the read request has a corresponding extended node in the mapping relationship or model;

[0015] In response to the existence of an extension node corresponding to the memory address in the mapping relationship or model, the working status of the extension node is determined, and in response to the working status of the extension node being closed, the extension node is turned on.

[0016] In some embodiments of the present invention, the method further includes:

[0017] In response to the corresponding extension node being in a closed state, and the processor issuing a corresponding memory access request on the bus connected to the extension node, the extension node sends a busy working state to the processor through the bus proxy.

[0018] In some embodiments of the present invention, constructing a mapping relationship or model based on the association between the corresponding memory data in memory during execution and the working state of the extended node further includes:

[0019] Collect memory read requests issued by the processor, as well as bus communications issued by the processor when the memory data corresponding to the memory read requests is executed in the processor, and identify the extended node corresponding to the bus communications. Use the address of the memory data and the extended node as training data to train the first neural network model.

[0020] In some embodiments of the present invention, the method further includes:

[0021] In response to a memory read request from the processor, the first neural network analyzes whether the memory data at the memory address corresponding to the memory read request will access the corresponding extended node during processor execution; and

[0022] In response to the memory access to the corresponding extended node when the memory data corresponding to the memory address is executed in the processor, and the extended node is in a closed state, the extended node is turned on.

[0023] In some embodiments of the present invention, the method further includes:

[0024] Obtain the memory addresses of all cached memory data in the processor cache, and use the memory addresses of the cached memory data and the bus communication requests issued by the processor to access the memory extension node when the cached memory data is stored as training data to train the second neural network model.

[0025] The memory address corresponding to the memory data in the processor cache is obtained in real time, and the memory address is input into the second neural network model. The second neural network model is then used to determine whether to close the corresponding extended node.

[0026] Another aspect of the present invention provides a processor low-power control system, comprising:

[0027] The data processing module is configured to construct a mapping relationship or model based on the association between the corresponding memory data in memory and the working state of the extended node during execution.

[0028] A status arbitration module is configured to determine the working status of the extended node based on the mapping relationship or model and memory data read by the processor.

[0029] Another aspect of the present invention provides a computer device comprising:

[0030] At least one processor; and

[0031] A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of any of the methods described in the above embodiments.

[0032] Another aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the methods described in the above embodiments.

[0033] The processor low-power control method proposed in this invention is based on the influence of processor-loaded memory data on the operating state of expansion nodes. When the processor reads memory data that can affect the expansion node, if the corresponding expansion node is in a closed state, then the corresponding expansion node is turned on. This enables a power control scheme with clock cycle granularity. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A flowchart of a processor low-power control method provided in an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the system structure of a processor low-power control system provided in an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of the structure of a computer device provided in an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present invention.

[0039] Figure 5 A schematic diagram illustrating the implementation principle of a processor low-power control method provided in an embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram illustrating part of the implementation principle of a processor low-power control method provided in an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0042] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0043] This invention aims to solve the problem of low control efficiency in low-power chip control schemes. With the development of semiconductor technology, the computing and data processing capabilities of chips have been greatly improved. At the same time, more and more functions are being integrated into chips. Even with improvements in process technology and architecture, chip power consumption and heat generation are still increasing. Therefore, many power control schemes have emerged, such as underclocking and "undervoltage overclocking" techniques for mainstream Intel and AMD CPUs on desktop platforms, or operating system power management schemes. These can reduce CPU power consumption to some extent, but often result in lower frequency and performance loss. Another example is power control using chip power gating technology, which requires adding holding registers, increasing chip area and limiting power reduction. Furthermore, it requires control by compatible software, which is also subject to performance degradation due to software execution limitations. Moreover, the software control logic needs to be modified according to different application scenarios, lacking universality.

[0044] like Figure 1 As shown, to solve the above problems, this invention proposes a processor low-power control method, comprising:

[0045] Step S1: Construct a mapping relationship or model based on the association between the corresponding memory data in memory and the working state of the extended node during execution;

[0046] Step S2: Determine the working status of the extended node based on the mapping relationship or model and the memory data read by the processor.

[0047] In embodiments of the present invention, an extension node refers to a functional module in the processor, excluding the core computing unit, used to connect to other peripherals or other devices on the computer. For example, taking a common x86 platform processor as an example, the processor needs to provide multiple data connection methods, i.e., multiple types of buses, such as PCIe, I2C, and UART, each with corresponding internal circuit modules implementing their respective functions. In this embodiment, modules outside the CPU core that have no impact on the processor's computing power, or modules whose operating state is subject to processor scheduling, are referred to as extension nodes. Working state refers to whether the extension node is invoked by the processor.

[0048] Specifically, in step S1, after the corresponding memory data in memory is loaded into the processor, it is monitored whether the processor generates a bus request to access (including sending data to and retrieving data from the expansion node) the corresponding expansion node during execution. If, after the data in memory is loaded into and executed by the processor, the processor issues a data read request to an expansion node, it is considered that the memory data will affect the working state of that expansion node. Further, the memory data affecting the working state of the expansion node is associated with a mapping relationship established with the expansion node, or with an artificial intelligence model. The established mapping relationship can be many-to-many, meaning that multiple memory data may affect the working state of a certain expansion node. Alternatively, one piece of memory data may affect the working state of multiple expansion nodes.

[0049] In step S2, based on the mapping relationship or model established in step S1, requests from the processor to read data from memory are monitored in real time. Then, based on the mapping relationship or model, a judgment is made: if the memory data to be read by the processor will trigger a data access request to an extended node when loaded into the processor for execution, the corresponding extended node should be in a working state. If the extended node is in a normal powered-on and standby state, no action is taken on the extended node. If the extended node is in a powered-off state, it is powered on and initialized.

[0050] In some embodiments of the present invention, based on the judgment result of the memory read request issued by the processor according to the mapping relationship or model, when controlling the expansion node according to the result, an existing gating technique can be selected to control the expansion node. The gating technique can quickly start the expansion node without the need for software to trigger it during processor execution.

[0051] Similarly, the expansion nodes can be controlled by power-on and power-off startup and shutdown methods. The specific method depends on the initialization time of different expansion nodes and the time it takes for the processor to read data from memory or cache. If the initialization time of an expansion module exceeds the time it takes for the processor to retrieve data from memory, the working state of the expansion node will not be controlled by power-on and power-off methods.

[0052] In some embodiments of the present invention, constructing a mapping relationship or model based on the association between the corresponding memory data in memory during execution and the working state of the extended node includes:

[0053] Monitor the memory read requests issued by the processor and record the memory address in memory corresponding to the memory read request;

[0054] Monitor the bus communication data between the processor and the expansion node, and determine whether the processor sends an access request to the expansion node after the memory data corresponding to the read request is loaded into the processor based on the bus communication.

[0055] In response to the processor issuing an access request to the corresponding extension node, a mapping relationship or model is established between the memory address and the extension node.

[0056] In this embodiment, reference Figure 5 , Figure 5 The diagram illustrates an embodiment of the present invention. The implemented hardware circuit, namely the data processing module shown in the diagram, is mounted on the memory bus to monitor memory read requests issued by the processor through the memory controller in real time. At the same time, the data processing module is connected to the bus of multiple expansion nodes connected to the processor, and monitors whether the processor issues a bus request to access the corresponding expansion node.

[0057] Furthermore, for monitored memory read requests, all information except the lower 6 bits of the address information in the memory read request is extracted; that is, the address of the memory data requested in memory is replaced with the address of the memory data itself. After the memory data is loaded into memory through the memory controller, the bus communication between each expansion node and the processor is monitored. If the processor initiates an access request to one or more expansion nodes, it is assumed that the execution of this memory data will call one or more expansion nodes. A mapping relationship is then established and saved between the memory address and one or more expansion nodes.

[0058] In some embodiments of the present invention, a predictive model for the state of memory addresses and extended nodes can be established by training a corresponding artificial intelligence model.

[0059] In some embodiments of the present invention, determining the working state of the extended node based on the mapping relationship or model and the memory data read by the processor includes:

[0060] Real-time monitoring of memory read requests issued by the processor, and determination of whether the memory address corresponding to the read request has a corresponding extended node in the mapping relationship or model;

[0061] In response to the existence of an extension node corresponding to the memory address in the mapping relationship or model, the working status of the extension node is determined, and in response to the working status of the extension node being closed, the extension node is turned on.

[0062] In this embodiment, as Figure 5As shown, after the mapping relationship or model has been established, the data processing module still monitors the memory read requests issued by the memory controller and intercepts the memory address of the memory read request. Then, it queries the mapping relationship or model in the status arbitration module to see if there is a corresponding extended node for the memory address. If there is a corresponding extended node, it determines whether the extended node is in a closed state. If it is in a closed state, it opens the extended node.

[0063] In some embodiments of the present invention, the method further includes:

[0064] In response to the corresponding extension node being in a closed state, and the processor issuing a corresponding memory access request on the bus connected to the extension node, the extension node sends a busy working state to the processor through the bus proxy.

[0065] In this embodiment, the mapping relationship or model established by the above embodiments of the present invention is based on the relationship between the memory data executed in the processor after the computer is powered on and the state of the corresponding extended node. Therefore, during computer operation, there may be instances where some memory data is loaded into the processor for the first time and the address of this memory data is not recognized by the mapping relationship or model, resulting in the corresponding extended node being in a closed state. However, the processor issues a corresponding bus request on the bus connected to the extended node to communicate with the corresponding external device through the extended node. At this time, since the extended node is in a closed state and cannot respond to the processor's request, the data processing module sends a busy status response to the processor on behalf of the corresponding extended node, that is, returns a busy status code.

[0066] In some embodiments of the present invention, constructing a mapping relationship or model based on the association between the corresponding memory data in memory during execution and the working state of the extended node further includes:

[0067] Collect memory read requests issued by the processor, as well as bus communications issued by the processor when the memory data corresponding to the memory read requests is executed in the processor, and identify the extended node corresponding to the bus communications. Use the address of the memory data and the extended node as training data to train the first neural network model.

[0068] In this embodiment, reference Figure 5 A simplified neural network model is established in the state arbitration module, and the memory address is used as a feature, along with the working states of multiple extended nodes as the results, to train the corresponding first neural network model. The algorithm for the first neural network model can employ a multi-class prediction algorithm, such as SVM, using the extended nodes as classification results and the memory address as input data for training.

[0069] In some embodiments of the present invention, the method further includes:

[0070] In response to a memory read request from the processor, the first neural network analyzes whether the memory data at the memory address corresponding to the memory read request will access the corresponding extended node during processor execution; and

[0071] In response to the memory access to the corresponding extended node when the memory data corresponding to the memory address is executed in the processor, and the extended node is in a closed state, the extended node is turned on.

[0072] In this embodiment, the addresses in the memory read requests issued by the processor are classified according to the trained classification model. If the address has a corresponding classification result, that is, the memory data corresponding to the address will call the corresponding extension node after being added to the processor for execution, the status of the corresponding extension node is determined. If it is in a closed state, it is turned on.

[0073] In some embodiments of the present invention, the method further includes:

[0074] Obtain the memory addresses of all cached memory data in the processor cache, and use the memory addresses of the cached memory data and the bus communication requests issued by the processor to access the memory extension node when the cached memory data is stored as training data to train the second neural network model.

[0075] The memory address corresponding to the memory data in the processor cache is obtained in real time, and the memory address is input into the second neural network model. The second neural network model is then used to determine whether to close the corresponding extended node.

[0076] In this embodiment, reference Figure 6 In the status arbitration module, an address cache module is established to store all memory data in the processor cache. The address cache module extracts the memory address of all caches in the processor cache except for the lower 6 bits and saves it to the address cache module.

[0077] Processor cache refers to a set of fixed-size data blocks called cache lines, which are typically 64 bytes in modern computers. When fetching data from memory into the cache, a cache line-sized region of memory is fetched at a time and stored in the corresponding cache line. Only the starting address of the corresponding 64 bytes of memory data needs to be stored. The lower six bits of the starting address are all 0, so the address above the lower six bits is retained to save space.

[0078] Furthermore, based on the mapping relationship or model in the above embodiments and the address of the cached memory data, it is determined which cached memory data in the processor cache will affect the running state of the corresponding extended nodes after being loaded into memory. The extended nodes affected by all the cached memory data are taken as the result, and the addresses of all the cached memory data are taken as features. A classification model is trained based on the cerebellum neural network algorithm, that is, multiple memory addresses of cached memory data and the extended nodes that multiple memory addresses can affect are used as feature data to train the corresponding neural network model.

[0079] Specifically, the address of the corresponding memory data in the processor cache is read, and then the extended nodes affected by the memory data address are marked through a mapping relationship or a first neural network model. Then, a cerebellar neural network model is trained based on the feature data composed of the memory data address and the corresponding extended nodes. In this embodiment, the memory address of each 64-byte address space in memory is used as a feature to construct a mapping relationship between features and memory addresses. Assuming the memory is 1GB, the corresponding feature dimension is 1024*16 = 16384 features. If the memory data address (the starting address of the 64-byte memory space) is 0x0000000, i.e., the first starting address of the memory space, and if the data corresponding to this memory address is in the cache, then the feature of the first feature dimension is set to 1. Figure 6 As shown, the value of feature a1 is 1. Further, if the data at this memory address will call extended node 0 after being loaded into the processor, and assuming that the cache only contains this memory data, then the data recorded in the feature record should be (1, 0, 0, 0...; 1, 0, 0). The first 1 indicates that the memory address of this stored data is the first one, and data at other memory addresses has not been loaded into the cache. The second 1 indicates that when the data in the cache is loaded into the processor, extended node 0 will be called, and other extended nodes will not be called. In this way, the address of the memory data in the cache during each cache update, and the extended nodes affected by the memory data, are used as feature data, as shown above. Figure 6 The cerebellum neural network model is dynamically trained in this way.

[0080] After the trained cerebellar neural network model (converges to a suitable range), the data updates in the processor cache are monitored, and the addresses of the updated memory data in the processor cache are synchronously updated to the address cache module (which only stores memory addresses). At the same time, the memory addresses in the address cache module are converted into corresponding feature data and input into the trained cerebellar neural network module. Based on the output of the cerebellar neural network model, it is determined whether to close the corresponding extension node. That is, if the corresponding memory data does not exist in the processor cache, the corresponding extension node can be closed.

[0081] In some embodiments of the present invention, the address cache may only store the block number of the corresponding memory data in memory, thereby reducing the data size of the address cache. For example, taking 0x0000000 as an example, 0x0000000 represents the first 64-byte memory space. Therefore, when storing, only the sequence number 0 needs to be stored, 0x0000001 needs to be stored as sequence number 1, and 0x0000003 needs to be stored as 3. This can save a lot of storage space. When inputting into the neural network model, if the address cache stores 1, 2, and 3, then the values ​​of the first, second, and third features of the feature dimension can be set to 1.

[0082] In some embodiments of the present invention, since the memory address space is represented by cache line blocks, the memory address can be represented by the block number where the memory data's initial address is located when constructing the mapping relationship between memory addresses and extended nodes. That is, when the block number is 0, it represents a 64-byte memory space starting from memory address 0x0000000, and when the block number is 1, it represents a 64-byte memory space starting from memory address 0x0000001. Therefore, in this embodiment, the mapping relationship between memory data and extended nodes can be simplified to a smaller data space. Taking {0:0} as an example, it can be said that memory data at memory address 0x0000000 will call extended node 0 after being loaded into the processor.

[0083] Furthermore, since most of the memory data that enables the processor to access extended nodes and external devices is the driver, the operating system loads the specified driver into a fixed location in memory after the computer boots up (some device drivers require a restart to take effect after installation because when the driver is loaded into memory, it may conflict with the memory address space of the existing device driver and cannot be reloaded to another address space). Therefore, the memory data available for calling extended nodes is limited. As a result, the access of network, disk and other devices by user-installed programs on the computer is implemented by the operating system's API.

[0084] Furthermore, the mapping relationship between memory addresses and feature numbers can be further compressed. For example, in the above embodiment, each 64 bytes of memory space corresponds to one dimension, and 1GB of memory space corresponds to 1024*16=16384. Therefore, 128 bytes can be chosen as the space. The corresponding feature dimensions are then reduced to 8192.

[0085] It should be noted that the processor low-power control system proposed in this invention is a functional logic implemented in hardware. By monitoring the memory read requests issued by the processor's memory controller, and then executing the memory data accessed in the memory read request in the processor, the behavior of the extended nodes is learned, i.e., a mapping relationship or model is established. The addresses of the memory data that can affect the corresponding extended nodes are saved. When the memory controller issues another memory data read request, the behavior of the memory data is judged based on the memory address and the mapping relationship or model. If the execution of the memory data will call the corresponding extended node, the extended node will be turned on in a timely manner if it is closed.

[0086] Additionally, during implementation, it is necessary to consider whether the corresponding expansion node can be enabled within the time frame of the processor initiating a memory read request → memory responding to the read request and returning the corresponding memory data to the processor → the processor issuing a memory access request to the expansion node. For those that cannot be enabled, it is possible to either not disable them or report a busy status to the processor.

[0087] This invention proposes a low-power processor control method that leverages the impact of processor-loaded memory data on the operating state of expansion nodes. When the processor reads memory data that affects an expansion node, if the corresponding expansion node is in a disabled state, it is then enabled. This allows for power control at the clock cycle level. It eliminates the lag inherent in software control, enabling and disabling expansion node functionality within a limited clock cycle, resulting in more efficient processor power consumption control. Figure 2 As shown, another aspect of the present invention provides a processor low-power control system, comprising:

[0088] Data processing module 1, configured to construct a mapping relationship or model based on the association between the corresponding memory data in memory during execution and the working state of the extended node;

[0089] State arbitration module 2 is configured to determine the working state of the extended node based on the mapping relationship or model and the memory data read by the processor.

[0090] like Figure 3 As shown, another aspect of the present invention also provides a computer device comprising:

[0091] At least one processor 21; and

[0092] The memory 22 stores computer instructions 23 that can be executed on the processor 21, which, when executed by the processor 21, implement the steps of any of the methods described in the above embodiments.

[0093] like Figure 4 As shown, another aspect of the present invention provides a computer-readable storage medium 401, which stores a computer program 402, which, when executed by a processor, implements the steps of any of the methods described in the above embodiments.

[0094] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0095] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0096] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0097] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0098] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of the different aspects of the invention as described above exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A processor low-power control method, characterized in that, include: A mapping relationship or model is constructed based on the association between the corresponding memory data in memory and the working state of the extended node during execution. The extended node refers to a functional module in the processor other than the core computing unit, which is used to connect to other peripherals or other devices on the computer. The working status of the extended node is determined based on the mapping relationship or model and the memory data read by the processor; The construction of a mapping relationship or model based on the association between the corresponding memory data in memory during execution and the working state of the extended node includes: Monitor the memory read requests issued by the processor and record the memory address in memory corresponding to the memory read request; Monitor the bus communication data between the processor and the expansion node, and determine whether the processor sends an access request to the expansion node after the memory data corresponding to the read request is loaded into the processor based on the bus communication. In response to the processor issuing an access request to the corresponding extension node, a mapping relationship or model is established between the memory address and the extension node.

2. The method according to claim 1, characterized in that, Determining the working state of the extended node based on the mapping relationship or model and the memory data read by the processor includes: Real-time monitoring of memory read requests issued by the processor, and determination of whether the memory address corresponding to the read request has a corresponding extended node in the mapping relationship or model; In response to the existence of an extension node corresponding to the memory address in the mapping relationship or model, the working status of the extension node is determined, and in response to the working status of the extension node being closed, the extension node is turned on.

3. The method according to claim 2, characterized in that, Also includes: In response to the corresponding extension node being in a closed state, and the processor issuing a corresponding memory access request on the bus connected to the extension node, the extension node sends a busy working state to the processor through the bus proxy.

4. The method according to claim 1, characterized in that, The construction of the mapping relationship or model based on the association between the corresponding memory data in memory during execution and the working state of the extended node also includes: Collect memory read requests issued by the processor, as well as bus communications issued by the processor when the memory data corresponding to the memory read requests is executed in the processor, and identify the extended node corresponding to the bus communications. Use the address of the memory data and the extended node as training data to train the first neural network model.

5. The method according to claim 4, characterized in that, Also includes: In response to a memory read request issued by the processor, the first neural network analyzes whether the memory data at the memory address corresponding to the memory read request will access the corresponding extended node when the processor executes the memory read request. as well as In response to the memory access to the corresponding extended node when the memory data corresponding to the memory address is executed in the processor, and the extended node is in a closed state, the extended node is turned on.

6. The method according to claim 1, characterized in that, Also includes: Obtain the memory addresses of all cached memory data in the processor cache, and train the second neural network model based on the memory addresses of the cached memory data and the bus communication requests for memory access extension nodes issued by the processor when caching the memory data. The memory address corresponding to the memory data in the processor cache is obtained in real time, and the memory address is input into the second neural network model. The second neural network model is then used to determine whether to close the corresponding extended node.

7. A processor low-power control system, characterized in that, include: The data processing module is configured to construct a mapping relationship or model based on the association between the corresponding memory data in memory and the working state of the extended node during execution. The extended node refers to a functional module in the processor other than the core computing unit, which is used to connect to other peripherals or other devices on the computer. A status arbitration module is configured to determine the working state of the extended node based on the mapping relationship or model and memory data read by the processor. The data processing module is also configured to: monitor memory read requests issued by the processor and record the memory address of the memory data corresponding to the memory read request in memory; monitor the bus communication data between the processor and the expansion node, and determine whether the processor issues an access request to the expansion node after the memory data corresponding to the read request is loaded into the processor based on the bus communication. In response to the processor issuing an access request to the corresponding extension node, a mapping relationship or model is established between the memory address and the extension node.

8. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-6.

9. A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1-6.

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