Method for verifying the setting of the print level of print information in a verification environment and verification method

Abstract

The application provides a setting method and a verification method for verifying the print level of print information in a verification environment, wherein the verification method comprises: obtaining a verification case; obtaining a configuration file, the configuration file describing the print level of at least one print label in the verification environment; configuring the verification process to not output print information and / or not parse the configuration file; executing verification using the verification case; when an error occurs in the verification, configuring the verification process to be able to output print information and parse the configuration file, and executing the verification again using the verification case; in the verification process, parsing the configuration file, setting the print level of the print label of the print information in the verification environment according to the configuration file, and outputting print information matching the print level threshold according to the set print level. The application can realize the rapid setting of the print level of the print information, and improve the efficiency of the verification process due to the repeatable adaptability of the configuration file.

Description

Technical Field

[0001] This application relates to the field of verification technology, and in particular to a method and apparatus for setting the print level of print information in a verification environment, as well as a verification method and apparatus. Background Technology

[0002] In the chip circuit development process, circuit design tools are typically used, such as Electronic Design Automation (EDA) tools. After the initial development of the chip circuit is completed, simulation tools are used to simulate the chip circuit, that is, to simulate the actual function of the chip. Then, a verification platform, such as a verification platform based on Universal Verification Methodology (UVM), is used to test and verify the expected function of the simulated chip circuit, in order to debug and optimize the chip design.

[0003] When using a verification platform to simulate and verify chip circuits, a verification environment is set up. Verification test cases are loaded into the verification environment to test and verify the running process of the chip circuit simulation. In order to display the verification process and facilitate developers to debug the designed chip circuit when problems are found, there will be a lot of printed information in the program code of the verification environment.

[0004] If all the print information is printed during the verification process, the resulting simulation log will be very large due to the sheer volume of print information. This will lead to two problems: firstly, the output of the print information will affect the verification progress due to the large volume of print information; secondly, the generated simulation log will be too large and the information will be too redundant, which will be detrimental to the debugging process for developers.

[0005] To address the aforementioned issues, a print level can be set for each print message in the verification environment, corresponding to the print label. During the verification process of chip circuit simulation, only print messages that meet the print level threshold requirements (generally referring to those below a set threshold) can be output. For example, in the UVM verification platform, for UVM_INFO type print messages, the print levels, from low to high, can include UVM_NONE, UVM_LOW, UVM_MEDIUM, UVM_HIGH, UVM_FULL, and UVM_DEBUG. When setting the print level, critical print messages can be set to a low level, while relatively optional print messages can be set to a high level, ensuring that critical print messages are output.

[0006] Currently, the print level settings for the aforementioned print information are added by developers within the program code corresponding to the established verification environment. If multiple print levels need to be set, this code becomes highly redundant, and the setting process also reduces the efficiency of the verification process. Furthermore, when using different verification test cases, the set print levels need to be readjusted accordingly. This means that if a problem occurs during a chip circuit simulation verification, and the chip circuit is debugged and then re-simulated for verification, the corresponding print levels must be reset if one or more verification test cases need to be reused, which also reduces the efficiency of the verification process.

[0007] Therefore, in this context, how to quickly set the print level corresponding to the print information in the verification environment in order to improve the efficiency of chip circuit simulation verification is a technical problem that needs to be solved. Summary of the Invention

[0008] In view of the above-mentioned problems of the prior art, this application provides a method for setting the printing level of printing information in a verification environment, a verification method, and a corresponding device, which can improve the efficiency of chip circuit simulation verification.

[0009] To achieve the above objectives, the first aspect of this application provides a method for setting the print level of print information in a verification environment, comprising: obtaining a configuration file describing the print level of at least one print label in the verification environment; parsing the configuration file and setting the print level for the print label of print information in the verification environment according to the configuration file.

[0010] As described above, the print level of print labels in the verification environment can be set via configuration files. This simplifies the verification environment code and loosely couples the verification process code with the configuration file, eliminating the need to write code related to print level settings during verification. This simplifies the process of setting print levels for print information and enables rapid setting of print levels, improving the efficiency of chip circuit simulation verification. Furthermore, the reusability of the configuration file makes setting the print level of print labels even easier, eliminating the need to manually add code repeatedly, thus improving the efficiency of the verification process.

[0011] A second aspect of this application provides a verification method, comprising: acquiring verification test cases; acquiring a configuration file describing the printing level of at least one printed label in a verification environment; configuring the verification process to output printing information and to parse the configuration file;

[0012] Optionally, if the print level of the print label is not specified in the configuration file, then it is not necessary to configure the print level of the print label in the configuration file.

[0013] The verification test case is used to perform the verification; during the verification process, the configuration file is parsed, the printing level is set for the printing labels of the printing information in the verification environment according to the configuration file, and the printing information matching the printing level threshold is output according to the set printing level.

[0014] As described above, print levels for different print labels on different components in the verification environment can be set via configuration files. This simplifies the verification environment code and loosely couples the verification process code with the configuration file, eliminating the need to write code related to print level settings during verification. This simplifies the process of setting print levels for print information during verification. By retrieving the configuration file to set print levels, rapid setting of print information print levels is achieved, improving the efficiency of chip circuit simulation verification. Furthermore, the reusability of the configuration file makes setting print levels for print labels even easier, eliminating the need for repeated manual code additions and further enhancing the efficiency of the verification process.

[0015] A third aspect of this application provides a verification method, comprising: obtaining verification test cases; obtaining a configuration file describing the print level of print labels in a verification environment, wherein if no print level exists for print labels, no configuration is required; configuring the verification process to not output print information and / or not parse the configuration file; performing verification using the verification test cases, wherein when an error occurs during verification, the verification process is configured to output print information and parse the configuration file, and the verification test cases are used to perform verification again; parsing the configuration file during the re-execution of verification, setting the print level for print labels in the verification environment according to the configuration file, and outputting print information matching a print level threshold according to the set print level.

[0016] As described above, the print level of print labels in the verification environment can be set via configuration files. This simplifies the verification environment code and loosely couples the verification process code with the configuration file, eliminating the need to write code related to level settings during verification. This simplifies the process of setting print levels for print information during verification and allows for rapid setting of print levels by accessing the configuration file, thus improving the efficiency of chip circuit simulation verification. Furthermore, the reusability of the configuration file makes setting the print level of print labels even easier, eliminating the need for repeated manual code additions and further improving verification efficiency. On the other hand, during the initial verification process, printing information can be disabled and the print level not set. If a verification test case fails during verification, that test case can be reused, and the print level of the print label can be set accordingly to print information. This way, print information is only output when verification fails, which can shorten the overall verification time and improve the efficiency of the verification process.

[0017] As a possible implementation of the second or third aspect, obtaining the configuration file includes: obtaining the configuration file associated with the verification test case according to the verification test case.

[0018] The above establishes the association between verification test cases and configuration files, allowing for flexible configuration file settings for each test case. Furthermore, as an optional implementation, multiple configuration files can be associated with the same verification test case, further enhancing the flexibility of configuration file usage. When multiple associated configuration files contain duplicate print levels for print labels, the print level for that label can be determined according to preset rules. These preset rules can be one of the following: using the highest print level, using the lowest print level, or having a priority setting in the configuration file itself, with the setting in the higher-priority configuration file taking precedence.

[0019] As one possible implementation of the first, second, or third aspect, the configuration file describes the following: at least one component, at least one print label included in the component, and the print grade of the print label.

[0020] The printing levels are set according to the hierarchy from components to printed labels, resulting in a clear structure.

[0021] A fourth aspect of this application provides an apparatus for setting the print level of print information in a verification environment, comprising: a first acquisition unit for acquiring a configuration file describing the print level of at least one print label in the verification environment; and a first setting unit for parsing the configuration file and setting the print level for the print label of print information in the verification environment according to the configuration file.

[0022] A fifth aspect of this application provides a verification apparatus, comprising: a second acquisition unit for acquiring verification test cases; the second acquisition unit is further configured to acquire a configuration file describing the print level of at least one print label in a verification environment; a first configuration unit for configuring the verification process to output print information and to parse the configuration file; a first execution unit for performing verification using the verification test cases; a second setting unit for parsing the configuration file and setting the print level of the print label in the verification environment according to the configuration file during the verification execution process; and a first output unit for outputting print information matching a print level threshold according to the set print level.

[0023] A sixth aspect of this application provides a verification apparatus, comprising: a third acquisition unit for acquiring verification test cases; the third acquisition unit is further configured to acquire a configuration file describing the print level of at least one print label in a verification environment; a second configuration unit for configuring the verification process to not output print information and / or not parse the configuration file; the second configuration unit is further configured to configure the verification process to output print information and parse the configuration file when an error occurs during verification using the verification test cases;

[0024] The second execution unit is used to perform verification using the verification test case, and to perform verification again using the verification test case; the third setting unit is used to parse the configuration file during the re-execution of verification, and set the printing level for the printing label of the printing information in the verification environment according to the configuration file; the second output unit is used to output the printing information matching the printing level threshold according to the set printing level.

[0025] A seventh aspect of this application provides a computing device, including: a communication interface and at least one processor; wherein the at least one processor is configured to execute program instructions, which, when executed by the at least one processor, cause the computing device to implement any of the methods described in the first to third aspects above.

[0026] An eighth aspect of this application provides a computer-readable storage medium having program instructions stored thereon, which, when executed by a computer, cause the computer to perform any of the methods described in the first to third aspects above. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a verification environment provided in an embodiment of this application;

[0028] Figure 2a This is a flowchart of an embodiment of the method for setting the print level of print information in the verification environment provided in this application;

[0029] Figure 2b This is a flowchart of the first embodiment of the verification method provided in this application;

[0030] Figure 2c This is a flowchart of the second embodiment of the verification method provided in this application;

[0031] Figure 3a This is a flowchart of the third embodiment of the verification method provided in this application;

[0032] Figure 3b This is a schematic diagram illustrating the contents of the configuration file provided in this application embodiment;

[0033] Figure 4a This is a schematic diagram of an embodiment of the device for setting the print level of print information in the verification environment provided in this application;

[0034] Figure 4b This is a schematic diagram of the first embodiment of the verification device provided in this application;

[0035] Figure 4c This is a schematic diagram of a second embodiment of the verification device provided in this application;

[0036] Figure 5 This is a schematic structural diagram of a computing device provided in an embodiment of this application.

[0037] It should be understood that the dimensions and shapes of the blocks in the above structural diagrams are for reference only and should not constitute an exclusive interpretation of the embodiments of the present invention. The relative positions and inclusion relationships between the blocks presented in the structural diagrams are only schematic representations of the structural relationships between the blocks, and are not intended to limit the physical connection methods of the embodiments of the present invention. Detailed Implementation

[0038] The technical solutions provided in this application will be further described below with reference to the accompanying drawings and embodiments. It should be understood that the system architecture and business scenarios provided in the embodiments of this application are mainly for illustrating possible implementations of the technical solutions of this application and should not be construed as the sole limitation on the technical solutions of this application. Those skilled in the art will recognize that the technical solutions provided in this application are equally applicable to similar technical problems as system architectures evolve and new business scenarios emerge.

[0039] It should be understood that the embodiments of this application provide a method and apparatus for setting the print level of print information in a verification environment, a verification method and apparatus, a computing device, and a computer storage medium. Since these technical solutions solve problems in the same or similar way, some repeated parts may not be described again in the following description of specific embodiments, but it should be regarded as that these specific embodiments have references to each other and can be combined with each other.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In case of any inconsistency, the meaning set forth in this specification or derived from the content described herein shall prevail. Furthermore, the terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application. To accurately describe the technical content of this application and to accurately understand the invention, the following explanations or definitions of the terms used in this specification are provided before describing specific embodiments:

[0041] 1) Universal Verification Methodology (UVM): UVM is a standard for developing verification environments from the module level to the system level. Based on UVM, reusable verification components can be developed.

[0042] 2) Verification Environment: A test environment / test platform built to verify the Device Under Test (DUT). The verification environment includes multiple components that implement different functions. Each component corresponds to a code module that implements the corresponding function. Multiple components form a component library for use, thereby improving code reusability. The DUT can be a real physical chip or a simulation of the chip circuit.

[0043] like Figure 1 An embodiment of a verification environment is shown, in which the basic components include a driver, a monitor, and a checker. Other embodiments may also include additional components. A brief description of the above components is as follows:

[0044] Driver: This component's function includes generating data or signals to be sent to the DUT port according to a series of instructions for the verification test case.

[0045] Monitor: This component's functions include observing the DUT's output data or internal signals. For example, for system signals such as clocks, it can monitor frequency changes; for bus signals, it can monitor the bus's transmission type and data content.

[0046] Comparator (checker): This component's function includes caching the DUT output data collected from various monitors and checking whether the collected DUT output data matches the expected data through data comparison.

[0047] 3) Printed Information: During DUT verification, various components within the verification environment can generate relevant printed information. This information includes, for example, information received / monitored by a component during verification, information generated / outputted, the analyzed DUT's operational information, notes or explanatory information for a verification step, and prompts / warnings. Each printed piece of information can be distinguished using a printed label. This printed information can be displayed to developers for debugging the DUT.

[0048] 4) Macros, also known as macro definitions, macro substitutions, or macro replacements. Generally speaking, a macro is a rule or pattern, or syntax substitution. When the interpreter or compiler encounters a macro, it automatically performs the corresponding substitution to pass parameters. When defining a macro, member parameters (i.e., the parameters to be replaced) and member functions (i.e., the operations performed by the macro, the functions it implements) can be defined.

[0049] In this application, a configuration file is defined, which describes the printing level of each printed label for each component. During simulation verification, the verification program acquires and parses this configuration file, sets the printing level of the printed information in the verification environment according to the configuration file, and then outputs printed information matching the preset printing level threshold based on the set printing level during the verification process. This application's configuration file approach avoids the situation mentioned in the background art where developers have to add corresponding code for each verification process. Furthermore, the reusability of the configuration file makes setting the printing level of each printed information more convenient, eliminating repetitive settings and thus enabling rapid setting of the printing level of printed information, improving the efficiency of chip circuit simulation verification.

[0050] The present application will now be described in detail with reference to specific embodiments.

[0051] This application provides an embodiment of a method for setting the print level of print information in a verification environment. This embodiment can be applied to a verification environment, as shown in the example below. Figure 2a The flowchart shown illustrates the method, which includes the following steps:

[0052] S11: Obtain the configuration file, which describes the print level of at least one print label in the verification environment.

[0053] In some embodiments, the configuration file can be predefined before the verification process is executed, for example... Figure 3b An example of the content defined in a configuration file is shown. In this example, the configuration file may contain fields such as: component, print labels contained within the component, and print level. Here, "component" refers to a component in the verification environment, and the field corresponds to the name of the component in this embodiment. The component can be, for example,... Figure 1 The components shown, such as drivers, detectors, and comparators, can also be Figure 1 Other components not shown. The print label serves as an identifier for the printed information.

[0054] In some embodiments, different types of print messages can be configured with different print levels. For example, for print messages of type UVM_INFO, the print levels from low to high can include UVM_NONE, UVM_LOW, UVM_MEDIUM, UVM_HIGH, UVM_FULL, and UVM_DEBUG.

[0055] In some embodiments, the configuration file may be loaded into the verification environment based on user actions, or the verification environment may read and load the configuration file from a specified directory.

[0056] S12: Parse the configuration file and set the print level for the print labels of the print information in the verification environment according to the configuration file.

[0057] In some embodiments, macros can be defined to parse configuration files and set print levels.

[0058] As described above, the printing level of the print information labels in the verification environment can be set through configuration files, which makes the verification environment code concise and loosely coupled with the configuration file. It eliminates the need to write code related to the level setting during the verification process, simplifies the process of setting the printing level of the print information in the verification process, enables the rapid setting of the printing level of the print information, and improves the efficiency of chip circuit simulation verification.

[0059] This application also provides a first embodiment of a verification method, which can be applied to a verification environment, as shown in the example below. Figure 2b The flowchart shown illustrates that the method includes the following steps:

[0060] S21: Obtain verification test cases.

[0061] In some embodiments, the verification test cases to be used can be loaded into the verification environment based on user actions. Alternatively, the verification environment can automatically read the verification test cases from a specified directory.

[0062] S22: Obtain a configuration file that describes the print level of at least one print label in the verification environment.

[0063] In some embodiments, the configuration file can be predefined before the verification process is executed, as described in step S11 above, and will not be repeated here.

[0064] In some embodiments, when the configuration file is predefined, it can be associated with the verification test cases to be used. In some embodiments, this association can be established in one of the following ways:

[0065] Method 1: Record the file identifier of the configuration file in the information of the verification test case. For example, the file identifier can be a filename. Therefore, when obtaining the configuration file, it is based on the file identifier of the configuration file recorded in the verification test case used.

[0066] Method 2: A separate file can be used to record the association between the two, for example, recording the file identifier of the configuration file and the identifier of the associated verification test case. Therefore, when retrieving the configuration file, this separate file is used to determine the file identifier of the configuration file associated with the verification test case, and then the configuration file is retrieved based on that file identifier.

[0067] Method 3: Store the configuration file and associated verification test cases in the same folder to indicate a relationship between them. Therefore, when retrieving the configuration file, it can be obtained from the same directory as the verification test cases.

[0068] In some embodiments, the same verification test case can be associated with multiple configuration files; that is, this step can obtain multiple configuration files associated with the verification test case. In some embodiments, when the print labels in these multiple configuration files have duplicate print levels configured, for example, the first configuration file and the second configuration file both describe the print level for the same print label, the print level of the print label can be determined according to a preset rule. The preset rule can be one of the following: using the highest print level, or using the lowest print level; or the configuration files themselves have a priority setting, and the setting in the configuration file with the higher priority is used.

[0069] S23: The configuration verification process can output printable information and can parse the configuration file.

[0070] In some embodiments, this step can be configured by defining macros in the verification command.

[0071] S24: Perform verification using the verification case.

[0072] This step involves performing verification on the DUT using verification test cases. In some embodiments, the DUT can be a simulation, such as a simulation of a chip circuit. In other embodiments, the DUT can also be a physical device, such as a chip.

[0073] S25: During the verification process, the configuration file is parsed, the printing level is set for the printing labels of the printing information in the verification environment according to the configuration file, and the printing information matching the printing level threshold is output according to the set printing level.

[0074] In some embodiments, the macros described above can be used to parse the configuration file and set the print level.

[0075] In some embodiments, when a certain print information needs to be output during the verification process, the set print level is compared with the print level threshold to determine whether to output the print information. If it is not higher than the threshold, the print information is output so that developers can debug and optimize the DUT.

[0076] In some embodiments, different display methods can be used to print information at different printing levels. For example, the display method may include font attributes, such as font size, weight, and color. The display method may also include the amount of space provided for displaying the print information, for example, the lower the level, the larger the display space.

[0077] This application also provides a second embodiment of the verification method, which can be applied to a verification environment, as shown in the example below. Figure 2c The flowchart shown illustrates that the method includes the following steps:

[0078] S31: Obtain verification test cases.

[0079] The optional implementation methods for this step can be found in the description of step S21 above, and will not be repeated here.

[0080] S32: Obtain a configuration file that describes the print level of at least one print label in the verification environment.

[0081] The optional implementation methods for this step can be found in the description of step S22 above, and will not be repeated here.

[0082] S33: The configuration verification process is configured to not output any print information and / or not parse the configuration file.

[0083] In some embodiments, this step can be the default step.

[0084] In some embodiments, the decision to parse the configuration file is made by checking whether macros are defined in the verification command. During the verification process, if it is determined that the verification test case is being used for the first time, macros are not defined by default, thus preventing the configuration file from being parsed and the print level from being set. Conversely, when it is determined that the verification test case is being used for the first time, no print information is output by default.

[0085] S34: Perform verification using the verification case. When an error occurs during verification, configure the verification process to output printable information and parse the configuration file, and then perform verification again using the verification case.

[0086] In some embodiments, when verification is performed again, the macros defined above can be used to parse the configuration file and set the print level.

[0087] S35: During the re-execution of the verification process, the configuration file is parsed, the printing level is set for the printing labels of the printing information in the verification environment according to the configuration file, and the printing information matching the printing level threshold is output according to the set printing level.

[0088] The optional implementation methods for this step can be found in the description of step S25 above, and will not be repeated here.

[0089] like Figure 3a This is a third embodiment of the verification method provided in this application. In this embodiment, a verification environment based on UVM is used to verify the DUT. In this example, the DUT is a simulation of a chip circuit designed by the developer. Figure 3a As shown, the verification method provided in this embodiment includes steps S110-S180:

[0090] S110: Define a configuration file that describes the print level of the print labels contained in the components of the verification environment involved in the verification test cases to be used.

[0091] The configuration file can be predefined before the verification process is executed, for example... Figure 3b An example of what a configuration file defines is shown. In this example, the configuration file may contain fields such as: component, print labels contained in the component, and print level.

[0092] Figure 3b In the example shown, the definition information for different print labels is set using line breaks, for example, as Figure 3b The content shown includes a line of configuration information in the configuration file that defines the print level of the print label `send_item_base` in the component `env.sc_mac_mdl` as `UVM_HIGH`. In some embodiments, the definition information of each print label can also be distinguished by an identifier.

[0093] When defining this configuration file, you can associate it with the verification test cases to be used. This can be done in the following ways:

[0094] For example, the file identifier of the configuration file (which may be a file name) is recorded in the information of the verification test case.

[0095] For example, the association between the two can be recorded in a separate file, such as the file identifier of the configuration file and the identifier of the associated verification test case.

[0096] For example, storing the configuration file and the associated verification test cases in the same folder indicates that they are related.

[0097] In some embodiments, the same verification use case can be associated with multiple configuration files. When the print labels in the associated multiple configuration files have duplicate print levels, the print level of the print label can be determined according to a preset rule. The preset rule can be one of the following: the highest print level or the lowest print level; or the configuration file itself has a priority setting, and the setting in the configuration file with the higher priority is used.

[0098] S120: Obtain verification test cases from the verification environment.

[0099] This can be achieved by loading the required verification cases into the verification environment based on user actions, or by having the verification environment automatically read the verification cases from a specified directory.

[0100] S130: Obtain the defined configuration file from the verification environment.

[0101] This could involve reading the configuration file associated with the verification test case.

[0102] Refer to the description in step S110. Depending on the association method used, read the data in the corresponding way. For example, read the data based on the file identifier of one or more configuration files recorded in the verification test case, or read the data based on the file identifier of one or more configuration files associated with the independent file, or read one or more configuration files in the same folder as the verification test case.

[0103] When a verification test case has multiple configuration files, and the print labels in these configuration files have duplicate print levels, the print level configuration to be used for the print label is determined according to the preset rules described in step S110.

[0104] S140: The configuration verification process does not output print information or parse the configuration file.

[0105] The configuration for this step can be the default configuration.

[0106] In this example, the decision to parse the configuration file is made by checking whether the macro "PRINT_CFG_FILE" is defined in the verification command. During the verification process, if it is determined that the verification test case is being used for the first time, the macro "PRINT_CFG_FILE" is not defined by default, thus the configuration file is not parsed and the print level is not set. On the other hand, when it is determined that the verification test case is being used for the first time, no print information is output by default.

[0107] The macro "PRINT_CFG_FILE" defined in this example parses the configuration file and sets the print level of the corresponding print label in each component of the verification environment according to the print level corresponding to the print label in the configuration file.

[0108] Specifically, a counter can be set in the verification environment to determine whether a verification test case is being used for the first time. When the counter is 0 or the initial value, it indicates a first use, and the code section defining the macro is skipped (i.e., the macro is not defined), and the print function is set to 0 to indicate that no print information is output. When the counter value changes, indicating a re-verification process using the verification test case, the code section defining the macro is executed, and the print function is set to 1 to indicate that print information is output.

[0109] S150: The verification environment uses the verification test case to perform verification on the DUT. If an error is found during verification, proceed to the next step; otherwise, end the current simulation verification.

[0110] Errors occurred during the verification process, such as the collected DUT output data not matching the expected data, or the verification process freezing.

[0111] After the simulation verification ends, you can return to step S120 to obtain the next verification case and continue to verify the DUT using the next verification case.

[0112] S160: Execute the re-verification process of the verification test case, and set the verification process output print information and set it to parse the configuration file.

[0113] In this example, the macro "PRINT_CFG_FILE" is defined in the verification command, as described in step S140, and will not be repeated here.

[0114] S170: During the process of re-executing the DUT verification, the configuration file is parsed through the macro "PRINT_CFG_FILE", and the print level is set for the print labels of each component in the verification environment according to the information in the configuration file, which means that the print level is set for each print information.

[0115] S180: Based on the set print level, output print information that matches the print level threshold during the re-execution of verification.

[0116] Specifically, when a certain print information needs to be output during the verification process, the system compares the set print level with the print level threshold to determine whether to output the print information. If the print information is not higher than the threshold, it will be output to facilitate debugging and optimization of the DUT by the developers.

[0117] In addition, different display methods can be set for printing information at different printing levels. For example, the display method can include font attributes, such as font size, weight, and color. The display method can also include the amount of space provided for the printing information to be displayed. For example, the lower the level, the larger the display space.

[0118] This application also provides embodiments of a device for setting the print level of print information in a verification environment and embodiments of a verification device. For the beneficial effects of these devices or the technical problems they solve, please refer to the descriptions in the methods corresponding to each device, which will not be repeated here.

[0119] This application provides an embodiment of a device for setting print levels of print information in a verification environment, such as... Figure 4a As shown, the device includes:

[0120] The first acquisition unit 11 is used to acquire a configuration file describing the print level of at least one print label in the verification environment. This unit is specifically used to implement step S11 and its optional embodiments described above.

[0121] The first setting unit 12 is used to parse the configuration file and set the print level for the print labels of the print information in the verification environment according to the configuration file. This unit is specifically used to implement the above step S12 and its optional embodiments.

[0122] This application provides a first embodiment of a verification device, such as... Figure 4b As shown, the verification device includes:

[0123] The second acquisition unit 21 is used to acquire verification test cases. This unit is specifically used to implement the above step S21 and its optional embodiments.

[0124] The second acquisition unit 21 is further configured to acquire a configuration file describing the print level of at least one print label in the verification environment. Specifically, this unit is also configured to implement step S22 and its optional embodiments described above.

[0125] The first configuration unit 22 is used to configure the verification process to output printable information and to parse the configuration file. This unit is specifically used to implement step S23 and its optional embodiments.

[0126] The first execution unit 23 is used to perform verification using the verification test case. This unit is specifically used to implement step S24 and its optional embodiments.

[0127] The second setting unit 24 is used to parse the configuration file during the verification process and set the print level for the print labels of the print information in the verification environment according to the configuration file. This unit is specifically used to implement some embodiments of step S25 above.

[0128] The first output unit 25 is used to output printing information that matches the set printing level threshold. This unit is specifically used to implement some embodiments of step S25 above.

[0129] This application provides a second embodiment of a verification device, such as... Figure 4c As shown, the verification device includes:

[0130] The third acquisition unit 31 is used to acquire verification test cases. This unit is specifically used to implement the above step S31 and its optional embodiments.

[0131] The third acquisition unit 31 is further configured to acquire a configuration file describing the print level of at least one printed label in the verification environment. Specifically, this unit is also configured to implement step S32 and its optional embodiments.

[0132] The second configuration unit 32 is used to configure the verification process to not output printed information and / or not parse the configuration file. This unit is specifically used to implement the above step S33 and its optional embodiments.

[0133] The second configuration unit 32 is further configured to configure the verification process to output printable information and parse the configuration file when an error occurs during verification using the verification test case. Specifically, this unit is also used to implement the above step S34 and its optional embodiments.

[0134] The second execution unit 33 is used to perform verification using the verification test case, and to perform verification again using the verification test case.

[0135] The third setting unit 34 is used to parse the configuration file during the re-execution of the verification process and set the print level for the print labels of the print information in the verification environment according to the configuration file. This unit is specifically used to implement some embodiments of step S35 above.

[0136] The second output unit 35 is used to output printing information that matches the set printing level threshold. This unit is specifically used to implement some embodiments of step S35 above.

[0137] Figure 5 This is a schematic structural diagram of a computing device 900 provided in an embodiment of this application. This computing device can serve as a device for outputting printed information in simulation verification, or as a simulation verification device, executing various optional embodiments of the above-mentioned simulation verification methods for outputting printed information or simulation verification. The computing device can be a terminal, or a chip or chip system within the terminal. Figure 5 As shown, the computing device 900 includes: a processor 910, a memory 920, and a communication interface 930.

[0138] It should be understood that Figure 5 The communication interface 930 in the computing device 900 shown can be used to communicate with other devices, and may specifically include one or more transceiver circuits or interface circuits.

[0139] The processor 910 can be connected to the memory 920. The memory 920 can be used to store the program code and data. Therefore, the memory 920 can be a storage unit inside the processor 910, an external storage unit independent of the processor 910, or a component that includes both the storage unit inside the processor 910 and the external storage unit independent of the processor 910.

[0140] Optionally, the computing device 900 may also include a bus. The memory 920 and communication interface 930 can be connected to the processor 910 via the bus. The bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 The symbol is represented by a line without an arrow, but this does not mean that there is only one bus or one type of bus.

[0141] It should be understood that in the embodiments of this application, the processor 910 may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor. Alternatively, the processor 910 may employ one or more integrated circuits to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0142] The memory 920 may include read-only memory and random access memory, and provides instructions and data to the processor 910. A portion of the processor 910 may also include non-volatile random access memory. For example, the processor 910 may also store device type information.

[0143] When the computing device 900 is running, the processor 910 executes computer execution instructions stored in the memory 920 to perform any of the operational steps of the above method and any of the optional embodiments thereof.

[0144] It should be understood that the computing device 900 according to the embodiments of this application can correspond to the corresponding subject in executing the methods according to the various embodiments of this application, and the above and other operations and / or functions of each module in the computing device 900 are respectively for implementing the corresponding processes of the methods of this embodiment. For the sake of brevity, they will not be described in detail here.

[0145] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. For example, the apparatuses described in the above embodiments, or the units or modules included in each apparatus, can be implemented through processes or software modules, where the software modules can be units obtained by functional logic decomposition. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0146] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0147] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0148] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0149] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0150] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is used to perform the above-described method, which includes at least one of the schemes described in the above embodiments.

[0151] The computer storage medium in this application embodiment can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0152] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0153] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including, but not limited to, wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0154] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0155] Furthermore, the terms "first, second, third, etc." or similar terms such as module A, module B, and module C used in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that, where permissible, a specific order or sequence may be interchanged so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0156] In the above description, the labels of the steps involved, such as S110, S120, etc., do not mean that the steps will necessarily be executed. The order of the steps can be interchanged or executed simultaneously if permitted.

[0157] The term "comprising" as used in the specification and claims should not be construed as limiting itself to what follows; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the mentioned feature, integral, step, or component, but does not exclude the presence or addition of one or more other features, integrals, steps, or components, or groups thereof. Thus, the statement "device comprising means A and B" should not be limited to a device consisting solely of components A and B.

[0158] The terms "an embodiment" or "an embodiment" as used in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in at least one embodiment of this application. Therefore, the terms "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics can be combined in any suitable manner, as will be apparent to those skilled in the art from this disclosure.

[0159] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, all of which fall within the scope of protection of this application.

Claims

1. A setting method of verifying a print level of print information in an environment, characterized by, Applications include chip circuit simulation and verification environments, including: Obtain a configuration file that describes the print level of at least one print label in the verification environment; the configuration file describes at least one component, at least one print label included in the component, and the print level of the print label; Parse the configuration file and set the print level for the print labels of the print information in the verification environment according to the configuration file; The configuration file and print levels are parsed and set by defining macros. During the verification process, if it is determined that the verification test case is being used for the first time, no macros will be defined, so that the configuration file will not be parsed, the print level will not be set, and no print information will be output.

2. A method of verification, characterized by, Applications include chip circuit simulation and verification environments, including: Obtain verification test cases; Obtain a configuration file that describes the print level of at least one print label in the verification environment; the configuration file describes at least one component, at least one print label included in the component, and the print level of the print label; The configuration verification process is designed to output printable information and parse the configuration file. Perform the verification using the aforementioned verification test case; During the verification process, the configuration file is parsed, and the printing level is set for the printing labels of the printing information in the verification environment according to the configuration file. The printing information matching the printing level threshold is also output according to the set printing level. The configuration file and print levels are parsed and set by defining macros. During the verification process, if it is determined that the verification test case is being used for the first time, then no macros are defined, so that the configuration file is not parsed, the print level is not set, and no print information is output.

3. The method of claim 2, wherein, The step of obtaining the configuration file includes: obtaining the configuration file associated with the verification test case based on the verification test case.

4. A method of verification, characterized by, Applications include chip circuit simulation and verification environments, including: Obtain verification test cases; Obtain a configuration file that describes the print level of at least one print label in the verification environment; the configuration file describes at least one component, at least one print label included in the component, and the print level of the print label; The configuration verification process is configured to not output any print information and / or not parse the configuration file; The verification is performed using the verification test case. When an error occurs during verification, the verification process is configured to output print information and parse the configuration file, and the verification is performed again using the verification test case. During the re-execution of the verification process, the configuration file is parsed, the print level is set for the print labels of the print information in the verification environment according to the configuration file, and the print information matching the print level threshold is output according to the set print level.

5. The method of claim 4, wherein, The step of obtaining the configuration file includes: obtaining the configuration file associated with the verification test case based on the verification test case.

6. An apparatus for verifying a setting of a print level of print information in an environment, characterized by, Applications include chip circuit simulation and verification environments, including: The first acquisition unit is used to acquire a configuration file, which describes the printing level of at least one print label in the verification environment; the configuration file describes the following: at least one component, at least one print label included in the component, and the printing level of the print label; The first setting unit is used to parse the configuration file and set the printing level for the printing label of the printing information in the verification environment according to the configuration file. The configuration file and print levels are parsed and set by defining macros. During the verification process, if it is determined that the verification test case is being used for the first time, no macros will be defined, so that the configuration file will not be parsed, the print level will not be set, and no print information will be output.

7. A verification device, characterized by Applications include chip circuit simulation and verification environments, including: The second acquisition unit is used to acquire verification test cases; The second acquisition unit is further configured to acquire a configuration file, which describes the printing level of at least one printed label in the verification environment; the configuration file describes the following: at least one component, at least one printed label included in the component, and the printing level of the printed label; The first configuration unit is used to configure the verification process to output printable information and to parse the configuration file; The first execution unit is used to perform verification using the verification test case; The second setting unit is used to parse the configuration file during the verification process and set the printing level for the printing labels of the printing information in the verification environment according to the configuration file. The first output unit is used to output printing information that matches the set printing level threshold according to the set printing level. The configuration file and print levels are parsed and set by defining macros. During the verification process, if it is determined that the verification test case is being used for the first time, then no macros are defined, so that the configuration file is not parsed, the print level is not set, and no print information is output.

8. A verification device, characterized by Applications include chip circuit simulation and verification environments, including: The third acquisition unit is used to acquire verification test cases; The third acquisition unit is also used to acquire a configuration file, which describes the printing level of at least one printed label in the verification environment; the configuration file describes the following: at least one component, at least one printed label included in the component, and the printing level of the printed label; The second configuration unit is used to configure the verification process to not output print information and / or not parse the configuration file; The second configuration unit is further configured to configure the verification process to output printable information and to parse the configuration file when an error occurs during verification using the verification test case; The second execution unit is used to perform verification using the verification test case, and to perform verification again using the verification test case; The third setting unit is used to parse the configuration file during the re-execution of the verification process and set the printing level for the printing labels of the printing information in the verification environment according to the configuration file. The second output unit is used to output printing information that matches the set printing level threshold.

9. A computing device, comprising: include: processor, and A memory having stored program instructions that, when executed by the processor, cause the processor to perform the method of any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that, It stores program instructions that, when executed by a computer, cause the computer to perform the method described in any one of claims 1 to 5.

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