A cache removal method for improving ZNS-SSD write performance
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHONGQING UNIV OF POSTS & TELECOMM
- Filing Date
- 2022-11-10
- Publication Date
- 2026-06-26
AI Technical Summary
When the onboard DRAM space of the ZNS-SSD is full, it leads to longer data write time or low utilization of flash memory chips, affecting write performance. In addition, the sequential write characteristic of a single partition increases the complexity of data removal.
A cache removal strategy that is aware of the flash memory chip's operating status and parallelism is adopted. By establishing a partitioned queue in the onboard DRAM, appropriate I/O request data is selected for removal, and the parallelism of the flash memory chip is used to optimize the data writing process.
It accelerates the data removal process, reduces application blocking time, maintains the high write performance of ZNS-SSD, and also features low cost and good scalability.
Smart Images
Figure CN115658558B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of computer storage technology, specifically relating to a cache removal method for improving the write performance of ZNS-SSD. Background Technology
[0002] Currently, ZNS-SSDs typically incorporate high-performance Dynamic Random Access Memory (DRAM) as onboard DRAM to improve overall read and write performance. The onboard DRAM primarily caches two types of data: partition mapping information and I / O request data. The purpose of caching I / O request data is to balance the speed difference between upper-layer applications and the internal flash memory chips of the ZNS-SSD. Generally, for data to be written to the ZNS-SSD, the upper-layer application only needs to transfer it to the onboard DRAM to consider the write operation complete, without waiting for the data to be actually written to the flash memory chips, thus shortening the I / O request response time.
[0003] When the onboard DRAM space of the ZNS-SSD is full, upper-layer applications will be blocked. New data cannot be put into the onboard DRAM until the data in the onboard DRAM is removed to the flash memory chip. Usually, in order to shorten the blocking time of upper-layer applications, the ZNS-SSD firmware will select a portion of the data, remove it from the onboard DRAM, and write this portion of the data back to the flash memory chip, thereby freeing up space to continue caching data.
[0004] However, during the process of writing data to flash memory chips, chip occupancy often occurs, prolonging the data writing time. Alternatively, the written data may not be able to fully occupy all flash memory chips, resulting in some chips being idle and making it difficult to leverage the parallelism between flash memory chips. In addition, ZNS-SSDs are equipped with ZNS interfaces, and the sequential writing characteristics of individual partitions need to be considered during the data writing process to flash memory chips, which provides new constraints for removing data from onboard DRAM. Summary of the Invention
[0005] To address the aforementioned technical problems, this invention proposes a cache removal method to improve the write performance of ZNS-SSD, comprising:
[0006] S1: Based on the number of partitions in the ZNS-SSD, establish the corresponding number of partition queues in the onboard DRAM;
[0007] S2: Whenever an I / O request arrives, determine the partition to be accessed based on the logical address it accesses, and place the I / O request into the corresponding partition queue;
[0008] S3: If the onboard DRAM is full of I / O request data, execute the cache removal strategy that is aware of the working status of the flash memory chip and select the I / O request data that needs to be removed;
[0009] S4: Determine the amount of I / O request data that needs to be removed based on the parallelism-aware cache removal strategy of the flash memory chip;
[0010] S5: Based on the determined number of I / O request data to be removed, perform the data removal operation of the onboard DRAM.
[0011] Preferably, a cache removal strategy that is aware of the flash memory chip's operating status is implemented, selecting the I / O request data to be removed, specifically including:
[0012] Each partition queue is traversed sequentially. If the flash memory chip corresponding to the partition queue is in an idle state, the I / O request data of the partition queue will be written back to the flash memory chip. Conversely, if the flash memory chip corresponding to the partition queue is in a busy state, the I / O request data of the partition queue will be skipped and cannot be written back to the flash memory chip temporarily. The I / O request data that cannot be written back to the flash memory chip temporarily is the I / O request data that needs to be removed.
[0013] Preferably, based on the flash memory chip parallelism-aware cache removal strategy, the number of I / O request data that needs to be removed is determined, including:
[0014] When the onboard DRAM space is full, the parallelism between flash memory chips is utilized to write the I / O request data that fills the onboard DRAM space back to the flash memory chips in a way that makes it possible to occupy all flash memory chips in each write-back I / O request data, so as to obtain the number of I / O request data that need to be removed.
[0015] Furthermore, the parallelism between the flash memory chips: I / O request data is written to multiple chips simultaneously.
[0016] The beneficial effects of this invention are as follows: This invention addresses the long-term blocking problem caused by the full occupancy of the onboard DRAM in ZNS-SSD by adopting a data removal strategy that is aware of the working status of the flash memory chip and the parallelism between flash memory chips. This accelerates the data removal process, shortens the time when the application is blocked, and thus maintains the high write performance of ZNS-SSD. At the same time, this invention has the advantages of low cost and easy implementation, and has good scalability and practicality. Attached Figure Description
[0017] Figure 1 This is a diagram showing the overall architecture and implementation principle of the present invention;
[0018] Figure 2This is a schematic diagram illustrating the mapping relationship between partitions and flash memory chips in the ZNS-SSD of the present invention;
[0019] Figure 3 This invention provides a cache removal strategy for flash memory chip operating status awareness.
[0020] Figure 4 This invention provides a parallelism-aware cache removal strategy for flash memory chips.
[0021] Figure 5 This is a flowchart of the cache management method of the present invention. Detailed Implementation
[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0023] A cache removal method to improve ZNS-SSD write performance, such as Figure 1 As shown, it includes:
[0024] S1: Based on the number of partitions in the ZNS-SSD, establish the corresponding number of partition queues in the onboard DRAM;
[0025] S2: Whenever an I / O request arrives, determine the partition to be accessed based on the logical address it accesses, and place the I / O request into the corresponding partition queue;
[0026] S3: If the onboard DRAM is full of I / O request data, execute the cache removal strategy that is aware of the working status of the flash memory chip and select the I / O request data that needs to be removed;
[0027] S4: Determine the amount of I / O request data that needs to be removed based on the parallelism-aware cache removal strategy of the flash memory chip;
[0028] S5: Based on the determined number of I / O request data to be removed, perform a data removal operation on the onboard DRAM and write the determined I / O request data to be removed into the flash memory chip.
[0029] The NVMe protocol establishes request queues for applications in host memory, including a Submission Queue (SQ) and a Completion Queue (CQ). I / O requests in these queues are sent to the ZNS-SSD device via the PCIe interface. Internally, each I / O request is placed into its corresponding partition based on its logical address. I / O request 1 needs to write data to partition 1, so it will be placed in the partition 1 queue; similarly, I / O requests 2 and 3 will be placed in the partition 2 and partition 3 queues, respectively. The Zone FTL's cache management module schedules these I / O requests to achieve data persistence. Furthermore, given the sequential write characteristics of the ZNS-SSD within its partitions, requests in each partition queue must be written back to the flash memory chip in a first-in, first-out (FIFO) manner.
[0030] like Figure 2 As shown, within the ZNS-SSD, to leverage the chip-level parallelism of flash memory, a partition is mapped to portions of flash memory blocks across multiple flash memory chips. Partition 1 is mapped to Blocks 1, 2, ..., 3N of chips 1 and 2; partition 2 is mapped to Blocks N+1, N+2, ..., 2N of chips 1 and 2. When data is written back from the onboard DRAM to the flash memory chips, if all selected I / O requests are for partitions 1 and 2, chips 1 and 2 will remain active, while chips 3 and 4 will be idle. This results in low utilization of flash memory chip resources, severely impacting data write performance.
[0031] like Figure 3 As shown, by sensing the operating status of the flash memory chip, the I / O request data that needs to be written back from the onboard DRAM is selected. When the onboard DRAM is full, each partition queue is traversed sequentially. If the flash memory chip corresponding to the partition queue is in an idle state, the I / O request data for that partition queue will be written back to the flash memory chip. Conversely, if the flash memory chip corresponding to the partition queue is in a busy state (these chips may be occupied by other I / O requests or are currently reading data), the I / O request data for that partition queue will be skipped and cannot be written back to the flash memory chip temporarily. The I / O request data that cannot be written back to the flash memory chip temporarily is the I / O request data that needs to be removed.
[0032] like Figure 4As shown, by sensing the parallelism of flash memory chips, the amount of I / O request data that needs to be written back to the onboard DRAM is determined. Since when the onboard DRAM space is full, I / O requests sent by upper-layer applications must wait for some data to be written back before new data can be written to the cache. To shorten the blocking time of upper-layer applications and fully utilize the parallelism between flash memory chips, the number of I / O requests to write back to the flash memory chip each time is determined. Based on the principle that each I / O request data should occupy as many flash memory chips as possible, the number of I / O request data written back to the flash memory chip when the onboard DRAM space is full is the determined number of I / O requests to write back to the flash memory chip each time. The basic idea is that each I / O request should occupy as many flash memory chips as possible. For example, if the ZNS-SSD has 4 partitions, and the mapping relationship between partitions and flash memory chips is shown in the figure, then the number of I / O requests to write back in this case is 2, specifically writing back the I / O requests from partition 1 queue and partition 3 queue, because these two I / O requests can be written to the flash memory chip simultaneously and can utilize all flash memory chip resources.
[0033] like Figure 5 As shown, when the onboard DRAM inside the ZNS-SSD is fully occupied, in order to continuously ensure the write performance of ZNS-SSD data, cache removal management will be performed on the data in the onboard DRAM. Starting from step 101, the specific steps are as follows:
[0034] In step 102, based on the number of partitions in the ZNS-SSD, a corresponding number of partition queues are established in the onboard DRAM;
[0035] In step 103, whenever an I / O request arrives, the partition to be accessed is determined based on the logical address it accesses, and the I / O request is placed in the corresponding partition queue.
[0036] In step 104, determine if the onboard DRAM is full. If it is full, proceed to step 105. Otherwise, proceed to step 103.
[0037] In step 105, based on the cache removal strategy that is aware of the working status of the flash memory chip, select the I / O request data that needs to be removed;
[0038] In step 106, the number of I / O request data that needs to be removed is determined according to the flash memory chip parallelism-aware cache removal strategy;
[0039] In step 107, based on the data and quantity of the determined I / O requests to be removed, the onboard DRAM data removal operation is performed;
[0040] Step 108, End.
[0041] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A cache removal method for improving write performance of ZNS-SSD, characterized in that, include: S1: Based on the number of partitions in the ZNS-SSD, establish the corresponding number of partition queues in the onboard DRAM; S2: Whenever an I / O request arrives, determine the partition to be accessed based on the logical address it accesses, and place the I / O request into the corresponding partition queue; S3: If the onboard DRAM is full of I / O request data, execute the cache removal strategy that is aware of the working status of the flash memory chip and select the I / O request data that needs to be removed; Execute a cache removal policy that is aware of the flash memory chip's operating status, selecting the I / O request data to be removed, specifically including: Each partition queue is traversed sequentially. If the flash memory chip corresponding to the partition queue is in an idle state, the I / O request data of the partition queue will be written back to the flash memory chip. Conversely, if the flash memory chip corresponding to the partition queue is in a busy state, the I / O request data of the partition queue will be skipped and cannot be written back to the flash memory chip temporarily. The I / O request data that cannot be written back to the flash memory chip temporarily is the I / O request data that needs to be removed. S4: Determine the amount of I / O request data that needs to be removed based on the parallelism-aware cache removal strategy of the flash memory chip; Based on the parallelism-aware cache removal strategy of the flash memory chip, determine the amount of I / O request data that needs to be removed, including: When the onboard DRAM space is full, the parallelism between flash memory chips is utilized to write the I / O request data that fills the onboard DRAM space back to the flash memory chips in a way that makes it possible to occupy all flash memory chips in each write-back I / O request data, so as to obtain the number of I / O request data that need to be removed. The parallelism between the flash memory chips is: I / O request data is written to multiple chips simultaneously; S5: Based on the determined number of I / O request data to be removed, perform the data removal operation of the onboard DRAM.