Address translation cache control method, apparatus, device, and medium
By allocating storage bit width to the page table index based on the operating system bit width and page global directory parameters, the problem of search time caused by inconsistent virtual address ranges during TLB refilling is solved, thus improving the TLB refilling speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- LOONGSON TECH CORP
- Filing Date
- 2022-10-31
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, the TLB refilling process is time-consuming due to the inconsistency between the storage range of virtual addresses and the retrieval range of page tables, which reduces the TLB refilling speed.
Based on the operating system bit width, determine the storage width occupied by the virtual address of the target data, and allocate storage width for the page table index according to the page global directory parameters, so that the address range retrieved by the page table is consistent with the storage width of the virtual address. Traverse the page table index to find the physical address mapped to the virtual address and refill it into the TLB.
By aligning the address range retrieved from the page table with the virtual address, the number of judgments and jumps during the refilling process is reduced, thus improving the TLB refilling speed.
Smart Images
Figure CN115658564B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to an address translation cache control method, apparatus, device and medium. Background Technology
[0002] The Translation Lookaside Buffer (TLB) is used for the interaction between virtual addresses and physical addresses. It reduces the time spent looking up physical addresses by providing a buffer for finding physical addresses.
[0003] If the required page table is stored in the TLB, a TLB hit occurs, meaning the corresponding physical address can be obtained through that page table. If a hit occurs, a page table containing the physical address needs to be searched for in computer memory and then refilled into the TLB; this process is called TLB refilling. In existing technology, when refilling the TLB, because the storage range of virtual addresses and the search range of page tables may differ, when the storage range of virtual addresses exceeds the search range, the out-of-range address needs to be checked and the process needs to jump to the page fault handler to search for the corresponding physical address.
[0004] However, existing technologies take a long time to search, which reduces the speed of TLB refilling. Summary of the Invention
[0005] This application provides an address translation cache control method, apparatus, device, and medium to solve the problem that the existing technology has a long search time, which reduces the refill speed of TLB.
[0006] Firstly, this application provides an address translation cache control method, including:
[0007] The first storage bit width is determined based on the operating system bit width. The first storage bit width is the storage bit width occupied by the virtual address of the target data. The virtual address is used as the address identifier for the CPU to access the target data.
[0008] When the first storage bit width is greater than the address range retrieved by the page table, the storage bit width is allocated to the page table index according to the page global directory parameter and the first storage bit width, so that the address range retrieved by the page table is consistent with the first storage bit width of the virtual address;
[0009] Based on the virtual address accessed by the CPU, the physical address mapped to the virtual address is retrieved by traversing the page table index.
[0010] The physical address is refilled into the address translation cache (TLB), and the physical address is used by the CPU to retrieve the target data from the cache that stores the physical address.
[0011] Optionally, the virtual address consists of an intra-page offset and the page table index, the page table index including the Page Global Directory (PGD); when the first storage width is greater than the address range retrieved by the page table, the storage width is allocated to the page table index according to the page global directory parameter and the first storage width, including:
[0012] Obtain the page size of the page table;
[0013] Based on the page size, determine the second storage bit width required to store the page offset;
[0014] Based on the page global directory parameters and the page size, determine the third storage bit width corresponding to the page table index and the bit width required for the PGD in the page table index.
[0015] Optionally, determining the third storage bit width corresponding to the page table index and the bit width required for the PGD in the page table index based on the page global directory parameters and the page size includes:
[0016] The number of page tables allocated by the PGD is determined based on the settings of the page global directory parameters.
[0017] Based on the number of page tables and the page size, determine the fourth storage bit width required to store the PGD.
[0018] Optionally, the step of traversing the page table index to find the physical address mapped to the virtual address based on the virtual address accessed by the CPU includes:
[0019] Based on the virtual address, a target item corresponding to the virtual address is matched in the PGD, and the target item is used to obtain the physical address frame number of the target data;
[0020] The physical address mapped to the virtual address is determined based on the physical address frame number and the page offset.
[0021] Optionally, before determining the storage width occupied by the virtual address of the target data based on the operating system bitness, the method further includes:
[0022] Obtain the virtual address used by the CPU to access the target data;
[0023] Based on the virtual address, search the TLB for the physical address that maps to the virtual address.
[0024] Optionally, the method further includes:
[0025] If the physical address is not found, the page table storing the physical address is traversed to refill the physical address found in the TLB.
[0026] Secondly, this application provides an address translation cache control device, comprising:
[0027] The determining module is used to determine a first storage bit width based on the operating system bit width, wherein the first storage bit width is the storage bit width occupied by the virtual address of the target data, and the virtual address is used as an address identifier for the CPU to access the target data;
[0028] The allocation module is used to allocate storage width to the page table index according to the page global directory parameter and the first storage width when the first storage width is greater than the address range retrieved by the page table, so that the address range retrieved by the page table is consistent with the first storage width of the virtual address.
[0029] The traversal module is used to traverse the physical address mapped to the virtual address based on the virtual address accessed by the CPU and using the page table index.
[0030] The processing module is used to refill the physical address into the address translation cache (TLB), and the physical address is used by the CPU to retrieve the target data from the cache that stores the physical address.
[0031] Thirdly, this application provides an electronic device, including: at least one processor and a memory;
[0032] The memory stores computer-executed instructions;
[0033] The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to perform the method described in any of the first aspects.
[0034] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the method described in any of the first aspects.
[0035] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the method described in any of the first aspects.
[0036] This application provides an address translation cache control method, apparatus, device, and medium. It determines the first storage bit width occupied by the virtual address of the target data based on the operating system bit width, where the virtual address serves as the address identifier for CPU access to the target data. When the first storage bit width is greater than the address range retrieved by the page table, storage bit width is allocated to the page table index based on the page global directory parameters and the first storage bit width, so that the address range retrieved by the page table is consistent with the first storage bit width of the virtual address. Based on the virtual address accessed by the CPU, the physical address mapped to the virtual address is traversed using the page table index, and the physical address is refilled into the address translation cache (TLB). The physical address is used by the CPU to retrieve the target data from the cache containing the physical address. By ensuring that the address range retrieved by the page table is consistent with the virtual address, this application reduces one judgment and jump in the refilling process, avoiding the process of jumping to the page fault handler to search for the corresponding physical address when the accessed virtual address exceeds the page table retrieval range, thus improving the TLB refilling speed. Attached Figure Description
[0037] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0038] Figure 1 A flowchart illustrating an address translation cache control method provided in an embodiment of this application;
[0039] Figure 2 A flowchart illustrating another address translation cache control method provided in this application embodiment;
[0040] Figure 3A A schematic diagram illustrating the allocation of storage bits for a page table index, provided as an embodiment of this application;
[0041] Figure 3B A schematic diagram illustrating another method for allocating storage bandwidth for page table indexes, provided as an embodiment of this application;
[0042] Figure 4 A schematic diagram of a traversal process provided in an embodiment of this application;
[0043] Figure 5 This is a schematic diagram of the structure of an address translation cache control device provided in an embodiment of this application;
[0044] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.
[0045] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0046] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0047] It should be noted that in the description of the embodiments of this application, terms such as "first," "second," and "third" are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate, so that the embodiments described herein can also be implemented in sequences other than those illustrated or described in this application. Terms such as "inner" and "outer," indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings and are merely for ease of description, not to indicate or imply that a device or component must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this application.
[0048] To facilitate understanding of the methods described in this application, the relevant technologies involved in this application are briefly explained below.
[0049] When a computer CPU wants to access a target data, it first obtains the virtual address of the data, then searches the page table in the TLB based on the virtual address to obtain the physical address corresponding to the virtual address, and finally accesses the target data through the physical address.
[0050] In computer memory management, the operating system divides the memory space into several fixed-size pages and establishes a mapping relationship between virtual addresses and physical addresses through page tables. The page table, also known as the page mapping table, is stored in memory and serves as an index for searching for physical addresses from virtual addresses.
[0051] The TLB (Telematics Load Balancer) can act as a cache for page tables. It stores the page table entries that are most likely to be accessed. If the physical address corresponding to the virtual address of the target data can be found through the currently stored page table entries, a TLB hit occurs. If not, the page tables need to be searched again in memory, and the page table containing the physical address found is then filled into the TLB. This process is called TLB refill.
[0052] In existing technologies, when refilling the TLB, the storage range of virtual addresses may differ from the page table retrieval range. When the storage range of virtual addresses exceeds the retrieval range, it is necessary to determine the out-of-range addresses and jump to the page fault management program to search for the corresponding physical addresses. However, existing technologies are time-consuming during the search process, reducing the speed of TLB refilling.
[0053] For example, taking a 64-bit computer operating system as an example, if the storage width occupied by the virtual address is greater than the address range retrieved by the page table, since the virtual address range is inconsistent with the page table retrieval range, when refilling the TLB, it is necessary to judge the address that exceeds the range and jump to the page fault exception management program to search for the corresponding physical address, which results in a long search time.
[0054] Therefore, to address the aforementioned technical problems of the prior art, this application proposes an address translation cache control method, apparatus, device, and medium. Based on the operating system bit width, a first storage bit width occupied by the virtual address of the target data is determined. When the first storage bit width is greater than the address range retrieved by the page table, storage bit width is allocated to the page table index according to the page global directory parameters and the first storage bit width, so that the address range retrieved by the page table is consistent with the first storage bit width of the virtual address. It should be noted that since the priority of address error exceptions is higher than that of TLB refill exceptions, an address error exception will occur first when the address exceeds the page table retrieval address. This ensures that the virtual address is within the page table retrieval range during TLB refilling, reducing one judgment and jump, and eliminating the need to jump to the page fault exception handler to search for the corresponding physical address, thereby improving the TLB refilling speed.
[0055] This application can be applied to both 32-bit and 64-bit operating systems. By setting the virtual address range to be the same as the page table retrieval range, it avoids entering the page fault management program when searching for physical addresses in the page table due to out-of-range errors, thereby improving search speed. It is understood that the address translation cache control method proposed in this application includes, but is not limited to, the scenarios described above, and these scenarios are not intended to limit this application.
[0056] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.
[0057] Figure 1This is a flowchart illustrating an address-translation cache control method provided in an embodiment of this application. The execution subject of this method can be an address-translation cache control device or equipment, or various intelligent terminals, such as computers, laptops, smartphones, tablets, and portable wearable devices. The method in this embodiment can be implemented through software, hardware, or a combination of both. Figure 1 As shown, the method specifically includes the following steps:
[0058] S101. Determine the first storage bit width according to the operating system bit width. The first storage bit width is the storage bit width occupied by the virtual address of the target data. The virtual address is used as the address identifier for the CPU to access the target data.
[0059] In this embodiment, the execution subject is a computer. The current operating system supports 32-bit or 64-bit. The number of bits refers to the data width of the CPU. That is, 64-bit means that the CPU can run 64 bits of data at a time.
[0060] In a 32-bit operating system, the virtual address space is 2^32, and 32 bits are typically used to represent it. In a 64-bit operating system, 48 bits are generally used, because a 64-bit operating system does not require an address space as large as 2^64; excessive space would only lead to resource waste. Furthermore, different memory bit widths can be set for the operating system according to usage requirements. Therefore, based on the bit width of the operating system, the first memory bit width occupied by the target data's virtual address, i.e., the virtual address space, can be determined.
[0061] To facilitate understanding of the method of this application, this embodiment uses a 64-bit operating system as an example for explanation. The determined virtual address space is 2^48, or 48 bits, where the virtual address is used as the address identifier for the CPU to access target data.
[0062] S102. When the first storage width is greater than the address range retrieved by the page table, allocate storage width for the page table index according to the page global directory parameters and the first storage width, so that the address range retrieved by the page table is consistent with the first storage width of the virtual address.
[0063] Instructions and data in a computer must be loaded into memory before the CPU can execute them. However, the CPU cannot directly access physical memory. Memory in a computer is divided into fixed-size pages, and address translation from virtual address to physical address is needed to reach the cache location where the actual data is stored. The most intuitive way to map virtual addresses to physical addresses is to create a mapping table. This mapping table is called a page table.
[0064] When the first storage width is greater than the address range retrieved by the page table, the storage width for the page table index is allocated according to the setting of the page global directory parameter (PGD_ORDER) in the page table and the first storage width, so that the address range retrieved by the page table is consistent with the virtual address. The page table index includes the Page Global Directory (PGD), and may also include the Page Upper Directory (PUD), Page Middle Directory (PMD), and page table entries (PTE). The entries included in the page table index depend on the page size and the number of bits supported by the operating system.
[0065] For a 64-bit operating system, a page table index with a page table size of 4KB has a 4-level index. Each page table is 4KB and stores the base address of the next-level page. Each level of the page table is PGD-PUD-PMD-PTE. Under the same operating system, a page table index with a page table size of 16KB has a 3-level index. Each page table is 16KB and stores the base address of the next-level page. Each level of the page table is PGD-PMD-PTE. Therefore, the number of levels in the page table index depends on the size of the page table and the bit width supported by the operating system.
[0066] S103. Based on the virtual address accessed by the CPU, use the page table index to traverse and find the physical address that maps to the virtual address.
[0067] Since computer operating systems typically employ a multi-level page table structure, the aforementioned page table index contains the following relationships: each entry in PGD stores the base address of a PUD, each entry in PUD stores the base address of a PMD, each entry in PMD stores the base address of a PTE, and the PTE contains page table entries. The physical address mapped to the virtual address is then searched through the page table entries.
[0068] In a computer, every CPU has a page directory base address register, where the base address of the highest-level page table, PGD, is stored. The CPU finds PGD based on the virtual address, and then searches level by level through the multi-level page table structure to eventually traverse and determine the physical address.
[0069] S104. Refill the physical address into the address translation cache TLB. The physical address is used by the CPU to retrieve the target data from the cache that stores the physical address.
[0070] After finding the physical address mapped to the virtual address by searching the page table, the page table is refilled into the TLB. The CPU then retrieves the target data to be accessed from the cache that stores the physical address, such as L1, L2, or L3.
[0071] It should be noted that steps S101-S104 are the processing method when TLB refill occurs. The triggering condition for TLB refill can be obtained by acquiring the virtual address of the CPU accessing the target data, and searching for the physical address mapped to the virtual address in the TLB according to the virtual address. If no physical address is found, the page table storing the physical address is traversed to refill the physical address found into the TLB.
[0072] In the above embodiments of this application, the first storage bit width occupied by the virtual address of the target data is determined according to the operating system bit width, wherein the virtual address is used as the address identifier for the CPU to access the target data. When the first storage bit width is greater than the address range retrieved by the page table, the storage bit width is allocated to the page table index according to the page global directory parameters and the first storage bit width, so that the address range retrieved by the page table is consistent with the first storage bit width of the virtual address. According to the virtual address accessed by the CPU, the physical address mapped to the virtual address is traversed using the page table index, and the physical address is refilled into the address translation cache (TLB), wherein the physical address is used by the CPU to retrieve the target data from the cache containing the physical address. This application improves the TLB refilling speed by making the address range retrieved by the page table consistent with the virtual address.
[0073] Furthermore, based on the above embodiments, the following will be conducted through... Figure 2 A detailed explanation is provided: when the first storage width is greater than the address range retrieved from the page table, storage width is allocated to the page table index based on the page global directory parameters and the first storage width. For example... Figure 2 As shown, Figure 2 This is a flowchart illustrating another address translation cache control method provided in an embodiment of this application. The method includes the following steps:
[0074] S201. Get the page size of the page table.
[0075] Page size relates to the space occupied by the page table. The page size varies depending on the bit width supported by the operating system. Page size is also related to the architecture; for example, an architecture supporting a 16kb page table size in a 64-bit operating system with a 48-bit virtual address space is described in the specific implementation of this invention.
[0076] S202. Determine the second storage bit width required for storing the offset within the storage page based on the page size.
[0077] In a computer, a virtual address (VA) can be represented by two parts: the page offset and the page table index. The storage bit width of the virtual address [47:0] from left to right is shown in Table 1, where "0" represents the least significant bit and "47" represents the most significant bit, for a total of 48 bits.
[0078] Table 1
[0079]
[0080] The page size is 16KB, which is 2^14B. Therefore, 14 storage bits need to be allocated for the page offset. In the computer's storage management, the page offset is located in the low part of the virtual address. Therefore, 14 storage bits are allocated to the right from the least significant bit of the virtual address storage width, i.e., VA[13:0].
[0081] S203. Based on the page global directory parameters and page size, determine the third storage bit width corresponding to the page table index and the bit width required for PGD in the page table index.
[0082] The page global directory parameter is the difference between the virtual address width and the page table index width. In this embodiment, when the page size is 16KB, the page table structure is typically three-level, meaning the page table index includes PGD, PMD, and PTE. Therefore, in this embodiment, the third storage width includes the width required for PMD and the width required for PTE.
[0083] Based on the page size, determine the required storage width for storing the PTE, and allocate the second storage width starting from the least significant bit of the remaining virtual address storage width. Accordingly, 16KB is 2^14B, and a page table entry is 8 bytes (2^3B). 2^14 / 2^3 = 2^11 = 2048. Therefore, the PTE can store 2048 page table entries, requiring 11 storage bits to be allocated for the PTE. Thus, allocate 11 storage bits to the right starting from the least significant bit of the remaining virtual address storage width (34 bits), i.e., VA[24:14].
[0084] Based on the page size, determine the required storage width for PMD, and allocate the third storage width starting from the least significant bit of the remaining virtual address storage width. The method for determining the PTE width is the same as described above, and will not be repeated here. Allocate 11 storage bits to PMD; therefore, allocate 11 storage bits to the right from the least significant bit of the remaining virtual address storage width (23 bits), i.e., [35:25], to PMD.
[0085] Furthermore, based on the settings of the page global directory parameters and the page size, the required bit width for PGD in the page table index is determined.
[0086] Based on the settings of the page global directory parameters, determine the number of page tables allocated to PGD, and based on the number of page tables and the page size, determine the fourth storage bit width required to store PGD.
[0087] One alternative approach is to set the page global directory parameter PGD_ORDER to 1, where 2^1 equals 2. Therefore, the number of page tables allocated to PGD is determined to be 2. The page size of 2 page tables is 2 × 16 KB, which is 2^15 B. Since one page table entry is 8 bytes (2^3 B), 2^15 / 2^3 = 2^12 = 4096. Therefore, PGD can store 4096 page table entries. PGD needs to be allocated 12 storage bits. Thus, 12 storage bits are allocated to the right from the least significant bit of the remaining virtual address storage width, i.e., VA[47:36].
[0088] Another option is that when the page global directory parameter PGD_ORDER is set to 0, 2^0 is 1, so the number of page tables allocated to PGD is determined to be 1. The page size of 1 page table is 16KB, which is 2^14B, and one page table entry is 8 bytes (2^3B). 2^14 / 2^3 = 2^11 = 2048. Therefore, PGD can store 2048 page table entries. It needs to allocate 11 storage bits for PGD. Therefore, 11 storage bits are allocated to the right from the least significant bit of the remaining virtual address storage width, which is VA[46:36].
[0089] Based on steps S201-S203 above, we can obtain the following: Figure 3A , Figure 3B Two methods are used to allocate storage bits for page table indexes within the storage width occupied by virtual addresses, thus ensuring that the address range for page table retrieval is consistent with the virtual address range. Figure 3A In this context, the page table retrieval range is VA[47:0], and the valid range of the virtual address is also [47:0]. Figure 3B In this context, the range of page table retrieval is VA[46:0], and the valid range of virtual addresses is also [46:0].
[0090] It should be noted that, for ease of understanding this application, the page size of 16KB in this embodiment is merely illustrative. The method of this application can also be used for page sizes of 4KB or 32KB, etc., and is not intended to limit this application. In the above embodiments of this application, by obtaining the page size of the page table, determining the second storage bit width required for storing the offset within the page based on the page size, and determining the third storage bit width corresponding to the page table index and the bit width required for PGD in the page table index based on the page global directory parameters and the page size, the address range retrieved by the page table is made consistent with the virtual address, thereby improving the TLB refill speed.
[0091] Furthermore, based on the virtual address accessed by the CPU, the physical address mapped to the virtual address is retrieved using the page table index. For example... Figure 4 As shown, Figure 4 This is a schematic diagram of a traversal process provided in an embodiment of this application.
[0092] Based on the virtual address, the target item corresponding to the virtual address is matched in PGD. The target item is used to obtain the physical address frame number of the target data.
[0093] Based on the physical address frame number and the offset within the page, determine the physical address that maps to the virtual address.
[0094] This embodiment also uses a 64-bit operating system, a 48-bit virtual address space, and a page size of 16KB as an example for illustration.
[0095] Specifically,
[0096] Based on the virtual address, match the base address of the PMD corresponding to the virtual address in the PGD.
[0097] Based on the base address of the PMD, the target item corresponding to the base address is matched in the PTE. The target item is used to obtain the physical address frame number of the target data.
[0098] Based on the physical address frame number and the offset within the page, determine the physical address that maps to the virtual address.
[0099] Finally, the physical address is refilled into the address translation cache (TLB), which is used by the CPU to retrieve the target data from the cache containing the physical address.
[0100] Figure 5 This is a schematic diagram of the structure of an address translation cache control device provided in an embodiment of this application, as shown below. Figure 5 As shown, the device includes: a determination module 501, an allocation module 502, a traversal module 503, and a processing module 504.
[0101] The determining module 501 is used to determine the first storage bit width according to the bit width of the operating system. The first storage bit width is the storage bit width occupied by the virtual address of the target data. The virtual address is used as the address identifier for the CPU to access the target data.
[0102] The allocation module 502 is used to allocate storage width for the page table index according to the page global directory parameters and the first storage width when the first storage width is greater than the address range of the page table retrieval, so that the address range of the page table retrieval is consistent with the first storage width of the virtual address.
[0103] Traversal module 503 is used to traverse the page table index to find the physical address that maps to the virtual address based on the virtual address accessed by the CPU.
[0104] Processing module 504 is used to refill the physical address into the address translation cache TLB. The physical address is used by the CPU to retrieve target data from the cache that stores the physical address.
[0105] One possible implementation is that the virtual address consists of an offset within the page and a page table index, where the page table index includes the Page Global Directory (PGD). Specifically, the allocation module 502 is used for:
[0106] Get the page size of the page table.
[0107] Determine the second storage bit width required for the storage page offset based on the page size.
[0108] Based on the page global directory parameters and page size, determine the third storage bit width corresponding to the page table index and the bit width required for PGD in the page table index. One possible implementation is that allocation module 502 is also used for:
[0109] The number of page tables allocated to PGD is determined based on the settings of the page global directory parameters.
[0110] Determine the fourth storage bit width required to store PGD based on the number of page tables and the page size.
[0111] One possible implementation is to iterate through module 503, specifically for:
[0112] Based on the virtual address, the target item corresponding to the virtual address is matched in PGD. The target item is used to obtain the physical address frame number of the target data.
[0113] Based on the physical address frame number and the offset within the page, determine the physical address that maps to the virtual address.
[0114] One possible implementation is that the device further includes an acquisition module 505, for:
[0115] Obtain the virtual address of the target data accessed by the CPU;
[0116] Based on the virtual address, search the TLB for the physical address that maps to the virtual address.
[0117] If no physical address is found, the page table storing the physical address is traversed to refill the TLB with the found physical address.
[0118] The address translation cache control device provided in this embodiment is used to execute the aforementioned method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.
[0119] Figure 6This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 6 As shown, the device may include at least one processor 601 and a memory 602.
[0120] The memory 602 is used to store programs. Specifically, the program may include program code, which includes computer operation instructions.
[0121] The memory 602 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.
[0122] The processor 601 is used to execute computer execution instructions stored in the memory 602 to implement the method described in the foregoing method embodiments. The processor 601 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.
[0123] Optionally, the heat pump system may also include a communication interface 603. In specific implementations, if the communication interface 603, memory 602, and processor 601 are implemented independently, they can be interconnected via a bus to communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc., but this does not imply that there is only one bus or one type of bus.
[0124] Optionally, in a specific implementation, if the communication interface 603, memory 602, and processor 601 are integrated on a single chip, then the communication interface 603, memory 602, and processor 601 can communicate through an internal interface.
[0125] The electronic device provided in this embodiment is used to execute the method executed in the foregoing embodiment. Its implementation principle and technical effect are similar, and will not be described again.
[0126] This application also provides a computer-readable storage medium, which may include various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk. Specifically, the computer-readable storage medium stores program instructions, which are used in the methods described in the above embodiments.
[0127] This application also provides a computer program product including executable instructions stored in a readable storage medium. At least one processor of an electronic device can read the executable instructions from the readable storage medium, and the at least one processor executes the executable instructions to cause the electronic device to implement the address translation cache control method provided in the various embodiments described above.
[0128] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0129] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A method for controlling an address-translation cache, characterized in that, include: Based on the operating system bit width, a first storage bit width is determined. The first storage bit width is the storage bit width occupied by the virtual address of the target data. The virtual address consists of an offset within the page and a page table index, and is used as an address identifier for the CPU to access the target data. The page table index includes the Page Global Directory (PGD). When the first storage bit width is greater than the address range retrieved by the page table, the storage bit width is allocated to the PGD in the page table index according to the page global directory parameter and the first storage bit width, so that the address range retrieved by the page table is consistent with the first storage bit width of the virtual address; Based on the virtual address accessed by the CPU, the physical address mapped to the virtual address is retrieved by traversing the page table index. The physical address is refilled into the address translation cache (TLB), and the physical address is used by the CPU to retrieve the target data from the cache that stores the physical address.
2. The method according to claim 1, characterized in that, When the first storage bit width is greater than the address range retrieved from the page table, the storage bit width is allocated to the PGD in the page table index according to the page global directory parameter and the first storage bit width, including: Obtain the page size of the page table; Based on the page size, determine the second storage bit width required to store the page offset; Based on the page global directory parameters and the page size, determine the third storage bit width corresponding to the page table index and the bit width required for the PGD in the page table index.
3. The method according to claim 2, characterized in that, The step of determining the third storage bit width corresponding to the page table index and the bit width required for the PGD in the page table index based on the page global directory parameters and the page size includes: The number of page tables allocated by the PGD is determined based on the page global directory parameters. Based on the number of page tables and the page size, determine the fourth storage bit width required to store the PGD.
4. The method according to claim 2 or 3, characterized in that, The step of retrieving the physical address mapped to the virtual address using the page table index based on the virtual address accessed by the CPU includes: Based on the virtual address, a target item corresponding to the virtual address is matched in the PGD, and the target item is used to obtain the physical address frame number of the target data; The physical address mapped to the virtual address is determined based on the physical address frame number and the page offset.
5. The method according to claim 1, characterized in that, Before determining the storage width occupied by the virtual address of the target data based on the operating system bit width, the method further includes: Obtain the virtual address used by the CPU to access the target data; Based on the virtual address, search the TLB for the physical address that maps to the virtual address.
6. The method according to claim 5, characterized in that, The method further includes: If the physical address is not found, the page table storing the physical address is traversed to refill the physical address found in the TLB.
7. An address translation cache control device, characterized in that, include: The determining module is used to determine a first storage bit width based on the operating system bit width. The first storage bit width is the storage bit width occupied by the virtual address of the target data. The virtual address consists of an offset within the page and a page table index, and is used as an address identifier for the CPU to access the target data. The page table index includes the Page Global Directory (PGD). The allocation module is used to allocate storage width to the PGD in the page table index according to the page global directory parameter and the first storage width when the first storage width is greater than the address range retrieved by the page table, so that the address range retrieved by the page table is consistent with the first storage width of the virtual address; The traversal module is used to traverse the physical address mapped to the virtual address based on the virtual address accessed by the CPU and using the page table index. The processing module is used to refill the physical address into the address translation cache (TLB), and the physical address is used by the CPU to retrieve the target data from the cache that stores the physical address.
8. An electronic device, comprising: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 6.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 6.
10. A computer program product comprising a computer program that, when executed by a processor, implements the method of any one of claims 1 to 6.