Multi-core processor system and method of controlling the same
By introducing a delayed backpressure circuit into the cache coherence unit of a multi-core processor system, the problems of cache inconsistency and data loss caused by excessively long data transmission paths in multi-core processor systems are solved, achieving high-performance and low-power data transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING ESWIN COMPUTING TECH CO LTD
- Filing Date
- 2022-09-27
- Publication Date
- 2026-07-21
AI Technical Summary
In multi-core processor systems, timing issues caused by excessively long data transmission paths can easily lead to cache inconsistencies and data loss, which are difficult to effectively resolve with existing technologies.
A delayed reverse-voltage circuit is introduced into the cache coherence unit. By prioritizing the output of the input data of the previous clock cycle when the handshake state is successful, data loss is avoided. The input data of the current clock cycle is output when the handshake state is successful, ensuring the continuity and high performance of data transmission.
It effectively avoids cache inconsistency, optimizes timing, reduces circuit power consumption, and ensures high performance and continuity of data transmission.
Smart Images
Figure CN115658601B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of processors, and more specifically to a multi-core processor system and its control method. Background Technology
[0002] With the continuous development of computer systems and manufacturing processes, significant performance improvements to commercial single-core processors have become increasingly difficult due to physical limitations in manufacturing processes. Single-core processors are becoming less and less suitable for today's high-computing scenarios. To improve the performance of computer systems and their availability for handling high-computing scenarios, processors are gradually evolving towards multi-core architectures. Figure 1 The diagram shows a quad-core processor model. The four processor cores (CPU0, CPU1, CPU2, and CPU3) are connected to each other through a cache coherence unit 20. At the same time, each processor core interacts with the slave device 40 through the cache coherence unit 20 and the on-chip network (Network Operation Center, NoC).
[0003] A persistent problem in the development of multi-core processors is multi-core cache coherence. Simply put, when processor core CPU0 modifies a cache line in its private cache, it needs to notify the other processor cores (CPU1, CPU2, CPU3) that hold that cache line to prevent multiple processor cores from simultaneously modifying the same address. Multi-core cache coherence is typically handled directly by hardware, which is transparent to the software layer. This greatly simplifies the work for software developers and improves software efficiency.
[0004] When implementing multi-core cache consistency, if the data transmission path is too long, it can easily cause some timing problems. These timing problems can usually be solved by padding, but padding is prone to a situation where the consistency module can successfully handshake with the upstream, but fails to handshake with the downstream, which can lead to data loss and cache inconsistency.
[0005] Therefore, it is necessary to provide improved technical solutions to overcome the above-mentioned technical problems existing in the prior art. Summary of the Invention
[0006] To address the aforementioned technical issues, this disclosure provides a multi-core processor system and its control method. By adding a delay circuit to the cache coherency unit, it is possible to optimize timing while ensuring high-performance pipeline transmission, effectively avoiding cache inconsistency caused by input data loss, and reducing circuit power consumption.
[0007] According to a first aspect of this disclosure, a multi-core processor system is provided, comprising: a plurality of processor cores;
[0008] A cache coherence unit, connected to the plurality of processor cores and slave devices, controls the data interaction between the slave devices and the plurality of processor cores to achieve cache coherence in the multi-core processor system.
[0009] The cache coherence unit includes:
[0010] The delayed reverse voltage circuit is used to buffer the input data transmitted in the previous clock cycle when outputting the input data transmitted in the current clock cycle, and to prioritize outputting the buffered input data when the handshake state between the buffer coherence unit and the slave device changes from unsuccessful to successful.
[0011] Optionally, the delayed reverse voltage circuit includes:
[0012] A logic control unit is configured to generate a selection signal based on a first handshake signal sent by the cache coherence unit to the slave device, a second handshake signal sent by the slave device to the cache coherence unit, and an information transmission request signal sent by the cache coherence unit to the slave device. The information transmission request signal is used to indicate whether there is a new information transmission request.
[0013] The selection unit is used to buffer the input data transmitted in the previous clock cycle when outputting the input data transmitted in the current clock cycle, and to prioritize outputting the buffered input data when the handshake state between the buffer coherence unit and the slave device changes from unsuccessful to successful according to the selection signal.
[0014] Optionally, the cache coherence unit and the slave device are in a handshake success state when both the first handshake signal and the second handshake signal are valid, and the selection unit outputs the cached input data in the first clock cycle when both the first handshake signal and the second handshake signal are valid, and outputs the input data transmitted in the current clock cycle starting from the second clock cycle when both the first handshake signal and the second handshake signal are valid.
[0015] Optionally, the selection unit includes:
[0016] The first D flip-flop receives the input data transmitted in the current clock cycle at its input terminal. The first D flip-flop is used to buffer the input data transmitted in the previous clock cycle when outputting the input data transmitted in the current clock cycle and output it at the output terminal.
[0017] A data selector has a first input terminal connected to the output terminal of the first D flip-flop and a second input terminal connected to the input terminal of the first D flip-flop. A control terminal receives the selection signal. When the selection signal is valid, the data selector outputs buffered input data, and when the selection signal is invalid, it outputs the input data transmitted in the current clock cycle. The selection signal is valid during the first clock cycle in which both the first handshake signal and the second handshake signal are valid.
[0018] Optionally, the first D flip-flop is enabled when the information transmission request signal is valid.
[0019] Optionally, the first handshake signal is configured to become active one clock cycle before the second handshake signal when there is an information transmission request, so that the selection signal is active during the first clock cycle in which both the first handshake signal and the second handshake signal are active.
[0020] In an optional embodiment, the selection unit includes:
[0021] The first OR gate logic circuit has a first input terminal that receives the information transmission request signal and a second input terminal that receives the selection signal.
[0022] The first NOR gate logic circuit has a first input terminal that receives the second handshake signal and a second input terminal that receives the first handshake signal through the first NOT gate logic circuit.
[0023] The first AND gate logic circuit has its first input terminal connected to the output terminal of the first OR gate logic circuit, and its second input terminal connected to the output terminal of the first NOR gate logic circuit.
[0024] The second D flip-flop has its signal input terminal connected to the output terminal of the first AND gate logic circuit, and its output terminal outputs the selection signal.
[0025] In another alternative embodiment, the selection unit includes:
[0026] The second OR gate logic circuit has a first input terminal that receives the information transmission request signal and a second input terminal that receives the selection signal.
[0027] The second AND gate logic circuit has a first input terminal that receives the second handshake signal through the second NOT gate logic circuit, and a second input terminal that receives the first handshake signal.
[0028] The third AND gate logic circuit has its first input terminal connected to the output terminal of the second OR gate logic circuit, and its second input terminal connected to the output terminal of the second AND gate logic circuit.
[0029] The third D flip-flop has its signal input terminal connected to the output terminal of the third AND gate logic circuit, and the output terminal of the third D flip-flop outputs the selection signal.
[0030] According to a second aspect of this disclosure, a control method for a multi-core processor system is provided, comprising: when a slave device interacts with multiple processor cores, using a cache coherence unit to cache input data transmitted in the previous clock cycle when outputting input data transmitted in the current clock cycle;
[0031] When the handshake state between the cache coherence unit and the slave device changes from unsuccessful to successful, the cached input data is output first.
[0032] Optionally, the cache coherence unit sends a first handshake signal to the slave device, and the slave device sends a second handshake signal to the cache coherence unit. The cache coherence unit outputs the cached input data in the first clock cycle when both the first handshake signal and the second handshake signal are valid, and outputs the input data transmitted in the current clock cycle starting from the second clock cycle when both the first handshake signal and the second handshake signal are valid.
[0033] By adopting the technical solution disclosed herein, high-performance pipeline transmission can be guaranteed while optimizing timing, effectively avoiding buffer inconsistencies caused by input data loss, and reducing circuit power consumption.
[0034] It should be noted that the above general description and the following detailed description are exemplary and explanatory, and do not limit this disclosure. Attached Figure Description
[0035] Figure 1 This diagram illustrates the structure of a quad-core processor model.
[0036] Figure 2 This diagram illustrates the structure of a multi-core processor system according to an embodiment of the present disclosure.
[0037] Figure 3 A schematic diagram of the structure of the delayed reverse voltage circuit provided according to an embodiment of the present disclosure is shown;
[0038] Figure 4 This diagram illustrates the structure of a logic control unit provided according to a first embodiment of the present disclosure.
[0039] Figure 5 This diagram illustrates the structure of a logic control unit provided according to a second embodiment of the present disclosure.
[0040] Figure 6 Show Figure 4 and Figure 5A schematic diagram of the timing waveforms of each signal in the logic control unit;
[0041] Figure 7 A flowchart illustrating a control method for a multi-core processor system provided according to an embodiment of the present disclosure is shown. Detailed Implementation
[0042] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure.
[0043] In a computer, instructions are executed by the CPU (Central Processing Unit), which involves reading and writing data. Early on, temporary data during program execution was stored in main memory (physical memory). With the addition of a cache, the CPU first reads data from the cache; if the data is not in the cache, it reads it from main memory and adds it to the cache, so it can be read directly from the cache the next time it's needed. When data is modified, the modified data is first written to the cache and then flushed to main memory, thus improving efficiency.
[0044] In a multi-core processor system (hereinafter referred to as "the system"), such as Figure 2 As shown, the system includes multiple processor cores, and programs or instructions can run on different processor cores through multiple threads. Each processor core has its own cache (see reference). Figure 1 For example, processor core CPU0 corresponds to cache 11, processor core CPU1 corresponds to cache 12, processor core CPU2 corresponds to cache 13, and processor core CPU3 corresponds to cache 14. This can lead to a situation where multiple CPUs modify the same data simultaneously, which is known as a cache coherence problem.
[0045] To address the cache coherence issue, a cache coherence unit 20 is also included in the system. This cache coherence unit 20 is connected to multiple processor cores in the multi-core processor 10 and is also connected to a slave device 40 (such as main memory) via an on-chip network 30 or a bus. The cache coherence unit 20 controls the data interaction between the slave device 40 and the multiple processor cores by executing a cache coherence protocol, thereby achieving cache coherence in the multi-core processor system.
[0046] Specifically, such as Figure 2As shown, each processor core in the multi-core processor 10 sends a handshake signal `valid_to_coh` and a handshake signal `ready_to_coh` to the cache coherence unit 20. The cache coherence unit 20 sends a handshake signal `ready_to_core` and a handshake signal `valid_to_core` to each processor core in the multi-core processor 10. When both `valid_to_coh` and `ready_to_core` are valid, it indicates that during the data transmission process where the processor core writes data to the slave device 40 through the cache coherence unit 20, the corresponding processor core and the cache coherence unit 20 are in a successful handshake state. At this time, the processor core outputs the data `infor_to_coh` to the cache coherence unit 20. When both `valid_to_core` and `ready_to_coh` are valid, it indicates that during the data transmission process where the processor core reads data from the slave device 40 through the cache coherence unit 20, the corresponding processor core and the cache coherence unit 20 are in a successful handshake state. At this time, the cache coherence unit 20 outputs the data `infor_to_core` to the corresponding processor core.
[0047] Cache coherence unit 20 sends handshake signals valid_to_slave and ready_to_slave to slave device 40, while slave device 40 sends handshake signals ready_to_coh and valid_to_coh to cache coherence unit 20. When both valid_to_slave and ready_to_coh are valid, it indicates that during the data transfer process where the processor core writes data to slave device 40 through cache coherence unit 20, cache coherence unit 20 and slave device 40 are in a successful handshake state, and cache coherence unit 20 outputs the data infor_to_slave to slave device 40. When both ready_to_slave and valid_to_coh are valid, it indicates that during the data transfer process where the processor core reads data from slave device 40 through cache coherence unit 20, cache coherence unit 20 and slave device 40 are in a successful handshake state, and slave device 40 outputs the data infor_to_coh to cache coherence unit 20.
[0048] In summary, when the handshake signals valid_to_coh and ready_to_core, as well as the handshake signals valid_to_slave and ready_to_coh, are all valid, the corresponding processor core can write data to the slave device 40 through the cache coherence unit 20. When the handshake signals valid_to_core and ready_to_coh, as well as the handshake signals ready_to_slave and valid_to_coh, are all valid, the corresponding processor core can read data from the slave device 40 through the cache coherence unit 20.
[0049] Based on the data transmission characteristics of the processor system, when using registers for data synchronization, the state change of the handshake signal between the slave device 40 (or the corresponding processor core) and the cache coherence unit 20 will be transmitted to the cache coherence unit 20 and the corresponding processor core (or slave device 40) one clock cycle later. That is, during the data transmission process, there will be a period of time when the cache coherence unit 20 successfully hands with the upstream processor core, but fails to handshake with the downstream slave device 40. During this period, the slave device 40 (or the corresponding processor core) cannot receive new data, but the corresponding processor core (or slave device 40) is still sending new data to the cache coherence unit 20, which can easily lead to the loss of some data and cause cache inconsistency.
[0050] Regarding this issue, please continue to refer to... Figure 2 In this embodiment, a delayed backpressure circuit 21 is provided in the cache coherence unit 20. Taking the data transmission process of the corresponding processor core writing data to the slave device 40 through the cache coherence unit 20 as an example, the delayed backpressure circuit 21 is used to cache the input data transmitted in the previous clock cycle (referred to as infor in this document) when outputting the input data new_infor transmitted in the current clock cycle, and to output the cached input data infor first when the handshake state between the cache coherence unit 20 and the slave device 40 changes from unsuccessful to successful. The delayed backpressure circuit 21 only caches input data for one unit of time (e.g., one clock cycle). That is, when the delayed backpressure circuit 21 caches new input data, it will overwrite the previously cached input data. Therefore, the delayed backpressure circuit 21 only needs to set a small cache space to achieve the required function, resulting in low cost. At the same time, no addressing operations are required when performing cache output, making the operation process simple and the output speed fast. Optionally, the input data new_infor in this document refers to all consistency-related information transmitted by the cache coherence unit 20 to the slave device 40.
[0051] In this embodiment, the delayed reverse voltage circuit 21 has a first input terminal for receiving the input data new_infor transmitted in the current clock cycle, a second input terminal for receiving the information transmission request signal infor_req, a third input terminal for receiving the handshake signal valid_to_slave, a fourth input terminal for receiving the handshake signal ready_to_coh, and an output terminal out_infor for output data. The information transmission request signal infor_req is sent to the slave device 40 by the cache coherence unit 20, and the signal is used to indicate whether there is a new information transmission request.
[0052] refer to Figure 3 , Figure 4 and Figure 5 The delayed reverse voltage circuit 21 further includes a logic control unit 211 and a selection unit 212. The logic control unit 211 generates a selection signal `select` based on the handshake signals `valid_to_slave`, `ready_to_coh`, and `infor_req`. The selection unit 212 buffers the input data `infor` transmitted in the previous clock cycle when outputting the input data `new_infor` transmitted in the current clock cycle, and prioritizes outputting the buffered input data `infor` when the handshake state between the buffer coherence unit 20 and the slave device 40 changes from unsuccessful to successful, based on the selection signal `select`.
[0053] It should be noted that the "priority" in this article refers to the comparison between the input data new_infor transmitted in the current clock cycle and the input data infor transmitted in the previous clock cycle in the cache. Specifically, after the handshake state between the cache coherence unit 20 and the slave device 40 changes from unsuccessful to successful, the delayed reverse voltage circuit 21 will select one of the input data new_infor transmitted in the current clock cycle and the input data infor transmitted in the previous clock cycle in the cache for output. The "priority output of the cached input data infor" in this article means that after the handshake state between the cache coherence unit 20 and the slave device 40 changes from unsuccessful to successful, the input data infor transmitted in the previous clock cycle in the cache is selected for output first, and then the input data new_infor transmitted in the current clock cycle is selected for output. This ensures the continuity of the current data transmission (each successful handshake represents one data transmission) and the previous data transmission, avoiding data loss.
[0054] like Figure 3 As shown, the selection unit 212 includes a D flip-flop 2121 and a data selector 2122.
[0055] In this configuration, the data input terminal of the D flip-flop 2121 receives the input data new_infor transmitted in the current clock cycle, the clock input terminal of the D flip-flop 2121 receives the clock signal CLK, the reset terminal of the D flip-flop 2121 receives the reset signal RST, and the enable terminal of the D flip-flop 2121 receives the enable signal ENABLE. The D flip-flop 2121 is used to buffer the input data infor transmitted in the previous clock cycle when outputting the input data new_infor transmitted in the current clock cycle and output it at the output terminal. Optionally, in other embodiments of this disclosure, the D flip-flop 2121 in the selection unit 212 may also be replaced by other devices or circuits with buffering functions.
[0056] In this embodiment, the enable signal ENABLE of the D flip-flop 2121 is determined by the internal signal of the cache coherence unit 20 (such as the information transmission request signal infor_req). That is, the D flip-flop 2121 is enabled and started only when the information transmission request signal infor_req is valid, so that the input data new_infor transmitted in the current clock cycle is input to the delayed inverse voltage circuit 21 only when the condition is met, and then output to the cache coherence unit 20 through the output terminal out_infor of the delayed inverse voltage circuit 21, and then continue to be transmitted to the slave device 40 through the output terminal of the cache coherence unit 20; when the condition is not met, the delayed inverse voltage circuit 21 will be in the off state, thereby reducing circuit power consumption.
[0057] The first input of data selector 2122 is connected to the output of D flip-flop 2121 to receive the input data 'infor' buffered by D flip-flop 2121 in the previous clock cycle. The second input of data selector 2122 is connected to the input of D flip-flop 2121 to receive the input data 'new_infor' buffered by D flip-flop 2121 in the current clock cycle. The control terminal of data selector 2122 is connected to the output of logic control unit 211 to receive the selection signal 'select'. When the selection signal 'select' is valid, data selector 2122 outputs the buffered input data 'infor'; when the selection signal 'select' is invalid, it outputs the input data 'new_infor' buffered by D flip-flop 2121 in the current clock cycle.
[0058] Optionally, in the first embodiment of this disclosure, as Figure 4As shown, the selection unit 211 includes: an OR gate logic circuit 2111, a NOR gate logic circuit 2112, a NOT gate logic circuit 2113, an AND gate logic circuit 2114, and a D flip-flop 2115. The first input of the OR gate logic circuit 2111 receives the information transmission request signal `infor_req`, and the second input receives the selection signal `select`. The first input of the NOR gate logic circuit 2112 receives the handshake signal `ready_to_coh`, and the second input receives the handshake signal `valid_to_slave` through the NOT gate logic circuit 2113; that is, the second input of the NOR gate logic circuit 2112 receives the inverted signal of the handshake signal `valid_to_slave`. The first input of the AND gate logic circuit 2114 is connected to the output of the OR gate logic circuit 2111, and the second input of the AND gate logic circuit 2114 is connected to the output of the NOR gate logic circuit 2112. The signal input terminal of the D flip-flop 2115 is connected to the output terminal of the AND gate logic circuit 2114. The clock terminal of the D flip-flop 2115 receives the clock signal CLK, the reset terminal of the D flip-flop 2115 receives the reset signal RST, and the output terminal of the D flip-flop 2115 outputs the select signal.
[0059] Optionally, in the second embodiment of this disclosure, as Figure 5 As shown, the selection unit 211 includes: an OR gate logic circuit 2116, an AND gate logic circuit 2117, a NOT gate logic circuit 2118, an AND gate logic circuit 2119, and a D flip-flop 2110. The first input of the OR gate logic circuit 2116 receives the information transmission request signal `infor_req`, and the second input receives the selection signal `select`. The first input of the AND gate logic circuit 2117 receives the handshake signal `ready_to_coh` through the NOT gate logic circuit 2118; that is, the first input of the AND gate logic circuit 2117 receives the inverted signal of the handshake signal `ready_to_coh`. The second input of the AND gate logic circuit 2117 receives the handshake signal `valid_to_slave`. The first input of the AND gate logic circuit 2119 is connected to the output of the OR gate logic circuit 2116, and the second input of the AND gate logic circuit 2119 is connected to the output of the AND gate logic circuit 2117. The signal input terminal of the D flip-flop 2110 is connected to the output terminal of the AND gate logic circuit 2119. The clock terminal of the D flip-flop 2110 receives the clock signal CLK, the reset terminal of the D flip-flop 2110 receives the reset signal RST, and the output terminal of the D flip-flop 2110 outputs the select signal.
[0060] The following is combined with Figure 6 The operation of the delayed reverse voltage circuit 21 disclosed in the foregoing embodiments of this disclosure will be described as follows:
[0061] like Figure 6 As shown, within a certain clock cycle T1, the information transmission request signal infor_req changes to a valid state (e.g., a high level state), and at the same time, the handshake signal valid_to_slave also changes to a valid state following the information transmission request signal infor_req, while the handshake signal ready_to_coh remains in an invalid state (e.g., a low level state). That is, the buffer coherence unit 20 and the slave device 40 are still in a handshake failure state within the clock cycle T1. At this time, OR gate 2111 and OR gate 2116 output a high level, NOR gate 2112 and AND gate 2117 output a high level, and then AND gate 2114 and AND gate 2119 output a high-level signal next_select within clock cycle T1. However, D flip-flops 2115 and D flip-flops 2110 still output the signal next_select from the previous clock cycle. That is, within clock cycle T1, the select signal select output by D flip-flops 2115 and D flip-flops 2110 is low, and the data selector 2122 does not output data or outputs invalid data within clock cycle T1.
[0062] Within the next clock cycle T2 of clock cycle T1, the handshake signal ready_to_coh also transitions to a valid state (e.g., a high-level state). This means that the handshake between cache coherence unit 20 and slave device 40 changes from an unsuccessful handshake state to a successful handshake state within clock cycle T2. At this time, the outputs of NOR gate 2112 and AND gate 2117 become low-level. Consequently, AND gate 2114 and AND gate 2119 output a low-level signal next_select within clock cycle T2. However, D flip-flops 2115 and 2110 output the signal next_select from the previous clock cycle T1. That is, within clock cycle T2, the select signal select output by D flip-flops 2115 and 2110 is high-level, causing data selector 2122 to output the input data infor cached by D flip-flop 2121 within clock cycle T2, and to continue transmitting this cached input data infor to the downstream slave device 40.
[0063] In the subsequent clock cycles of clock cycle T2, if the handshake signals valid_to_slave and ready_to_coh remain unchanged, AND gate logic circuits 2114 and 2119 will continuously output the low-level signal next_select, and D flip-flops 2115 and 2110 will output the corresponding signal next_select from the previous clock cycle T1. That is, in the subsequent clock cycles of clock cycle T2, D flip-flops 2115 and 2110 will also continuously output the low-level selection signal select, causing data selector 2122 to output the input data new_infor transmitted in the current clock cycle in the subsequent clock cycles of clock cycle T2, and continue to transmit the input data new_infor to the downstream slave device 40. At the same time, D flip-flop 2121 will also buffer the input data infor transmitted in the previous clock cycle when outputting the input data new_infor transmitted in the current clock cycle. During the clock cycle in which the handshake signal `ready_to_coh` becomes invalid, D flip-flop 2121 buffers the input data `infor` transmitted in the previous clock cycle, but the cache coherence unit 20 no longer transmits data to the slave device 40. During the clock cycle in which the handshake signal `valid_to_slave` also becomes invalid, D flip-flop 2121 holds the buffered data, but the delay backpressure unit 21 is turned off, and the clock cycle is paused until a new information transmission request is received, at which point the above process is repeated. It can be understood that when the cache coherence unit 20 successfully hands over the upstream processor core but fails to handshake over the downstream slave device 40, temporarily storing the data to be transmitted during that period in the delay backpressure circuit effectively prevents data loss.
[0064] In summary, the handshake signal `valid_to_slave` is configured to become active one clock cycle before the handshake signal `ready_to_coh` when an information transmission request (i.e., the information transmission request signal `infor_req`) is active. This ensures that the selection signal `select` is active during the first clock cycle T1 when both `valid_to_slave` and `ready_to_coh` are active. Consequently, the selection unit 212 can output the buffered input data during the first clock cycle when both `valid_to_slave` and `ready_to_coh` are active, and start outputting the input data `new_infor` transmitted in the current clock cycle from the second clock cycle when both are active. This optimizes timing to avoid losing the input data `new_infor` while also ensuring data transmission continuity, which is beneficial for achieving high-performance data transmission.
[0065] Furthermore, this disclosure also provides a control method for a multi-core processor system, which can be applied to the aforementioned Figures 2-5 In the circuit structure shown. Specifically, as Figure 7 As shown, taking the data transmission process of the corresponding processor core writing data to the slave device 40 through the cache coherence unit 20 as an example, the control method includes performing the following steps:
[0066] In step S1, when data interaction occurs between the slave device and multiple processor cores, the cache coherency unit is used to cache the input data transmitted in the previous clock cycle when outputting the input data transmitted in the current clock cycle.
[0067] Referring to the above Figures 2 to 6 According to the relevant description, when data interaction occurs between the device and multiple processor cores, by reasonably setting the timing of each input signal of the D flip-flop 2121 set in the cache coherency unit 20, the D flip-flop 2121 can be used to cache the input data transmitted in the previous clock cycle when outputting the input data new_infor transmitted in the current clock cycle.
[0068] In step S2, when the handshake state between the cache consistency unit and the slave device changes from unsuccessful to successful, the cached input data is output first.
[0069] Referring to the above Figures 2 to 6 According to the relevant description, the cache coherence unit 20 sends a handshake signal valid_to_slave to the slave device 40, and the slave device 40 sends a handshake signal ready_to_coh to the cache coherence unit 20. Furthermore, the cache coherence unit 20 and the slave device 40 are only in a successful handshake state when both the handshake signal valid_to_slave and the handshake signal ready_to_coh are valid.
[0070] Meanwhile, the delayed reverse voltage circuit 21 in the cache coherence unit 20 includes a D flip-flop 2121 for buffering the input data infor transmitted in the previous clock cycle when outputting the input data new_infor transmitted in the current clock cycle, and a data selector for selecting one of the buffered input data infor and the input data new_infor transmitted in the current clock cycle according to the select signal. By setting the select signal to be valid in the first clock cycle T2 when both the handshake signals valid_to_slave and ready_to_coh are valid, the cache coherence unit 20 can output the buffered input data infor in the first clock cycle T2 when both the handshake signals valid_to_slave and ready_to_coh are valid, and start outputting the input data new_infor transmitted in the current clock cycle from the second clock cycle (the next clock cycle after clock cycle T2) when both the handshake signals valid_to_slave and ready_to_coh are valid. While optimizing the timing to avoid the loss of input data new_infor, it also ensures the continuity of data transmission, which is beneficial to achieving high-performance data transmission.
[0071] It should be noted that the technical solution disclosed herein is also applicable to the data transmission process in which the processor core reads data from the device 40 through the cache coherence unit 20, only requiring a reasonable modification to the received signal of the delay reverse voltage circuit 21.
[0072] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this disclosure and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of this disclosure.
Claims
1. A multi-core processor system, wherein, include: Multiple processor cores; A cache coherence unit, connected to the plurality of processor cores and slave devices, controls the data interaction between the slave devices and the plurality of processor cores to achieve cache coherence in the multi-core processor system. The cache coherence unit includes: The delayed reverse voltage circuit is used to buffer the input data transmitted in the previous clock cycle when outputting the input data transmitted in the current clock cycle, and to output the buffered input data first when the handshake state between the buffer coherence unit and the slave device changes from unsuccessful to successful. The delayed reverse voltage circuit includes: A logic control unit is configured to generate a selection signal based on a first handshake signal sent by the cache coherence unit to the slave device, a second handshake signal sent by the slave device to the cache coherence unit, and an information transmission request signal sent by the cache coherence unit to the slave device. The information transmission request signal is used to indicate whether there is a new information transmission request. The selection unit is used to buffer the input data transmitted in the previous clock cycle when outputting the input data transmitted in the current clock cycle, and to prioritize outputting the buffered input data when the handshake state between the buffer coherence unit and the slave device changes from unsuccessful to successful according to the selection signal.
2. The multi-core processor system according to claim 1, wherein, The cache coherence unit and the slave device are in a handshake success state when both the first handshake signal and the second handshake signal are valid. The selection unit outputs the cached input data in the first clock cycle when both the first handshake signal and the second handshake signal are valid, and outputs the input data transmitted in the current clock cycle starting from the second clock cycle when both the first handshake signal and the second handshake signal are valid.
3. The multi-core processor system according to claim 1, wherein, The selection unit includes: The first D flip-flop receives the input data transmitted in the current clock cycle at its input terminal. The first D flip-flop is used to buffer the input data transmitted in the previous clock cycle when outputting the input data transmitted in the current clock cycle and output it at the output terminal. A data selector has a first input terminal connected to the output terminal of the first D flip-flop and a second input terminal connected to the input terminal of the first D flip-flop. A control terminal receives the selection signal. When the selection signal is valid, the data selector outputs buffered input data, and when the selection signal is invalid, it outputs the input data transmitted in the current clock cycle. The selection signal is valid during the first clock cycle in which both the first handshake signal and the second handshake signal are valid.
4. The multi-core processor system according to claim 3, wherein, The first D flip-flop is enabled when the information transmission request signal is valid.
5. The multi-core processor system according to claim 1, wherein, The first handshake signal is configured to become active one clock cycle before the second handshake signal when there is an information transmission request, so that the selection signal is active during the first clock cycle in which both the first handshake signal and the second handshake signal are active.
6. The multi-core processor system according to claim 5, wherein, The selection unit includes: The first OR gate logic circuit has a first input terminal that receives the information transmission request signal and a second input terminal that receives the selection signal. The first NOR gate logic circuit has a first input terminal that receives the second handshake signal and a second input terminal that receives the first handshake signal through the first NOT gate logic circuit. The first AND gate logic circuit has its first input terminal connected to the output terminal of the first OR gate logic circuit, and its second input terminal connected to the output terminal of the first NOR gate logic circuit. The second D flip-flop has its signal input terminal connected to the output terminal of the first AND gate logic circuit, and its output terminal outputs the selection signal.
7. The multi-core processor system according to claim 5, wherein, The selection unit includes: The second OR gate logic circuit has a first input terminal that receives the information transmission request signal and a second input terminal that receives the selection signal. The second AND gate logic circuit has a first input terminal that receives the second handshake signal through the second NOT gate logic circuit, and a second input terminal that receives the first handshake signal. The third AND gate logic circuit has its first input terminal connected to the output terminal of the second OR gate logic circuit, and its second input terminal connected to the output terminal of the second AND gate logic circuit. The third D flip-flop has its signal input terminal connected to the output terminal of the third AND gate logic circuit, and the output terminal of the third D flip-flop outputs the selection signal.
8. A control method for a multi-core processor system, applied to the multi-core processor system as described in any one of claims 1-7, wherein, The control method includes: When data is exchanged between a device and multiple processor cores, a cache coherency unit is used to cache the input data transmitted in the previous clock cycle when outputting the input data transmitted in the current clock cycle. When the handshake state between the cache coherence unit and the slave device changes from unsuccessful to successful, the cached input data is output first.
9. The control method for a multi-core processor system according to claim 8, wherein, The cache coherence unit sends a first handshake signal to the slave device, and the slave device sends a second handshake signal to the cache coherence unit. The cache coherence unit outputs the cached input data in the first clock cycle when both the first handshake signal and the second handshake signal are valid, and starts outputting the input data transmitted in the current clock cycle from the second clock cycle when both the first handshake signal and the second handshake signal are valid.