Graphical display method and apparatus for clock structure of integrated circuit

Abstract

The embodiment of the present disclosure discloses a method and device for graphically displaying a clock structure of an integrated circuit, a computer readable storage medium and an electronic device, wherein the method comprises: obtaining a design file of the integrated circuit; extracting clock frequency division relationship information and clock attribute information from the design file; determining a first clock structure diagram representing the frequency division relationship between a plurality of clocks based on the clock frequency division relationship information; determining clock description information of each clock node in the clock structure diagram based on the clock frequency division relationship information and the clock attribute information; and generating a graphically displayed page based on the first clock structure diagram and the clock description information. The embodiment of the present disclosure automatically generates a graphically displayed page for displaying the clock structure diagram and the clock description information, which helps users to conveniently and accurately obtain the relationship between the clocks and the detailed information of the clocks, and improves the efficiency of integrated circuit design.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a method, apparatus, computer-readable storage medium, and electronic device for graphically displaying the clock structure of an integrated circuit. Background Technology

[0002] As integrated circuits become increasingly larger, the clock structures in integrated circuit designs are also becoming more complex. An integrated circuit may contain hundreds or even thousands of clocks, including the master clock and clocks divided from the master clock. Designers need to use design constraint documents (SDCs, Synopsys Design Constraints) to describe in detail the properties of each clock and the relationships between different clocks, while other designers also need to use design constraint documents to understand the properties of each clock. Because design constraint documents are plain text files and their content is quite cumbersome, the efficiency of designers consulting them is low.

[0003] To visually view the relationships between clocks defined in the design constraint file, the current common method is for designers to manually draw clock structure diagrams and then consult the clock constraint file. This requires designers to manually examine hundreds or thousands of clocks, making the workflow cumbersome, time-consuming, and prone to errors. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure is proposed. Embodiments of this disclosure provide a method, apparatus, computer-readable storage medium, and electronic device for graphically displaying the clock structure of an integrated circuit.

[0005] Embodiments of this disclosure provide a graphical display method for the clock structure of an integrated circuit. The method includes: acquiring the design file of the integrated circuit; extracting clock division relationship information and clock attribute information from the design file; determining a first clock structure diagram representing the division relationship between multiple clocks based on the clock division relationship information; determining clock description information for each clock node in the clock structure diagram based on the clock division relationship information and the clock attribute information; and generating a graphical display page based on the first clock structure diagram and the clock description information.

[0006] According to another aspect of the present disclosure, a graphical display device for the clock structure of an integrated circuit is provided. The device includes: an acquisition module for acquiring a design file of the integrated circuit; an extraction module for extracting clock division relationship information and clock attribute information from the design file; a first determination module for determining a first clock structure diagram representing the division relationship between multiple clocks based on the clock division relationship information; a second determination module for determining clock description information for each clock node in the clock structure diagram based on the clock division relationship information and the clock attribute information; and a generation module for generating a graphical display page based on the first clock structure diagram and the clock description information.

[0007] According to another aspect of the present disclosure, a computer-readable storage medium is provided, which stores a computer program for execution by a processor to implement a graphical display method for executing the clock structure of the integrated circuit described above.

[0008] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; and a method for graphically displaying the clock structure of the integrated circuit by reading the executable instructions from the memory and executing the instructions.

[0009] The graphical display method, apparatus, computer-readable storage medium, and electronic device for integrated circuit clock structures provided in the above embodiments of this disclosure acquire the integrated circuit design documents, extract clock division relationship information and clock attribute information from the design documents, then determine a first clock structure diagram representing the division relationship between multiple clocks based on the clock division relationship information, and determine the clock description information of each clock node in the clock structure diagram based on the clock division relationship information and clock attribute information. Finally, a graphical display page is generated based on the first clock structure diagram and the clock description information, thereby realizing the automated generation of a graphical display page for displaying clock structure diagrams and clock description information. Users can view detailed information about each clock through the clock structure diagram and clock description information, which helps users to conveniently and accurately understand the relationship between various clocks and the detailed information of the clocks, thereby improving the efficiency of integrated circuit design.

[0010] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0011] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0012] Figure 1 This is the system diagram to which this disclosure applies.

[0013] Figure 2 This is a flowchart illustrating a graphical display method for the clock structure of an integrated circuit provided in an exemplary embodiment of this disclosure.

[0014] Figure 3A This is an exemplary schematic diagram of a first clock structure diagram according to an embodiment of the present disclosure.

[0015] Figure 3B This is an exemplary schematic diagram of the descriptive information corresponding to a clock node in an embodiment of this disclosure.

[0016] Figure 4 This is a flowchart illustrating a method for graphically displaying the clock structure of an integrated circuit according to another exemplary embodiment of this disclosure.

[0017] Figure 5 This is a flowchart illustrating a method for graphically displaying the clock structure of an integrated circuit according to another exemplary embodiment of this disclosure.

[0018] Figure 6 This is a flowchart illustrating a method for graphically displaying the clock structure of an integrated circuit according to another exemplary embodiment of this disclosure.

[0019] Figure 7A This is an exemplary schematic diagram of a cascading relationship diagram of an embodiment of this disclosure.

[0020] Figure 7B This is an exemplary schematic diagram of a second clock structure according to an embodiment of the present disclosure.

[0021] Figure 8A This is an exemplary schematic diagram of a first search interface according to an embodiment of this disclosure.

[0022] Figure 8B This is an exemplary schematic diagram of a second search interface according to an embodiment of this disclosure.

[0023] Figure 9 This is a flowchart illustrating a method for graphically displaying the clock structure of an integrated circuit according to another exemplary embodiment of this disclosure.

[0024] Figure 10This is a schematic diagram of the structure of a graphical display device for an integrated circuit clock structure provided in an exemplary embodiment of the present disclosure.

[0025] Figure 11 This is a schematic diagram of the structure of a graphical display device for an integrated circuit clock structure provided in another exemplary embodiment of this disclosure.

[0026] Figure 12 This is a structural diagram of an electronic device provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0027] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present disclosure, and not all embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0028] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0029] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0030] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0031] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0032] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0033] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0034] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0035] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0036] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0037] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0038] The embodiments disclosed herein can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0039] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0040] Application Overview

[0041] The current method of manually drawing clock structure diagrams requires designers to look at hundreds or thousands of clocks with their naked eyes. The workflow is cumbersome, time-consuming, and prone to errors.

[0042] Currently, there are methods for automatically generating clock structure diagrams, but these diagrams typically only contain a simple logical structure with limited other information. For example, displaying clock names and clock definition paths on the logical structure diagram can result in cluttered diagrams when clock relationships are very complex. This makes it difficult for designers to understand the clock relationships and identify problems in the design documents.

[0043] Exemplary System

[0044] Figure 1 An exemplary system architecture 100 is shown, which illustrates a graphical display method for the clock structure of an integrated circuit or a graphical display device for the clock structure of an integrated circuit to which embodiments of the present disclosure may be applied.

[0045] like Figure 1 As shown, system architecture 100 may include terminal device 101, network 102, and server 103. Network 102 is used as a medium to provide a communication link between terminal device 101 and server 103. Network 102 may include various connection types, such as wired or wireless communication links or fiber optic cables, etc.

[0046] Users can use terminal device 101 to interact with server 103 via network 102 to receive or send messages, etc. Various communication client applications, such as search applications and web browser applications, can be installed on terminal device 101.

[0047] Terminal device 101 can be various electronic devices, including but not limited to mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (such as in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers.

[0048] Server 103 can be a server that provides various services, such as a backend server that supports the graphical display page on terminal device 101. The backend server can analyze the received text as a design file, obtain a graphical display page containing a clock structure diagram and clock description information, and send the graphical display page to terminal device 101.

[0049] It should be noted that the graphical display method of the clock structure of an integrated circuit provided in the embodiments of this disclosure can be executed by the server 103 or by the terminal device 101. Accordingly, the graphical display device of the clock structure of an integrated circuit can be set in the server 103 or in the terminal device 101.

[0050] It should be understood that Figure 1 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included. If the integrated circuit design documents do not need to be obtained remotely, the above system architecture may exclude networks and servers, including only terminal devices.

[0051] Exemplary methods

[0052] Figure 2 This is a flowchart illustrating a graphical display method for an integrated circuit clock structure provided in an exemplary embodiment of this disclosure. This embodiment can be applied to electronic devices (such as...). Figure 1 On the terminal device 101 or server 103 shown, such as Figure 2 As shown, the method includes the following steps:

[0053] Step 201: Obtain the design documents for the integrated circuit.

[0054] In this embodiment, the electronic device can obtain the design files of the integrated circuit from a local location or from a remote location.

[0055] The design file for an integrated circuit can be a file that defines the relationships between the various clocks of the integrated circuit. As an example, the design file may include, but is not limited to, at least one of the following: a design constraint (SDC, Synopsys DesignConstraints) file, and a timing library (lib) file.

[0056] Design constraint files are used to constrain the timing, area, and power consumption of integrated circuits, and are typically plain text files. Timing library files are used to define certain clocks, including information on the frequency division relationships between these clocks. For example, timing library files may include PMA (Physical Media Attachment) library files, which contain information on the frequency division relationships between certain clocks. This clock frequency division relationship information can be extracted from the PMA library files.

[0057] Step 202: Extract clock division relationship information and clock attribute information from the design documents.

[0058] In this embodiment, the electronic device can extract clock division relationship information and clock attribute information from the design documents.

[0059] The clock division information is used to define the division relationship between the master clock and the generated clock obtained by dividing the master clock.

[0060] As an example, frequency division relationship information and clock attribute information can be extracted from commands such as `create_clock` and `create_generated_clock` defined in the SDC file. This information includes the names, definition points, periods, frequency relationship information between the master clock and the divided clock (e.g., divided by), clock trigger edge information (edges), and trigger edge shift information (edge_shift). Among these, the period, frequency relationship information, trigger edge information, and trigger edge shift information can be used as frequency division relationship information, while the other information can be used as clock attribute information.

[0061] Step 203: Based on the clock division relationship information, determine the first clock structure diagram representing the division relationship between multiple clocks.

[0062] In this embodiment, the electronic device can determine a first clock structure diagram representing the frequency division relationship between multiple clocks based on clock frequency division relationship information.

[0063] like Figure 3A As shown, it illustrates a portion of the first clock structure diagram, in which each node represents a clock. For example, the node phy0_maplla_ana_word_clk_i is the master clock, and the four nodes connected to the master clock by lines represent frequency-divided clocks obtained by dividing the master clock.

[0064] Step 204: Based on the clock division relationship information and clock attribute information, determine the clock description information of each clock node in the clock structure diagram.

[0065] In this embodiment, the electronic device can determine the clock description information of each clock node in the clock structure diagram based on clock division relationship information and clock attribute information.

[0066] Each clock node represents a clock, and the corresponding clock description information describes the characteristics of the clock node in the form of displayable text. As an example, the clock description information for a clock may include a text box containing at least one of the following: the clock name, frequency and period, frequency division relationship information with other clocks (e.g., divided_by (defining the clock division ratio), edges (selecting a portion of the master clock's edges to create a divided clock), edge_shift (selecting a portion of the master clock's edges and adding an offset to create a divided clock), the clock node's path information, and other information (e.g., information defined by statements such as add (the current clock will not cover other clocks on the same path) and combined (when calculating the clock tree length, only combinational logic will be included, but sequential logic will not be included) in the SDC command).

[0067] like Figure 3B As shown, it illustrates an exemplary schematic diagram of the descriptive information corresponding to a clock node, which includes the clock node's name, attributes, clock frequency, clock period, and path information (Source).

[0068] Step 205: Generate a graphical display page based on the first clock structure diagram and clock description information.

[0069] In this embodiment, the electronic device can generate a graphical display page based on the first clock structure diagram and clock description information.

[0070] Specifically, electronic devices can automatically generate display page files, such as HTML (Hypertext Markup Language) files. Within these display page files, pre-defined scripts (such as JavaScript) can be invoked to add the aforementioned first clock structure diagram and clock description information to the graphical display page.

[0071] Optionally, since the first clock structure diagram includes a large number of clock nodes, for each master clock, its corresponding multiple frequency divider clocks can be collapsed or expanded under user control during display. The corresponding description information can be hidden by default. When a viewing operation is performed on a displayed clock node (e.g., the cursor moves to that clock node), a pop-up window will appear. Figure 3B The text box shown contains clock description information.

[0072] The method provided by the above embodiments of this disclosure obtains the design documents of an integrated circuit, extracts clock division relationship information and clock attribute information from the design documents, then determines a first clock structure diagram representing the division relationship between multiple clocks based on the clock division relationship information, and determines the clock description information of each clock node in the clock structure diagram based on the clock division relationship information and clock attribute information. Finally, a graphical display page is generated based on the first clock structure diagram and the clock description information, thereby realizing the automated generation of a graphical display page for displaying the clock structure diagram and clock description information. Users can view the detailed information of each clock through the clock structure diagram and clock description information, which helps users to conveniently and accurately understand the relationship between various clocks and the detailed information of the clocks, thereby improving the efficiency of integrated circuit design.

[0073] In some optional implementations, the design file includes a design constraint file and a timing library file. The design constraint file (SDC file) is used to constrain the timing, area, and power consumption of the integrated circuit, and is typically a plain text file. The timing library file also defines some clock division relationships; for example, the timing library file may include a PMA library file.

[0074] like Figure 4 As shown, step 202 includes:

[0075] Step 2021: Determine the clock generation information from the timing library file.

[0076] The clock generation information refers to the information defined in the timing library file used to generate the clock. For example, a clock generation command can be defined in the timing library. This command can include the name of the generated clock, the corresponding master clock, the division factor, etc. This information constitutes the clock generation information. Electronic devices can find the clock generation command in the timing library file and extract the clock generation information from the command.

[0077] Step 2022: Based on the clock generation information, generate the corresponding clock division relationship information in the design constraint file.

[0078] Specifically, in integrated circuit design tools, when generating clocks, specific clock generation statements (e.g., `create_clock`) are typically written into the design constraint file, along with the generated clock's hierarchy. However, the clock generation commands (e.g., `generated_clock`) in the timing library file differ from those in the design constraint file. When importing a timing library file into an integrated circuit design tool, it's impossible to generate commands identical to those in the design constraint file. Therefore, it's necessary to extract the clock paths defined in the timing library file and combine them with the clock paths generated in the design constraint file to determine the frequency division relationship between the clocks created in the timing library file and those created in the design constraint file.

[0079] As an example, a clock pin_b is created in the timing library file, which specifies that pin_b is a divided clock of pin_a, and defines the division relationship between pin_b and pin_a (e.g., pin_b is a 2-division clock of pin_a). After importing the timing library file into the integrated circuit design file, if a divided clock is created based on pin_a as the master clock, the path of the divided clock pin_b will be automatically created (e.g., u_wrapper / pma / pin_b). Therefore, the path of pin_b can be written into the design constraint file, and combined with the path of pin_a (e.g., u_wrapper / pma / pin_a), the division relationship information between pin_a and pin_b can be determined.

[0080] Step 2023: Extract clock division relationship information from the design constraint file.

[0081] This embodiment combines timing library files and design constraint files to determine clock division relationship information, which can automatically extract comprehensive clock division relationship information, so that the generated first clock structure diagram can fully reflect the clock structure of the integrated circuit.

[0082] In some alternative implementations, such as Figure 5 As shown, step 204 includes:

[0083] Step 2041: Based on the clock division relationship information of each clock node in the first clock structure diagram, determine the clock cycle information of each clock node.

[0084] The clock cycle information can include the clock period value or the clock frequency value. For example, if the frequency of the master clock A is known to be 1 GHz, then the period of clock A is 1 ns. If the divided clock B is a 2-fold division of the master clock A (e.g., the division statement is divided_by: 2), then the frequency of the divided clock B is 500 MHz, and thus the period of the divided clock B is determined to be 2 ns.

[0085] Step 2042: Based on the clock cycle information and attribute information of each clock node, determine the clock description information of each node.

[0086] Specifically, clock description information may include clock cycle information and other attribute information. For example... Figure 3B As shown, the clock description information in the text box includes clock frequency and clock period, which are the same as clock period information.

[0087] This embodiment generates clock cycle information based on clock division relationship information, and then displays the clock cycle information when displaying clock description information. This helps users directly view the clock cycle information. In cases where the clock division relationship is complex, it is easier to quickly identify potential problems when defining the clock. Compared to the solution of directly extracting statements such as divided_by from the design file and having the user determine the clock cycle information, this embodiment does not require manual determination of the clock cycle information, which helps to improve the efficiency of integrated circuit design.

[0088] In some alternative implementations, the design document includes a set of cascading relationship information representing the cascading relationships between clocks. Each cascading relationship information in the set includes cascading node type information. The cascading relationship information represents the physical connection relationship between clocks, and the cascading node type information represents the type of cascading node connecting the two clock nodes.

[0089] As an example, the cascading relationship information set is shown below:

[0090] clk_a,port,,clk_c

[0091] clk_b,port,,clk_c

[0092] clk_c,mux,clk_aclk_b,clk_dclk_e

[0093] clk_d,icg,clk_c,

[0094] clk_e,divider,clk_c,clk_f

[0095] clk_f,icg,clk_e,

[0096] In the example above, each line is formatted as follows: clock node name, cascade node type information, parent clock name, and child clock name. If no parent or child clock exists, leave it blank. In the example, clk_a-clk_f represents the name of the cascade node, port indicates the cascade node type is an input port, mux indicates the cascade node type is a clock selection switch, icg is the clock gating unit, and divider is the frequency divider unit.

[0097] like Figure 6 As shown, after step 201, the method further includes:

[0098] Step 206: Extract the cascading relationship information set from the design documents.

[0099] Specifically, a dedicated cascading relationship information extraction tool can be used to extract a set of cascading relationship information from the design documents. For example, in the integrated circuit synthesis design tool DesignCompiler, a preset TCL (ToolCommand Language) script can be used to extract the cascading relationship information set. Typically, a table file can be generated based on the extracted cascading relationship information set; for example, the table file can be a CSV (Comma-Separated Values) format file. Each row of data in the CSV file is shown in the example of the cascading relationship information set mentioned above.

[0100] Step 207: Generate the node icon corresponding to the cascading node type information included in each cascading relationship information set.

[0101] The shape and label of the node icon can be pre-defined, for example, by designing the node icon using CSS (Cascading Style Sheets) and JavaScript. Figure 7B As shown, port, mux, icg, and divider are all node icons.

[0102] Step 208: Based on each cascading relationship information in the cascading relationship information set, determine the connection lines to each node icon to obtain the second clock structure diagram.

[0103] Specifically, such as Figure 7A As shown, it illustrates the cascading relationship diagram between clock nodes corresponding to each cascading relationship information in the cascading relationship information set. This cascading relationship diagram is generated based on the example of the aforementioned cascading relationship information set. Each line in the diagram indicates that the two connected nodes have a hierarchical relationship. Optionally, a D3 JavaScript script can be used to draw the diagram as shown. Figure 7A The diagram shows the cascade relationship of clock nodes.

[0104] like Figure 7B As shown, it illustrates an exemplary schematic diagram of a second clock structure. Typically, it can be... Figure 7A Based on the cascading relationship diagram shown, set the icons of each node to their corresponding positions and adjust the connections between each clock node and the cascading nodes to generate a result as shown. Figure 7B The diagram shows the second clock structure.

[0105] Step 209: Display the second clock structure diagram on the graphical display page.

[0106] Optionally, the graphical display page may include a structure diagram selection component, which users can use to select and display the first clock structure diagram and / or the second clock structure diagram mentioned above.

[0107] This embodiment generates a second clock structure diagram representing the physical connections between clocks, allowing users to easily view these connections and providing an intuitive reference for integrated circuit design, thus improving the efficiency of integrated circuit design.

[0108] In some optional implementations, a search interface can be generated based on specific types of information included in the design file, such as clock relationship information and clock attribute information. This search interface is used to retrieve relevant information from the aforementioned specific types of information based on the input search keywords. Typically, the search interface may include, but is not limited to, at least one of the following: a first search interface for searching clock group relationship information, and a second search interface for searching target attribute information of the target clock.

[0109] That is, the method also includes:

[0110] Determine clock group relationship information from the design documents, and based on this information, generate a first search interface for searching clock group relationships; and / or,

[0111] Based on the clock attribute information, a second search interface is generated for searching the target clock's target attribute information.

[0112] Specifically, the clock group relationship information mentioned above can be extracted from information such as `set_clock_group` and `set_false_path` in the SDC file. The `set_clock_group` is divided into several categories, including: physically_exclusive, logically_exclusive, asynchronous, and asynchronous-allow_path.

[0113] The `set_false_path` parameter mentioned above is used to set asynchronous clocks. The format is roughly `set_false_path –from[get_clocks A] –to[get_clocks B]` and `set_false_path –from[get_clocks B] –to[get_clocksA]`, etc. This information is crucial for users designing integrated circuits. Therefore, a primary search interface can be set up in the graphical display page to allow users to search for relevant information between different clock groups.

[0114] As an example, such as Figure 8A The diagram shows a schematic of the first search interface, where "group type" is used to select group types such as all, physically_exclusive, logically_exclusive, asynchronous, asynchronous-allow_path, and false_path. "group1" and "group2" are used to specify the clocks to search for. Leaving them blank means matching all clocks.

[0115] If only one "clock A" is filled in in "group1" and "group2", and the other box is left empty, then all group information containing "A" and satisfying the "group type" will be searched.

[0116] If clock A is entered in "group1" and clock B is entered in "group2", then the search will find group information between A and B that meets the requirements specified in "group type". However, it will not search for information related to A and B being in the same group to avoid redundant information interfering with reading (for example, if there are sdc1: set_clock_group–async–group{AB}–group{C} and sdc2: set_clock_group–async–group{A}–group{B}, then only sdc2 will be displayed).

[0117] The SDC file also includes information such as `set_clock_uncertainty`, `set_clock_transition`, and `set_clock_latency`. Since these types of information are strongly correlated with different stages of integrated circuit design, they may have different values ​​at different stages. For example, different design stages may include, but are not limited to, at least one of the following: synthesis, floorplan, place (standard cell placement), CTS (clock tree synthesis), and route. In each of these stages, the aforementioned `set_clock_uncertainty`, `set_clock_transition`, and `set_clock_latency` information are set to different values. To avoid interference between various information types, a second search interface can be set up for separate searches to display specific target attribute information.

[0118] like Figure 8B As shown, the second search interface includes a drop-down menu and a search box. From the drop-down menu, you can select attribute information types such as all, uncertainty, transition, and latency. In the search box, you can enter the name of the clock, and the search results will be the target attribute information corresponding to the entered clock name.

[0119] This embodiment, by setting a first search interface and a second search interface on the graphical display page, enables users to freely search for clock groups to which any clock belongs and target attribute information of any clock, thereby enriching the functionality of the graphical display page. Users can view richer information more flexibly through the graphical display page, which helps to further improve the efficiency of integrated circuit design.

[0120] In some alternative implementations, the method also includes:

[0121] A page adjustment control interface for generating graphical display pages is provided, which is used to adjust the display mode of the graphical display pages.

[0122] As an example, the page adjustment control interface may include drop-down menus for selecting whether to display only the first clock structure diagram or the second clock structure diagram, only the first search interface or the second search interface, and combining different types of display interfaces. Furthermore, the page adjustment control interface can also be used to more graphically display the window size, window ratio, and the size of each interface within the window.

[0123] This embodiment allows users to flexibly adjust the display mode of the graphical display page by setting the page adjustment control interface, which helps users to flexibly view various clock-related information, thereby improving the efficiency of integrated circuit design.

[0124] In some alternative implementations, such as Figure 9 As shown, the method also includes:

[0125] Step 210: Perform a design constraint check to determine whether the design documents contain non-standard information that does not conform to the preset design constraint rules.

[0126] Non-standard information may include problems with the design file itself, such as the design file not being found or unreadable, or the design file output path being non-writable. Non-standard information may also include syntax problems within the design file (such as not specifying a clock name, not specifying the period of the master clock, or not specifying the division ratio of the divider clock), and integrity problems of the design file (such as the master clock specified in the command to generate the divider clock not being found).

[0127] The aforementioned design constraint check operation can be manually triggered by the user or executed automatically, and can be performed at any stage of the graphical display method of the clock structure of the integrated circuit, such as when extracting clock division relationship information and clock attribute information from the design file, or when generating the graphical display interface. The steps included in the embodiments of this disclosure are typically executed by running a preset script file (e.g., a Python script), that is, the script file includes code for executing the embodiments of this disclosure. As an example, if the operation of running the script file is triggered, a design constraint check operation can be performed during the script file's execution, checking for non-standard information in the design constraint file in real time. If non-standard information is detected, corresponding prompt information is output.

[0128] Step 211: In response to the design constraint file including non-standard information, output a prompt message about the non-standard information.

[0129] As an example, if clock_a is not defined, the output message can include the name and path of clock_a, as follows:

[0130] Clock not found:phy0 / pma / clock_a.

[0131] This embodiment determines non-standard information in the design documents by performing design constraint detection operations, thereby ensuring that the design documents conform to design constraint rules when generating graphical display pages, thus improving the accuracy of generating graphical display pages.

[0132] Exemplary device

[0133] Figure 10 This is a schematic diagram of a graphical display device illustrating the clock structure of an integrated circuit according to an exemplary embodiment of this disclosure. This embodiment can be applied to electronic devices, such as... Figure 10 As shown, the graphical display device for the clock structure of an integrated circuit includes: an acquisition module 1001 for acquiring the design file of the integrated circuit; an extraction module 1002 for extracting clock division relationship information and clock attribute information from the design file; a first determination module 1003 for determining a first clock structure diagram representing the division relationship between multiple clocks based on the clock division relationship information; a second determination module 1004 for determining the clock description information of each clock node in the clock structure diagram based on the clock division relationship information and the clock attribute information; and a first generation module 1005 for generating a graphical display page based on the first clock structure diagram and the clock description information.

[0134] In this embodiment, the acquisition module 1001 can acquire the design files of the integrated circuit from local or remote sources.

[0135] The design file for an integrated circuit can be a file that defines the relationships between the various clocks of the integrated circuit. As an example, the design file may include, but is not limited to, at least one of the following: a design constraint (SDC, Synopsys DesignConstraints) file, and a timing library (lib) file.

[0136] Design constraint files are used to constrain the timing, area, power consumption, and other aspects of integrated circuits, and are typically plain text files. Timing library files also define some clock division relationships; for example, timing library files may include PMA library files.

[0137] In this embodiment, the extraction module 1002 can extract clock division relationship information and clock attribute information from the design file.

[0138] The clock division information is used to define the division relationship between the master clock and the generated clock obtained by dividing the master clock.

[0139] As an example, frequency division relationship information and clock attribute information can be extracted from commands such as `create_clock` and `create_generated_clock` defined in the SDC file. This information includes the names, definition points, periods, frequency relationship information between the master clock and the divided clock (e.g., divided by), clock trigger edge information (edges), and trigger edge shift information (edge_shift). Among these, the period, frequency relationship information, trigger edge information, and trigger edge shift information can be used as frequency division relationship information, while the other information can be used as clock attribute information.

[0140] In this embodiment, the first determining module 1003 can determine a first clock structure diagram representing the frequency division relationship between multiple clocks based on clock frequency division relationship information.

[0141] like Figure 3A As shown, it illustrates a portion of the first clock structure diagram, in which each node represents a clock. For example, the node phy0_maplla_ana_word_clk_i is the master clock, and the four nodes connected to it by lines represent frequency-divided clocks obtained by dividing the master clock.

[0142] In this embodiment, the second determining module 1004 can determine the clock description information of each clock node in the clock structure diagram based on the clock division relationship information and the clock attribute information.

[0143] Each clock node represents a clock, and the corresponding clock description information describes the characteristics of the clock node in the form of displayable text. For example, the clock description information for a clock may include a text box containing at least one of the following: the clock name, frequency and period, frequency division relationship with other clocks (e.g., divided_by, edges, edge_shift, etc.), the clock node's path information, and other information (e.g., information defined by the add and combined statements in the SDC command).

[0144] like Figure 3B As shown, it illustrates an exemplary schematic diagram of the descriptive information corresponding to a clock node, which includes the clock node's name, attributes, clock frequency, clock period, and path information (Source).

[0145] In this embodiment, the generation module 1005 can generate a graphical display page based on the first clock structure diagram and clock description information.

[0146] Specifically, the generation module 1005 can automatically generate a display page file, such as an HTML (Hypertext Markup Language) file. Within the display page file, a pre-defined script (e.g., a D3 JavaScript script) can be invoked to add the aforementioned first clock structure diagram and clock description information to the graphical display page.

[0147] Reference Figure 11 , Figure 11 This is a schematic diagram of the structure of a graphical display device for an integrated circuit clock structure provided in another exemplary embodiment of this disclosure.

[0148] In some optional implementations, the design file includes a design constraint file and a timing library file; the extraction module 1002 includes: a first determining unit 10021, used to determine clock generation information from the timing library file; a generating unit 10022, used to generate corresponding clock division relationship information in the design constraint file based on the clock generation information; and an extraction unit 10023, used to extract clock division relationship information from the design constraint file.

[0149] In some optional implementations, the second determining module 1004 includes: a second determining unit 10041, used to determine the clock cycle information of each clock node based on the clock division relationship information of each clock node in the first clock structure diagram; and a third determining unit 10042, used to determine the clock description information of each node based on the clock cycle information of each clock node and the attribute information of each clock node.

[0150] In some optional implementations, the design document includes a set of cascading relationship information representing the cascading relationships between clocks, and each cascading relationship information in the set includes cascading node type information; the device further includes: a second extraction module 1006, used to extract the set of cascading relationship information from the design document; a second generation module 1007, used to generate node icons corresponding to the cascading node type information included in each cascading relationship information in the set; a third determination module 1008, used to determine the connection lines connected to each node icon based on each cascading relationship information in the set, to obtain a second clock structure diagram; and a display module 1009, used to display the second clock structure diagram on a graphical display page.

[0151] In some alternative implementations, the device further includes: a third generation module 1010, used to determine clock group relationship information from the design file and generate a first search interface for searching clock group relationships based on the clock group relationship information; and / or, a fourth generation module 1011, used to generate a second search interface for searching target attribute information of a target clock based on clock attribute information.

[0152] In some optional implementations, the device further includes a fifth generation module 1012 for generating a page adjustment control interface for a graphical display page, wherein the page adjustment control interface is used to adjust the display mode of the graphical display page.

[0153] In some alternative implementations, the device further includes: a checking module 1013 for performing a design constraint checking operation to determine whether the design document contains non-standard information that does not conform to preset design constraint rules; and an output module 1014 for outputting a prompt message about the non-standard information in response to the design constraint document containing non-standard information.

[0154] The graphical display device for the clock structure of an integrated circuit provided in the above embodiments of this disclosure acquires the design documents of the integrated circuit, extracts clock division relationship information and clock attribute information from the design documents, then determines a first clock structure diagram representing the division relationship between multiple clocks based on the clock division relationship information, and determines the clock description information of each clock node in the clock structure diagram based on the clock division relationship information and clock attribute information. Finally, a graphical display page is generated based on the first clock structure diagram and the clock description information, thereby realizing the automatic generation of a graphical display page for displaying the clock structure diagram and clock description information. Users can view the detailed information of each clock through the clock structure diagram and clock description information, which helps users to conveniently and accurately understand the relationship between various clocks and the detailed information of the clocks, thereby improving the efficiency of integrated circuit design.

[0155] Exemplary electronic devices

[0156] Below, for reference Figure 12 To describe an electronic device according to embodiments of the present disclosure. The electronic device may be as follows: Figure 1 The terminal device 101 and server 103 shown, or either one or both, or a standalone device independent of them, can communicate with the terminal device 101 and server 103 to receive the collected input signals from them.

[0157] Figure 12 A block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0158] like Figure 12As shown, the electronic device 1200 includes one or more processors 1201 and memory 1202.

[0159] The processor 1201 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1200 to perform desired functions.

[0160] The memory 1202 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1201 may execute the program instructions to implement the graphical display method of the clock structure of the integrated circuit in the various embodiments of this disclosure described above, and / or other desired functions. Various contents such as design documents may also be stored in the computer-readable storage medium.

[0161] In one example, the electronic device 1200 may also include an input device 1203 and an output device 1204, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0162] For example, when the electronic device is a terminal device 101 or a server 103, the input device 1203 can be a mouse, keyboard, or other similar device for inputting design documents, various commands, etc. When the electronic device is a standalone device, the input device 1203 can be a communication network connector for receiving input design documents, various commands, etc., from the terminal device 101 and the server 103.

[0163] The output device 1204 can output various information to the outside, including graphical display pages. The output device 1204 may include, for example, a monitor, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0164] Of course, for the sake of simplicity, Figure 12 Only some of the components of the electronic device 1200 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 1200 may include any other suitable components depending on the specific application.

[0165] Exemplary computer program products and computer-readable storage media

[0166] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the graphical display method for an integrated circuit clock structure according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0167] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0168] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the graphical display method of the clock structure of an integrated circuit according to various embodiments of this disclosure as described in the "Exemplary Methods" section above.

[0169] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0170] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0171] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0172] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0173] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0174] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0175] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0176] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A method for graphically displaying the clock structure of an integrated circuit, comprising: Obtain the design files of the integrated circuit, which include design constraint files and timing library files; Extract clock division relationship information and clock attribute information from the design documents; Based on the clock division relationship information, a first clock structure diagram representing the division relationship between multiple clocks is determined; Based on the clock division relationship information and the clock attribute information, determine the clock description information of each clock node in the clock structure diagram; A graphical display page is generated based on the first clock structure diagram and the clock description information; Extracting clock division relationship information from the design document includes: Determine the clock generation information from the timing library file; Based on the clock generation information, corresponding clock division relationship information is generated in the design constraint file. The clock division relationship information is determined by combining the clock path defined in the timing library file with the clock path generated in the design constraint file. Extract the clock division relationship information from the design constraint file; The step of determining the clock description information of each clock node in the clock structure diagram based on the clock division relationship information and the clock attribute information includes: Based on the clock frequency division relationship information of each clock node in the first clock structure diagram, the clock cycle information of each clock node is determined. Based on the clock cycle information and attribute information of each clock node, the clock description information of each node is determined.

2. The method according to claim 1, wherein, The design document includes a set of cascading relationship information representing the cascading relationship between clocks, and each cascading relationship information in the set of cascading relationship information includes cascading node type information; The method further includes: Extract the cascading relationship information set from the design file; Generate the node icon corresponding to the cascading node type information included in each cascading relationship information set; Based on each cascading relationship information in the cascading relationship information set, the connection line to each node icon is determined to obtain the second clock structure diagram; The second clock structure diagram is displayed on the graphical display page.

3. The method according to claim 1, wherein, Also includes: The clock group relationship information is determined from the design file, and a first search interface for searching the group relationships of clocks is generated based on the clock group relationship information. And / or, Based on the clock attribute information, a second search interface is generated for searching the target attribute information of the target clock.

4. The method according to claim 1, wherein, Also includes: A page adjustment control interface for generating the graphical display page is provided, wherein the page adjustment control interface is used to adjust the display mode of the graphical display page.

5. The method according to claim 1, wherein, The method further includes: Perform a design constraint check to determine whether the design documents contain non-standard information that does not conform to preset design constraint rules; In response to the design constraint file including the non-standard information, a prompt message regarding the non-standard information is output.

6. A graphical display device for an integrated circuit clock structure, comprising: The acquisition module is used to acquire the design files of the integrated circuit, which include design constraint files and timing library files; The extraction module is used to extract clock division relationship information and clock attribute information from the design file; The extraction module includes a first determining unit, a generating unit, and an extraction unit; The first determining unit is used to determine clock generation information from the timing library file; The generation unit is used to generate corresponding clock frequency division relationship information in the design constraint file based on the clock generation information. The clock frequency division relationship information is determined by combining the clock path defined in the timing library file with the clock path generated in the design constraint file. The extraction unit is used to extract the clock division relationship information from the design constraint file; The first determining module is used to determine a first clock structure diagram representing the frequency division relationship between multiple clocks based on the clock frequency division relationship information; The second determining module is used to determine the clock description information of each clock node in the clock structure diagram based on the clock division relationship information and the clock attribute information; The second determining module includes a second determining unit and a third determining unit. The second determining unit is used to determine the clock cycle information of each clock node based on the clock division relationship information of each clock node in the first clock structure diagram. The third determining unit is used to determine the clock description information of each node based on the clock cycle information of each clock node and the attribute information of each clock node. The generation module is used to generate a graphical display page based on the first clock structure diagram and the clock description information.

7. A computer-readable storage medium storing a computer program for execution by a processor to implement the method of any one of claims 1-5.

8. An electronic device, the electronic device comprising: processor; Memory for storing the executable instructions of the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method described in any one of claims 1-5.

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