Method, apparatus and electronic device for shortening image display delay

Abstract

The application provides a method and device for shortening image display delay and an electronic device. In the application, the conventional installation mode (inverted mode) of a display module in a medical display is broken, the display module is installed in a forward direction, and under the premise of the forward installation of the display module, the SOC chip is controlled to disable the original image processing functions of the SOC chip, such as frame rate completion function, frame rate conversion function, image rotation function and image cache function. Compared with the prior art, the delay of the medical display is optimized, and the image display delay time is shortened. Tests show that the delay can be shortened by at least 19 ms.

Description

Technical Field

[0001] This application relates to image display technology, and more particularly to methods, apparatus and electronic devices for reducing image display latency. Background Technology

[0002] In medical applications, there are stringent latency requirements for medical systems (including medical displays, mainframes, and imaging systems), such as a requirement that the latency of the entire medical system not exceed 70 milliseconds (ms). However, in practice, the medical display itself within the entire medical system has a latency of at least 50 ms, resulting in an image display delay of at least 50 ms. In medical applications such as surgical procedures, this 50 ms image display delay poses significant medical risks. Summary of the Invention

[0003] This application provides methods, apparatus, and electronic devices for reducing image display latency, thereby reducing the latency of medical displays for image display.

[0004] This application provides at least the following solutions:

[0005] A method for reducing image display latency, applied to a medical display, the medical display including at least a SOC chip, an FPGA chip, and a display module; the SOC chip is configured to perform image processing functions; the image processing functions include at least: frame rate padding, frame rate conversion, image rotation, and image buffering; the display module is used for image display, and the FPGA chip is newly deployed with a latency reduction module, the latency reduction module being used to reduce the latency of the display module in displaying the image; the method includes:

[0006] The mounting structure of the display module is obtained through the delay reduction module; the mounting structure is a normal mounting structure or an inverted mounting structure; the normal mounting structure is used to indicate that the display module is mounted in the normal direction, and the inverted mounting structure is used to indicate that the display module is mounted in the inverted direction;

[0007] If the mounting structure is a standard mounting structure, then the delay reduction module communicates with the SOC chip to disable the image processing function that has been configured on the SOC chip.

[0008] When the delay reduction module detects that the FPGA chip receives an image frame output by the SOC chip after the image processing function is disabled, it controls the FPGA chip to transmit the image frame forwarded by the SOC chip from the signal source to the display module for display at the frame rate required by the display module.

[0009] An apparatus for reducing image display latency is applied to a medical display, the medical display including at least a SOC chip, an FPGA chip, and a display module; the SOC chip is configured to perform image processing functions; the image processing functions include at least: frame rate padding, frame rate conversion, image rotation, and image buffering; the display module is used for image display, and the FPGA chip is newly equipped with a latency reduction module for reducing the latency of the display module in displaying images; the apparatus includes:

[0010] A receiving unit is used to obtain the mounting structure of the display module; the mounting structure is a forward mounting structure or an inverted mounting structure; the forward mounting structure is used to indicate that the display module is mounted in the forward direction, and the inverted mounting structure is used to indicate that the display module is mounted in the inverted direction;

[0011] The processing unit is configured to communicate with the SOC chip when the mounting structure is a standard mounting structure, so as to disable the image processing function that has been configured on the SOC chip.

[0012] The control unit is used to control the FPGA chip to transmit the image frames forwarded by the SOC chip from the signal source to the display module for display at the frame rate required by the display module after the SOC chip outputs the image frames after the image processing function is disabled.

[0013] This application also provides an electronic device. The electronic device includes: a processor and a machine-readable storage medium;

[0014] The machine-readable storage medium stores machine-executable instructions that can be executed by the processor;

[0015] The processor is used to execute machine-executable instructions to implement the steps of the disclosed method.

[0016] As can be seen from the above technical solutions, this application breaks with the conventional installation method (inverted mounting) of display modules in medical monitors. By installing the display module upright, and under the premise of upright installation, controlling the SOC chip to disable its original image processing functions such as frame rate completion, frame rate conversion, image rotation, and image caching, this optimizes the latency of medical monitors and shortens the image display delay time compared to existing methods. Tests have shown that it can shorten the latency by at least 19ms. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0018] Figure 1 A structural diagram of a medical display provided in an embodiment of this application;

[0019] Figure 2 A flowchart illustrating the method provided in this application embodiment;

[0020] Figure 3 This is a schematic diagram of display control provided in an embodiment of this application;

[0021] Figure 4 This is a structural diagram of the device provided in the embodiments of this application;

[0022] Figure 5 This is a structural diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0024] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application are also intended to include the plural forms unless the context clearly indicates otherwise.

[0025] To enable those skilled in the art to better understand the technical solutions provided in the embodiments of this application, and to make the above-mentioned objectives, features and advantages of the embodiments of this application more apparent and understandable, the technical solutions in the embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0026] See Figure 1 , Figure 1 An example is shown illustrating the structure of the main components in a medical display. For example... Figure 1 As shown, a medical display includes at least: a system-on-a-chip (SOC), an FPGA chip, and a display module.

[0027] The inventors of this application, through inventive analysis of the operations performed by the main components in a medical display, discovered that applications such as... Figure 1 The image display delay shown in the medical monitor is mainly caused by the image processing performed by the SOC chip in the medical monitor.

[0028] As an example, the SOC chip performs image processing based on the image processing functions configured on the SOC. These image processing functions include, for example, image rotation, image buffering, frame rate conversion, and frame rate padding.

[0029] The frame rate padding function mentioned above is designed based on the requirements of the FPGA chip in the medical display. It is used to ensure that the image frames output from the SOC chip to the FPGA chip are all complete frames. In specific implementation, if the image frame entering the SOC is not a complete frame, the SOC chip will need to buffer it to a complete frame before outputting it to the FPGA chip.

[0030] The aforementioned frame rate conversion function is used to enable the SOC chip to transmit image frames at the frame rate required by the display module in the medical monitor. In specific implementation, if the transmission frame rate of the image frames received by the SOC chip differs from the frame rate required by the display module, the SOC chip will first perform image frame buffering processing when transmitting image frames to the display module to adjust the transmission frame rate of the received image frames to the frame rate required by the display module. For example, if the transmission frame rate of the received image frames is 30 Hz, and the frame rate required by the display module is 60 Hz, then image frame buffering processing can be performed to interpolate the received image frames from 30 Hz to 60 Hz. Afterward, image frames can be transmitted at the frame rate required by the display module in the medical monitor.

[0031] The aforementioned image rotation function is used to control image rotation. In current applications, to ensure medical displays pass EMC testing, the display module in the medical display is often installed in an inverted configuration (this is also considered an inverted structure). Here, inverted configuration means the display module is installed upside down. Once the display module in the medical display is installed in an inverted configuration, the direction (which is forward) of the image frame that the signal source needs to send to the display module is mismatched with this inverted structure. Under this premise, when the SOC chip outputs the image frame from the signal source to the display module, in order to ensure that the image frame is displayed normally, the SOC chip will flip the image frame based on the aforementioned image rotation function, for example, flipping the image frame 180 degrees, before outputting it to the display module.

[0032] The aforementioned image caching function is used to implement image caching by the SOC chip. For example, when performing frame rate completion based on the aforementioned frame rate completion function, image frames are cached to ensure that a complete frame of image is output to the FPGA; when performing frame rate conversion based on the aforementioned frame rate conversion function, image frames are cached to ensure that the SOC chip transmits image frames to the display module according to the frame rate required by the display module; when performing image flipping based on the aforementioned image flipping function, image frames are cached to ensure that the SOC chip transmits image frames that can be displayed normally on the display module to the display module based on the mounting structure of the display module, etc.

[0033] Based on the above description, in order to shorten the image display latency of medical displays, this embodiment creatively analyzes the performance of the main components in the medical display and discovers that, without affecting the normal image display of the medical display, the existing display logic and structure of the medical display can be adjusted. For details, please refer to... Figure 2 The process shown is as follows:

[0034] See Figure 2 , Figure 2 This is a flowchart illustrating a method provided in an embodiment of this application. The method is applied to, for example... Figure 1 The medical display shown is an example of an improvement on existing medical displays. In this embodiment, the FPGA chip in the medical display is further improved by adding (or deploying) a latency reduction module to the FPGA chip. This latency reduction module is used to shorten the latency of the image displayed by the display module. A detailed analysis follows:

[0035] like Figure 2 As shown, the process may include the following steps:

[0036] Step 201: Obtain the mounting structure of the display module through the aforementioned delay reduction module.

[0037] In this embodiment, the display module itself has a corresponding driver, which can record the attribute information of the display module into the register of the display module. Here, the attribute information of the display module may include, for example, the installation structure of the display module, unusable display units in the display module, etc., which are not specifically limited in this embodiment. As an example, the installation structure of the display module in the above-mentioned medical display can be set when the display is manufactured. As for whether the set installation structure of the display module is installed forward or backward, as an example, it can be indicated by the corresponding installation label. For example, if the installation label indicates forward installation, the driver can record the installation structure of the display module as forward installation into the register of the display module; if the installation label indicates backward installation, the driver can record the installation structure of the display module as backward installation into the register of the display module. Of course, as another embodiment, whether the set installation structure of the display module is installed forward or backward can also be derived from the current installation parameters of the display module, such as the interface positions on the display module. For example, the installation parameter is the orientation of the interface on the display module. If the interface on the display module is facing downwards (normally, when the display module is installed upright, the interface on the display module faces downwards), then the installation structure of the display module can be recorded as upright installation in the display module's register; if the interface on the display module is facing upwards (normally, when the display module is installed upside down, the interface on the display module faces upwards), then the installation structure of the display module can be recorded as upside down installation in the display module's register.

[0038] Based on this, optionally, in step 201, the mounting structure of the display module recorded in the register of the display module can be read through the aforementioned delay reduction module, thus ultimately achieving the acquisition of the mounting structure of the display module through the aforementioned delay reduction module. It should be noted that the reason for obtaining the mounting structure of the display module through the aforementioned delay reduction module in this embodiment is that, unlike the prior art, this embodiment does not require the mounting structure of the display module to be an inverted structure in order to meet EMC testing. In this embodiment, the mounting structure of the display module can also be a regular mounting structure. Under this premise, this embodiment will adaptively and dynamically adjust the processing logic of each component inside the medical display, such as the SOC chip and FPGA chip, based on different mounting structures of the display module, as illustrated below.

[0039] Step 202: If the mounting structure is a standard mounting structure, then the above-mentioned delay reduction module communicates with the above-mentioned SOC chip to disable the image processing function that has been configured on the SOC chip.

[0040] In this embodiment, the aforementioned delay reduction module can communicate according to the protocol between the FPGA chip and the SOC chip, so that the SOC chip disables the image processing functions configured on the SOC chip as described above.

[0041] After disabling the aforementioned image processing function in the SOC chip, when the SOC chip subsequently receives an image frame from the signal source destined for the display module, it will no longer perform corresponding image processing on the received image frame based on this function. Correspondingly, since the SOC chip no longer performs corresponding image processing on the received image frame based on the aforementioned image processing function, the aforementioned delay will not occur.

[0042] Step 203: When the delay reduction module detects that the FPGA chip receives the image frame output by the SOC chip after the above image processing function is disabled, it controls the FPGA chip to transmit the image frame forwarded by the SOC chip from the signal source to the display module for display according to the frame rate required by the display module.

[0043] In this embodiment, although the SOC chip no longer performs corresponding image processing on the received image frames based on the aforementioned image processing function, step 203 still ensures normal display of the display module by controlling the FPGA chip to transmit the image frames forwarded from the signal source by the SOC chip to the display module for display according to the frame rate required by the display module through the delay shortening module. The specific reasons are described below:

[0044] Specifically, in the application, the image frame sent by the signal source is forward-facing, which matches the forward-facing structure of the display module. Under this premise, even if the image flipping function in the above image processing function is disabled by the SOC chip, there is no need to add an image flipping function on other components such as the FPGA chip.

[0045] Specifically, in applications, display modules typically require a specific frame rate (i.e., refresh rate) for image frames to ensure optimal display quality, such as 50Hz or 60Hz. If the frame rate of the image frames transmitted by the signal source does not meet the display module's requirements—for example, if the signal source transmits image frames at 25Hz or 30Hz, while the display module requires 50Hz or 60Hz—then the frame rate conversion function deployed in the FPGA chip can be enabled through the aforementioned latency reduction module. This allows the FPGA chip to control the transmission of image frames from the signal source based on the frame rate conversion function, ensuring that the image frames are transmitted to the display module at the required frame rate. Here, the frame rate conversion function is similar to the one described above; its ultimate goal is for the FPGA chip to transmit image frames to the display module at the required frame rate. Optionally, frame rate conversion can be achieved through frame interpolation or buffering of image frames. Of course, if the frame rate of the image frames transmitted by the signal source meets the frame rate required by the display module, the FPGA chip can be controlled to directly transmit the received image frames to the display module for display. Ultimately, the above description provides an embodiment of controlling the FPGA chip to transmit image frames forwarded from the signal source by the SOC chip to the display module for display at the frame rate required by the display module. Figure 3 An example diagram is shown.

[0046] It should be noted that, as described above, since the FPGA chip itself is used for image processing and has relatively high performance to perform image processing, the latency caused by the FPGA chip to perform the above frame rate conversion is relatively low and can be ignored.

[0047] Specifically, in applications, FPGA chips typically require image frames sent from SOC chips to the FPGA chip to be complete frames (e.g., meeting preset image frame integrity requirements). In this embodiment, even if the image frame sent from the SOC chip to the FPGA chip is not a complete frame (e.g., does not meet preset image frame integrity requirements), the aforementioned delay shortening module can control the FPGA chip to discard the received incomplete image frame. It should be noted that in this embodiment, as described above, the FPGA chip transmits image frames to the display module for display according to the frame rate required by the display module. This is equivalent to the FPGA chip controlling the frame rate of the image frames transmitted to the display module (also equivalent to controlling the refresh rate of the display module). Under this premise, even if the image frame sent from the SOC chip to the FPGA chip is not a complete frame, discarding the incomplete image frame will not affect the display of the entire display module. Therefore, even if the image processing function disabled by the SOC chip includes the aforementioned frame rate padding function, there is no need to add frame rate padding functionality to other components such as the FPGA.

[0048] This concludes the process. Figure 2 The process is shown below.

[0049] pass Figure 2 As shown in the flowchart, this embodiment breaks away from the conventional installation method (inverted mounting) of display modules in medical displays. By installing the display module upright, and under the premise of upright installation, controlling the SOC chip to disable its original image processing functions such as frame rate completion, frame rate conversion, image rotation, and image caching, this optimizes the latency of the medical display and shortens the image display delay time compared to existing methods. Tests have shown that it can shorten the latency by at least 19ms.

[0050] In applications where the display module is mounted in a standard configuration, to prevent EMC test failures due to the standard mounting structure, as an example, a shielding module can be deployed on the medical display. The shielding module is used to eliminate EMC test failures caused by the standard mounting structure of the display module.

[0051] As another embodiment, at least one known component in the medical display can be improved to eliminate EMC test failures caused by the display module's upright mounting structure. For example, when the known component is the circuit board containing the interface on the display module, the improvement refers to increasing the thickness of the circuit board; when the known component is the back panel of the medical display, the improvement refers to adding at least one grounding component, such as a screw, to the back panel to prevent excessive current or voltage from causing melting and thus EMC test failure.

[0052] It should be noted that, in this embodiment, if the mounting structure of the display module is a flip-chip structure, then when it is discovered that the image processing function configured on the SOC chip was disabled when the mounting structure was previously known to be a standard mounting structure, as an example, the latency reduction module can communicate with the SOC chip to enable the image processing function configured on the SOC chip. Correspondingly, to avoid repeatedly executing the same image processing, frame rate conversion functions and other functions deployed on the FPGA chip that were previously enabled when the mounting structure was a standard mounting structure can be disabled accordingly.

[0053] After the SOC chip enables the aforementioned image processing function configured on the SOC chip, when the SOC chip subsequently receives an image frame from the signal source destined for the display module, it will perform image processing on the image frame based on the enabled image processing function and output it to the FPGA chip. The FPGA chip can then output the image frame to the display module for display in the existing manner.

[0054] The methods provided in the embodiments of this application have been described above. The apparatus provided in the embodiments of this application is described below:

[0055] See Figure 4 , Figure 4 This is a structural diagram of a device provided in an embodiment of this application. The device is applied to a medical display, which includes at least a SOC chip, an FPGA chip, and a display module. The SOC chip is configured to perform image processing functions. The image processing functions include at least: frame rate completion, frame rate conversion, image rotation, and image buffering. The display module is used for image display, and the FPGA chip has a newly deployed latency reduction module for reducing the latency of the image displayed by the display module. The device includes:

[0056] A receiving unit is used to obtain the mounting structure of the display module; the mounting structure is a standard mounting structure or an inverted mounting structure.

[0057] The processing unit is configured to communicate with the SOC chip when the mounting structure is a standard mounting structure, so as to disable the image processing function that has been configured on the SOC chip.

[0058] The control unit is used to control the FPGA chip to transmit the image frames forwarded by the SOC chip from the signal source to the display module for display at the frame rate required by the display module after the SOC chip outputs the image frames after the image processing function is disabled.

[0059] Optionally, controlling the FPGA chip to transmit the image frames forwarded by the SOC chip from the signal source to the display module for display at the frame rate required by the display module includes:

[0060] If the frame rate of the image frame transmitted by the signal source meets the frame rate required by the display module, then the FPGA chip is controlled to directly transmit the image frame to the display module for display.

[0061] If the frame rate of the image frame transmitted by the signal source does not meet the frame rate required by the display module, the frame rate conversion function deployed in the FPGA chip is enabled, so that the FPGA chip controls the transmission of the image frame from the signal source based on the frame rate conversion function, so that the image frame is transmitted to the display module for display according to the frame rate required by the display module.

[0062] Optionally, if the mounting structure is a standard mounting structure, the medical display is also equipped with a shielding module; the shielding module is used to eliminate EMC test failures caused by the standard mounting structure of the display module.

[0063] or,

[0064] If the mounting structure is a standard mounting structure, at least one known component in the medical display is improved to eliminate EMC test failures caused by the standard mounting structure of the display module; wherein, when the known component is the board containing the interface on the display module, the improvement of the known component means that the thickness of the board is increased; when the known component is the back panel of the medical display, the improvement of the known component means that at least one grounding component for grounding is added to the back panel.

[0065] This concludes the process. Figure 4 The hardware structure diagram of the device is shown.

[0066] This application also provides embodiments that... Figure 4 The hardware structure of the device shown. See also Figure 5 , Figure 5This is a structural diagram of an electronic device provided in an embodiment of this application. Figure 5 As shown, the hardware structure may include: a processor and a machine-readable storage medium, the machine-readable storage medium storing machine-executable instructions that can be executed by the processor; the processor is used to execute the machine-executable instructions to implement the method disclosed in the above example of this application.

[0067] Based on the same application concept as the above method, this application embodiment also provides a machine-readable storage medium storing a plurality of computer instructions, which, when executed by a processor, can implement the method disclosed in the above examples of this application.

[0068] For example, the aforementioned machine-readable storage medium can be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, etc. For instance, machine-readable storage media can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drives (such as hard disk drives), solid-state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or combinations thereof.

[0069] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which can take the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email sending and receiving device, game console, tablet computer, wearable device, or any combination of these devices.

[0070] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0071] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0072] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0073] Furthermore, these computer program instructions can also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in the process. Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0074] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0075] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for shortening image display delay, characterized in that, This method is applied to medical displays, which include at least a SOC chip, an FPGA chip, and a display module; The SOC chip is at least configured with image processing functions for performing image processing on the SOC chip; The image processing functions include at least: frame rate completion, frame rate conversion, image rotation, and image caching; the display module is used for image display at least, and a latency reduction module has been newly deployed on the FPGA chip to reduce the latency of the display module displaying the image; the method includes: The mounting structure of the display module is obtained through the delay reduction module; If the mounting structure is a forward mounting structure, which indicates that the display module is mounted in the correct orientation, then the delay reduction module communicates with the SOC chip to disable the image processing function that has been configured on the SOC chip; wherein, the medical display is also equipped with a shielding module, or at least one known component in the medical display is modified to eliminate EMC test failures caused by the forward mounting structure of the display module; When the delay reduction module detects that the FPGA chip receives an image frame output by the SOC chip after the image processing function is disabled, it controls the FPGA chip to transmit the image frame forwarded by the SOC chip from the signal source to the display module for display at the frame rate required by the display module.

2. The method according to claim 1, characterized in that, The step of controlling the FPGA chip to transmit image frames forwarded from the signal source by the SOC chip to the display module for display at the frame rate required by the display module includes: If the frame rate of the image frame transmitted by the signal source meets the frame rate required by the display module, then the FPGA chip is controlled to directly transmit the image frame to the display module for display. If the frame rate of the image frame transmitted by the signal source does not meet the frame rate required by the display module, the frame rate conversion function deployed in the FPGA chip is enabled, so that the FPGA chip controls the transmission of the image frame from the signal source based on the frame rate conversion function, so that the image frame is transmitted to the display module for display according to the frame rate required by the display module.

3. The method according to claim 1, characterized in that, When the known component is the board where the interface on the display module is located, the improvement of the known component means that the thickness of the board is increased; when the known component is the back plate of the medical display, the improvement of the known component means that at least one grounding component for grounding is added to the back plate.

4. The method according to claim 1, characterized in that, The method further includes: If the mounting structure is an inverted structure, which indicates that the display module is mounted upside down, then if it is discovered that the image processing function configured on the SOC chip was disabled when it was previously known that the mounting structure was an upright structure, the delay reduction module communicates with the SOC chip to enable the image processing function configured on the SOC chip.

5. The method according to claim 1, characterized in that, The installation structure for obtaining the display module through the delay reduction module includes: The delay reduction module reads the installation structure of the display module recorded in the register of the display module.

6. The method according to claim 2, characterized in that, The display module requires a frame rate of 50Hz or 60Hz.

7. An apparatus for shortening image display delay, characterized in that, This device is used in medical displays, which include at least a SOC chip, an FPGA chip, and a display module. The SOC chip is at least configured with image processing functions for performing image processing on the SOC chip; The image processing functions include at least: frame rate completion, frame rate conversion, image rotation, and image buffering; the display module is used for image display at least; the FPGA chip has a newly deployed latency reduction module, which is used to reduce the latency of the display module displaying the image; the device includes: A receiving unit is used to obtain the mounting structure of the display module; A processing unit is configured to, when the mounting structure is a forward mounting structure, instruct the display module to be mounted in the correct orientation, communicate with the SOC chip to disable the image processing function that has been configured on the SOC chip; wherein the medical display is further equipped with a shielding module, or at least one known component in the medical display is modified to eliminate EMC test failures caused by the forward mounting structure of the display module; The control unit is used to control the FPGA chip to transmit the image frames forwarded by the SOC chip from the signal source to the display module for display at the frame rate required by the display module after the SOC chip outputs the image frames after the image processing function is disabled.

8. The apparatus according to claim 7, characterized in that, The step of controlling the FPGA chip to transmit image frames forwarded from the signal source by the SOC chip to the display module for display at the frame rate required by the display module includes: If the frame rate of the image frame transmitted by the signal source meets the frame rate required by the display module, then the FPGA chip is controlled to directly transmit the image frame to the display module for display. If the frame rate of the image frame transmitted by the signal source does not meet the frame rate required by the display module, the frame rate conversion function deployed in the FPGA chip is enabled, so that the FPGA chip controls the transmission of the image frame from the signal source based on the frame rate conversion function, so that the image frame is transmitted to the display module for display according to the frame rate required by the display module.

9. The apparatus according to claim 7, characterized in that, When the known component is the board where the interface on the display module is located, the improvement of the known component means that the thickness of the board is increased; when the known component is the back plate of the medical display, the improvement of the known component means that at least one grounding component for grounding is added to the back plate.

10. An electronic device, characterized in that, The electronic device includes: a processor and a machine-readable storage medium; The machine-readable storage medium stores machine-executable instructions that can be executed by the processor; The processor is configured to execute machine-executable instructions to implement the method steps of any one of claims 1-6.

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