Method for adjusting polysilicon resistance and semiconductor device

Abstract

The application provides a polysilicon resistance adjusting method and a semiconductor device, and is applied to the technical field of semiconductor devices, wherein the polysilicon resistance adjusting method comprises the following steps: adjusting the resistance of polysilicon by the discharge effect of electrons in an etching process. Compared with the prior art, the resistance of polysilicon is adjusted by ion implantation on the layer where the polysilicon is located, and the resistance adjusting range of the polysilicon is larger, and the cost is relatively low.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, specifically to a method for adjusting the resistance of polysilicon and a semiconductor device. Background Technology

[0002] Polycrystalline silicon possesses semiconductor properties and is an extremely important and excellent semiconductor material. Polycrystalline silicon requires heavy ion doping to reduce its resistivity. Currently, the resistance of polycrystalline silicon is generally achieved through ion implantation. By varying the implantation energy and implantation time, the resistance value of polycrystalline silicon can be adjusted to meet the different resistance requirements of various customers.

[0003] like Figure 1 As shown, in the prior art, during the device formation process in the front end of semiconductor manufacturing, a first oxide layer is deposited on the semiconductor substrate, and polysilicon is deposited on the first oxide layer. Then, the resistance of the polysilicon can be adjusted by ion implantation. Different implantation energies and implantation times are generally used to adjust the resistance to meet different customer requirements.

[0004] However, the ion implantation method, which involves adjusting the implantation energy and implantation time, has the drawbacks of a small range for adjusting the resistance of polycrystalline silicon and relatively high cost.

[0005] Therefore, a new technical solution for adjusting the resistance of polysilicon is needed. Summary of the Invention

[0006] In view of this, embodiments of this specification provide a method and semiconductor device for adjusting the resistance of polycrystalline silicon, in order to solve the technical problems of small adjustment range and high cost of polycrystalline silicon resistance caused by the prior art method of adjusting polycrystalline silicon resistance by adjusting the implantation energy and implantation time.

[0007] The embodiments in this specification provide the following technical solutions:

[0008] Firstly, embodiments of this specification provide a method for adjusting the resistance of polysilicon, including:

[0009] The resistance of polysilicon is adjusted by the discharge effect of electrons during the etching process.

[0010] The above technical solution adjusts the resistance of polysilicon during the etching process through the discharge effect of electrons. Compared with the existing technology, adjusting the resistance of polysilicon during the etching process can achieve flexible adjustment of the polysilicon resistance. Moreover, compared with the ion implantation method, it can reduce the cost of adjusting the polysilicon resistance.

[0011] In an alternative embodiment, prior to adjusting the resistance of the polysilicon through the discharge effect of electrons during the etching process, the method further includes:

[0012] The resistance of the polycrystalline silicon is adjusted by ion implantation on the surface of the polycrystalline silicon.

[0013] The above technical solution can combine the adjustment of polysilicon resistance during ion implantation and etching, making the range of polysilicon resistance adjustment wider and more precise, thereby reducing the polysilicon resistance adjustment while improving the adjustment accuracy.

[0014] In one optional implementation, adjusting the resistance of polysilicon during the etching process through the discharge effect of electrons includes:

[0015] During the etching process, plasma is applied to the polycrystalline silicon through the discharge effect of electrons via metal wires, thereby adjusting the resistance of the polycrystalline silicon. The metal wires consist of a metal layer and corresponding connecting holes.

[0016] Through the above technical solution, during the etching process, plasma is applied to the polycrystalline silicon through the discharge effect of electrons and metal wires, thereby adjusting the resistance of the polycrystalline silicon.

[0017] In one alternative implementation, the resistance of the polysilicon is adjusted by etching the protective layer.

[0018] The above technical solution allows for adjustment of the resistance of polysilicon during the etching of the protective layer.

[0019] In one alternative implementation, the resistance of the polysilicon is adjusted by changing the amount of over-etching during the etching process.

[0020] Through the above technical solution, the resistance of polysilicon can be adjusted by over-etching during the etching process, thereby reducing or increasing the resistance of polysilicon and achieving precise adjustment of the resistance of polysilicon.

[0021] In one alternative implementation, the resistance of the polysilicon is adjusted by changing the etching energy during the etching process.

[0022] The above technical solution allows for precise adjustment of the resistance of polysilicon by changing the etching energy.

[0023] In one alternative implementation, during the etching process, the resistance of the polysilicon is adjusted by changing the amount of over-etching of the protective layer.

[0024] The above technical solution allows for precise adjustment of the resistance of polysilicon by adjusting the amount of over-etching during the etching of the protective layer.

[0025] In one alternative embodiment, the resistance of the polycrystalline silicon surface is adjusted by regulating the implantation energy of ion implantation.

[0026] In one alternative embodiment, the resistance of the polycrystalline silicon surface is adjusted by regulating the implantation time of ion implantation.

[0027] With the above technical solution, when adjusting the resistance of polycrystalline silicon by ion implantation, the resistance of polycrystalline silicon can be precisely adjusted by controlling the implantation energy and implantation time.

[0028] Secondly, embodiments of this specification also provide a semiconductor device, comprising: polysilicon obtained using the above-described method for adjusting the resistance of polysilicon.

[0029] Compared with the prior art, the beneficial effects that can be achieved by the above-mentioned at least one technical solution adopted in the embodiments of this specification include at least the following: the method of adjusting the resistance of polysilicon by means of electron discharge effect during the etching process, compared with the method of adjusting the resistance of polysilicon by means of ion implantation in the layer where polysilicon is located in the prior art, has a wider range of adjustment for the resistance of polysilicon and is relatively lower in cost. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of a structure for adjusting the resistance of polysilicon through ion implantation, provided in an embodiment of this application.

[0032] Figure 2 This is an experimental data showing the relationship between polysilicon resistance and over-etching amount provided in an embodiment of this application, and a schematic diagram of the fitting curve obtained based on the experimental data;

[0033] Figure 3 This is an experimental data on the relationship between polysilicon resistance and energy provided in an embodiment of this application, and a schematic diagram of the fitting curve obtained based on the experimental data;

[0034] Figure 4 This is a schematic diagram of etching a protective layer according to an embodiment of this application. Detailed Implementation

[0035] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0036] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0038] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0039] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0040] Figure 1 This is a schematic diagram of a structure for adjusting the resistance of polysilicon through ion implantation, as provided in an embodiment of this application. Figure 1 As shown, where, Figure 1 The arrow in the image indicates ion implantation. In the existing technology, during the device formation process in the front end of semiconductor manufacturing, a first oxide layer is deposited on the substrate, and then polysilicon is deposited on the first oxide layer. The resistance of the polysilicon can then be adjusted by ion implantation. Different implantation energies and implantation times are generally used to adjust the resistance to meet different customer needs.

[0041] Specifically, after molding, ion implantation is performed on the surface of polycrystalline silicon. However, the methods of adjusting the implantation energy and implantation time during the ion implantation process have the disadvantages of a small range of polycrystalline silicon resistance adjustment and relatively high cost.

[0042] Based on this, the embodiments of this specification propose a processing solution: adjusting the resistance value of polysilicon by adjusting the protective layer etching process.

[0043] Extensive experimental data revealed that protective layer etching can regulate the resistance of polysilicon, demonstrating that the resistance can be adjusted not only through ion implantation but also through etching. Experiments showed that different over-etching amounts during the protective layer etching process modulate the polysilicon resistance, while the energy used in the etching process is another means of adjustment.

[0044] Figure 2 This application provides experimental data on the relationship between polysilicon resistivity and over-etching amount, as well as a schematic diagram of the fitting curve obtained from the experimental data. Figure 2 As shown, the horizontal axis represents the etching time in seconds; the vertical axis represents the polysilicon resistance in ohms. The dots represent experimental data, and the dotted line represents the fitted curve. The fitted curve is expressed as: y = 0.0246x + 17.938, R0 2 =0.9079; The R-squared value is an indicator of the degree of fit of the trend line. Its value can reflect the degree of fit between the estimated value of the trend line and the corresponding actual data. The higher the degree of fit, the higher the reliability of the trend line. It can be seen that there is a relationship between the resistance of polysilicon and the over-etching time. The resistance of polysilicon can be adjusted by changing the over-etching time.

[0045] Figure 3 This application provides experimental data on the relationship between the resistance and energy of polysilicon, and a schematic diagram of the fitting curve obtained from the experimental data, as shown in the embodiments. Figure 3 As shown, the horizontal axis represents energy in watts, and the vertical axis represents the resistance of polycrystalline silicon in ohms. The dots represent experimental data, and the dotted line represents the fitted curve, which is represented as: y = 0.05x - 45, R0 2 =0.8929. It can be seen that the resistance of polysilicon can be adjusted by changing the etching energy.

[0046] The experimental data above shows that the resistance of polysilicon can be adjusted by modifying the protective layer etching process, and this method can reduce costs and expand the range of polysilicon resistance adjustment compared to existing technologies.

[0047] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0048] Figure 4 This is a schematic diagram of etching a protective layer according to an embodiment of this application, as shown below. Figure 4 As shown in the embodiments of this specification, a method for adjusting the resistance of polysilicon is provided, including: adjusting the resistance of polysilicon through the discharge effect of electrons during the etching process.

[0049] Etching is a crucial step in semiconductor manufacturing, integrated circuit (IC) manufacturing, and micro / nano manufacturing processes. It's a primary patterning process associated with photolithography. In a narrow sense, etching is photolithographic etching, where photoresist is first exposed using photolithography, and then other methods are used to etch away the unwanted material. Etching is the process of selectively removing unwanted material from the surface of a silicon wafer using chemical or physical methods. Its basic goal is to accurately replicate the mask pattern on the coated silicon wafer. With the development of microfabrication processes, in a broader sense, etching has become a general term for the stripping and removal of material using solutions, reactive ions, or other mechanical methods, becoming a common term in microfabrication.

[0050] Etching technology is a technique that removes materials using chemical reactions and physical impacts. It can be divided into: wet etching, which uses a chemical solution to achieve the etching effect after a chemical reaction; and dry etching, which utilizes plasma etching. The etching process in plasma etching may involve the physical action of ions bombarding the wafer surface, the chemical reaction between active free radicals in the plasma and atoms on the wafer surface, or even a combination of both. Currently, the main application technology is plasma etching.

[0051] Among them, the discharge effect of electrons refers to the release of electrical energy after electrons aggregate to a certain concentration, which is conducted through metal wires and affects the resistance of polycrystalline silicon.

[0052] Furthermore, the embodiments in this specification do not limit the adjustment of the polysilicon resistance value. It can be described according to the specific situation. For example, the polysilicon resistance value can be reduced or increased.

[0053] The embodiments in this specification utilize the discharge effect of electrons during the etching process to adjust the resistance of polysilicon. The adjustment range of the resistance is wider than that of the ion implantation process on the polysilicon layer. Compared with the ion implantation process, it can save costs and is more flexible. The resistance of polysilicon can be adjusted again after ion implantation, or it can be adjusted whenever the resistance of polysilicon needs to be adjusted.

[0054] Extensive experimental data revealed that protective layer etching can regulate the resistance of polysilicon, demonstrating that the resistance can be adjusted not only through ion implantation but also through etching. Experiments showed that different over-etching amounts during the protective layer etching process modulate the polysilicon resistance, while the energy used in the etching process is another means of adjustment.

[0055] In a specific implementation, during the etching process, plasma is applied to the polycrystalline silicon through the discharge effect of electrons via metal wires, adjusting the resistance of the polycrystalline silicon. The metal wires consist of a metal layer and corresponding connecting holes.

[0056] Among them, the metal wire represents the path formed by the metal layer and the connecting hole in the semiconductor device. Plasma can be applied to polysilicon through the metal wire to achieve precise adjustment of the resistance value of polysilicon.

[0057] Specifically, the semiconductor device includes a substrate, a first oxide layer, a second oxide layer, and a protective layer. Polycrystalline silicon is deposited on the upper surface of the first oxide layer, and a first interconnect, a first metal layer, a second interconnect, a second metal layer, a third interconnect, and a third metal layer are sequentially connected to form a metal wire. During the etching process, plasma can act on the polycrystalline silicon through the metal wire, thereby adjusting the resistance of the polycrystalline silicon.

[0058] In the embodiments of this specification, before adjusting the resistance of polysilicon through the discharge effect of electrons during the etching process, the method further includes: adjusting the resistance of polysilicon on the surface of polysilicon by ion implantation.

[0059] Specifically, the adjustment of polysilicon resistance during ion implantation and etching can be combined to make the range of polysilicon resistance adjustment wider and more precise, thereby reducing the polysilicon resistance adjustment while improving the adjustment accuracy.

[0060] Specifically, the resistance of polycrystalline silicon is adjusted by adjusting the implantation energy of ion implantation on the polycrystalline silicon surface, and the resistance of polycrystalline silicon is adjusted by adjusting the implantation time of ion implantation on the polycrystalline silicon surface.

[0061] In the embodiments of this specification, when adjusting the resistance of polysilicon via ion implantation, the precise adjustment of the polysilicon resistance can be achieved by adjusting the implantation energy and implantation time. By combining ion implantation with the etching process, the cost of adjusting the polysilicon resistance is reduced, while the adjustable range of the polysilicon resistance is increased through the combination of ion implantation and etching. This goal is achieved by adjusting the protective layer etching process.

[0062] Specifically, the resistance of polysilicon is adjusted by etching the protective layer. This allows for adjustment of the polysilicon resistance during the etching process, meaning that the resistance can be adjusted while the semiconductor device is in the protective layer etching step. Compared to existing technologies, this makes the adjustment of polysilicon resistance more flexible, allows for a wider adjustment range, and reduces the cost of adjusting the polysilicon resistance.

[0063] The material of the protective layer is not limited in the embodiments of this specification, and can be set according to the specific situation. For example, it can be photoresist.

[0064] The polysilicon resistance adjustment method provided in the embodiments of this specification can achieve precise adjustment of the polysilicon resistance, or adjust the polysilicon resistance to meet actual needs when the polysilicon resistance does not meet the requirements.

[0065] Furthermore, the resistance of the polysilicon can be adjusted by changing the amount of etching during the etching process.

[0066] Over-etching refers to the portion of etching that continues after the basic etching is completed, ensuring that all areas are etched cleanly.

[0067] In the embodiments of this specification, during the etching process, the resistance of polysilicon can be adjusted by over-etching amount, thereby reducing or increasing the resistance of polysilicon and achieving precise adjustment of the resistance of polysilicon.

[0068] Furthermore, the resistance of polysilicon can be adjusted by changing the etching energy during the etching process.

[0069] Among them, energy refers to the total amount of plasma extracted and the free path velocity.

[0070] In the embodiments of this specification, during the etching process, the resistance of polysilicon can be adjusted by changing the amount of over-etching of the protective layer, thereby achieving precise adjustment of the resistance of polysilicon.

[0071] The technical principle of this application is that the protective layer etching requires stronger energy due to its thicker film. Through the charging effect, plasma is conducted via metal wires and ultimately acts on the polysilicon. The effect of etching on the polysilicon resistance will vary slightly between different products due to differences in the number of wire layers and the thickness of the protective layer.

[0072] The polysilicon resistance adjustment method provided in the embodiments of this specification can solve the technical problems of high cost when using ion implantation to adjust the resistance of polysilicon in the prior art, and small adjustment range when adjusting the resistance of polysilicon by adjusting the implantation time and implantation energy during ion implantation, which cannot meet the actual needs.

[0073] The polysilicon resistance adjustment method provided in this specification achieves the adjustment of polysilicon resistance through the discharge effect of electrons during the etching process. Compared with the ion implantation method described above, it can save costs, improve the flexibility of polysilicon resistance adjustment, and expand the adjustment range.

[0074] Furthermore, the adjustment of the ion implantation and etching processes can be combined to make the range of polysilicon resistance adjustment wider and to achieve precise adjustment of polysilicon resistance. Since the polysilicon resistance can be adjusted in two stages, compared with the prior art, flexible and precise adjustment of polysilicon resistance can be achieved, which greatly improves the practicality of semiconductor devices.

[0075] Furthermore, the resistance of polysilicon can be precisely adjusted by controlling the amount of etching and the energy.

[0076] This specification also provides a semiconductor device, comprising: polysilicon obtained using the above-described method for adjusting the resistance of polysilicon.

[0077] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions in the system embodiments.

[0078] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for adjusting the resistance of polycrystalline silicon, characterized in that, include: The protective layer is etched; during the etching process, plasma acts on the polycrystalline silicon through metal wires, and the resistance of the polycrystalline silicon is adjusted through the discharge effect of electrons, thereby increasing the resistance of the polycrystalline silicon; the metal wires are composed of metal layers and connecting holes; the discharge effect of electrons is that after electrons aggregate to a certain concentration, electrical energy is released.

2. The method for adjusting the resistance of polycrystalline silicon according to claim 1, characterized in that, Prior to the etching process, the following is also included: The resistance of the polycrystalline silicon is adjusted by ion implantation on the surface of the polycrystalline silicon.

3. The method for adjusting the resistance of polycrystalline silicon according to claim 1, characterized in that, During the etching process, the resistance of the polysilicon is adjusted by changing the amount of etching.

4. The method for adjusting the resistance of polycrystalline silicon according to claim 1, characterized in that, The resistance of the polysilicon is adjusted by changing the etching energy during the etching process.

5. The method for adjusting the resistance of polycrystalline silicon according to claim 1 or 3, characterized in that, During the etching process, the resistance of the polysilicon is adjusted by changing the amount of over-etching of the protective layer.

6. The method for adjusting the resistance of polycrystalline silicon according to claim 2, characterized in that, The resistance of the polycrystalline silicon surface is adjusted by regulating the implantation energy of ion implantation.

7. The method for adjusting the resistance of polycrystalline silicon according to claim 2, characterized in that, The resistance of the polycrystalline silicon surface is adjusted by regulating the implantation time of ion implantation.

8. A semiconductor device, characterized in that, include: Polycrystalline silicon obtained using the polycrystalline silicon resistance adjustment method according to any one of claims 1-7.

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