Shallow trench isolation structure and method of manufacturing the same
By employing a three-layer isolation structure in DRAM devices, especially the bottom surface of the second isolation layer with a V-groove design, the leakage current problem between adjacent source/drain regions is solved, improving isolation performance and device stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2021-07-08
- Publication Date
- 2026-07-14
Smart Images
Figure CN115662941B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a shallow trench isolation structure and its fabrication method. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices.
[0003] The substrate of a DRAM device includes multiple spaced-apart source / drain regions, with isolation regions between adjacent source / drain regions. These isolation regions typically have isolation structures to block adjacent source / drain regions. The source / drain isolation layers in the isolation regions are mostly fabricated using shallow trench isolation (STI) technology.
[0004] However, the aforementioned isolation layer configuration cannot effectively reduce leakage current between adjacent source / drain regions. Summary of the Invention
[0005] To address at least one of the problems mentioned in the background art, the present invention provides a shallow trench isolation structure and its preparation method, which can effectively reduce the leakage current of adjacent source / drain regions at the shallow trench isolation structure, thereby improving the isolation effect of the shallow trench isolation structure.
[0006] To achieve the above objectives, in a first aspect, the present invention provides a shallow trench isolation structure, comprising:
[0007] The substrate includes a first trench.
[0008] A first isolation layer is located in a first trench, and the first isolation layer has a second trench.
[0009] The second isolation layer is located in the second trench and has a third trench.
[0010] The third isolation layer fills the third trench.
[0011] The second groove is a V-shaped groove, and the bottom surface of the second isolation layer is a V-shaped surface that matches the shape of the second groove.
[0012] The shallow trench isolation structure provided by this invention, by setting a first isolation layer, a second isolation layer, and a third isolation layer, forms a barrier structure using three isolation layers to isolate adjacent source / drain regions and avoid leakage current between adjacent source / drain regions. By setting the second trench as a V-shaped trench, and the bottom surface of the second isolation layer being a V-shaped surface adapted to the shape of the second trench, the number of holes accumulating at the bottom surface of the second isolation layer is reduced, avoiding leakage current at the interface between the second and first isolation layers due to hole accumulation, thereby improving the isolation effect of the shallow trench isolation structure.
[0013] In the aforementioned shallow trench isolation structure, optionally, the first trench is a trapezoidal trench, and the cross-sectional area of the first trench gradually increases from the bottom of the first trench to the opening of the first trench.
[0014] The bottom surface of the first isolation layer has a planar extension.
[0015] This design can effectively reduce the length of the planar extension section at the bottom of the first trench, thereby reducing the number of holes that accumulate there and lowering the possibility of leakage current.
[0016] In the shallow trench isolation structure described above, optionally, the first trench is a V-shaped groove and the bottom surface of the first isolation layer is a V-shaped surface.
[0017] This setup can effectively prevent leakage current from occurring at the bottom of the first trench, thereby improving the isolation effect of the first trench and the first isolation layer.
[0018] In the aforementioned shallow trench isolation structure, the third trench may be a trapezoidal trench, with the cross-sectional area of the third trench gradually increasing from the bottom of the third trench to the opening of the third trench.
[0019] The top surface of the second isolation layer has a planar extension.
[0020] This design can effectively reduce the length of the planar extension section at the bottom of the third trench, thereby reducing the number of holes that accumulate there and lowering the possibility of leakage current.
[0021] In the shallow trench isolation structure described above, optionally, the third trench is a V-shaped groove and the top surface of the second isolation layer is a V-shaped surface.
[0022] This setup can effectively prevent leakage current at the bottom of the third trench, improving the isolation effect of the third trench and the second isolation layer.
[0023] In the shallow trench isolation structure described above, it is optional that the first isolation layer and the third isolation layer are made of the same material, or that the first isolation layer and the second isolation layer are made of different materials.
[0024] In the shallow trench isolation structure described above, the material of the first isolation layer may include silicon oxide, and the material of the second isolation layer may include silicon nitride.
[0025] This setup can reduce the fabrication difficulty of the shallow trench isolation structure while improving the stability at the interface between the first isolation layer and the substrate.
[0026] In the shallow trench isolation structure described above, optionally, the thickness of the second isolation layer is the same at different locations in the second trench.
[0027] This configuration can improve the uniformity of the second isolation layer, thereby enhancing the structural stability of the shallow trench isolation structure.
[0028] In the shallow trench isolation structure described above, optionally, the substrate has spaced-apart source / drain regions, with the first trench located between adjacent source / drain regions. PMOS transistors are formed in the source / drain regions.
[0029] This setup can use the shallow trench isolation structure to isolate the source / drain regions of adjacent PMOS transistors, preventing hot carriers in the PMOS transistors from passing through the gate oxide layer into the shallow trench isolation structure, and preventing the hot carriers from getting stuck at the interface of the adjacent isolation layers of the shallow trench isolation structure. This reduces the leakage current caused by the accumulation of hot carriers and improves the isolation effect on the source / drain regions of adjacent PMOS transistors.
[0030] Secondly, the present invention also provides a method for preparing a shallow trench isolation structure, comprising:
[0031] The first trench is formed in the substrate.
[0032] A first isolation layer with a second trench is formed in the first trench.
[0033] A second isolation layer with a third trench is formed in the second trench.
[0034] A third isolation layer is formed in the third trench.
[0035] The second groove is a V-shaped groove, and the bottom surface of the second isolation layer is a V-shaped surface that matches the shape of the second groove.
[0036] The shallow trench isolation structure fabrication method provided by this invention involves sequentially forming a first isolation layer, a second isolation layer, and a third isolation layer in a first trench. These three isolation layers form a barrier structure to isolate adjacent source / drain regions, preventing leakage current between them. By setting the second trench as a V-shaped trench and making the bottom surface of the second isolation layer a V-shaped surface adapted to the shape of the second trench, the number of holes accumulating at the bottom surface of the second isolation layer is reduced, preventing leakage current at the interface between the second and first isolation layers due to hole accumulation. This improves the isolation effect of the shallow trench isolation structure.
[0037] In the above-described method for preparing a shallow trench isolation structure, optionally, the step of forming a first isolation layer having a second trench in the first trench specifically includes:
[0038] A first insulating layer is filled into the first trench, and at least part of the first insulating layer covers the opening of the first trench.
[0039] The first isolation layer is etched back, forming a V-shaped second groove.
[0040] In the above-described method for preparing a shallow trench isolation structure, optionally, the step of forming a second isolation layer with a third trench in the second trench specifically includes:
[0041] A second isolation layer is filled into the second trench, and at least part of the second isolation layer covers the opening of the second trench.
[0042] The second isolation layer is then engraved, forming the third trench.
[0043] The thickness of the second isolation layer is the same at different locations in the second trench.
[0044] This setup can reduce the difficulty of fabricating the second isolation layer, while improving the uniformity of the second isolation layer and enhancing the structural stability of the shallow trench isolation structure.
[0045] In the above-described method for preparing a shallow trench isolation structure, optionally, the step of forming a third isolation layer in the third trench includes filling the third trench with the third isolation layer. This can improve the structural stability of the shallow trench isolation structure.
[0046] In the above-described method for fabricating a shallow trench isolation structure, optionally, after forming the third isolation layer in the third trench, the method further includes planarizing the top surfaces of the first, second, and third isolation layers. This arrangement facilitates the fabrication of other layer structures above the substrate.
[0047] In the above-described method for preparing a shallow trench isolation structure, optionally, in the step of filling a first isolation layer in a first trench and at least partially covering the opening of the first trench, the top surface of the first isolation layer has a recessed portion.
[0048] The step of re-etching the first isolation layer and forming a V-shaped second groove specifically includes: re-etching the first isolation layer along the recess and forming a V-shaped second groove.
[0049] This setup utilizes the depressions created by the step effect during deposition as the basic structure for re-etching, reducing the difficulty of re-etching.
[0050] In the above-mentioned methods for preparing shallow trench isolation structures, the first isolation layer may be prepared by atomic layer deposition, in-situ water vapor generation, or spin coating.
[0051] The structure of the present invention, as well as its other inventive objects and beneficial effects, will become more apparent from the description of preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description
[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0053] Figure 1 This is a schematic diagram of a shallow trench isolation structure in related technologies;
[0054] Figure 2 This is a schematic diagram of the structure in which a SiO2 oxide layer is formed in a substrate in a related technology;
[0055] Figure 3 This is a schematic diagram of the structure in which a SiO2 oxide layer and a SiN inner liner are formed in a substrate in a related technology.
[0056] Figure 4 This is a schematic diagram of the structure in which a SiO2 oxide layer, a SiN inner liner layer, and a dielectric material are formed in a substrate in a related technology.
[0057] Figure 5 This is a schematic diagram of the shallow trench isolation structure provided in an embodiment of the present invention;
[0058] Figure 6 A schematic diagram of a substrate with a first trench providing a shallow trench isolation structure according to an embodiment of the present invention;
[0059] Figure 7A schematic diagram of a first isolation layer with a recessed portion formed in the first trench of a shallow trench isolation structure provided in an embodiment of the present invention;
[0060] Figure 8 A schematic diagram of a first isolation layer having a second trench formed in the first trench of a shallow trench isolation structure provided in an embodiment of the present invention;
[0061] Figure 9 A schematic diagram of a second isolation layer having a third trench formed in the second trench of a shallow trench isolation structure provided in an embodiment of the present invention;
[0062] Figure 10 This is a schematic diagram of the structure in which a third isolation layer is formed in the third trench of the shallow trench isolation structure provided in an embodiment of the present invention;
[0063] Figure 11 This is a schematic diagram of another shallow trench isolation structure provided in an embodiment of the present invention;
[0064] Figure 12 A schematic flowchart illustrating the fabrication method of the shallow trench isolation structure provided in an embodiment of the present invention;
[0065] Figure 13 A schematic diagram of the process for forming the first isolation layer in the method for preparing the shallow trench isolation structure provided in an embodiment of the present invention;
[0066] Figure 14 This is a schematic diagram of the process for forming the second isolation layer in the method for preparing the shallow trench isolation structure provided in an embodiment of the present invention.
[0067] Explanation of reference numerals in the attached figures:
[0068] 10, 1-Substrate; 11-First trench;
[0069] 20 - First isolation layer; 21 - Second trench;
[0070] 22 - Recessed portion; 30 - Second isolation layer;
[0071] 31 - Third trench; 40 - Third isolation layer;
[0072] 50, 2 - Source / Drain region; 60, 6 - Gate oxide layer;
[0073] 70, 7-gate layer; 3-SiO2 oxide layer;
[0074] 4-SiN inner liner; 5-Dielectric material. Detailed Implementation
[0075] The inventors of this application discovered during actual research that an isolation structure is provided between adjacent source / drain regions in the substrate of a DRAM device, and this isolation structure is prepared by a shallow trench isolation process. Figure 1 This is a schematic diagram of a shallow trench isolation structure in related technologies. Figure 2 This is a schematic diagram of the structure in which a SiO2 oxide layer is formed in a substrate in a related technology. Figure 3 This is a schematic diagram of the structure in which a SiO2 oxide layer and a SiN inner liner are formed in a substrate in a related technology. Figure 4 This is a schematic diagram of the structure in which a SiO2 oxide layer, a SiN inner liner, and a dielectric material are formed in a substrate in a related technology.
[0076] Reference Figures 1 to 4 As shown, the substrate 1 of the DRAM device has source / drain regions 2, which can be the source / drain regions 2 of a PMOS transistor or an NMOS transistor. Trenches (not shown in the figure) are formed between adjacent source / drain regions 2. Figures 2 to 4 As shown, a SiO2 oxide layer 3, a SiN liner layer 4, and a dielectric material 5 are sequentially formed in the trench. The SiO2 oxide layer 3, the SiN liner layer 4, and the dielectric material 5 together constitute a shallow trench isolation structure. A channel region is formed between the source region and the drain region of the active region, and a gate oxide layer 6 and a gate layer 7 are formed above the channel region.
[0077] As the feature size of DRAM devices continues to shrink, taking PMOS transistors as an example, a strong electric field causes hot carriers to be generated in highly integrated PMOS transistors. Since hot carriers typically have high energy, they can penetrate the SiO2 oxide layer 3 and enter the shallow trench isolation structure.
[0078] Hot carriers penetrating into the shallow trench isolation structure tend to get trapped at the interface between the SiO2 oxide layer 3 and the SiN liner layer 4, causing a large number of holes to accumulate at this interface, which in turn causes leakage current near the shallow trench isolation structure. This leakage current leads to a decrease in the stability of the source / drain region 2 of the adjacent PMOS transistor.
[0079] The inventors analyzed that the main reason for the leakage current is that in the shallow trench isolation structure, the SiO2 oxide layer 3 has a long planar extension, that is, the SiO2 oxide layer 3 located at the bottom of the SiN inner liner layer 4. The planar extension of the SiO2 oxide layer 3 results in a large contact area between the SiO2 oxide layer 3 and the substrate 1 (Si), thus a large number of hot carriers accumulate at the interface between the planar extension of the SiO2 oxide layer 3 and the substrate 1 (Si), that is, a large number of holes accumulate, resulting in a large leakage current at this point.
[0080] In view of this, the shallow trench isolation structure and its preparation method provided in this embodiment of the invention, by setting a first isolation layer, a second isolation layer and a third isolation layer in the shallow trench isolation structure, utilizes the three isolation layers to form a barrier structure to isolate adjacent source / drain regions and avoid leakage current between adjacent source / drain regions. By setting the second trench as a V-shaped trench, and the bottom surface of the second isolation layer being a V-shaped surface adapted to the shape of the second trench, the number of holes accumulating at the bottom surface of the second isolation layer is reduced, and leakage current is avoided at the interface between the second isolation layer and the first isolation layer due to the accumulation of holes, thereby improving the isolation effect of the shallow trench isolation structure.
[0081] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be described in more detail below with reference to the accompanying drawings of the preferred embodiments. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of the present invention. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0082] Figure 5 This is a schematic diagram of the shallow trench isolation structure provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of a substrate with a first trench, provided in an embodiment of the present invention, for a shallow trench isolation structure. Figure 7 This is a schematic diagram of a first isolation layer with a recessed portion formed in the first trench of a shallow trench isolation structure provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of a first isolation layer with a second trench formed in the first trench of a shallow trench isolation structure provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of a second isolation layer with a third trench formed in the second trench of a shallow trench isolation structure provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of the formation of a third isolation layer in the third trench of the shallow trench isolation structure provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of another shallow trench isolation structure provided in an embodiment of the present invention.
[0083] Reference Figure 5 As shown, the shallow trench isolation structure provided in the embodiments of the present invention includes:
[0084] Substrate 10, which includes a first trench 11.
[0085] The first isolation layer 20 is located in the first trench 11 and has a second trench 21.
[0086] The second isolation layer 30 is located in the second trench 21 and has a third trench 31.
[0087] The third isolation layer 40 fills the third trench 31.
[0088] The second groove 21 is a V-shaped groove, and the bottom surface of the second isolation layer 30 is a V-shaped surface that matches the shape of the second groove 21.
[0089] It should be noted that the substrate 10 in the shallow trench isolation structure provided in this embodiment can provide a supporting foundation for the other structural layers to be disposed on the substrate 10. The substrate 10 can be silicon, that is, it can be monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound or silicon-on-insulator (SOI), or other materials known to those skilled in the art.
[0090] The substrate 10 may have a semiconductor layer forming an active region of the substrate 10, which includes a source region and a drain region, and a channel region is formed between the source region and the drain region. That is, the substrate 10 has spaced-apart source / drain regions 50, a first trench 11 is located between adjacent source / drain regions 50, and an isolation region may be formed between adjacent source / drain regions 50, in which the aforementioned shallow channel isolation structure may be provided.
[0091] In this structure, a first trench 11 is formed between adjacent source / drain regions 50 in the substrate 10, which can structurally isolate adjacent source / drain regions 50. At the same time, a first isolation layer 20, a second isolation layer 30 and a third isolation layer 40 are formed sequentially in the first trench 11, which together form the main isolation structure of the shallow trench isolation structure.
[0092] Specifically, the second isolation layer 30 is formed in the second trench 21 on the first isolation layer 20, and the third isolation layer 40 is formed in the third trench 31 of the second isolation layer 30. This arrangement can ensure the stable setting of the first isolation layer 20, the second isolation layer 30 and the third isolation layer 40 in the first trench 11, with a low degree of mutual interference.
[0093] It should be emphasized that in this embodiment, the second groove 21 is a V-shaped groove, that is, the bottom of the second groove 21 is the tip of the V-shaped groove, and the second isolation layer 30 is filled in the second groove 21, so that the bottom surface of the second isolation layer 30 has a V-shaped surface that matches the shape of the second groove 21.
[0094] In this embodiment, the bottom of the second trench 21 and the bottom surface of the second isolation layer 30 do not exist. Figure 1 The related technology shown in the figure has a planar extension segment. Therefore, the number of holes that can accumulate between the second isolation layer 30 and the substrate 10 (Si) is reduced, and the leakage current caused by the holes will be reduced, thereby improving the isolation effect of the shallow trench isolation structure.
[0095] Specifically, in this embodiment, a PMOS transistor is formed in the source / drain region 50, that is, the source / drain region 50 is the source / drain region 50 of a PMOS transistor. The PMOS transistor also includes a gate oxide layer 60 and a gate layer 70 formed on the substrate 10. Through the shallow trench isolation structure described above, the source / drain regions 50 of adjacent PMOS transistors can be isolated, preventing hot carriers in the PMOS transistors from passing through the gate oxide layer 60 and entering the shallow trench isolation structure. Furthermore, it prevents hot carriers from getting trapped at the interface of adjacent isolation layers in the shallow trench isolation structure, mainly preventing them from getting trapped at the interface between the first isolation layer 20 and the second isolation layer 30. Thus, the above method can reduce the leakage current generated at the interface due to the accumulation of hot carriers, and improve the isolation effect on the source / drain regions 50 of adjacent PMOS transistors.
[0096] In one possible implementation, the first isolation layer 20 and the third isolation layer 40 are made of the same material, with the first isolation layer 20 being made of silicon oxide. Alternatively, the first isolation layer 20 and the second isolation layer 30 may be made of different materials, with the second isolation layer 30 being made of silicon nitride.
[0097] It should be noted that the first isolation layer 20 and the third isolation layer 40 are made of the same material, which can reduce the fabrication difficulty of the shallow trench isolation structure. Furthermore, the first isolation layer 20 is in contact with the substrate 10. The first isolation layer 20 is made of silicon oxide, which has a high degree of interface fusion with the silicon substrate 10. Therefore, the interface stability between the first isolation layer 20 and the substrate 10 is high.
[0098] Furthermore, the second isolation layer 30 is made of silicon nitride, or silicon oxide. Silicon nitride has better electrical isolation effect and higher interface stability with the silicon oxide of the first isolation layer 20.
[0099] As one feasible implementation, the thickness of the second isolation layer 30 is equal at different locations in the second trench 21. It should be noted that the equal thickness of the second isolation layer 30 improves its uniformity. Simultaneously, the third isolation layer 40 is formed within the third trench 31 of the second isolation layer 30; therefore, the more uniform second isolation layer 30 facilitates the placement of the third isolation layer 40, thereby improving the overall structural stability of the shallow trench isolation structure.
[0100] Based on the above structure, the leakage current at the shallow trench isolation structure can be further reduced by adjusting the structure of the first trench 11.
[0101] Specifically, refer to Figure 5 As shown, the first groove 11 is a trapezoidal groove, and the cross-sectional area of the first groove 11 gradually increases from the bottom of the groove to the opening of the groove. The bottom surface of the first isolation layer 20 has a planar extension section.
[0102] It should be noted that in related technologies, the trenches in shallow trench isolation structures are generally rectangular, meaning the width of the trench opening and the width of the trench bottom are approximately equal. The above-described configuration in this embodiment, based on related technologies, reduces the width of the bottom of the first trench 11, i.e., reduces the length of the planar extension of the first isolation layer 20. This helps reduce the possibility of hole accumulation at this location, thereby reducing leakage current.
[0103] Among them, reference Figure 11 As shown, the first trench 11 is a V-shaped groove, and the bottom surface of the first isolation layer 20 is a V-shaped surface. The first trench 11 can be configured to have the same shape as the second trench 21, so that the bottom of the first trench 11 is the tip of the V-shaped groove, and the bottom surface of the first isolation layer 20 is a matching V-shaped surface. Therefore, the bottom surface of the first isolation layer 20 does not have the aforementioned planar extension segment. The leakage current caused by hole accumulation between the first isolation layer 20 and the second isolation layer 30 is less likely to exist on the bottom surface of the first isolation layer 20, thus effectively reducing the leakage current at this location and improving the isolation effect at the first trench 11 and the first isolation layer 20.
[0104] Based on the above structure, the leakage current at the shallow trench isolation structure can be further reduced by adjusting the structure of the third trench 31.
[0105] Specifically, the third groove 31 is a trapezoidal groove, and its cross-sectional area gradually increases from the bottom to the opening of the third groove 31. The top surface of the second isolation layer 30 has a planar extension section.
[0106] It should be noted that in related technologies, trenches are generally formed on the SiN inner liner 4 to be filled with dielectric material 5. These trenches are generally rectangular, meaning the width of the trench opening and the width of the trench bottom are approximately equal. The above-described arrangement in this embodiment, based on related technologies, reduces the width of the bottom of the third trench 31, i.e., reduces the length of the planar extension of the third isolation layer 40. This helps reduce hole accumulation between the second isolation layer 30 and the third isolation layer 40, thereby reducing leakage current formation.
[0107] Among them, reference Figure 5 and Figure 11 As shown, the third trench 31 is a V-shaped trench, and the top surface of the second isolation layer 30 is a V-shaped surface. The third trench 31 can be configured to have the same shape as the second trench 21, such that the bottom of the third trench 31 is the tip of the V-shaped trench, and the top surface of the second isolation layer 30 or the bottom surface of the third isolation layer 40 is a matching V-shaped surface. This can reduce the accumulation of holes at the interface between the third isolation layer 40 and the second isolation layer 30, thereby helping to reduce the leakage current that can be formed there and improving the isolation effect of the third trench 31, the second isolation layer 30, and the third isolation layer 40.
[0108] Based on the above embodiments, referring to Figures 12 to 14 As shown, and in combination Figures 5 to 10 As shown, the present invention also provides a method for preparing a shallow trench isolation structure, comprising:
[0109] S1: Form the first trench in the substrate.
[0110] It should be noted that, referring to Figure 6 As shown, the first trench 11 can be formed by a mask and photolithography, that is, a hard mask and photoresist are formed sequentially on the substrate 10, and the mask pattern is transferred to the hard mask by high selectivity etching, and then transferred to the substrate 10 to form the first trench 11.
[0111] S2: A first isolation layer with a second trench is formed in the first trench.
[0112] In step 2, refer to Figure 13 As shown, it can specifically include:
[0113] S21: A first isolation layer is filled into the first trench, with at least a portion of the first isolation layer covering the opening of the first trench. The first isolation layer 20 can be formed by deposition, such as atomic layer deposition. Of course, in practical applications, the preparation method of the first isolation layer 20 can also include in-situ water vapor generation and spin coating methods to ensure that the first isolation layer 20 completely fills the first trench 11 and covers the opening of the first trench 11.
[0114] Reference Figure 7 As shown, the top surface of the first isolation layer 20 has a recess 22. This recess 22 is formed due to the step effect of deposition during the deposition process. That is, the deposition rate of the first isolation layer 20 near the center of the first trench 11 is lower, and the deposition rate of the first isolation layer 20 near the edge of the first trench 11 is higher. The recess 22 is formed based on the difference in deposition rate at different locations in the first trench 11. This recess 22 can serve as the structural basis for etching back the first isolation layer 20.
[0115] S22: Etch back the first isolation layer and form a V-shaped second trench. See details... Figure 8 As shown, the first isolation layer 20 is etched back along the recess 22 to form a V-shaped second groove 21. This effectively reduces the difficulty of etching back to form the second groove 21.
[0116] S3: A second isolation layer with a third trench is formed in the second trench.
[0117] In step 3, refer to Figure 9 and Figure 14 As shown, it specifically includes:
[0118] S31: A second isolation layer is filled into the second trench, with at least a portion of the second isolation layer covering the opening of the second trench. The second isolation layer 30 can be formed in the same way as the first isolation layer 20. The second trench 21 is a V-shaped groove, and the bottom surface of the second isolation layer 30 is a V-shaped surface that matches the shape of the second trench 21. This arrangement can reduce leakage current at the bottom surface of the second isolation layer 30.
[0119] S32: The second isolation layer is etched back to form the third trench. The thickness of the second isolation layer 30 is uniform at different locations within the second trench 21. This configuration improves the uniformity of the second isolation layer 30. Furthermore, to ensure the required thickness of the second isolation layer 30, the etch-back process can be performed using a dry etching method to improve the accuracy of the etch-back.
[0120] S4: A third isolation layer is formed in the third trench. For details, refer to... Figure 10 As shown, the third isolation layer 40 fills the third trench 31. This improves the stability of the third trench 31, thereby ensuring the overall structural stability of the shallow trench isolation structure. The third isolation layer 40 can be formed in the same way as the first isolation layer 20 and the second isolation layer 30.
[0121] Furthermore, after step 4, the process may further include planarizing the top surfaces of the first isolation layer 20, the second isolation layer 30, and the third isolation layer 40. This process facilitates the placement of other layer structures above the substrate 10. The planarization process can be completed by etching, ultimately ensuring that the top surfaces of the first isolation layer 20, the second isolation layer 30, and the third isolation layer 40 are flush with the top surface of the substrate 10 (this structure is not shown in the figure).
[0122] The method for fabricating a shallow trench isolation structure provided in this invention involves sequentially forming a first isolation layer 20, a second isolation layer 30, and a third isolation layer 40 in a first trench 11. These three isolation layers form a barrier structure to isolate adjacent source / drain regions 50, preventing leakage current between them. By setting the second trench 21 as a V-shaped trench and making the bottom surface of the second isolation layer 30 a V-shaped surface adapted to the shape of the second trench 21, the number of holes accumulating on the bottom surface of the second isolation layer 30 is reduced. This prevents leakage current from occurring at the interface between the second isolation layer 30 and the first isolation layer 20 due to hole accumulation, thereby improving the isolation effect of the shallow trench isolation structure.
[0123] Based on the above, this embodiment also provides a semiconductor structure, which can be a DRAM device. In addition to the substrate described above, the semiconductor structure may further include bit lines located in the substrate, as well as word lines, transistor structures, and capacitor structures located on the substrate.
[0124] A DRAM device comprises an array of multiple memory cells on a substrate, each memory cell including a capacitor structure and a transistor structure. The capacitor structure stores data, while the transistor structure controls data access via the capacitor structure. The gate layer of the transistor structure is connected to the word line. The drain region in the substrate is connected to the bit line structure, and the source region is connected to the capacitor structure. Voltage signals on the word line control the transistor structure to turn on or off, thereby reading data stored in the capacitor structure via the bit line, or writing data to the capacitor structure via the bit line for storage, thus realizing data access in the DRAM device. Therefore, using a substrate with the aforementioned shallow channel isolation structure in a DRAM device can improve the stability of the DRAM device, thereby enhancing its access performance.
[0125] In the above description, it should be understood that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection or an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, "a plurality of" means two or more, unless otherwise precisely specified.
[0126] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A shallow trench isolation structure for reducing hot carrier accumulation in a PMOS transistor, characterized in that, include: A substrate, the substrate including a first trench; the substrate having spaced-apart source / drain regions, the first trench being located between adjacent source / drain regions, and the PMOS transistor being formed in the source / drain regions; A first isolation layer, the first isolation layer being located in the first trench, and the first isolation layer having a second trench; A second isolation layer, the second isolation layer being located in the second trench, and the second isolation layer having a third trench; A third isolation layer, wherein the third isolation layer fills the third trench; The second groove is a V-shaped groove, and the bottom surface of the second isolation layer is a V-shaped surface that matches the shape of the second groove.
2. The shallow trench isolation structure according to claim 1, characterized in that, The first groove is a trapezoidal groove, and the cross-sectional area of the first groove gradually increases from the bottom of the first groove to the opening of the first groove. The bottom surface of the first isolation layer has a planar extension.
3. The shallow trench isolation structure according to claim 1, characterized in that, The first groove is a V-shaped groove, and the bottom surface of the first isolation layer is a V-shaped surface.
4. The shallow trench isolation structure according to claim 2 or 3, characterized in that, The third groove is a trapezoidal groove, and the cross-sectional area of the third groove gradually increases from the bottom of the third groove to the opening of the third groove. The top surface of the second isolation layer has a planar extension.
5. The shallow trench isolation structure according to claim 2 or 3, characterized in that, The third groove is a V-shaped groove, and the top surface of the second isolation layer is a V-shaped surface.
6. The shallow trench isolation structure according to any one of claims 1-3, characterized in that, The first isolation layer and the third isolation layer are made of the same material, while the first isolation layer and the second isolation layer are made of different materials.
7. The shallow trench isolation structure according to any one of claims 1-3, characterized in that, The first isolation layer is made of silicon oxide, and the second isolation layer is made of silicon nitride.
8. The shallow trench isolation structure according to any one of claims 1-3, characterized in that, The thickness of the second isolation layer is the same at different locations in the second trench.
9. A method for fabricating a shallow trench isolation structure for reducing hot carrier aggregation in a PMOS transistor, characterized in that, include: A first trench is formed in the substrate; A first isolation layer having a second trench is formed in the first trench; A second isolation layer having a third trench is formed in the second trench; A third isolation layer is formed in the third trench; Wherein, the second groove is a V-shaped groove, and the bottom surface of the second isolation layer is a V-shaped surface adapted to the shape of the second groove; The shallow trench isolation structure is formed between the source / drain regions of adjacent PMOS transistors.
10. The method for preparing the shallow trench isolation structure according to claim 9, characterized in that, The step of forming a first isolation layer having a second trench in the first trench specifically includes: The first isolation layer is filled into the first trench, and at least part of the first isolation layer covers the opening of the first trench; The first isolation layer is etched back, and a V-shaped second trench is formed.
11. The method for preparing the shallow trench isolation structure according to claim 9, characterized in that, The step of forming a second isolation layer with a third trench in the second trench specifically includes: The second isolation layer is filled into the second trench, and at least part of the second isolation layer covers the opening of the second trench; The second isolation layer is etched back, and the third trench is formed; The thickness of the second isolation layer is the same at different locations in the second trench.
12. The method for preparing the shallow trench isolation structure according to claim 9, characterized in that, The step of forming the third isolation layer in the third trench specifically includes: The third isolation layer fills the third trench.
13. The method for preparing the shallow trench isolation structure according to any one of claims 9-12, characterized in that, After the step of forming the third isolation layer in the third trench, the method further includes: The top surfaces of the first isolation layer, the second isolation layer, and the third isolation layer are planarized.
14. The method for preparing the shallow trench isolation structure according to claim 10, characterized in that, In the step of filling the first isolation layer in the first trench, wherein at least a portion of the first isolation layer covers the opening of the first trench, the top surface of the first isolation layer has a recessed portion. The step of etching back the first isolation layer and forming a V-shaped second trench specifically includes: The first isolation layer is etched back along the recessed portion to form a V-shaped second groove.
15. The method for preparing the shallow trench isolation structure according to any one of claims 9-12, characterized in that, The preparation methods of the first isolation layer include atomic layer deposition, in-situ water vapor generation, and spin coating.