A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors, aiming to improve the control ability of a first transistor and a second transistor on channel current. The semiconductor device comprises a semiconductor substrate, a first isolation medium wall, a first transistor and a second transistor. The first isolation medium wall is formed on a first medium layer included in the semiconductor substrate. The first transistor is formed on the first medium layer and located at one side of the first isolation medium wall along a width direction. A first channel region included in the first transistor is arranged apart from the first isolation medium wall and has at least two first channel sections. The at least two first channel sections are distributed apart along the width direction parallel to the first isolation medium wall. The second transistor is formed on the first medium layer and located at a side of the first isolation medium wall away from the first transistor. A second channel region included in the second transistor is arranged apart from the first isolation medium wall. The second transistor is opposite to the first transistor in a conduction type.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Forksheet (FSH) devices are made by introducing a "dielectric wall" between P-type and N-type transistors before gate patterning, which further reduces the spacing between P-type and N-type transistors and facilitates the miniaturization of semiconductor devices.

[0003] However, the existing P-type and N-type transistors in Forksheet devices have poor control over channel current, which is not conducive to improving the electrical performance of Forksheet devices. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method, which improves the control capability of the first transistor and the second transistor over the channel current, thereby enhancing the electrical performance of the Forksheet device.

[0005] In a first aspect, the present invention provides a semiconductor device. The semiconductor device includes: a semiconductor substrate, a first insulating dielectric wall, a first transistor, and a second transistor.

[0006] The aforementioned semiconductor substrate includes a semiconductor substrate and a first dielectric layer located on the semiconductor substrate. A first isolation dielectric wall is formed on the first dielectric layer. A first transistor is formed on the first dielectric layer and located on one side of the first isolation dielectric wall along its width direction. The first transistor includes a first channel region spaced apart from the first isolation dielectric wall and has at least two first channel portions. At least two first channel portions are spaced apart along a width direction parallel to the first isolation dielectric wall. Each first channel portion has a gap with the first dielectric layer, and a first gate stack structure of the first transistor surrounds the outer periphery of each first channel portion. A second transistor is formed on the first dielectric layer and located on the side of the first isolation dielectric wall opposite to the first transistor. The second transistor includes a second channel region spaced apart from the first isolation dielectric wall. The second transistor has an opposite conductivity type to the first transistor.

[0007] Compared with the prior art, the semiconductor device provided by the present invention has a first isolation dielectric wall formed on a first dielectric layer of the semiconductor substrate. A first transistor and a second transistor are formed on both sides of the first isolation dielectric wall along its width direction, and the first transistor and the second transistor have opposite conductivity types. Therefore, the semiconductor device provided by the present invention is a forksheet device. Furthermore, the first channel region of the first transistor is spaced apart from the first isolation dielectric wall. And, along the width direction parallel to the first isolation dielectric wall, at least two first channel portions of the first channel region are spaced apart. Each first channel portion has a gap with the first dielectric layer. At this time, the top surface, bottom surface, and side surface along the width direction of each first channel portion of the first channel region are exposed, allowing the first gate stack structure of the first transistor to surround the outer periphery of each first channel portion. This solves the problem in existing forksheet devices where the channel regions of P-type and N-type transistors are in contact with the dielectric wall, resulting in the gate stack structure not being able to cover the sidewalls of the channel regions near the dielectric wall. This improves the control capability of the first gate stack structure of the first transistor over each first channel portion. Similarly, since the second channel region of the second transistor is spaced apart from the first isolation dielectric wall, the second gate stack structure of the second transistor can also cover the sidewall of the second channel portion near the first isolation dielectric wall, thereby improving the control capability of the second gate stack structure over the second channel portion and enhancing the electrical performance of the semiconductor device.

[0008] Furthermore, in the semiconductor device provided by the present invention, both the first transistor and the second transistor are formed on the first dielectric layer, and the first dielectric layer is a non-conductive insulating layer. Therefore, the presence of the first dielectric layer can prevent parasitic channel leakage and further improve the gate control capability of the first gate stack structure and the second gate stack structure.

[0009] Secondly, the present invention also provides a method for manufacturing a semiconductor device, the method comprising:

[0010] A semiconductor substrate is provided. The semiconductor substrate includes a semiconductor substrate and a first dielectric layer located on the semiconductor substrate.

[0011] A first isolation medium wall is formed on the first medium layer.

[0012] A first transistor and a second transistor are formed on a first dielectric layer. The first transistor is located on one side of a first isolation dielectric wall along its width direction. The first transistor includes a first channel region spaced apart from the first isolation dielectric wall and has at least two first channel portions. At least two first channel portions are spaced apart along a width direction parallel to the first isolation dielectric wall. Each first channel portion has a gap with the first dielectric layer, and a first gate stack structure of the first transistor surrounds the outer periphery of each first channel portion. The second transistor is located on the side of the first isolation dielectric wall opposite to the first transistor. The second transistor includes a second channel region spaced apart from the first isolation dielectric wall. The second transistor has the opposite conductivity type to the first transistor.

[0013] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided by the present invention can be found in the analysis of the beneficial effects of the semiconductor device provided by the present invention, which will not be repeated here. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0015] Figure 1 This is a schematic diagram of the longitudinal section of an existing Forksheet device.

[0016] Figure 2 This is a schematic diagram of the first structure after the formation of the first fin-like structure in an embodiment of the present invention;

[0017] Figure 3 This is a schematic diagram of the second structure after the first fin-like structure is formed in an embodiment of the present invention;

[0018] Figure 4 This is a schematic diagram of the structure after the formation of the first semiconductor layer and the second semiconductor layer in an embodiment of the present invention;

[0019] Figure 5 This is a schematic diagram of the structure after the formation of the first semiconductor layer, the sacrificial layer, and the second semiconductor layer in an embodiment of the present invention;

[0020] Figure 6 This is a schematic diagram of the structure after removing the first fin structure in an embodiment of the present invention;

[0021] Figure 7 This is a schematic diagram of the structure after the isolation medium material is formed in an embodiment of the present invention;

[0022] Figure 8 This is a schematic diagram of the structure after the first isolation medium wall is formed in an embodiment of the present invention;

[0023] Figure 9 This is a schematic diagram of the structure after the formation of the first isolation medium wall, the first isolation material, and the second isolation material in an embodiment of the present invention;

[0024] Figure 10 This is a schematic diagram of the first structure after the sacrificial gate is formed in an embodiment of the present invention;

[0025] Figure 11 This is a schematic diagram of the second structure after the sacrificial gate is formed in an embodiment of the present invention;

[0026] Figure 12 This is a schematic diagram of the structure after the gate sidewall is formed in an embodiment of the present invention;

[0027] Figure 13 This is a schematic diagram of the structure after removing portions of the first semiconductor layer and the second semiconductor layer located in the first region and the second region, as shown in an embodiment of the present invention.

[0028] Figure 14 This is a schematic diagram of the longitudinal cross-section of the structure along the length of the first isolation dielectric wall and at the first material layer after removing portions of the first semiconductor layer and the second semiconductor layer located in the first region and the second region, according to an embodiment of the present invention.

[0029] Figure 15 This is a longitudinal cross-sectional schematic diagram of the first structure after forming the first source / drain region and the second source / drain region in an embodiment of the present invention.

[0030] Figure 16 This is a longitudinal cross-sectional schematic diagram of the second structure after forming the first source / drain region and the second source / drain region in an embodiment of the present invention.

[0031] Figure 17 This is a schematic diagram of the structure after the second dielectric layer is formed in an embodiment of the present invention;

[0032] Figure 18 This is a longitudinal cross-sectional schematic diagram of the first structure in the third region after the sacrificial gate is removed in an embodiment of the present invention.

[0033] Figure 19 This is a longitudinal cross-sectional schematic diagram of the second structure in the third region after removing the sacrificial gate in an embodiment of the present invention;

[0034] Figure 20 This is a schematic longitudinal cross-sectional view of the structure after simultaneously removing the first material layer included in the first semiconductor layer and the second semiconductor layer in an embodiment of the present invention.

[0035] Figure 21 This is a schematic diagram of the longitudinal cross-section of the structure after selectively removing the first material layer included in the first semiconductor layer in an embodiment of the present invention;

[0036] Figure 22 This is a schematic longitudinal cross-sectional view of the structure after selectively removing the second material layer, which is included in the second semiconductor layer, in an embodiment of the present invention.

[0037] Figure 23 This is a schematic diagram of the longitudinal cross-section of the structure after forming the first and second channel regions with different materials in an embodiment of the present invention;

[0038] Figure 24 This is a schematic longitudinal cross-sectional view of the structure after selectively removing the second material layer, which is included in the second semiconductor layer, in an embodiment of the present invention.

[0039] Figure 25 This is a schematic longitudinal cross-sectional view of the structure after selectively removing the first material layer, which is included in the first semiconductor layer, in an embodiment of the present invention.

[0040] Figure 26 This is a schematic diagram of the longitudinal section of the structure after the portion of the first dielectric layer located near the first channel region of the first isolation dielectric wall has been etched back in an embodiment of the present invention.

[0041] Figure 27 This is a schematic diagram of the longitudinal cross-section of the structure after removing the corresponding mask layer in an embodiment of the present invention;

[0042] Figure 28 This is a schematic diagram of the longitudinal section of the structure after the portion of the first dielectric layer located on both sides of the first isolation dielectric wall along the width direction has been etched back in an embodiment of the present invention;

[0043] Figure 29 This is a longitudinal cross-sectional schematic diagram of the first structure after forming the first gate stack structure and the second gate stack structure in an embodiment of the present invention;

[0044] Figure 30 This is a longitudinal cross-sectional schematic diagram of the second structure after forming the first gate stack structure and the second gate stack structure in an embodiment of the present invention;

[0045] Figure 31 This is a schematic cross-sectional view of the structure after forming the first gate stack structure and the second gate stack structure in an embodiment of the present invention;

[0046] Figure 32 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0047] Reference numerals: 11 is a semiconductor substrate, 111 is a semiconductor substrate, 112 is a first dielectric layer, 12 is a first fin structure, 13 is a first semiconductor layer, 14 is a second semiconductor layer, 15 is a stacked layer, 151 is a first material layer, 152 is a second material layer, 16 is a sacrificial layer, 17 is an isolation region, 18 is an isolation dielectric material, 181 is a first isolation dielectric wall, 182 is a first isolation material, 1821 is a second isolation dielectric wall, 183 is a second isolation material, 1831 is a third isolation dielectric wall, 19 is... The second fin structure comprises: 191, the first region; 192, the second region; 193, the third region; 20, the sacrificial gate; 21, the gate sidewall; 22, the first source / drain region; 23, the second source / drain region; 24, the second dielectric layer; 25, the first channel region; 251, the first channel portion; 26, the second channel region; 261, the second channel portion; 27, the first gate stack structure; 28, the second gate stack structure; 29, the N-type transistor; 30, the P-type transistor; 31, the dielectric wall; 32, the gate stack structure; and 33, the channel region. Detailed Implementation

[0048] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0049] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0050] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0052] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0053] With the rapid development of the integrated circuit industry, the demand for high-speed, high-voltage circuit design is increasing. Simultaneously, the number of transistors per unit area is also increasing. Forksheet devices can reduce the spacing between N-type and P-type transistors, further reducing chip area while maintaining a horizontally stacked nanowire / sheet structure. Therefore, forksheet devices have become one of the best choices for next-generation device structures. Specifically, such as... Figure 1 As shown, existing Forksheet devices reduce the spacing between P-type transistors 30 and N-type transistors 29 by introducing a "dielectric wall 31" between P-type transistors 30 and N-type transistors 29 before gate patterning, which is beneficial for the miniaturization of semiconductor devices.

[0054] However, as Figure 1 As shown, in existing Forksheet devices, the channel regions 33 of the P-type transistor 30 and N-type transistor 29 are in contact with the dielectric wall 31. As a result, the gate stack structure 32 of the P-type transistor 30 and N-type transistor 29 does not cover the sidewall of the channel near the dielectric wall 31, which reduces the control capability of the P-type transistor 30 and N-type transistor 29 over the channel current and is not conducive to improving the electrical performance of the Forksheet device.

[0055] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by these embodiments, a first channel region of a first transistor and a second channel region of a second transistor are respectively spaced apart from a first isolation dielectric wall. This improves the control capability of the first gate stack structure over each first channel portion and the control capability of the second gate stack structure over the second channel portion, thereby enhancing the electrical performance of the semiconductor device.

[0056] like Figures 29 to 31 As shown, an embodiment of the present invention provides a semiconductor device. The semiconductor device includes: a semiconductor substrate 11, a first isolation dielectric wall 181, a first transistor, and a second transistor.

[0057] like Figures 29 to 31 As shown, the semiconductor substrate 11 includes a semiconductor substrate 111 and a first dielectric layer 112 located on the semiconductor substrate 111. A first isolation dielectric wall 181 is formed on the first dielectric layer 112. A first transistor is formed on the first dielectric layer 112 and located on one side of the first isolation dielectric wall 181 along its width direction. The first transistor includes a first channel region 25 spaced apart from the first isolation dielectric wall 181 and has at least two first channel portions 251. At least two first channel portions 251 are spaced apart along a width direction parallel to the first isolation dielectric wall 181. Each first channel portion 251 has a gap with the first dielectric layer 112, and a first gate stack structure 27 of the first transistor surrounds the outer periphery of each first channel portion 251. A second transistor is formed on the first dielectric layer 112 and located on the side of the first isolation dielectric wall 181 opposite to the first transistor. The second transistor includes a second channel region 26 spaced apart from the first isolation dielectric wall 181. The second transistor has an opposite conductivity type to the first transistor.

[0058] Specifically, the specific structure and materials of the aforementioned semiconductor substrate can be set according to the actual application scenario. For example: Figure 2 As shown, the semiconductor substrate 11 can be a silicon-on-insulator (SiI), a germanium-silicon-on-insulator (SiI), or a germanium-on-insulator (GU). In this case, the first dielectric layer 112 is a buried oxide layer located on the semiconductor substrate 111. For example, the first dielectric layer 112 included in the semiconductor substrate 11 is a shallow trench isolation layer formed on the semiconductor substrate 111 by processes such as chemical vapor deposition. In this case, the semiconductor substrate 111 can be a substrate made of semiconductor materials such as a silicon substrate, a germanium-silicon substrate, or a germanium substrate. Figure 3As shown, after the first fin structure 12 is formed on the semiconductor substrate 111, a first dielectric layer 112 can be formed on the portion of the semiconductor substrate 111 exposed outside the first fin structure 12 using processes such as chemical vapor deposition and etch-back. The thickness of the first dielectric layer 112 can be set according to actual needs and is not specifically limited here. The material of the first dielectric layer 112 can be an insulating material such as SiN, Si3N4, SiO2, or SiCO.

[0059] For the aforementioned first isolation dielectric wall, its shape and specifications can be set according to the actual application scenario, as long as it can isolate the first transistor and the second transistor with opposite conductivity types. For example: Figures 29 to 31 As shown, the first insulating dielectric wall 181 can be a fin-like structure formed on the first dielectric layer 112. The first insulating dielectric wall 181 can be a linear insulating dielectric wall, a wavy insulating dielectric wall, or an arc-shaped insulating dielectric wall, etc. The material of the first insulating dielectric wall 181 can be an insulating material such as SiN, Si3N4, SiO2, or SiCO.

[0060] Regarding the first and second transistors mentioned above, in terms of conductivity type, the first transistor can be an N-type transistor, in which case the second transistor is a P-type transistor. Alternatively, the first transistor can also be a P-type transistor, in which case the second transistor is an N-type transistor.

[0061] In terms of device type, such as Figure 29 and Figure 30 As shown, the first transistor is a gate-around transistor. The second transistor can be either a fin field-effect transistor or a gate-around transistor.

[0062] Specifically, the number of first channel portions in the first channel region of the first transistor can be set according to actual needs and is not specifically limited here. Furthermore, the spacing between two adjacent first channel portions, the minimum spacing between a first channel portion and the first isolation dielectric wall, and the spacing between each first channel portion and the first dielectric layer can be determined according to the specifications of the first gate stack structure included in the first transistor, and is not specifically limited here. Additionally, the materials of at least two first channel portions in the first channel region can be the same. For example, the materials of all first channel portions in the first channel region can be silicon, silicon germanium, or germanium. Alternatively, at least one first channel portion in the first channel region may be made of a different material than the remaining first channel portions. For example, in the case where the first channel region includes two first channel portions, the material of the first channel portion may be silicon, and the material of the other first channel portion may be silicon germanium.

[0063] The first transistor includes a first source / drain region and a first gate stack structure. The material of the first source / drain region can be a semiconductor material such as silicon, germanium-silicon, germanium, or a group III-V semiconductor material. The first gate stack structure includes at least a gate dielectric layer formed on the outer periphery of each first channel portion, and a gate formed on the gate dielectric layer. The material of the gate dielectric layer can be an insulating material with a low dielectric constant, such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant, such as HfO2, ZrO2, TiO2, or Al2O3. The material of the gate can be a conductive material such as polysilicon, TiN, TaN, or TiSiN.

[0064] As for the second transistor, the second transistor includes second source / drain regions formed on both sides of the second channel region along its length. The material of the second source / drain regions can be the same as or different from the material of the first source / drain regions. The specific structure of the second channel region and the second gate stack structure included in the second transistor can be determined according to the device type of the second transistor. For example, as shown... Figure 29 As shown, when the second transistor is a fin field-effect transistor, the second channel region 26 includes at least one second channel portion 261 formed on the first dielectric layer 112. Furthermore, the second gate stack structure 28 of the second transistor is formed on the top of each second channel portion 261 and on both sides along its width direction. The width direction of the second channel portion 261 is parallel to the width direction of the first insulating dielectric wall 181.

[0065] Or, such as Figure 30 As shown, when the second transistor is a gate-to-ring transistor, the second channel region 26 includes at least one second channel portion 261 formed above and spaced apart from the first dielectric layer 112. Furthermore, the second gate stack structure 28 of the second transistor surrounds the outer periphery of each second channel portion 261.

[0066] Regardless of whether the second transistor is a finned field-effect transistor or a gate-to-ring transistor, the number of second channel portions included in the second channel region can be one or more. The specific number of second channel portions included in the second channel region can be set according to the actual application scenario, and is not specifically limited here. For example, when the second channel region includes at least two second channel portions, the at least two second channel portions are distributed at intervals along the width direction parallel to the first isolation dielectric wall.

[0067] Specifically, the minimum spacing between all the second channel sections included in the second channel region and the first isolation medium wall, as well as the spacing between two adjacent second channel sections when the second channel region includes multiple second channel sections, can be set according to the specifications of the second grid stack structure, and are not specifically limited here.

[0068] Furthermore, when the second channel region includes multiple second channel sections, all second channel sections can be made of the same material, or at least one second channel section can be made of a different material than the others. Secondly, as... Figure 20 As shown, the material of the first channel region 25 can be the same as the material of the second channel region 26. Or, as... Figure 29 and Figure 30 As shown, the materials of the first channel region 25 and the second channel region 26 can also be different. In this case, by adjusting the materials of the first channel region 25 and the second channel region 26 respectively, the threshold voltages of the first transistor and the second transistor can be controlled, and the integration of N-type transistors and P-type transistors with heterogeneous channel materials in the Forksheet device can be achieved.

[0069] The second gate stack structure includes at least a gate dielectric layer forming the outer periphery of the second channel region, and a gate electrode formed on the gate dielectric layer. The materials of the gate dielectric layer and the gate electrode in the second gate stack structure can be referenced to the materials of the gate dielectric layer and the gate electrode in the first gate stack structure described above. Specifically, the material of the gate dielectric layer in the second gate stack structure can be the same as or different from the material of the gate dielectric layer in the first gate stack structure. The material of the gate electrode in the second gate stack structure can be the same as or different from the material of the gate electrode in the first gate stack structure.

[0070] As can be seen from the above, such as Figures 29 to 31As shown, in the semiconductor device provided in this embodiment of the invention, a first isolation dielectric wall 181 is formed on a first dielectric layer 112 included in the semiconductor substrate 11. A first transistor and a second transistor are respectively formed on both sides of the first isolation dielectric wall 181 along the width direction, and the first transistor and the second transistor have opposite conductivity types. Therefore, the semiconductor device provided in this embodiment of the invention is a forksheet device. In addition, the first channel region 25 included in the first transistor is spaced apart from the first isolation dielectric wall 181. Furthermore, along the width direction parallel to the first isolation dielectric wall 181, at least two first channel portions 251 included in the first channel region 25 are spaced apart. Each first channel portion 251 has a gap with the first dielectric layer 112. In this case, the top surface, bottom surface, and side surface along the width direction of each first channel portion 251 included in the first channel region 25 are exposed. This allows the first gate stack structure 27 included in the first transistor to surround the outer periphery of each first channel portion 251. This solves the problem in existing forksheet devices where the channel regions of both P-type and N-type transistors are in contact with the dielectric wall, preventing the gate stack structure from covering the sidewalls of the channel regions near the dielectric wall. This improves the control capability of the first gate stack structure 27 of the first transistor over each first channel portion 251. Similarly, because the second channel region 26 of the second transistor is spaced apart from the first isolation dielectric wall 181, the second gate stack structure 28 of the second transistor can also cover the sidewalls of the second channel portion 261 near the first isolation dielectric wall 181. This improves the control capability of the second gate stack structure 28 over the second channel portion 261 and enhances the electrical performance of the semiconductor device.

[0071] In addition, such as Figures 29 to 31 As shown, in the semiconductor device provided in the embodiment of the present invention, both the first transistor and the second transistor are formed on the first dielectric layer 112, and the first dielectric layer 112 is a non-conductive insulating layer. Therefore, the presence of the first dielectric layer 112 can prevent parasitic channel leakage and further improve the gate control capability of the first gate stack structure 27 and the second gate stack structure 28.

[0072] In one example, such as Figure 29 and Figure 30 As shown, the crystal orientation of the first channel region 25 can be

[110] . In this case, since a channel with a

[110] crystal orientation is conducive to the transmission of holes, when the crystal orientation of the first channel region 25 is

[110] , it is beneficial to improve the hole mobility of the first channel region 25.

[0073] Of course, the crystal orientation of the first channel region can be

[110] or

[100] . Since a channel with a

[100] crystal orientation is conducive to electron transport, when the crystal orientation of the first channel region is

[100] , it is beneficial to improve the electron mobility of the first channel region.

[0074] It is worth noting that, since the electron and hole mobilities of channels with

[100] and

[110] crystal orientations are different, the crystal orientation of the first channel region can be determined according to the conductivity type of the first transistor. For example, when the first transistor is an N-type transistor, the crystal orientation of the first channel region can be

[100] . As another example, when the first transistor is a P-type transistor, the crystal orientation of the first channel region can be

[110] .

[0075] In one example, such as Figure 29 and Figure 30 As shown, the crystal orientation of the second channel region 26 can be

[110] . The beneficial effects in this case can be referred to the analysis of the beneficial effects of the first channel region 25 having a

[110] crystal orientation described above, and will not be repeated here.

[0076] In addition, the crystal orientation of the second channel region can also be

[100] . The specific crystal orientation of the second channel region can be determined according to the conductivity type of the second channel region, and is not specifically limited here.

[0077] In one example, such as Figure 31 As shown, the semiconductor device described above may further include a second isolation dielectric wall 1821. This second isolation dielectric wall 1821 is formed on the side of the first source / drain region 22 included in the first transistor that faces away from the first isolation dielectric wall 181. In this case, as... Figure 13 and Figure 16 As shown, when the first source / drain region 22 of the first transistor is formed using a source-drain epitaxy method, the first isolation material 182 used to manufacture the second isolation dielectric wall can, together with the first isolation dielectric wall 181, define the formation space of the first source / drain region 22, which is beneficial to make the longitudinal cross-sectional shape of the first source / drain region 22 formed between the two rectangular. Figure 15 and Figure 16 As shown, all other things being equal, the rectangular source / drain region has a larger cross-sectional area than the rhomboid source / drain region. Therefore, the presence of this second isolation dielectric wall helps to reduce the resistance of the first source / drain region 22. The material of this second isolation dielectric wall can be referenced from the material of the first isolation dielectric wall 181 described above, and will not be repeated here.

[0078] In one example, such as Figure 31As shown, the semiconductor device also includes a third isolation dielectric wall 1831. This third isolation dielectric wall 1831 is formed on the side of the second source / drain region 23 included in the second transistor that faces away from the first isolation dielectric wall 181. Specifically, the beneficial effects in this case can be referred to the beneficial effect analysis of the second isolation dielectric wall 1821 described above, and will not be repeated here. Furthermore, the material of the third isolation dielectric wall 1831 can also be referred to the material of the first isolation dielectric wall 181 described above.

[0079] like Figure 32 As shown, this embodiment of the invention provides a method for manufacturing a semiconductor device. The following will describe a method based on... Figures 2 to 31 The illustrated perspective or cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes:

[0080] First, a semiconductor substrate is provided. The semiconductor substrate includes a semiconductor substrate and a first dielectric layer located on the semiconductor substrate. Specific information regarding the structure and materials of the semiconductor substrate can be found in the preceding text and will not be repeated here.

[0081] In practical applications, after providing the aforementioned semiconductor substrate and before performing subsequent operations, the method for manufacturing the semiconductor device may further include the following steps:

[0082] like Figure 2 and Figure 3 As shown, a first fin structure 12 is formed on a semiconductor substrate 11.

[0083] Specifically, the first fin structure is a pre-formed structure for creating the first isolation dielectric wall. The first isolation dielectric wall will subsequently be formed at the location where the first fin structure was removed. Therefore, the morphology of the first fin structure and its formation location on the semiconductor substrate can be determined based on the morphology and formation location of the first isolation dielectric wall. Furthermore, the material of the first fin structure can be silicon, germanium-silicon, germanium, or group III-V semiconductor materials, etc., to facilitate the subsequent formation of the first and second semiconductor layers using the first fin structure as a seed layer through epitaxial growth or other methods.

[0084] Understandably, the process of forming the first fin structure may differ depending on the semiconductor substrate structure. For example: Figure 2 As shown, when the semiconductor substrate 11 is a silicon-on-insulator (SiI), germanium-on-insulator (GNI), or germanium-silicon-on-insulator (CHSI) substrate, the semiconductor layer on the first dielectric layer 112 can be directly etched using photolithography and etching processes to form the first fin structure 12. Alternatively, a semiconductor material of a certain thickness can be formed on the semiconductor substrate 11 first, and then the semiconductor layer and semiconductor material on the first dielectric layer 112 can be etched using photolithography and etching processes to form the first fin structure 12.

[0085] For example: Figure 3 As shown, when the first dielectric layer 112 included in the semiconductor substrate 11 is a shallow trench isolation layer, the semiconductor substrate 111 can be directly etched using processes such as photolithography and etching to form the first fin structure 12. Then, the first dielectric layer 112 can be formed on the portion of the semiconductor substrate 111 exposed outside the first fin structure 12 using processes such as chemical vapor deposition and etching. Alternatively, a semiconductor material can be first formed on the semiconductor substrate 111 using processes such as epitaxial growth. Then, at least the semiconductor material can be etched using processes such as photolithography and etching to form the first fin structure 12. Finally, the first dielectric layer 112 is formed using the above method, thereby achieving the formation of the first fin structure 12 on the semiconductor substrate 11.

[0086] like Figure 4 As shown, a first semiconductor layer 13 is formed covering one side of the first fin structure 12 along its width direction, and a second semiconductor layer 14 is formed covering the other side of the first fin structure 12 along its width direction. Along a direction parallel to the width of the first fin structure 12, the first semiconductor layer 13 includes at least two stacked layers 15, and the second semiconductor layer 14 includes at least one stacked layer 15. Each stacked layer 15 includes a first material layer 151 and a second material layer 152 formed on the side of the first material layer 151 facing away from the first fin structure 12. The first material layer 151 and the second material layer 152 are made of different materials.

[0087] Specifically, each second material layer included in the first semiconductor layer is a film layer used to form the corresponding first channel portion included in the first channel region. Therefore, the number of layers in the stack included in the first semiconductor layer is equal to the number of first channel portions included in the first channel region. Information such as the material and specifications of the second material layers included in the first semiconductor layer can be determined based on information such as the material and specifications of each first channel portion included in the first channel region. Furthermore, the material of the first material layer included in the stack can be any semiconductor material different from the material of the second material layer. For example, if the material of the second material layer is Si, the material of the first material layer can also be Si. 0.5 Ge 0.5 .

[0088] For the second semiconductor layer, when the materials of the first channel region and the second channel region are the same, the second material layer included in the second semiconductor layer is a film layer used to form the corresponding second channel portion included in the second channel region. Therefore, the number of layers included in the second semiconductor layer is equal to the number of second channel portions included in the second channel region. The material and specifications of the second material layer included in the second semiconductor layer can be determined based on the material and specifications of each second channel portion included in the second channel region.

[0089] When the materials of the first channel region and the second channel region are different, the first material layer included in the second semiconductor layer is a film layer used to form the corresponding second channel portion included in the second channel region. Therefore, the number of layers included in the stack of the second semiconductor layer is equal to the number of second channel portions included in the second channel region. Information such as the material and specifications of the first material layer included in the second semiconductor layer can be determined based on information such as the material and specifications of each second channel portion included in the second channel region. Furthermore, in this case, if... Figure 5 As shown, after forming the first fin structure 12 and before forming the second semiconductor layer 14, a sacrificial layer 16 needs to be formed covering the other side of the first fin structure 12 along its width direction. After removing this sacrificial layer 16, the gap between the second channel region and the first isolation dielectric wall can be formed; therefore, the thickness of the sacrificial layer 16 can be determined according to the specifications of the second gate stack structure. Furthermore, the material of the sacrificial layer 16 can be any semiconductor material different from the material of the first material layer 151. The material of the sacrificial layer 16 can be the same as or different from the material of the second material layer 152.

[0090] In practical applications, the first semiconductor layer and the second semiconductor layer can be formed simultaneously. For example, epitaxial growth or other processes can be used to simultaneously form a first semiconductor material layer and a second semiconductor material layer for manufacturing the aforementioned first and second semiconductor layers. Then, chemical mechanical polishing or other processes can be used to planarize the first and second semiconductor material layers, exposing the top of the first fin structure. Correspondingly, the remaining portion of the first semiconductor material layer forms the first semiconductor layer, and the remaining portion of the second semiconductor material layer forms the second semiconductor layer.

[0091] Alternatively, the first semiconductor layer and the second semiconductor layer can be formed in different operational steps under the masking effect of corresponding mask layers. For example, a first mask layer can be formed first, covering one side of the first fin structure along its width. Then, using the exposed portion of the first fin structure as a seed layer, one of the first semiconductor layer and the second semiconductor layer is formed using the above-described process. The first mask layer is then removed, and a second mask layer is formed covering the first of the first and second semiconductor layers. Under the masking effect of the second mask layer, the other of the first and second semiconductor layers is formed using the above-described process, and finally, the second mask layer is removed.

[0092] like Figure 6 As shown, the first fin structure is removed to obtain an isolation region 17 between the first semiconductor layer 13 and the second semiconductor layer 14.

[0093] In practical applications, dry etching or wet etching processes can be used to selectively remove the first fin structure using an etchant that only has an etching effect on the first fin structure, thereby obtaining an isolation area.

[0094] like Figure 8 As shown, after removing the first fin structure, a first isolation medium wall 181 is formed on the first medium layer 112. Specifically, forming the first isolation medium wall 181 on the first medium layer 112 includes the step of forming the first isolation medium wall 181 within the isolation area.

[0095] In practical applications, such as Figure 7 As shown, the insulating medium material 18 used for manufacturing the first insulating medium wall can be formed using processes such as chemical vapor deposition. Next, as... Figure 8 and Figure 9 As shown, excess isolation dielectric material can be removed using processes such as dry etching or wet etching. Specifically, the portion of the isolation dielectric material to be removed can be determined based on the specific structure of the semiconductor device to be manufactured.

[0096] For example: Figure 8 As shown, if the semiconductor device to be manufactured only includes the first isolation dielectric wall 181 and does not include the second and third isolation dielectric walls, it is necessary to remove the portion of the isolation dielectric material located outside the isolation region. In this case, as... Figure 8 As shown, the first semiconductor layer 13, the second semiconductor layer 14, and the first isolation dielectric wall 181 constitute the second fin structure 19. Along the width direction of the second fin structure 19, the second fin structure 19 includes a first region 191, a second region 192, and a third region 193 located between the first region 191 and the second region 192.

[0097] For example, if the semiconductor device to be manufactured only includes a first isolation dielectric wall and a second isolation dielectric wall, it is necessary to remove the portion of the isolation dielectric material covering the top of the first semiconductor layer, the second semiconductor layer and the isolation region, as well as the portion covering the sidewall of the second semiconductor layer away from the isolation region.

[0098] For example, if the semiconductor device to be manufactured only includes a first isolation dielectric wall and a third isolation dielectric wall, it is necessary to remove the portion of the isolation dielectric material covering the top of the first semiconductor layer, the second semiconductor layer and the isolation region, as well as the portion covering the sidewall of the first semiconductor layer away from the isolation region.

[0099] For example: Figure 9As shown, when the semiconductor device to be manufactured includes a first isolation dielectric wall 181, a second isolation dielectric wall, and a third isolation dielectric wall, only the portion of the isolation dielectric material covering the first semiconductor layer 13, the second semiconductor layer 14, and the top of the isolation region needs to be removed. At this time, the portion of the isolation dielectric material remaining on the side of the first semiconductor layer 13 opposite to the first isolation dielectric wall 181 is the first isolation material 182. The portion of the isolation dielectric material remaining on the side of the second semiconductor layer 14 opposite to the first isolation dielectric wall 181 is the second isolation material 183.

[0100] like Figures 29 to 31 As shown, after the first isolation dielectric wall 181 is formed, a first transistor and a second transistor are formed on the first dielectric layer 112. The first transistor is located on one side of the first isolation dielectric wall 181 along its width direction. The first transistor includes a first channel region 25 spaced apart from the first isolation dielectric wall 181 and has at least two first channel portions 251. At least two first channel portions 251 are spaced apart along a width direction parallel to the first isolation dielectric wall 181. Each first channel portion 251 has a gap with the first dielectric layer 112, and the first gate stack structure 27 of the first transistor surrounds the outer periphery of each first channel portion 251. The second transistor is located on the side of the first isolation dielectric wall 181 opposite to the first transistor. The second transistor includes a second channel region 26 spaced apart from the first isolation dielectric wall 181. The second transistor has the opposite conductivity type to the first transistor.

[0101] Specifically, information regarding the conductivity type, structure, and materials of the first and second transistors can be found in the preceding text and will not be repeated here. Furthermore, the manufacturing order of the first and second transistors can be set according to actual needs and is not specifically limited here. For example, one of the first and second transistors can be manufactured first under the masking effect of the corresponding mask layer, and then the other can be manufactured. Another example is that the first and second transistors can also be formed simultaneously.

[0102] In practical applications, alternative gate processes are typically used to form the first gate stack structure of the first transistor and the second gate stack structure of the second transistor, in order to improve the formation quality of the manufactured first and second gate stack structures. In this case, after forming the first isolation dielectric wall on the first dielectric layer and before forming the first and second transistors on the first dielectric layer, such as... Figure 10 As shown, a sacrificial gate 20 can be formed across the third region included in the second fin structure 19 using processes such as chemical vapor deposition and etching. The material of the sacrificial gate 20 can be polysilicon or other materials that are easy to remove.

[0103] It should be noted that, as Figure 11As shown, if the manufactured semiconductor device further includes a second isolation dielectric wall and / or a third isolation dielectric wall, the sacrificial gate 20 also spans a portion of the third region corresponding to the first isolation material and / or the second isolation material.

[0104] For example, such as Figure 12 As shown, after forming the sacrificial gate 20, chemical vapor deposition and etching processes can be used to form gate sidewalls 21 located on at least both sides of the sacrificial gate 20 along its length direction. This isolates the subsequently formed first gate stack structure and second gate stack structure from other conductive structures, improving the electrical characteristics of the semiconductor device. The length direction of the sacrificial gate 20 is parallel to the length direction of the first isolation dielectric wall. The thickness of the gate sidewall 21 can be set according to actual needs and is not specifically limited here. The material of the gate sidewall 21 can be an insulating material such as silicon oxide or silicon nitride.

[0105] In practical applications, after forming the sacrificial gate and before subsequent operations, the portion of the first semiconductor layer located in the first and second regions can be processed to form the first source / drain region of the first transistor; and the portion of the second semiconductor layer located in the first and second regions can be processed to form the second source / drain region of the second transistor. Specifically, the formation order and process of the first and second source / drain regions can be set according to actual needs and are not specifically limited here. For example, the first source / drain region can be formed first under the masking effect of the corresponding mask layer, and then the second source / drain region can be formed. Alternatively, the second source / drain region can be formed first under the masking effect of the corresponding mask layer, and then the first source / drain region can be formed.

[0106] The formation processes of the first and second source / drain regions will be divided into at least two cases based on their different formation processes:

[0107] The first method: The first and second source / drain regions are formed using source-drain epitaxy. In this case, such as... Figure 13 and Figure 14 As shown, at least under the masking effect of the sacrificial gate 20, wet etching or dry etching processes can be used to simultaneously remove portions of the first semiconductor layer located in the first and second regions, as well as portions of the second semiconductor layer located in the first and second regions. Alternatively, portions of one of the first and second semiconductor layers located in the first and second regions can be removed first, and after forming the corresponding source / drain regions, portions of the other semiconductor layer located in the first and second regions can be removed.

[0108] The following example illustrates the process of simultaneously removing portions of the first semiconductor layer located in the first and second regions, as well as portions of the second semiconductor layer located in the first and second regions, and first forming a first source / drain region. Figure 13 and Figure 14 As shown, after the above removal operation, the sidewalls of the portions of the first and second semiconductor layers located in the third region 193 are exposed. At this time, photolithography and etching processes can be used to form a first mask layer covering at least the sidewalls of the portion of the second semiconductor layer located in the third region 193. Then, under the masking effect of the first mask layer, and using the portion of the first semiconductor layer located in the third region 193 as a seed layer, epitaxial growth and other processes are used to form first source / drain regions on both sides of the remaining portion of the first semiconductor layer along the length direction. Next, the first mask layer is removed, and a second mask layer is formed covering the first source / drain regions. Then, under the masking effect of the second mask layer, and using the portion of the second semiconductor layer located in the third region as a seed layer, epitaxial growth and other processes are used to form second source / drain regions on both sides of the remaining portion of the second semiconductor layer along the length direction. Finally, as... Figure 15 and Figure 16 As shown, the second mask layer is removed.

[0109] It should be noted that, as mentioned above, after forming the first semiconductor layer covering one side of the first fin structure along its width, as... Figure 9 As shown, a first insulating material 182 is formed covering the side of the first semiconductor layer 13 opposite to the first fin structure. In this case, as... Figure 16 As shown, the first source / drain region 22 can be formed between the first isolation material 182 and the first isolation dielectric wall 181, and on both sides of the first semiconductor layer located in the third region, in the manner described above. The first isolation material 182 and the first isolation dielectric wall 181 can jointly restrict the formation space of the first source / drain region 22, which is conducive to forming the first source / drain region 22 with a rectangular longitudinal cross-section.

[0110] In addition, for the second source-drain region, it can be as follows: Figure 15 As shown, the second source / drain region 23 is formed using the methods described above. Alternatively, as previously stated, after forming a second semiconductor layer covering the other side of the first fin structure along its width direction, as... Figure 9 As shown, a second insulating material 183 is formed covering the side of the second semiconductor layer 14 opposite to the first fin structure. In this case, as... Figure 16 As shown, after removing the portion of the second semiconductor layer located in the first and second regions, the second source / drain region 23 of the second transistor can be formed between the second isolation material 183 and the first isolation dielectric wall 181, and on both sides of the second semiconductor layer located in the third region, in the manner described above.

[0111] The second method involves forming the first and second source / drain regions using ion implantation. In this case, taking the formation of the first source / drain region as an example, after forming a sacrificial gate (or sacrificial gate and gate sidewall) spanning the third region included in the second fin structure, photolithography and etching processes can be used to form a first mask layer covering the portions of the second semiconductor layer located in the first and second regions. Then, under the masking effect of the first mask layer, ion implantation is used to process the portions of the first semiconductor layer located in the first and second regions to form the first source / drain region. Next, the first mask layer is removed, and a second mask layer is formed covering the first source / drain region. Under the masking effect of the second mask layer, ion implantation is used to process the portions of the second semiconductor layer located in the first and second regions to form the second source / drain region. Finally, the second mask layer is removed.

[0112] It is understandable that the above method can also be used, after forming the sacrificial gate across the third region included in the second fin structure, to use an ion implantation process to first process the portion of the second semiconductor layer located in the first and second regions to form the second source / drain region, and then form the first source / drain region.

[0113] Furthermore, the first source / drain region and the second source / drain region can both be formed using source / drain epitaxy or ion implantation. Alternatively, one of the first source / drain region and the second source / drain region can be formed using source / drain epitaxy, while the other can be formed using ion implantation.

[0114] like Figure 17 As shown, a second dielectric layer 24 covering the first dielectric layer 112 can be formed using processes such as chemical vapor deposition and chemical mechanical polishing. When a replacement gate process is used to form the first gate stack structure and the second gate stack structure, the presence of this second dielectric layer 24 can protect the first source / drain region and the second source / drain region from subsequent operations such as removing the sacrificial gate 20, thereby improving the yield of the semiconductor device. Specifically, the top of the second dielectric layer 24 is flush with the top of the sacrificial gate 20. The material of the second dielectric layer can be any insulating material different from the material of the first dielectric layer 112, to prevent the second dielectric layer 24 from being affected during subsequent etch-back processing, at least on the portion of the first dielectric layer 112 located below the first transistor. For example, if the material of the first dielectric layer 112 is silicon oxide, the material of the second dielectric layer 24 can be silicon nitride.

[0115] like Figure 18 As shown, wet etching or dry etching processes can be used to remove the sacrificial gate under the masking effect of the second dielectric layer.

[0116] Understandably, after removing the sacrificial gate, portions of the first and second semiconductor layers located in the third region are exposed. At this point, the formation process of the first and second channel regions can be determined based on the materials of the first and second channel regions and the actual application scenario.

[0117] In one example, forming a first transistor on a first dielectric layer may include the following steps: after removing the sacrificial gate, such as Figure 20 , Figure 21 and Figure 25 As shown, the portion of the first material layer 151 included in the first semiconductor layer located in the third region is selectively removed. For example... Figure 27 and Figure 28 As shown, the portion of the first dielectric layer 112 located on the side of the first isolation dielectric wall 181 near the first semiconductor layer is etched back to form a corresponding first channel portion 251 in the second material layer included in the first semiconductor layer. Figures 29 to 31 As shown, a first gate stack structure 27 is formed around the outer periphery of each first channel portion 251.

[0118] In practical applications, such as Figure 20 As shown, when the materials of the first channel region and the second channel region are the same, wet etching or dry etching processes can be used to selectively remove the first material layer 151 of the first semiconductor layer and the first semiconductor layer 13 of the second semiconductor layer. Alternatively, the first material layer 151 of the first semiconductor layer and the first material layer 151 of the second semiconductor layer can be selectively removed in different operation steps.

[0119] Or, such as Figure 21 As shown, when the materials of the first channel region and the second channel region are different, the first material layer comprising the first semiconductor layer can be selectively removed under the masking effect of the corresponding mask layer using the above-described process. Then, as... Figure 22 As shown, under the masking effect of the corresponding mask layer, the sacrificial layer and the second semiconductor layer, including the second material layer, are selectively removed. Finally, as... Figure 23 As shown, the corresponding mask layer is removed.

[0120] Or, if the materials in the first trench area and the second trench area are different, such as Figure 24 As shown, under the masking effect of the corresponding mask layer, the sacrificial layer and the second semiconductor layer, including the second material layer, can be selectively removed first. Then, as... Figure 25 As shown, under the masking effect of the corresponding mask layer, the first material layer including the first semiconductor layer is selectively removed. Finally, the corresponding mask layer is removed.

[0121] After forming at least the gap between adjacent first channel portions, the gap between the first channel region and the first isolation dielectric wall, and the gap between the second channel region and the first isolation dielectric wall in the manner described above, the formation process of the first gate stack structure and the second gate stack structure can be determined according to the device types of the first transistor and the second transistor.

[0122] Specifically, because the first transistor is a gate-around transistor, after the first channel region is formed, as... Figure 26 As shown, under the masking effect of the corresponding mask layer, wet etching or dry etching processes can be used to etch back the portion of the first dielectric layer 112 located on the side of the first isolation dielectric wall 181 close to the first semiconductor layer, so as to form a gap between the first dielectric layer 112 and the second material layer included in the first semiconductor layer, so that the second material layer included in the first semiconductor layer forms the corresponding first channel portion 251.

[0123] Additionally, when the first transistor is a fin field-effect transistor, such as Figure 20 As shown, when the materials of the first channel region and the second channel region are the same, after the above-described selective removal operation, the second material layer included in the second semiconductor layer can form the second channel region. For example... Figure 22 and Figure 24 As shown, when the materials of the first channel region and the second channel region are different, after the above-described selective removal operation, the first material layer 151 included in the second semiconductor layer can form the second channel region.

[0124] When the first transistor is a gate-around transistor, forming the second channel region also includes the following steps: Figure 28 As shown, the portion of the first dielectric layer 112 located on the side of the first isolation dielectric wall 181 near the second semiconductor layer is etched back to form a gap between the first dielectric layer 112 and the second channel region 26.

[0125] It should be noted that, as mentioned above, if the first isolation material is formed before the formation of the first source / drain region and the second source / drain region, then after removing the sacrificial gate and before forming the first channel region; or after forming the first channel region and before forming the first gate stack structure, the semiconductor device manufacturing method further includes the step of: Figures 20 to 31 As shown, wet etching and other processes are used to remove the portion of the first isolation material exposed outside the second dielectric layer 24, so that the remaining portion of the first isolation material forms the second isolation dielectric wall 1821.

[0126] Accordingly, as mentioned above, if the second isolation material is formed before the formation of the first source / drain region and the second source / drain region, then after removing the sacrificial gate and before forming the second channel region; or after forming the second channel region and before forming the second gate stack structure, the method for manufacturing the semiconductor device further includes the step of: Figures 20 to 31 As shown, wet etching and other processes are used to remove the portion of the second isolation material exposed outside the second dielectric layer 24, so that the remaining portion of the second isolation material forms the third isolation dielectric wall 1831.

[0127] Finally, as Figure 29 and Figure 30 As shown, a first gate stack structure 27 surrounding each first channel portion 251 can be formed using processes such as atomic layer deposition. The first gate stack structure 27 can be formed after the first channel region 25 and the second channel region 26 are formed. Alternatively, it can be formed after the first channel region 25 is formed under the masking effect of the corresponding mask layer, but before the second channel region 26 is formed. The material of the first gate stack structure 27 can be referred to the preceding text.

[0128] As for the second gate stack structure, processes such as atomic layer deposition can be used to form the second gate stack structure at least around the outer periphery of the second channel region. The formation sequence of the second gate stack structure can be after the formation of the first and second channel regions. Alternatively, it can be formed after the second channel region is formed under the masking effect of the corresponding mask layer, but before the formation of the first channel region. The material for this second gate stack structure can be found in the preceding text.

[0129] It should be noted that the first gate stack structure and the second gate stack structure can be formed in various ways. How the first gate stack structure and the second gate stack structure are formed is not the main feature of this invention. Therefore, this specification only provides a brief description to enable those skilled in the art to easily implement this invention. Those skilled in the art can certainly conceive of other ways to fabricate the above structure.

[0130] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided in the embodiments of the present invention can be found in the analysis of the beneficial effects of the semiconductor device provided in the embodiments of the present invention, which will not be repeated here.

[0131] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0132] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate, the semiconductor substrate comprising a semiconductor substrate and a first dielectric layer located on the semiconductor substrate; A first isolation medium wall is formed on the first medium layer; A first transistor is formed on the first dielectric layer and located on one side of the first isolation dielectric wall along its width direction; the first transistor includes a first channel region spaced apart from the first isolation dielectric wall and having at least two first channel portions; at least two first channel portions are spaced apart along a width direction parallel to the first isolation dielectric wall; each first channel portion has a gap with the first dielectric layer; the first transistor includes a first gate stack structure surrounding the outer periphery of each first channel portion; the first dielectric layer isolates the first transistor from the semiconductor substrate; A second transistor is formed on the first dielectric layer and located on the side of the first isolation dielectric wall opposite to the first transistor; the second transistor includes a second channel region that is spaced apart from the first isolation dielectric wall; the second transistor has a conductivity type opposite to that of the first transistor; the first dielectric layer isolates the second transistor from the semiconductor substrate; Gate sidewalls are formed on the first dielectric layer; The gate sidewalls are located at least on both sides of the first gate stack structure along the length direction and at least on both sides of the second gate stack structure included in the second transistor along the length direction; The overall structure formed by the first gate stack structure and the second gate stack structure, and the gate sidewall spanning the first isolation dielectric wall.

2. The semiconductor device according to claim 1, characterized in that, At least two of the first channel sections are made of the same material; or, At least one of the first channel portions is made of a different material than the rest of the first channel portions.

3. The semiconductor device according to claim 1, characterized in that, When the second transistor is a fin field-effect transistor, the second channel region includes at least one second channel portion formed on the first dielectric layer; The second transistor includes a second gate stack structure formed on the top of each second channel portion and on both sides along the width direction; the width direction of the second channel portion is parallel to the width direction of the first isolation dielectric wall.

4. The semiconductor device according to claim 1, characterized in that, When the second transistor is a gate-around transistor, the second channel region includes at least one second channel portion formed above and spaced apart from the first dielectric layer; The second transistor includes a second gate stack structure surrounding the outer periphery of each of the second channel portions.

5. The semiconductor device according to claim 3 or 4, characterized in that, In the case where the second channel region includes at least two second channel portions, the at least two second channel portions are distributed at intervals along the width direction parallel to the first isolation medium wall.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that, The materials of the first channel region and the second channel region are different.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that, The crystal orientation of the first channel region is [110]; and / or, The crystal orientation of the second channel region is [110].

8. The semiconductor device according to any one of claims 1 to 4, characterized in that, The semiconductor device further includes a second isolation dielectric wall formed on the side of the first source / drain region of the first transistor opposite to the first isolation dielectric wall; and / or, The semiconductor device further includes a third isolation dielectric wall formed on the side of the second source / drain region of the second transistor opposite to the first isolation dielectric wall.

9. A method for manufacturing a semiconductor device, characterized in that, include: Provide a semiconductor substrate; The semiconductor substrate includes a semiconductor substrate and a first dielectric layer located on the semiconductor substrate; A first isolation medium wall is formed on the first medium layer; A first transistor, a second transistor, and a gate sidewall are formed on the first dielectric layer. The first transistor is located on one side of the first isolation dielectric wall along its width direction. The first transistor includes a first channel region spaced apart from the first isolation dielectric wall and has at least two first channel portions. At least two first channel portions are spaced apart along a width direction parallel to the first isolation dielectric wall. Each first channel portion has a gap with the first dielectric layer. The first gate stack structure of the first transistor surrounds the outer periphery of each first channel portion. The first dielectric layer isolates the first transistor from the semiconductor substrate. The second transistor is located on the side of the first isolation dielectric wall opposite to the first transistor. The second channel region of the second transistor is spaced apart from the first isolation dielectric wall. The second transistor has an opposite conductivity type to the first transistor. The first dielectric layer isolates the second transistor from the semiconductor substrate. The gate sidewall is formed on the first dielectric layer. The gate sidewall is located at least on both sides of the first gate stack structure along its length direction and at least on both sides of the second gate stack structure of the second transistor along its length direction. The overall structure formed by the first gate stack structure and the second gate stack structure, and the gate sidewall spanning the first isolation dielectric wall.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, After providing a semiconductor substrate, and before forming a first isolation dielectric wall on the first dielectric layer, the method for manufacturing the semiconductor device further includes: A first fin-like structure is formed on the semiconductor substrate; A first semiconductor layer is formed covering one side of the first fin structure along its width direction, and a second semiconductor layer is formed covering the other side of the first fin structure along its width direction; along a direction parallel to the width of the first fin structure, the first semiconductor layer includes at least two stacked layers, and the second semiconductor layer includes at least one stacked layer; each stacked layer includes a first material layer and a second material layer formed on the side of the first material layer opposite to the first fin structure; the first material layer and the second material layer are made of different materials; Remove the first fin structure to obtain an isolation region between the first semiconductor layer and the second semiconductor layer; The step of forming a first isolation medium wall on the first medium layer includes: forming the first isolation medium wall within the isolation area.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The first semiconductor layer, the second semiconductor layer, and the first isolation dielectric wall constitute a second fin structure; along the width direction of the second fin structure, the second fin structure includes a first region, a second region, and a third region located between the first region and the second region; After forming a first isolation dielectric wall on the first dielectric layer and before forming a first transistor and a second transistor on the first dielectric layer, the method for manufacturing the semiconductor device further includes: A sacrificial gate is formed across the third region included in the second fin structure; Form gate sidewalls at least on both sides of the sacrificial gate along its length; A second dielectric layer is formed over the first dielectric layer; the top of the second dielectric layer is flush with the top of the sacrificial gate. Remove the sacrificial gate.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, Forming the first transistor on the first dielectric layer includes: Selectively remove the portion of the first material layer, which is part of the first semiconductor layer, located within the third region; The portion of the first dielectric layer located on the side of the first isolation dielectric wall near the first semiconductor layer is etched back so that the second material layer included in the first semiconductor layer forms the corresponding first channel portion; A first gate stack structure is formed around the outer periphery of each first channel portion.

13. The method for manufacturing a semiconductor device according to claim 11, characterized in that, When the materials of the first channel region and the second channel region are the same, forming the second transistor on the first dielectric layer includes: Selectively remove a portion of the first material layer included in the second semiconductor layer located within the third region; and cause the second material layer included in the second semiconductor layer to form the second channel region.

14. The method for manufacturing a semiconductor device according to claim 11, characterized in that, When the materials of the first channel region and the second channel region are different, After forming the first fin structure on the semiconductor substrate, before forming the second semiconductor layer covering the other side of the first fin structure along the width direction, the method for manufacturing the semiconductor device further includes: forming a sacrificial layer covering the other side of the first fin structure along the width direction. Forming the second transistor on the first dielectric layer includes: selectively removing a portion of the sacrificial layer corresponding to the third region, and a portion of the second material layer included in the second semiconductor layer located within the third region; and causing the first material layer included in the second semiconductor layer to form the second channel region.

15. The method for manufacturing a semiconductor device according to claim 13 or 14, characterized in that, When the second transistor is a gate-around transistor, forming the second channel region includes: The portion of the first dielectric layer located on the side of the first isolation dielectric wall near the second semiconductor layer is etched back.

16. The method for manufacturing a semiconductor device according to claim 11, characterized in that, After forming a first semiconductor layer covering one side of the first fin structure along its width direction, and before forming the first transistor on the first dielectric layer, the method for manufacturing the semiconductor device further includes: forming a first isolation material covering the side of the first semiconductor layer opposite to the first fin structure. After forming a sacrificial gate spanning the third region included in the second fin structure, and before forming a second dielectric layer covering the first dielectric layer, the method of manufacturing the semiconductor device further includes: Remove the portion of the first semiconductor layer located within the first and second regions; The first source / drain region of the first transistor is formed between the first isolation material and the first isolation dielectric wall, and on both sides of the first semiconductor layer located in the third region; Before forming the first gate stack structure of the first transistor after removing the sacrificial gate, the method for manufacturing the semiconductor device further includes: removing the portion of the first isolation material exposed outside the second dielectric layer, such that the remaining portion of the first isolation material forms a second isolation dielectric wall.

17. The method for manufacturing a semiconductor device according to claim 11, characterized in that, After forming a second semiconductor layer covering the other side of the first fin structure along its width direction, and before forming the second transistor on the first dielectric layer, the method for manufacturing the semiconductor device further includes: forming a second isolation material covering the side of the second semiconductor layer opposite to the first fin structure; After forming a sacrificial gate spanning the third region included in the second fin structure, and before forming a second dielectric layer covering the first dielectric layer, the method of manufacturing the semiconductor device further includes: Remove the portion of the second semiconductor layer located within the first and second regions; The second source / drain region of the second transistor is formed between the second isolation material and the first isolation dielectric wall, and on both sides of the second semiconductor layer located in the third region; Before forming the second gate stack structure of the second transistor after removing the sacrificial gate, the method for manufacturing the semiconductor device further includes: removing the portion of the second isolation material exposed outside the second dielectric layer, such that the remaining portion of the second isolation material forms a third isolation dielectric wall.

18. The method for manufacturing a semiconductor device according to claim 11, characterized in that, After forming the sacrificial gate spanning the third region included in the second fin structure, and before forming the second dielectric layer covering the first dielectric layer, the method of manufacturing the semiconductor device further includes: using an ion implantation process to process portions of the first semiconductor layer located in the first and second regions to form the first source / drain region included in the first transistor; and / or, After forming the sacrificial gate spanning the third region included in the second fin structure and before forming the second dielectric layer covering the first dielectric layer, the method of manufacturing the semiconductor device further includes: using an ion implantation process to process portions of the second semiconductor layer located in the first and second regions to form the second source / drain region included in the second transistor.

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