Silicon carbide mosfet devices hardened against single event effects and methods of making the same

Abstract

The application provides a single-particle radiation hardened silicon carbide MOSFET device and a preparation method thereof, and the single-particle radiation hardened silicon carbide MOSFET device is obtained by introducing a protruding P-type body region and a low-doped N-type resistance region, and the single-particle radiation resistance is improved; in a blocking state, when a heavy ion is incident on the silicon carbide MOSFET device and a large number of electron-hole pairs are generated along the incident path, the deposited holes are quickly extracted from the protruding P-type body region, and the parasitic NPN transistor is inhibited from being turned on; if the parasitic NPN transistor is turned on, the low-doped N-type resistance region can effectively inhibit the injection efficiency of the electrons, the N-type gradual doping region close to the N+ substrate region modulates the space electric field, the high electric field at the N+ substrate region / N-drift region caused by the base region widening effect is inhibited, the occurrence of the internal local hot spot of the device and the single-particle burnout are effectively reduced. The application effectively improves the single-particle radiation resistance of the silicon carbide MOSFET under the premise that the static parameters of the trench-type silicon carbide MOSFET device are not degraded.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, specifically a single-particle irradiation-hardened silicon carbide MOSFET device. Background Technology

[0002] In aviation, aerospace, and military equipment, power semiconductor devices are mainly used in power supply and distribution subsystems and are core components. Power semiconductor devices using Si materials are gradually reaching their theoretical limits, and it is difficult to further achieve high-frequency, high-power-density, and miniaturized power converters at the current research level.

[0003] The American Astronautical Federation (ANAS) has proposed a solar-powered electric propulsion platform for near-Earth spacecraft propulsion and orbital transfer. Calculations show that increasing the spacecraft bus voltage from 100V to 300V would reduce the weight of the power and propulsion systems of the solar-powered platform by 2457 kg. However, a 300V bus voltage platform requires 600V-rated MOSFET devices. Existing silicon-based radiation-hardened MOSFET devices cannot meet this requirement, while high-voltage SiC devices are in significant demand in the 300V bus spacecraft power subsystems (DDU, PPU), and Hall thrusters.

[0004] Silicon carbide (SiC) materials, characterized by a large bandgap, high critical breakdown electric field, high thermal conductivity, and high electron saturation drift velocity, can better meet the demands of rapidly developing aerospace technology for higher operating frequencies, higher operating voltages, lower on-resistance, and high power density in power semiconductor devices. They also possess the ability to withstand radiation, extreme high temperatures, and other special environmental conditions. Summary of the Invention

[0005] To address the aforementioned issues, this invention proposes a single-particle irradiation-hardened silicon carbide MOSFET device and its fabrication method. By introducing a prominent P-type body region and a lightly doped N-type resistive region, the single-particle irradiation resistance is enhanced. In the blocking state, when heavy ions are incident on the silicon carbide MOSFET device and generate a large number of electron-hole pairs along the incident path, the deposited holes are rapidly extracted from the prominent P-type body region, suppressing the turn-on of parasitic NPN transistors. Simultaneously, if parasitic NPN transistors are turned on, the lightly doped N-type resistive region can effectively suppress electron injection efficiency. The N-type slowly varying doped region near the N+ substrate region can modulate the spatial electric field, suppressing the high electric field at the N+ substrate region / N- drift region caused by the base region broadening effect, effectively reducing the occurrence of local hot spots and single-particle burn-off within the device. This invention effectively improves the single-particle irradiation resistance of silicon carbide MOSFETs without degrading the static parameters of the trench-type silicon carbide MOSFET device.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A single-particle irradiation-hardened silicon carbide MOSFET device includes a drain metal 6, an N+ substrate region 5 above the drain metal 6, an N-type gradually changing doped region 9 above the N+ substrate region 5, and an N- drift region 4 above the N-type gradually changing doped region 9. The doping concentration of the N-type gradually changing doped region 9 gradually decreases along the direction from the N+ substrate region 5 to the N- drift region 4. A gate groove is provided in the upper middle of the interior of the N- drift region 4. A polysilicon gate 51 and a gate dielectric 62 of the gate groove are provided in the gate groove. A first P-type base region 3 is located to the lower left of the gate groove, and a first N-ballast resistor region 8 is located to the upper left of the gate groove. A first P+ ohmic contact region A is located to the left of the first N-ballast resistor region 8, and a first N+ source region is located to the upper left of the first N-ballast resistor region 8 and to the right of the first P+ ohmic contact region A. Region 7: The first P+ ohmic contact region B is located to the upper right of the first N-ballast resistor region 8 and to the left of the gate recess; the second P-type base region 31 is located to the lower right of the gate recess; the second N-ballast resistor region 81 is located to the upper right of the gate recess; the second P+ ohmic contact region A is located to the right of the second N-ballast resistor region 81; the second N+ source region 71 is located to the upper right of the second N-ballast resistor region 81 and to the left of the second P+ ohmic contact region A; the second P+ ohmic contact region B is located to the upper left of the second N-ballast resistor region 81 and to the right of the gate recess; source metal 1 is located above the first P+ ohmic contact region A, the first P+ ohmic contact region B, and the first N+ source region 7; source metal 1 is located above the second P+ ohmic contact region A, the second P+ ohmic contact region B, and the second N+ source region 71.

[0008] As a preferred embodiment, the gate dielectric 62 is SiO2.

[0009] As a preferred embodiment, the first P+ ohmic contact region 2, the first N+ source region 7, the first N- ballast resistor region 8, the first P-type base region 3, the second P+ ohmic contact region 21, the second N+ source region 71, the second N- ballast resistor region 81, and the second P-type base region 31 are all formed by multiple ion implantations.

[0010] As a preferred embodiment, the materials of the first P+ ohmic contact region 2, the first N+ source region 7, the first N- ballast resistor region 8, the first P-type base region 3, the second P+ ohmic contact region 21, the second N+ source region 71, the second N- ballast resistor region 81, the second P-type base region 31, the N- drift region 4, the N-type slow-change doping region 9, and the N+ substrate region 5 are all silicon carbide.

[0011] This invention also provides a method for fabricating a single-particle irradiation-hardened silicon carbide MOSFET device, comprising the following steps:

[0012] Step 1: Clean the epitaxial wafer and implant aluminum ions onto the N-epitaxial layer to form a P-type base region;

[0013] Step 2: Nitrogen ions are implanted into polysilicon as an implantation barrier layer to form an N-ballast resistance region;

[0014] Step 3: Using polysilicon as an implantation barrier layer, aluminum ions are implanted to form a P+ ohmic contact region;

[0015] Step 4: Nitrogen ions are injected using polysilicon as an implantation barrier layer to form an N+ source region;

[0016] Step 5: Etching to form gate trenches;

[0017] Step 6: Dry oxygen oxidation is used to generate a gate oxide layer, followed by annealing and deposition of polysilicon in a nitrogen atmosphere to pattern the polysilicon;

[0018] Step 7: Deposit and etch metal to form electrodes.

[0019] This invention enhances the resistance to single-event irradiation by introducing a prominent P-type body region and a lightly doped N-type resistive region. In the blocking state, when heavy ions are incident on a silicon carbide MOSFET device and generate a large number of electron-hole pairs along the incident path, the deposited holes are rapidly extracted from the prominent P-type body region, suppressing the turn-on of parasitic NPN transistors. Simultaneously, if parasitic NPN transistors are turned on, the lightly doped N-type resistive region effectively suppresses electron injection efficiency. The N-type gradually varying doped region near the N+ substrate region modulates the spatial electric field, suppressing the high electric field at the N+ substrate / N- drift region caused by the base region broadening effect, effectively reducing the occurrence of localized hot spots and single-event burn-off within the device. This invention effectively improves the resistance to single-event irradiation of silicon carbide MOSFETs without degrading the static parameters of the trench-type silicon carbide MOSFET device. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a traditional trench silicon carbide MOSFET structure with a P+ shielding layer.

[0021] Figure 2 This is a schematic diagram of the single-particle irradiation-hardened silicon carbide MOSFET device structure according to Embodiment 1 of the present invention;

[0022] Figure 3 This is a schematic diagram of the cleaning epitaxial wafer of Embodiment 3 of the present invention, showing the formation of a P-type base region by implanting aluminum ions on the N-epitaxial layer;

[0023] Figure 4 This is a schematic diagram of the formation of an N-ballast resistor region by injecting nitrogen ions using polycrystalline silicon as an implantation barrier layer in Embodiment 3 of the present invention;

[0024] Figure 5 This is a schematic diagram of the formation of a P+ ohmic contact region by implanting aluminum ions using polycrystalline silicon as an implantation barrier layer in Embodiment 3 of the present invention.

[0025] Figure 6 This is a schematic diagram of the formation of an N+ source region by injecting nitrogen ions using polycrystalline silicon as an injection barrier layer in Embodiment 3 of the present invention;

[0026] Figure 7 This is a schematic diagram of etching to form a gate trench in Embodiment 3 of the present invention;

[0027] Figure 8 This is a schematic diagram of the process of generating a gate oxide layer by dry oxygen oxidation in Embodiment 3 of the present invention, followed by annealing and depositing polycrystalline silicon in a nitrogen atmosphere, and patterning the polycrystalline silicon.

[0028] Figure 9 This is a schematic diagram of the deposition and etching of metal to form an electrode according to Embodiment 3 of the present invention.

[0029] 1 is the source metal, 2 is the first P+ ohmic contact region, 3 is the first P-type base region, 4 is the N- drift region, 5 is the N+ substrate region, 6 is the drain metal, 7 is the first N+ source region, 8 is the first N- ballast resistor region, 9 is the N-type slowly doped region, 21 is the second P+ ohmic contact region, 31 is the second P-type base region, 51 is the polysilicon gate, 62 is the gate dielectric, 71 is the second N+ source region, and 81 is the second N- ballast resistor region. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] Example 1

[0032] like Figure 2As shown, a single-particle irradiation-hardened silicon carbide MOSFET device includes a drain metal 6, an N+ substrate region 5 above the drain metal 6, an N-type gradually changing doped region 9 above the N+ substrate region 5, and an N-drift region 4 above the N-type gradually changing doped region 9. The doping concentration of the N-type gradually changing doped region 9 gradually decreases along the direction from the N+ substrate region 5 to the N-drift region 4. A gate groove is provided in the upper middle of the interior of the N-drift region 4. A polysilicon gate 51 and a gate dielectric 62 of the gate groove are provided in the gate groove. A first P-type base region 3 is located to the lower left of the gate groove, and a first N-ballast resistor region 8 is located to the upper left of the gate groove. A first P+ ohmic contact region A2 is located to the left of the first N-ballast resistor region 8, and a first N+ source region 7 is located to the upper left of the first N-ballast resistor region 8 and to the right of the first P+ ohmic contact region A2. The first P+ ohmic contact region B2 is located above the first N-ballast resistor region 8 and to the left of the gate recess; the second P-type base region 31 is located below the right of the gate recess, and the second N-ballast resistor region 81 is located above the right of the gate recess; the second P+ ohmic contact region A21 is located to the right of the second N-ballast resistor region 81; the second N+ source region 71 is located above the right of the second N-ballast resistor region 81 and to the left of the second P+ ohmic contact region A21; the second P+ ohmic contact region B21 is located above the left of the second N-ballast resistor region 81 and to the right of the gate recess; the source metal 1 is located above the first P+ ohmic contact region A2, the first P+ ohmic contact region B2, and the first N+ source region 7; the source metal 1 is located above the second P+ ohmic contact region A21, the second P+ ohmic contact region B21, and the second N+ source region 71.

[0033] Specifically, the gate dielectric 62 is SiO2.

[0034] Specifically, the first P+ ohmic contact region 2, the first N+ source region 7, the first N- ballast resistor region 8, the first P-type base region 3, the second P+ ohmic contact region 21, the second N+ source region 71, the second N- ballast resistor region 81, and the second P-type base region 31 were all formed by multiple ion implantations.

[0035] Specifically, the materials of the first P+ ohmic contact region 2, the first N+ source region 7, the first N- ballast resistor region 8, the first P-type base region 3, the second P+ ohmic contact region 21, the second N+ source region 71, the second N- ballast resistor region 81, the second P-type base region 31, the N- drift region 4, the N-type slowly changing doped region 9, and the N+ substrate region 5 are all silicon carbide.

[0036] This example enhances single-event irradiation resistance by introducing a prominent P-type body region and a lightly doped N-type resistive region. In the blocking state, when heavy ions are incident on the silicon carbide MOSFET device and generate a large number of electron-hole pairs along the incident path, the deposited holes are rapidly extracted from the prominent P-type body region, suppressing the turn-on of parasitic NPN transistors. Simultaneously, if parasitic NPN transistors are turned on, the lightly doped N-type resistive region effectively suppresses electron injection efficiency. The N-type gradually varying doped region near the N+ substrate region modulates the spatial electric field, suppressing the high electric field at the N+ substrate / N- drift region caused by the base region broadening effect, effectively reducing the occurrence of localized hot spots and single-event burn-out within the device. This invention effectively improves the single-event irradiation resistance of silicon carbide MOSFETs without degrading the static parameters of the trench-type silicon carbide MOSFET device.

[0037] Example 2

[0038] like Figures 3-9 As shown, this example provides a method for fabricating a single-particle irradiation-hardened silicon carbide MOSFET device, including the following steps:

[0039] Step 1: Clean the epitaxial wafer, implant aluminum ions onto the N-epitaxial layer to form a P-type base region; such as Figure 3 As shown;

[0040] Step 2: Nitrogen ions are implanted into polysilicon as an implantation barrier layer to form an N-ballast resistance region; such as... Figure 4 As shown;

[0041] Step 3: Using polycrystalline silicon as an implantation barrier layer, aluminum ions are implanted to form a P+ ohmic contact region; such as... Figure 5 As shown;

[0042] Step 4: Nitrogen ions are implanted using polycrystalline silicon as an implantation barrier layer to form an N+ source region; for example... Figure 6 As shown;

[0043] Step 5: Etching to form gate trenches; such as Figure 7 As shown;

[0044] Step 6: Dry oxygen oxidation is used to generate a gate oxide layer, followed by annealing and deposition of polysilicon under a nitrogen atmosphere to pattern the polysilicon; for example... Figure 8 As shown;

[0045] Step 7: Deposit and etch metal to form electrodes; such as Figure 9 As shown.

[0046] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A single-particle irradiation-hardened silicon carbide MOSFET device, characterized in that: This includes a drain metal (6), an N+ substrate region (5) above the drain metal (6), an N-type gradually changing doped region (9) above the N+ substrate region (5), and an N-drift region (4) above the N-type gradually changing doped region (9). The doping concentration of the N-type gradually changing doped region (9) gradually decreases along the direction from the N+ substrate region (5) to the N-drift region (4). A gate groove is provided in the upper middle of the interior of the N-drift region (4). A polysilicon gate (51) and a gate dielectric (62) of the gate groove are provided in the gate groove. The lower left of the gate groove is the first P-type base region (3), and the upper left of the gate groove is the first N-ballast resistor region (8). The left side of the first N-ballast resistor region (8) is the first P+ ohmic contact region A. The upper left of the first N-ballast resistor region (8) and the first P+ ohmic contact region A are located on the left side of the first P+ ohmic contact region A. The first N+ source region (7) is located to the right of the P+ ohmic contact region A. The first P+ ohmic contact region B is located to the upper right of the first N-ballast resistor region (8) and to the left of the gate groove. The second P-type base region (31) is located to the lower right of the gate groove. The second N-ballast resistor region (81) is located to the upper right of the gate groove. The second P+ ohmic contact region A is located to the right of the second N-ballast resistor region (81). The second N+ source region (71) is located to the upper right of the second N-ballast resistor region (81) and to the left of the second P+ ohmic contact region A. The second P+ ohmic contact region B is located to the upper left of the second N-ballast resistor region (81) and to the right of the gate groove. The source metal (1) is located above the first P+ ohmic contact region A, the first P+ ohmic contact region B and the first N+ source region (7).The second P+ ohmic contact region A, the second P+ ohmic contact region B and the second N+ source region (71) are above the source metal (1). The depth of the first P-type base region (3) and the second P-type base region (31) both exceed the bottom of the gate groove. The first P+ ohmic contact region A is in contact with the first N-ballast resistor region (8) and the first N+ source region (7). The second P+ ohmic contact region A is in contact with the second N-ballast resistor region (81) and the second N+ source region (71). The upper surface of the first P+ ohmic contact region A is flush with the upper surface of the first N+ source region (7) and the first P+ ohmic contact region B. The upper surface of the second P+ ohmic contact region A is flush with the second N+ source region (71) and the second P+ ohmic contact region B. The first P+ ohmic contact region B, the second P+ ohmic contact region B, the first N-ballast resistor region (8) and the second N-ballast resistor region (81) are all in contact with the gate groove. The lower surface of the P+ ohmic contact region A is flush with the lower surface of the first N-ballast resistor region (8), the lower surface of the second P+ ohmic contact region A is flush with the lower surface of the second N-ballast resistor region (81), the lower surfaces of the first P+ ohmic contact region A and the first N-ballast resistor region (8) are in contact with the upper surface of the first P-type base region (3), the lower surfaces of the second P+ ohmic contact region A and the second N-ballast resistor region (81) are in contact with the upper surface of the second P-type base region (31), the first N+ source region (7) is in contact with the first P+ ohmic contact region B, the second N+ source region (71) is in contact with the second P+ ohmic contact region B, the lower surfaces of the first N+ source region (7) and the first P+ ohmic contact region B are both in contact with the upper surface of the first N-ballast resistor region (8), and the lower surfaces of the second N+ source region (71) and the second P+ ohmic contact region B are both in contact with the upper surface of the second N-ballast resistor region (81).

2. The single-particle irradiation-hardened silicon carbide MOSFET device according to claim 1, characterized in that: The gate dielectric (62) is SiO2.

3. The single-particle irradiation-hardened silicon carbide MOSFET device according to claim 1, characterized in that: The first P+ ohmic contact region A, the first P+ ohmic contact region B, the first N+ source region (7), the first N- ballast resistance region (8), the first P-type base region (3), the second P+ ohmic contact region A, the second P+ ohmic contact region B, the second N+ source region (71), the second N- ballast resistance region (81), and the second P-type base region (31) were all formed by multiple ion implantations.

4. The single-particle irradiation-hardened silicon carbide MOSFET device according to claim 1, characterized in that: The materials of the first P+ ohmic contact region A, the first P+ ohmic contact region B, the first N+ source region (7), the first N- ballast resistor region (8), the first P-type base region (3), the second P+ ohmic contact region A, the second P+ ohmic contact region B, the second N+ source region (71), the second N- ballast resistor region (81), the second P-type base region (31), the N- drift region (4), the N-type slow-change doping region (9), and the N+ substrate region (5) are all silicon carbide.

5. The method for fabricating a single-particle irradiation-hardened silicon carbide MOSFET device according to any one of claims 1 to 4, characterized in that, Includes the following steps: Step 1: Clean the epitaxial wafer and implant aluminum ions onto the N-epitaxial layer to form a P-type base region; Step 2: Nitrogen ions are implanted into polysilicon as an implantation barrier layer to form an N-ballast resistance region; Step 3: Using polysilicon as an implantation barrier layer, aluminum ions are implanted to form a P+ ohmic contact region; Step 4: Nitrogen ions are injected using polysilicon as an implantation barrier layer to form an N+ source region; Step 5: Etching to form gate trenches; Step 6: Dry oxygen oxidation is used to generate a gate oxide layer, followed by annealing and deposition of polysilicon in a nitrogen atmosphere to pattern the polysilicon; Step 7: Deposit and etch metal to form electrodes.

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