An overcurrent protection circuit with time delay function

Abstract

The present application relates to the field of integrated circuit design, and particularly relates to an overcurrent protection circuit with delay function, which comprises a current detection module and a delay module, the input end of the current detection module inputs a to-be-detected current, the output end of the current detection module is connected with the input end of the delay module, and the output end of the delay module is connected with the enable end of the to-be-detected module; the delay module can convert the driving signal into a closing signal when the to-be-detected current rises above the overcurrent threshold and the duration is greater than the delay time, and can convert the closing signal into the driving signal after the to-be-detected current reduces below the overcurrent threshold. Through the delay module, the to-be-detected module is closed when the to-be-detected current overflows and the duration is greater than the delay time, compared with the traditional overcurrent protection circuit, the present application can filter out the interference of noise and current pulse, so as to avoid frequent start and stop of the to-be-detected module, and ensure that the load capacitor is fully discharged through delay reset.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more specifically to an overcurrent protection circuit with a delay function. Background Technology

[0002] Overcurrent detection and protection are an indispensable part of analog and mixed-signal circuit systems. In practical applications, the load current of many circuits has a certain range limit. When the load current exceeds its maximum limit, it will cause circuit malfunction, logic confusion, or even damage to the semiconductor devices in the circuit. Therefore, it is often necessary to monitor the load current of these circuits in real time, so as to shut down the circuit module in time when the load current of the circuit module under test exceeds the limit value to avoid circuit malfunction or device damage.

[0003] Traditional overcurrent protection modules have several problems: Sometimes, due to the closing and opening of switches in the circuit, or sudden changes in the load of the module under test, large current pulses may be generated in the load current. These current pulses have large peak values, but their duration is often very short. Traditional overcurrent protection modules will immediately trigger to shut down the circuit module when they detect the rising edge of a large current pulse, and then immediately turn the circuit module back on at the falling edge of the current pulse. However, such current pulses do not affect the circuit function, so there is no need to treat them as overcurrent and shut down the circuit module. Furthermore, due to the influence of various noise sources in the circuit, the load current may fluctuate around the overcurrent threshold, which will cause the current detection module to trigger frequently. If the overcurrent protection circuit is directly connected to the enable terminal of the module under test, it will lead to… The frequent switching between on and off of the module under test (DUT) affects the stability and reliability of the circuit. When the DUT is carrying a large load, if the load capacitor has no direct discharge path to ground, the charge on the load capacitor cannot be released quickly even if the module is turned off. In this case, if the overcurrent protection module detects the overcurrent and turns off the DUT, the voltage on the load capacitor at its output terminal will also take some time to decrease. Often, turning off the enable of the DUT can quickly reduce its load current to near zero. Therefore, after the DUT is turned off, the current detection module can detect that the load current has dropped below the overcurrent threshold almost instantly and turn the circuit back on. At this time, the load capacitor of the DUT has not had time to discharge, and the load current is often still in an overcurrent state after the DUT is turned on again. Summary of the Invention

[0004] This invention provides an overcurrent protection circuit with a delay function, which solves at least one technical problem existing in the prior art.

[0005] The technical solution provided by this invention is as follows: an overcurrent protection circuit with a delay function, comprising a current detection module and a delay module, wherein the input terminal of the current detection module is input to the current to be measured, the output terminal of the current detection module is connected to the input terminal of the delay module, and the output terminal of the delay module is connected to the enable terminal of the module to be measured; When the current to be measured is lower than the overcurrent threshold, the current detection module generates a drive signal; when the current to be measured is higher than or equal to the overcurrent threshold, the current detection module generates a shutdown signal. The delay module can convert the drive signal into a shutdown signal after the measured current rises above the overcurrent threshold and the duration is greater than the delay time, and can also convert the shutdown signal back into a drive signal after a delay when the measured current drops below the overcurrent threshold.

[0006] Furthermore, the delay module includes a filtering delay module and a reset delay module. The input terminal of the filtering delay module is connected to the output terminal of the current detection module, the output terminal of the filtering delay module is connected to the input terminal of the reset delay module, and the output terminal of the reset delay module is connected to the enable terminal of the module under test. The filtering delay module can generate a first intermediate signal based on the driving signal and a second intermediate signal based on the shutdown signal. When the drive signal is converted to the off signal, the filtering delay module delays the conversion of the first intermediate signal to the second intermediate signal. When the off signal is converted to the drive signal, the filtering delay module converts the second intermediate signal to the first intermediate signal in real time. The reset delay module can generate a drive signal based on the first intermediate signal and a shutdown signal based on the second intermediate signal; When the first intermediate signal is converted to the second intermediate signal, the reset delay module converts the drive signal to the off signal in real time. When the second intermediate signal is converted to the first intermediate signal, the reset delay module converts the off signal to the drive signal after a delay.

[0007] Furthermore, the filtering delay module includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a second PMOS transistor MP2, a first current source I1, a second current source I2, a first inverter INV1, a second inverter INV2, a third inverter INV3, and a first capacitor C1. The input terminal of the first inverter INV1 and the gate of the third NMOS transistor MN3 are both connected to the output terminal of the current detection module. The current input terminal of the first current source I1 is connected to the power supply, and the current output terminal of the first current source I1 is connected to the drain of the third NMOS transistor MN3, one end of the first capacitor C1, the input terminal of the second inverter INV2, and the gate of the fourth NMOS transistor MN4. The current input terminal of the second current source I2 is connected to the power supply, and the current output terminal of the second current source I2 is connected to the other end of the first capacitor C1, the drain of the fourth NMOS transistor MN4, and the drain of the second PMOS transistor MP2, respectively. The source of the third NMOS transistor MN3 and the source of the fourth NMOS transistor MN4 are both connected to signal ground. The output of the first inverter INV1 is connected to the gate of the second PMOS transistor MP2. The source of the second PMOS transistor MP2 is connected to the power supply. The output of the second inverter INV2 is connected to the input of the third inverter INV3. The output of the third inverter INV3 is connected to the input of the reset delay module.

[0008] Furthermore, the delay module includes a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a third PMOS transistor MP3, a third current source I3, a fourth current source I4, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, and a second capacitor C2. The gate of the fifth NMOS transistor MN5 and the input of the fourth inverter INV4 are both connected to the output of the filter delay module. The current input terminal of the third current source I3 is connected to the power supply, and the current output terminal of the third current source I3 is connected to the drain of the fifth NMOS transistor MN5, one end of the second capacitor C2, the input terminal of the fifth inverter INV5, and the gate of the sixth NMOS transistor MN6. The current input terminal of the fourth current source I4 is connected to the power supply, and the current output terminal of the fourth current source I4 is connected to the other end of the second capacitor C2, the drain of the sixth NMOS transistor MN6, and the drain of the third PMOS transistor MP3, respectively. The sources of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are both connected to signal ground. The output of the fourth inverter INV4 is connected to the gate of the third PMOS transistor MP3. The source of the third PMOS transistor MP3 is connected to the power supply. The output of the fifth inverter INV5 is connected to the input of the sixth inverter INV6. The output of the sixth inverter INV6 is connected to the enable terminal of the module under test.

[0009] Furthermore, the current detection module includes a first PMOS transistor MP1, a first NMOS transistor MN1, and a second NMOS transistor MN2; The source of the first NMOS transistor MN1 is connected to signal ground, and both the gate and drain of the first NMOS transistor MN1 are connected to the current to be measured. The gates of the second NMOS transistor MN2 and the first PMOS transistor MP1 are both connected to the gate of the first NMOS transistor MN1. The source of the second NMOS transistor MN2 is connected to signal ground, and both the drains of the second NMOS transistor MN2 and the drain of the first PMOS transistor MP1 are connected to the input terminal of the delay module. The source of the first PMOS transistor MP1 is connected to the power supply.

[0010] The beneficial effects of this invention are as follows: This invention, through a delay module, shuts down the module under test when the current under test is excessive and the duration exceeds the delay time. Compared to traditional overcurrent protection circuits, this invention can filter out noise and current pulse interference, thus avoiding frequent start-stop of the module under test, and the delayed reset ensures sufficient discharge of the load capacitor. Furthermore, the delay circuit used in this invention utilizes the Miller effect of an amplifier circuit to amplify the equivalent capacitance by a factor of (1+A), where A is the amplifier's amplification factor. Therefore, compared to other delay circuits that utilize capacitor charging and discharging, the capacitance value used in this invention can be significantly reduced to achieve the same delay time under the same charging and discharging current, thereby saving circuit area. Attached Figure Description

[0011] Figure 1 The structural diagram of the overcurrent protection circuit with delay function proposed in this invention.

[0012] Figure 2 The equivalent circuit diagram of the filter delay module and reset module when the input is high level proposed in this invention.

[0013] Figure 3 The equivalent circuit diagram of the filter delay module and reset module when the input is low level proposed in this invention. Detailed Implementation

[0014] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. The described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0015] In a specific embodiment of the present invention Figure 1 According to the present invention, an overcurrent protection circuit with a delay function is provided, such as... Figure 1As shown, the present invention includes a current detection module 10 and a delay module. The input terminal of the current detection module receives the current to be measured, the output terminal of the current detection module is connected to the input terminal of the delay module, and the output terminal of the delay module is connected to the enable terminal of the module to be measured.

[0016] When the current to be measured is lower than the overcurrent threshold, the current detection module generates a drive signal; when the current to be measured is higher than or equal to the overcurrent threshold, the current detection module generates a shutdown signal.

[0017] The delay module can switch the drive signal to a shutdown signal and shut down the module under test after the current under test rises above the overcurrent threshold for a duration greater than the delay time. Since pulse interference and other noise interference are short-lived, they can briefly raise the current under test above the overcurrent threshold. Therefore, the delay module will not switch the drive signal to a shutdown signal during the delay time. Only when the current under test is still greater than the overcurrent threshold after the delay time will the drive signal be switched to a shutdown signal.

[0018] Furthermore, the delay module can convert the shutdown signal into a drive signal after a delay when the measured current drops below the overcurrent threshold. After a certain delay, the load capacitance of the module under test can be fully discharged before the module under test is turned on.

[0019] It should be noted that the drive signal and the stop signal can be high level and low level, or they can be implemented in the form of other signals.

[0020] Specifically, the delay module includes a filter delay module 20 and a reset delay module 30. The input terminal of the filter delay module 20 is connected to the output terminal of the current detection module 10, the output terminal of the filter delay module 20 is connected to the input terminal of the reset delay module 30, and the output terminal of the reset delay module 30 is connected to the enable terminal of the module under test.

[0021] The filtering delay module 20 can generate a first intermediate signal based on the driving signal and a second intermediate signal based on the shutdown signal; When the drive signal is converted to the off signal, the filter delay module 20 delays and converts the first intermediate signal into the second intermediate signal. When the off signal is converted to the drive signal, the filter delay module 20 converts the second intermediate signal into the first intermediate signal in real time. In this circuit, the drive signal is high, the first intermediate signal is low, the shutdown signal is low, and the second intermediate signal is high. When the input of the filter delay module 20 changes from high to low, the output changes from low to high after a delay; when the input of the filter delay module 20 changes from low to high, the output changes from high to low in real time.

[0022] The reset delay module 30 can generate a drive signal based on the first intermediate signal and a shutdown signal based on the second intermediate signal; When the first intermediate signal is converted to the second intermediate signal, the reset delay module 30 converts the drive signal to the off signal in real time. When the second intermediate signal is converted to the first intermediate signal, the reset delay module 30 delays the conversion of the off signal to the drive signal.

[0023] In this configuration, the drive signal is high, the first intermediate signal is low, the shutdown signal is low, and the second intermediate signal is high. When the input of the reset delay module 30 changes from low to high, the output immediately changes from high to low; when the input of the reset delay module 30 changes from high to low, the output changes from low to high after a delay.

[0024] To better understand the overcurrent protection circuit with delay function provided by this invention, its working principle is explained below: In one embodiment of the present invention, the current detection module 10 includes a first PMOS transistor MP1, a first NMOS transistor MN1, and a second NMOS transistor MN2.

[0025] The source of the first NMOS transistor MN1 is connected to signal ground, and both the gate and drain of the first NMOS transistor MN1 are connected to the current to be measured. The gates of the second NMOS transistor MN2 and the first PMOS transistor MP1 are both connected to the gate of the first NMOS transistor MN1. The source of the second NMOS transistor MN2 is connected to signal ground, and both the drains of the second NMOS transistor MN2 and the drain of the first PMOS transistor MP1 are connected to the input terminal of the delay module. The source of the first PMOS transistor MP1 is connected to the power supply.

[0026] To achieve the function of converting whether the measured current is overcurrent into a high or low output level, the measured current is input through port I. T The current inflow detection module 10, with the second NMOS transistor MN2 and the first PMOS transistor MP1 connected in the same manner as a typical inverter, features the same dimensions for both the first NMOS transistor MN1 and the second NMOS transistor MN2. These transistors form a current mirror circuit. When the current I flowing through the first NMOS transistor MN1... T As the current increases, since the first NMOS transistor MN1 is configured as a diode, its gate voltage adaptively increases with the increase of current. Therefore, the gate voltages of the second NMOS transistor MN2 and the first PMOS transistor MP1 will also increase with the current being measured I. T If the measured current I increases, TIf the current is small and does not reach the set overcurrent threshold, the first PMOS transistor MP1 operates in the linear region, and the second NMOS transistor MN2 operates in the saturation region. The drain voltages of the first PMOS transistor MP1 and the second NMOS transistor MN2 output a high level. When the measured current IT increases to the set overcurrent threshold, the second NMOS transistor MN2 enters the linear region, and the first PMOS transistor MP1 operates in the saturation region. The drain voltages of the first PMOS transistor MP1 and the second NMOS transistor MN2 output a low level. Therefore, when the measured current is lower than the overcurrent threshold, the current detection module outputs a high level, and when the measured current is higher than or equal to the overcurrent threshold, the current detection module outputs a low level.

[0027] The required overcurrent threshold can be set by properly adjusting the first NMOS transistor MN1, the second NMOS transistor MN2, and the first PMOS transistor.

[0028] In one embodiment of the present invention, a filtering delay module 20 is provided to filter out overcurrent signals such as noise and current pulses detected by the current detection module that are below a preset delay time. The filtering delay module 20 includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a second PMOS transistor MP2, a first current source I1, a second current source I2, a first inverter INV1, a second inverter INV2, a third inverter INV3, and a first capacitor C1; The input terminal of the first inverter INV1 and the gate of the third NMOS transistor MN3 are both connected to the output terminal of the current detection module 10; The current input terminal of the first current source I1 is connected to the power supply, and the current output terminal of the first current source I1 is connected to the drain of the third NMOS transistor MN3, one end of the first capacitor C1, the input terminal of the second inverter INV2, and the gate of the fourth NMOS transistor MN4. The current input terminal of the second current source I2 is connected to the power supply, and the current output terminal of the second current source I2 is connected to the other end of the first capacitor C1, the drain of the fourth NMOS transistor MN4, and the drain of the second PMOS transistor MP2, respectively. The source of the third NMOS transistor MN3 and the source of the fourth NMOS transistor MN4 are both connected to signal ground. The output of the first inverter INV1 is connected to the gate of the second PMOS transistor MP2. The source of the second PMOS transistor MP2 is connected to the power supply. The output of the second inverter INV2 is connected to the input of the third inverter INV3. The output of the third inverter INV3 is connected to the input of the reset delay module 30.

[0029] If the measured current does not exceed the overcurrent threshold, the high-level output from the current detection module 10 passes through the first inverter INV1, causing the output of the first inverter INV1 to output a low-level signal, which turns on the second PMOS transistor MP2. This pulls up the other end of the first capacitor C1 and the drain voltage of the fourth NMOS transistor MN4 to the power supply voltage. Simultaneously, because the output of the current detection module 10 is high, the third NMOS transistor MN3 turns on, shorting one end of the first capacitor C1, the gate of the fourth NMOS transistor MN4, and the current output of the first current source to ground. This results in a low-level output from the second inverter INV2 and the third inverter INV3, which is then sent to the reset delay module 30. The equivalent circuit is as follows: Figure 2 As shown, since the two ends of the first capacitor C1 are equivalent to being connected to ground and power supply respectively, the original charge on the capacitor is released almost instantaneously. Therefore, when the input of the delay module 20 changes from low level to high level, the output changes from high level to low level without delay.

[0030] When the current under test exceeds the overcurrent threshold, the low-level output of the current detection module 10 passes through the first inverter INV1, causing the output of the first inverter INV1 to go high, turning off the second PMOS transistor MP2. Simultaneously, because the output of the current detection module 10 goes low, the third NMOS transistor MN3 turns off, and the first current source I1 charges capacitor C1, causing the voltage at one end of the first capacitor C1 to rise from 0. The equivalent circuit is as follows: Figure 3 As shown in diagram a. When the voltage at one end of the first capacitor C1 rises to the saturation bias voltage of the fourth NMOS transistor MN4, MN4 operates in the saturation region and forms a common-source amplifier with the second current source I2 as the current source load. At this time, the first capacitor C1 connected between the gate and drain of the fourth NMOS transistor MN4 becomes the Miller capacitance, which is equivalent to a capacitor with a size of 1 + A1 connected in parallel between the gate and source of the fourth NMOS transistor MN4. A1 is the amplification factor of the common-source amplifier formed by the fourth NMOS transistor MN4 and the second current source I2. The equivalent circuit is shown in diagram a. Figure 3 As shown in b, due to the increased capacitance, the charging speed of the Miller capacitor 1+A1C1 by the first current source I1 is slower. The second inverter INV2 will only output a low level when the voltage at one end of the first capacitor C1 rises to the flip threshold of the second inverter INV2, and then output a high level after passing through the third inverter INV3. Therefore, when the input voltage of the filter delay module 20 changes from high to low, the time required for its output to change from low to high is determined by the time required for the first current source I1 to charge the first capacitor C1, causing the voltage at one end of the first capacitor C1 and the input voltage of the second inverter INV2 to reach the flip threshold of the second comparator INV2. The required delay time can be obtained by reasonably adjusting the current magnitude of the first current source I1 and the capacitance value of the first capacitor C1.

[0031] In summary, the filter delay module 20 only delays the falling edge of the input, and has no effect on the rising edge. Therefore, when the aforementioned current detection module detects an overcurrent in the load but the duration is less than the preset delay time of the delay module 20, the current detection module 10 outputs a falling edge at the instant the overcurrent is detected. However, the output of the delay module 20 will not immediately output a high level, but will remain low for a period of time, which is the delay time of the filter delay module 20. If the current detection module 10 outputs a rising edge during this period, the charge on the first capacitor C1 will be released instantaneously, causing the output of the delay module 20 to remain low without changing. Therefore, if the overcurrent duration is less than the delay time of the filter delay module 20, the output of the filter delay module 20 will not change, thus filtering it out. Therefore, by reasonably setting the delay time of the delay module 20, unwanted shutdowns caused by current pulses and frequent start-stops caused by various noise sources in the circuit can be avoided.

[0032] The delay module used in this invention utilizes the Miller effect of the amplifier circuit to amplify the equivalent capacitance by a factor of 1+A, where A is the amplification factor of the amplifier. Therefore, compared with other delay circuits that utilize capacitor charging and discharging, the capacitance value used in this invention can be significantly reduced to achieve the same delay time under the same charging and discharging current, thereby saving circuit area.

[0033] In one embodiment of the present invention, in order to fully discharge the load capacitor, the module under test is turned on after a certain period of time following a load current below the overload threshold. The present invention provides a reset delay circuit.

[0034] The reset delay module 30 includes a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a third PMOS transistor MP3, a third current source I3, a fourth current source I4, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, and a second capacitor C2. The gate of the fifth NMOS transistor MN5 and the input of the fourth inverter INV4 are both connected to the output of the filter delay module 20.

[0035] The current input terminal of the third current source I3 is connected to the power supply, and the current output terminal of the third current source I3 is connected to the drain of the fifth NMOS transistor MN5, one end of the second capacitor C2, the input terminal of the fifth inverter INV5, and the gate of the sixth NMOS transistor MN6.

[0036] The current input terminal of the fourth current source I4 is connected to the power supply, and the current output terminal of the fourth current source I4 is connected to the other end of the second capacitor C2, the drain of the sixth NMOS transistor MN6, and the drain of the third PMOS transistor MP3.

[0037] The sources of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are both connected to signal ground. The output of the fourth inverter INV4 is connected to the gate of the third PMOS transistor MP3. The source of the third PMOS transistor MP3 is connected to the power supply. The output of the fifth inverter INV5 is connected to the input of the sixth inverter INV6. The output of the sixth inverter INV6 is connected to the enable terminal of the module under test.

[0038] from Figure 1 As can be seen from the above, the filter delay module and the reset delay module have the same structure. According to the above, when the current detection module 10 detects an overcurrent and the duration exceeds the delay time of the filter delay module 20, the filter delay module 20 outputs a rising edge to the input terminal of the reset delay module 30. Since the reset delay module 30 does not delay the input rising edge, its output terminal outputs a falling edge almost immediately, turning off the module under test.

[0039] When the module under test (DUT) is shut down, the measured current IT drops below the overcurrent threshold. The current detection module 10 outputs a rising edge to the filter delay module 20. Since the delay module 20 does not delay the rising edge, its output almost immediately outputs a falling edge to the reset delay module 30. After receiving the falling edge signal, the reset delay module 30 delays for a period of time before outputting a rising edge, generating a high level to turn on the DUT. The delay time of the reset delay module 30 can be adjusted by reasonably setting the current value of the third current source I3 and the capacitance value of the second capacitor C2. By setting an appropriate delay time for the delay module 30, it can be ensured that the load capacitor of the DUT is fully discharged.

[0040] In summary, this invention proposes an overcurrent protection circuit with a time delay function, which avoids the problems of traditional overcurrent protection circuits being shut down due to current pulses, frequently starting and stopping due to various noise sources in the circuit, and the load capacitor in the module under test not being able to fully discharge because the overcurrent protection triggers and then instantly turns on the module under test.

[0041] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An overcurrent protection circuit with a time delay function, characterized in that, It includes a current detection module (10) and a delay module. The input terminal of the current detection module is used to input the current to be measured, the output terminal of the current detection module is connected to the input terminal of the delay module, and the output terminal of the delay module is connected to the enable terminal of the module to be measured. When the current to be measured is lower than the overcurrent threshold, the current detection module generates a drive signal; when the current to be measured is higher than or equal to the overcurrent threshold, the current detection module generates a shutdown signal. The delay module can convert the drive signal into a shutdown signal after the measured current rises above the overcurrent threshold and the duration is greater than the delay time, and can also convert the shutdown signal into a drive signal after a delay when the measured current drops below the overcurrent threshold. The delay module includes a filter delay module (20) and a reset delay module (30). The input terminal of the filter delay module (20) is connected to the output terminal of the current detection module (10), the output terminal of the filter delay module (20) is connected to the input terminal of the reset delay module (30), and the output terminal of the reset delay module (30) is connected to the enable terminal of the module under test. The filtering delay module (20) can generate a first intermediate signal based on the driving signal and a second intermediate signal based on the shutdown signal; When the drive signal is converted to the off signal, the filter delay module (20) delays and converts the first intermediate signal into the second intermediate signal. When the off signal is converted to the drive signal, the filter delay module (20) converts the second intermediate signal into the first intermediate signal in real time. The reset delay module (30) can generate a drive signal based on the first intermediate signal and a shutdown signal based on the second intermediate signal; When the first intermediate signal is converted to the second intermediate signal, the reset delay module (30) converts the drive signal to the off signal in real time. When the second intermediate signal is converted to the first intermediate signal, the reset delay module (30) delays and converts the off signal to the drive signal.

2. The overcurrent protection circuit with delay function as described in claim 1, characterized in that, The filtering delay module (20) includes a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), a second PMOS transistor (MP2), a first current source (I1), a second current source (I2), a first inverter (INV1), a second inverter (INV2), a third inverter (INV3), and a first capacitor (C1). The input terminal of the first inverter (INV1) and the gate of the third NMOS transistor (MN3) are both connected to the output terminal of the current detection module (10); The current input terminal of the first current source (I1) is connected to the power supply, and the current output terminal of the first current source (I1) is connected to the drain of the third NMOS transistor (MN3), one end of the first capacitor (C1), the input terminal of the second inverter (INV2), and the gate of the fourth NMOS transistor (MN4). The current input terminal of the second current source (I2) is connected to the power supply, and the current output terminal of the second current source (I2) is connected to the other end of the first capacitor (C1), the drain of the fourth NMOS transistor (MN4), and the drain of the second PMOS transistor (MP2). The source of the third NMOS transistor (MN3) and the source of the fourth NMOS transistor (MN4) are both connected to signal ground. The output of the first inverter (INV1) is connected to the gate of the second PMOS transistor (MP2). The source of the second PMOS transistor (MP2) is connected to the power supply. The output of the second inverter (INV2) is connected to the input of the third inverter (INV3). The output of the third inverter (INV3) is connected to the input of the reset delay module (30).

3. The overcurrent protection circuit with delay function as described in claim 1, characterized in that, The reset delay module (30) includes a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a third PMOS transistor (MP3), a third current source (I3), a fourth current source (I4), a fourth inverter (INV4), a fifth inverter (INV5), a sixth inverter (INV6), and a second capacitor (C2). The gate of the fifth NMOS transistor (MN5) and the input of the fourth inverter (INV4) are both connected to the output of the filter delay module (20); The current input terminal of the third current source (I3) is connected to the power supply, and the current output terminal of the third current source (I3) is connected to the drain of the fifth NMOS transistor (MN5), one end of the second capacitor (C2), the input terminal of the fifth inverter (INV5), and the gate of the sixth NMOS transistor (MN6). The current input terminal of the fourth current source (I4) is connected to the power supply, and the current output terminal of the fourth current source (I4) is connected to the other end of the second capacitor (C2), the drain of the sixth NMOS transistor (MN6), and the drain of the third PMOS transistor (MP3). The sources of the fifth NMOS transistor (MN5) and the sixth NMOS transistor (MN6) are both connected to signal ground. The output of the fourth inverter (INV4) is connected to the gate of the third PMOS transistor (MP3). The source of the third PMOS transistor (MP3) is connected to the power supply. The output of the fifth inverter (INV5) is connected to the input of the sixth inverter (INV6). The output of the sixth inverter (INV6) is connected to the enable terminal of the module under test.

4. The overcurrent protection circuit with delay function as described in claim 1, characterized in that, The current detection module (10) includes a first PMOS transistor (MP1), a first NMOS transistor (MN1), and a second NMOS transistor (MN2). The source of the first NMOS transistor (MN1) is connected to signal ground, and the gate and drain of the first NMOS transistor (MN1) are both connected to the current to be measured. The gates of the second NMOS transistor (MN2) and the first PMOS transistor (MP1) are both connected to the gate of the first NMOS transistor (MN1). The source of the second NMOS transistor (MN2) is connected to signal ground, and the drains of the second NMOS transistor (MN2) and the first PMOS transistor (MP1) are both connected to the input terminal of the delay module. The source of the first PMOS transistor (MP1) is connected to the power supply.

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