Domain controller and vehicle

Abstract

The application discloses a domain controller and a car, and relates to the technical field of cars, which comprises a main control chip, a high-side drive chip and a sleep power supply circuit, wherein the sleep power supply circuit comprises a first PMOS, a first resistor and a shutdown circuit. When the main control chip receives a wake-up signal, that is, the domain controller is in a wake-up state, the main control chip controls the high-side drive chip to supply power to a normal power module, and sends a shutdown signal to the sleep power supply circuit to control the sleep power supply circuit to stop supplying power to the normal power module. When the main control chip receives a sleep signal, that is, the domain controller is in a sleep state, the main control chip stops outputting the shutdown signal to the sleep power supply circuit, so that the sleep power supply circuit supplies power to the normal power module, and the sleep power supply circuit utilizes the characteristic that the first PMOS is connected to the ground and turned on, so that the main control chip does not need to generate an opening signal and maintain the first PMOS to be turned on and not consume current when the domain controller is in the sleep state, and the power consumption of a secondary power distribution circuit for supplying power to the normal power module when the domain controller is in the sleep state is reduced.

Description

Technical Field

[0001] This invention relates to the field of automotive technology, and in particular to a domain controller and an automobile. Background Technology

[0002] A domain controller is a system that divides a vehicle into different electronic control units (ECUs) based on their geographical regions. These ECUs are then centrally controlled by the domain controller, which also provides power to modules that cannot be centrally controlled. Please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic diagram of the structure of a domain controller commonly used in the prior art. A domain controller typically includes a primary power supply circuit, power rails, a board-level power supply module, a main control chip, and a secondary power distribution circuit. The primary power supply circuit integrates the output voltage of the battery and battery pack and supplies it to the board-level power supply module and the secondary power distribution circuit through the power rails. The secondary power distribution circuit is used to supply power to the constant power module (which needs to supply power regardless of whether the domain controller is in sleep or wake-up state) and the power-down module (which needs to supply power only when the domain controller is in wake-up state).

[0003] The secondary power distribution circuit includes high-side driver chips that are connected one-to-one with the constant-power modules and the power-down modules. Since the constant-power modules require power from the secondary power distribution circuit regardless of whether the domain controller is in sleep or wake-up mode, the high-side driver chips connected to the constant-power modules need to be activated when the domain controller is in sleep mode. Activating the high-side driver chips requires using the boost circuit inside the chip to drive the NMOS transistors, resulting in a relatively large current consumption. Furthermore, the current consumption increases with the number of constant-power modules. Therefore, it is necessary to reduce the power consumption of the secondary power distribution circuit when supplying power to the constant-power modules in the domain controller's sleep mode. Summary of the Invention

[0004] The purpose of this invention is to provide a domain controller and an automobile that can reduce the power consumption of the secondary power distribution circuit when the domain controller is in sleep mode and is supplying power to the constant power module.

[0005] To solve the above technical problems, the present invention provides a domain controller, including a main control chip, a high-side driver chip, and a sleep power supply circuit, wherein the sleep power supply circuit includes a first PMOS, a first resistor, and a shutdown circuit;

[0006] The voltage input terminal of the high-side driver chip and the voltage input terminal of the sleep power supply circuit are both connected to the voltage output terminal of the first-level power supply circuit, and the voltage output terminal of the high-side driver chip and the voltage output terminal of the sleep power supply circuit are both connected to the power supply terminal of the constant power module.

[0007] The main control chip is used to enable the high-side driver chip to supply power to the constant power module when a wake-up signal is received, and at the same time output a shutdown signal to the sleep power supply circuit so that the sleep power supply circuit stops supplying power to the constant power module; and to control the high-side driver chip to stop supplying power to the constant power module when a sleep signal is received, and at the same time stop outputting the shutdown signal to the sleep power supply circuit so that the sleep power supply circuit supplies power to the constant power module.

[0008] The source of the first PMOS is the voltage input terminal of the sleep power supply circuit, the drain is the voltage output terminal of the sleep power supply circuit, the gate is connected to the first terminal of the first resistor and the output terminal of the shutdown circuit, the second terminal of the first resistor is grounded, and the shutdown circuit is used to turn off the first PMOS by pulling up the voltage of the gate of the first PMOS when the shutdown signal is received.

[0009] Preferably, the shutdown circuit includes a first NMOS and a second PMOS;

[0010] The gate of the first NMOS is used to receive the shutdown signal, the source of the first NMOS is grounded, the drain of the first NMOS is connected to the gate of the second PMOS, the drain of the second PMOS is the output terminal of the shutdown circuit, and the source of the second PMOS is connected to the source of the first PMOS.

[0011] Preferably, the shut-off circuit further includes a second resistor, a third resistor, a tenth resistor, a first Zener diode, and a second Zener diode;

[0012] The third resistor is connected between the gate and the source of the first NMOS, the second resistor is connected between the gate and the source of the second PMOS, the positive terminal of the second Zener diode is connected to the gate of the second PMOS, the negative terminal of the second Zener diode is connected to the source of the second PMOS, and the tenth resistor is connected between the source of the second PMOS and the voltage input terminal of the sleep power supply circuit.

[0013] The common terminal of the gate of the first PMOS and the first resistor is connected to the positive terminal of the first Zener diode, and the negative terminal of the first Zener diode is connected to the source of the first PMOS.

[0014] Preferably, the main control chip is further configured to acquire the current on the current feedback pin of the high-side driver chip after receiving the wake-up signal, and start timing when it is determined that the constant power module is overcurrent based on the current on the current feedback pin, and control the high-side driver chip to stop supplying power to the constant power module when the timing time is greater than a preset duration.

[0015] Preferably, the high-side driver chip is further configured to stop supplying power to the constant-power module when the current on its own current feedback pin determines that the constant-power module is short-circuited.

[0016] Preferably, it also includes a current detection circuit and a latching circuit;

[0017] The current detection circuit is used to output an overcurrent wake-up signal to the main control chip and an overcurrent and short-circuit trigger signal to the latch circuit when the current flowing through the circuit connecting the sleep power supply circuit and the constant power module is greater than a preset overcurrent threshold; and to output a short-circuit wake-up signal to the main control chip and the overcurrent and short-circuit trigger signal to the latch circuit when the current flowing through the circuit connecting the sleep power supply circuit and the constant power module is greater than a preset short-circuit threshold.

[0018] The latching circuit is used to enter a self-locking state when it receives the overcurrent and short-circuit trigger signals in order to output the shutdown signal to the sleep power supply circuit and enable the high-side driver chip to supply power to the constant power module.

[0019] The main control chip is also used to enable the high-side driver chip to supply power to the constant power module when receiving the overcurrent wake-up signal, and output a latch clear signal to the latch circuit to make the latch circuit exit the self-locking state; and to output the latch clear signal to the latch circuit when receiving the short-circuit wake-up signal to make the latch circuit exit the self-locking state.

[0020] Preferably, the current detection circuit includes a first sampling resistor, a second sampling resistor, a third diode, a fourth diode, a first PNP transistor, and a second PNP transistor, wherein the resistance value of the first sampling resistor is greater than the resistance value of the second sampling resistor.

[0021] The first end of the first sampling resistor is connected to the output terminal of the sleep power supply circuit, the second end of the first sampling resistor is connected to the first end of the second sampling resistor, and the second end of the second sampling resistor is connected to the power supply terminal of the constant power module.

[0022] The base of the first PNP transistor is connected to the second end of the first sampling resistor, the emitter is connected to the first end of the first sampling resistor, and the collector is the first output terminal of the current detection circuit used to output the overcurrent wake-up signal.

[0023] The base of the second PNP transistor is connected to the second end of the second sampling resistor, the emitter is connected to the first end of the second sampling resistor, and the collector is the second output terminal of the current detection circuit used to output the short-circuit wake-up signal.

[0024] The anode of the third diode is connected to the first output terminal of the current detection circuit, the anode of the fourth diode is connected to the second output terminal of the current detection circuit, and the cathode of the third diode is connected to the cathode of the fourth diode to form the third output terminal of the current detection circuit for outputting the overcurrent and short-circuit trigger signals.

[0025] Preferably, the current detection circuit further includes a first capacitor, a second capacitor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor;

[0026] The fourth resistor and the fifth resistor are connected in series. One end of the series circuit is connected to the second end of the first sampling resistor, and the other end of the series circuit is connected to the base of the first PNP transistor. The first capacitor is connected between the first end of the first sampling resistor and the common terminal of the fourth and fifth resistors. One end of the sixth resistor is connected to the collector of the first PNP transistor, and the other end of the sixth resistor is the first output terminal of the current detection circuit used to output the overcurrent wake-up signal.

[0027] The seventh resistor and the eighth resistor are connected in series. One end of the series circuit is connected to the second end of the second sampling resistor, and the other end of the series circuit is connected to the base of the second PNP transistor. The first end of the second capacitor is connected to the first end of the second sampling resistor, and the second end of the second capacitor is connected to the common terminal of the seventh and eighth resistors. One end of the ninth resistor is connected to the collector of the second PNP transistor, and the other end of the ninth resistor is the second output terminal of the current detection circuit used to output the short-circuit wake-up signal.

[0028] Preferably, the latching circuit includes a Schmitt trigger, an NPN transistor, a fifth diode, a first bias resistor, and a second bias resistor;

[0029] The input terminal of the Schmitt trigger is the input terminal of the latch circuit, and the output terminal of the Schmitt trigger is the output terminal of the latch circuit. The output terminal of the Schmitt trigger is connected to the anode of the fifth diode, and the input terminal of the Schmitt trigger is connected to the cathode of the fifth diode. The Schmitt trigger is used to output an overcurrent and short-circuit latch signal when it receives the overcurrent and short-circuit trigger signal at its own input terminal. The overcurrent and short-circuit latch signal is used to control the sleep power supply circuit to stop supplying power to the constant power module and to control the high-side driver chip to supply power to the constant power module.

[0030] The collector of the NPN transistor is connected to the input terminal of the Schmitt trigger. The first terminal of the first bias resistor is connected to the base of the NPN transistor and the second terminal of the second bias resistor. The second terminal of the second bias resistor and the emitter of the NPN transistor are both grounded. The second terminal of the first bias resistor is used to receive the latch clear signal so that the Schmitt trigger stops outputting the overcurrent and short-circuit latch signals.

[0031] Preferably, the main control chip is further configured to detect whether the constant power module is malfunctioning when it receives the overcurrent wake-up signal or the short-circuit wake-up signal, and when it is determined that the constant power module is not malfunctioning, output a latch clear signal to the latch circuit to control the latch circuit to exit the self-locking state.

[0032] To address the aforementioned technical problems, this application also provides an automobile, including the aforementioned domain controller.

[0033] In summary, this invention discloses a domain controller and an automobile, including a main control chip, a high-side driver chip, and a sleep power supply circuit. The sleep power supply circuit includes a first PMOS, a first resistor, and a shutdown circuit. When the main control chip receives a wake-up signal (i.e., the domain controller is in a wake-up state), it controls the high-side driver chip to supply power to the constant-power module and sends a shutdown signal to the sleep power supply circuit to control the sleep power supply circuit to stop supplying power to the constant-power module. When the main control chip receives a sleep signal (i.e., the domain controller is in a sleep state), it stops outputting a shutdown signal to the sleep power supply circuit, allowing the sleep power supply circuit to supply power to the constant-power module. Furthermore, the sleep power supply circuit utilizes the grounded and conductive characteristic of the first PMOS, so that the main control chip does not need to generate an enable signal when the domain controller is in a sleep state and maintains the first PMOS conduction without consuming current, thus reducing the power consumption of the secondary power distribution circuit when supplying power to the constant-power module while the domain controller is in a sleep state. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the structure of a domain controller commonly used in existing technologies;

[0036] Figure 2 A schematic diagram of the structure of a domain controller provided by the present invention;

[0037] Figure 3A schematic diagram of the circuit structure of a current detection circuit in a domain controller provided by the present invention;

[0038] Figure 4 A schematic diagram of the circuit structure of a latch circuit in a domain controller provided by the present invention.

[0039] Figure 5 This is a schematic diagram of the working mode of a domain controller provided by the present invention. Detailed Implementation

[0040] The core of this invention is to provide a domain controller and an automobile that can reduce the power consumption of the secondary power distribution circuit when the domain controller is in sleep mode and supplies power to the constant power module.

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] Please refer to Figure 2 , Figure 2 This invention provides a schematic diagram of the structure of a domain controller, which includes a main control chip 1, a high-side driver chip 2, and a sleep power supply circuit 3. The sleep power supply circuit 3 includes a first PMOS P1, a first resistor R1, and a shutdown circuit.

[0043] The voltage input terminal of the high-side driver chip 2 and the voltage input terminal of the sleep power supply circuit 3 are both connected to the voltage output terminal of the first-level power supply circuit, and the voltage output terminal of the high-side driver chip 2 and the voltage output terminal of the sleep power supply circuit 3 are both connected to the power supply terminal of the constant power module.

[0044] The main control chip 1 is used to enable the high-side driver chip 2 to supply power to the constant power module when a wake-up signal is received, and at the same time output a shutdown signal to the sleep power supply circuit 3 so that the sleep power supply circuit 3 stops supplying power to the constant power module; when a sleep signal is received, it controls the high-side driver chip 2 to stop supplying power to the constant power module, and at the same time stops outputting a shutdown signal to the sleep power supply circuit 3 so that the sleep power supply circuit 3 supplies power to the constant power module.

[0045] The source of the first PMOS P1 is the voltage input terminal of the sleep power supply circuit 3, the drain is the voltage output terminal of the sleep power supply circuit 3, the gate is connected to the first terminal of the first resistor R1 and the output terminal of the shutdown circuit, the second terminal of the first resistor R1 is grounded, and the shutdown circuit is used to turn off the first PMOS P1 by pulling up the voltage of the gate of the first PMOS P1 when a shutdown signal is received.

[0046] In the prior art, when the domain controller is in sleep mode, it is necessary to supply power to the constant power module through the high-side driver chip in the secondary power distribution circuit. Turning on the high-side driver chip itself will consume a considerable current. This current is mainly caused by the boost circuit inside the high-side driver chip (the boost circuit is used to turn on the NMOS inside the high-side driver chip, so that the high-side driver chip can conduct and output voltage).

[0047] To address the aforementioned issues, this application provides a domain controller. The domain controller includes a sleep power supply circuit 3, which supplies power to the constant power module when the main control chip receives a sleep signal, i.e., when the domain controller is in sleep mode. On the one hand, the domain controller provided in this application does not require the main control chip 1 to activate the sleep power supply circuit 3 when the domain controller is in sleep mode. On the other hand, the sleep power supply circuit 3 in the domain controller of this application does not include NMOS, so there is no need to use a boost circuit to turn on the sleep power supply circuit 3 and output voltage.

[0048] Specifically, the module supplying power to the constant power module in this application includes a high-side driver chip 2 and a sleep power supply circuit 3. The voltage input terminals of both the high-side driver chip 2 and the sleep power supply circuit 3 are connected to the voltage output terminal of the primary power supply circuit to receive the voltage provided by the primary power supply circuit after integrating the battery and battery pack. The voltage output terminals of the high-side driver chip 2 and the sleep power supply circuit 3 are first connected together and then connected to the power supply terminal of the constant power module so that either the high-side driver chip 2 or the sleep power supply circuit 3 can supply power to the constant power module. Furthermore, the enable terminals of the high-side driver chip 2 and the sleep power supply circuit 3 can be connected to the enable output terminal of the main control chip 1 so that the main control chip 1 can control the high-side driver chip 2 and the sleep power supply circuit 3.

[0049] When the main control chip 1 receives a wake-up signal, it outputs a shutdown signal to the sleep power supply circuit 3. That is, when the domain controller enters the wake-up state, the sleep power supply circuit 3 stops supplying power to the constant-power module. The sleep power supply circuit 3 remains on, meaning it always supplies power to the constant-power module, unless a shutdown signal is received. Therefore, the switching logic of the sleep power supply circuit 3 in this application, which supplies power to the constant-power module when the domain controller is in sleep mode, differs from the switching logic of commonly used power supply circuits in the prior art. The sleep power supply circuit 3 in this application is normally open and only shuts down when a shutdown signal is received; therefore, there is no need to provide the startup signal required to start the sleep power supply circuit 3. Furthermore, designing the sleep power supply circuit 3 as a shut-off circuit also ensures that the sleep power supply circuit 3 can be disconnected when the constant-power module is short-circuited, thereby ensuring the safety of the domain controller. Please refer to [further details omitted]. Figure 5 , Figure 5 This is a schematic diagram of the operating mode of a domain controller provided by the present invention. Figure 5The HSD in the code is a high-side driver chip. In order to ensure low power consumption when the domain controller is in sleep mode, the main control chip 1 will also control the high-side driver chip 2 to stop supplying power to the constant-power module when it receives a sleep signal. That is, the high-side driver chip 2, which consumes more current, will also enter sleep mode.

[0050] Furthermore, the sleep power supply circuit 3 in this application includes a first PMOS P1, a first resistor R1, and a shutdown circuit. The switching characteristics of a PMOS differ from current-type control devices such as NPN or PNP types; a PMOS is a voltage-type control device. Turning on a PMOS requires applying voltage to its gate and source, and it consumes no current after being turned on. In the sleep power supply circuit 3 provided in this application, the gate of the first PMOS P1 is directly grounded through the first resistor R1. The current consumed when the first PMOS P1 is turned on is 0mA (negligible at the μA level). Therefore, the sleep power supply circuit 3 in this application does not require a control signal to turn on and does not consume current when turned on, solving the problem of current consumption in the power supply itself. Simultaneously, the shutdown circuit rapidly pulls up the voltage of the gate of the first PMOS P1 upon receiving a shutdown signal, achieving rapid shutdown of the first PMOS P1. This enables the main control chip 1 to output a shutdown signal to the sleep power supply circuit 3, causing the sleep power supply circuit 3 to stop supplying power to the constant power module.

[0051] It should also be noted that when the domain controller is in the wake-up state, the main control chip 1 can control the high-side driver chip 2 to work normally and provide the current required for the constant power module. Furthermore, when the domain controller also needs to supply power to the power-down module, it can control the high-side driver chip 2 connected to each power-down module to work normally in order to provide the current required for the power-down module to work.

[0052] In summary, this application provides a domain controller, including a main control chip 1, a high-side driver chip 2, and a sleep power supply circuit 3. The sleep power supply circuit 3 includes a first PMOS P1, a first resistor R1, and a shutdown circuit. When the domain controller enters a wake-up state, the main control chip 1 sends a shutdown signal to the sleep power supply circuit 3 to turn it off. The sleep power supply circuit 3 remains on unless it receives a shutdown signal. That is, the sleep power supply circuit 3 does not require an on signal, only a shutdown signal, so that no on signal needs to be generated when the domain controller is in sleep mode, and the first PMOS P1 does not consume current when it is conducting. Furthermore, the sleep power supply circuit 3 does not contain an NMOS, therefore, a boost circuit is not needed to drive the sleep power supply circuit 3, thereby reducing the power consumption of the secondary power distribution circuit when supplying power to the constant-power module in the sleep state of the domain controller.

[0053] Based on the above embodiments:

[0054] In a preferred embodiment, the shutdown circuit includes a first NMOS N1 and a second PMOS P2;

[0055] The gate of the first NMOS N1 is used to receive the turn-off signal. The source of the first NMOS N1 is grounded. The drain of the first NMOS N1 is connected to the gate of the second PMOS P2. The drain of the second PMOS P2 is the output terminal of the turn-off circuit. The source of the second PMOS P2 is connected to the source of the first PMOS P1.

[0056] In this embodiment, the shutdown circuit specifically includes a first NMOS N1 and a second PMOS P2. The gate of the first NMOS N1 is used to receive a shutdown signal. Through the first NMOS N1 and the second PMOS P2, after the first NMOS N1 receives the shutdown signal, it quickly shorts the gate and source of the first PMOS P1, thereby disconnecting the first PMOS P1. This achieves the purpose of the main control chip 1 outputting a shutdown signal to the sleep power supply circuit 3, so that the sleep power supply circuit 3 stops supplying power to the constant power module. Moreover, the circuit structure is simple and the cost is low.

[0057] In a preferred embodiment, the shutdown circuit further includes a second resistor R2, a third resistor R3, a tenth resistor R10, a first Zener diode D1, and a second Zener diode D2;

[0058] The third resistor R3 is connected between the gate and the source of the first NMOS N1, the second resistor R2 is connected between the gate and the source of the second PMOS P2, the positive terminal of the second Zener diode D2 is connected to the gate of the second PMOS P2, the negative terminal of the second Zener diode D2 is connected to the source of the second PMOS P2, and the tenth resistor R10 is connected between the source of the second PMOS P2 and the voltage input terminal of the sleep power supply circuit 3.

[0059] The common terminal of the first PMOS P1, which is connected to the gate of the first PMOS P1 and the first resistor R1, is connected to the positive terminal of the first Zener diode D1, and the negative terminal of the first Zener diode D1 is connected to the source of the first PMOS P1.

[0060] Considering that the charge stored when the MOSFET gate is turned on needs to be discharged when the MOSFET in the shutdown circuit is turned off, thereby accelerating the MOSFET shutdown speed and avoiding the problem of channel burnout due to slow MOSFET shutdown, a second resistor R2 is provided in this embodiment for discharging charge, a third resistor R3 is provided to prevent the first NMOS from being falsely triggered by noise, and a tenth resistor R10 is provided to suppress the current surge generated when the gate and source of the first PMOS P1 are shorted through the second PMOS P2. In addition, a first Zener diode D1 and a second Zener diode D2 are provided (the Zener diode model can be a ±15V to ±18V clamping model, such as a ±18V Zener diode). The first Zener diode D1 and the first resistor R1 form a clamping circuit, so that when the source voltage of the first PMOS P1 is greater than 18V, the first Zener diode D1 clamps the voltage between the gate and source of the first PMOS P1 to be around 18V, which is less than the maximum gate-source withstand voltage of 20V of the PMOS, thus protecting the gate and source of the first PMOS P1 from overvoltage breakdown. In summary, this embodiment further optimizes the shutdown circuit to ensure its stability, thereby ensuring the stability of the entire domain controller.

[0061] In a preferred embodiment, the main control chip 1 is also used to acquire the current on the current feedback pin of the high-side drive chip 2 when a wake-up signal is received, and to start timing when the current on the current feedback pin determines that the constant power module is overcurrent, and to control the high-side drive chip 2 to stop supplying power to the constant power module when the timing time is longer than a preset duration.

[0062] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the operating mode of a domain controller provided by the present invention. Figure 5 The HSD in this example is a high-side driver chip. Considering that when the domain controller is in a wake-up state and supplies power to the constant-power module through the high-side driver chip 2, the constant-power module may experience overcurrent or short-circuit abnormalities. Therefore, in this embodiment, the main control chip 1 is also used to detect whether the constant-power module is experiencing overcurrent, and when it is determined that the constant-power module is experiencing overcurrent, it controls the high-side driver chip 2 to stop supplying power to the constant-power module, so as to avoid the wiring harness connected to the constant-power module being affected by excessive current and operating at high temperature for a long time.

[0063] It should also be noted that overcurrent situations may occur in the constant power module, including when switching from sleep mode to startup mode. The main control chip detects whether the constant power module is experiencing overcurrent by acquiring the current on the current feedback pin of the high-side driver chip, and then determining whether the current on the current feedback pin is greater than a preset overcurrent threshold and less than a preset short-circuit threshold. If so, it is determined that the constant power module is experiencing overcurrent.

[0064] In a preferred embodiment, the high-side driver chip 2 is also used to stop supplying power to the constant-current module when the current on its own current feedback pin determines that the constant-current module is short-circuited.

[0065] In this embodiment, the high-side driver chip 2 has a built-in short-circuit instantaneous shutdown protection mechanism. When the current of the constant power module is short-circuited, it can ignore the control signal of the main control chip 1 and immediately stop supplying power to the constant power module, thereby further ensuring the safety of the high-side driver chip 2 and the entire domain controller.

[0066] In a preferred embodiment, it also includes a current detection circuit 4 and a latching circuit 5;

[0067] The current detection circuit 4 is used to output an overcurrent wake-up signal to the main control chip and an overcurrent and short-circuit trigger signal to the latch circuit 5 when the current flowing through the circuit connecting the sleep power supply circuit and the constant power module is greater than the preset overcurrent threshold; and to output a short-circuit wake-up signal to the main control chip and an overcurrent and short-circuit trigger signal to the latch circuit 5 when the current flowing through the circuit connecting the sleep power supply circuit and the constant power module is greater than the preset short-circuit threshold.

[0068] The latch circuit 5 is used to enter a self-locking state when it receives overcurrent and short-circuit trigger signals to output a shutdown signal to the sleep power supply circuit and enable the high-side driver chip to supply power to the constant power module.

[0069] The main control chip is also used to enable the high-side driver chip to supply power to the constant power module when it receives an overcurrent wake-up signal, and to output a latch clear signal to the latch circuit 5 so that the latch circuit 5 exits the self-locking state; and to output a latch clear signal to the latch circuit 5 when it receives a short-circuit wake-up signal so that the latch circuit 5 exits the self-locking state.

[0070] In practical applications, it's possible for a constant power module to suddenly start and operate while the domain controller is in sleep mode (referred to as abnormal operation), leading to a power drain in the vehicle. Existing technologies often involve the main control chip 1 periodically waking up to detect the current of each constant power module, thereby determining if abnormal operation has occurred. While this method can detect abnormal operation, it requires the main control chip 1 to constantly wake up from sleep mode, resulting in significant power consumption.

[0071] When the domain controller is in sleep mode, the main control chip 1 cannot actively detect whether the constant power module has experienced overcurrent or short circuit abnormalities. Therefore, it is necessary to implement overcurrent and short circuit detection of the constant power module through hardware. In the prior art, the voltage across the sampling resistor is detected, amplified by an operational amplifier, and then input to a comparator with a preset threshold for judgment. However, both the operational amplifier and the comparator consume a large amount of current. The current detection circuit provided in this embodiment only operates when the current exceeds a preset overcurrent threshold or a preset short circuit threshold, and does not consume current under normal circumstances.

[0072] This embodiment replaces the detection method of the main control chip 1 in the prior art with a current detection circuit. When the constant power module starts to work abnormally (the operating current of the constant power module is in the tens of milliamps after abnormal wake-up, and the current is only in the few milliamps in sleep state, so the current detection circuit will consider the current at the power supply terminal of the constant power module to be an overcurrent situation when the constant power module works abnormally), the first output terminal of the current detection circuit will output an overcurrent trigger signal. After receiving the overcurrent trigger signal, the main control chip 1 enters the wake-up state to passively obtain the abnormal working status of the constant power module. The main control chip 1 does not consume power while waiting to be woken up, thus realizing the low power consumption of the domain controller.

[0073] Specifically, this application uses a current detection circuit 4 to detect the current in the circuit connecting the sleep power supply circuit and the constant power module. When the current exceeds a preset overcurrent threshold, it determines that an overcurrent has occurred in the constant power module. Therefore, it outputs an overcurrent wake-up signal to the main control chip 1 and an overcurrent and short-circuit trigger signal to the latch circuit 5. The preset current threshold can be set by adjusting the parameters of the components selected in the current detection circuit 4; this application does not impose any specific limitations on this. After receiving the overcurrent wake-up signal, the main control chip 1 enters a wake-up state and controls the high-side driver chip 2 to supply power to the constant power module. Simultaneously, the current detection circuit outputs overcurrent and short-circuit trigger signals to the latch circuit 5, causing the latch circuit 5 to enter a self-locking state, thereby controlling the sleep power supply circuit 3 to stop supplying power to the constant power module.

[0074] Furthermore, considering that if the current detection circuit controls the sleep power supply circuit 3 to shut down when it detects that the current at the power supply terminal of the constant power module is greater than the preset current value, the current at the power supply terminal of the constant power module will become zero. This would cause the current detection circuit to mistakenly believe that the constant power module has returned to normal and thus control the sleep power supply circuit 3 to supply power to the constant power module again. This process, repeated cyclically, may eventually damage the current detection circuit and the sleep power supply circuit 3. Therefore, this embodiment also includes a latch circuit 5. The latch circuit 5 enters a self-locking state when it receives an overcurrent and short-circuit trigger signal. When 5 is in the self-locking state, it will latch overcurrent and short-circuit signals. The overcurrent and short-circuit latch signals are used as the output shutdown signal of the sleep power supply circuit 3 to control the sleep power supply circuit 3 to stop supplying power to the constant power module, ensuring the safety of the sleep power supply circuit 3. At the same time, the overcurrent and short-circuit latch signals are also used as the enable signal of the high-side driver chip 2 to control the high-side driver chip 2 to supply power to the constant power module. The high-side driver chip 2 undertakes the task of supplying power to the constant power module by means of its own short-circuit shutdown mechanism. At the same time, since the high-side driver chip 2 also has the ability to shut down the constant power module port instantaneously when short-circuited, it can ensure the safety of the domain controller.

[0075] In a preferred embodiment, the current detection circuit includes a first sampling resistor Rc1, a second sampling resistor Rc2, a first PNP transistor PNP1, a second PNP transistor PNP2, a third diode, and a fourth diode, wherein the resistance value of the first sampling resistor Rc1 is greater than the resistance value of the second sampling resistor Rc2.

[0076] The first end of the first sampling resistor Rc1 is connected to the output terminal of the sleep power supply circuit, the second end of the first sampling resistor Rc1 is connected to the first end of the second sampling resistor Rc2, and the second end of the second sampling resistor Rc2 is connected to the power supply terminal of the constant power module.

[0077] The base of the first PNP transistor PNP1 is connected to the second end of the first sampling resistor Rc1, the emitter is connected to the first end of the first sampling resistor Rc1, and the collector is the first output terminal of the current detection circuit used to output an overcurrent wake-up signal.

[0078] The base of the second PNP transistor PNP2 is connected to the second end of the second sampling resistor Rc2, the emitter is connected to the first end of the second sampling resistor Rc2, and the collector is the second output terminal of the current detection circuit used to output a short-circuit wake-up signal.

[0079] The anode of the third diode is connected to the first output terminal of the current detection circuit 4, the anode of the fourth diode is connected to the second output terminal of the current detection circuit 4, and the cathode of the third diode is connected to the cathode of the fourth diode to form the third output terminal of the current detection circuit 4, which is used to output overcurrent and short-circuit trigger signals.

[0080] The current detection circuits commonly used in the prior art cannot distinguish between overcurrent and short circuit. Furthermore, when the domain controller is in sleep mode, the current can only be collected and judged by the main control chip 1 periodically waking it up from sleep mode. The entire process of waking up, sampling and data processing of the main control chip 1 takes a certain amount of time, which cannot meet the timeliness requirement.

[0081] Therefore, this embodiment provides a current detection circuit that balances overcurrent and short-circuit detection with timely detection. Specifically, the resistance of the first sampling resistor Rc1 in the current detection circuit is greater than the resistance of the second sampling resistor Rc2. The conduction characteristics of a PNP transistor are used to detect overcurrent and short circuit. The collector output current of the first PNP transistor PNP1 corresponds to an overcurrent situation in the constant-current module, while the collector output current of the second PNP transistor PNP2 corresponds to a short circuit situation. In other words, the overcurrent or short circuit situation in the constant-current module can be determined by judging whether the signal is from the collector output of the first PNP transistor PNP1 or the collector output signal of the second PNP transistor PNP2.

[0082] Please refer to Figure 5 , Figure 5This invention provides a schematic diagram of the operating modes of a domain controller. When the domain controller is in sleep mode, an overcurrent wake-up signal is output from the collector of the first PNP transistor PNP1 in the current detection circuit, indicating an overcurrent in the constant power module; or a short-circuit wake-up signal is output from the collector of the second PNP transistor PNP1 in the current detection circuit, indicating a short circuit in the constant power module. Both wake-up signals can cause the domain controller to enter the operating mode. After entering the operating mode, the HSD (High-Side Driver) chip, which has stronger driving capability, supplies power to the constant power module and shuts down the sleep power supply circuit. On the other hand, both wake-up signals can trigger a latching mode: during the initialization process of the main control chip 1 in the operating mode, the latching circuit 5 takes over the control of the high-side driver chip 2 to supply power to the constant power module to maintain uninterrupted power supply; and takes over the control of the sleep circuit 3 to shut down, quickly shutting down the sleep power supply circuit with weaker driving capability. It should be noted that even in the case of a short circuit, the high-side driver chip 2 is enabled in the latching mode, relying on the short-circuit shutdown mechanism of the high-side driver chip 2 itself, which is sufficient to ensure the safety of the domain controller. In protection mode, the high-side driver chip 2, relying on its own short-circuit recovery mechanism, will attempt to automatically turn on when the short-circuit current disappears and the current returns to normal (this characteristic is present when enabled, which is why the high-side driver chip 2 is enabled even in latching mode when a short circuit occurs). After the main control chip 1 detects and clears the fault in the constant power module, it clears the latch state so that the control of the high-side driver chip 2 and the sleep power supply circuit 3 is restored from the latch circuit to the control of the main control chip 1.

[0083] Taking the first sampling resistor Rc1 as an example, its resistance is set to 5Ω. When the current flowing through it is 120mA (under normal circumstances, the sleep current consumption of the constant power module is less than 3mA, and its rated operating current is between 50mA and 100mA; reaching 120mA is considered an abnormal operation of the constant power module), the first PNP transistor PNP1 conducts (transistor turn-on voltage 0.6V = 5Ω * 120mA), and the collector output of the first PNP transistor PNP1 is 12V, which is the overcurrent signal. Here, setting 120mA as the overcurrent threshold conforms to the electrical engineering regulations for conductors and electrical appliances of 1.2 to 1.3 times the overcurrent multiple (as specified in Chapter 11 of the "Industrial and Civil Power Supply and Distribution Design Manual (Fourth Edition)"). On the other hand, the first PMOS in the sleep power supply circuit 3 is a common signal MOS transistor with a rated current of 100mA. From the perspective of protecting the electronic switch, it should be shut down in time if the current exceeds the rated current (not instantaneous, as the electronic switch itself has a certain overload capacity). When calculating low-voltage short-circuit current, the internal resistance of the battery, the resistance of the wires, and the contact resistance of each connector must be considered (as stipulated in Chapter 4 of the "Industrial and Civil Power Supply and Distribution Design Manual (Fourth Edition)"). These factors vary greatly depending on the wire harness diameter, length, and connector contact method. For example, if the battery internal resistance is 4.5mΩ (typical value for 55AH), the total short-circuit circuit contact resistance is 100mΩ. The internal resistance of a 2m long, 0.5mm² diameter insulated wire is R = 0.0184 * 2 / 0.5 = 73.6mΩ (resistivity 0.0184, see Appendix E of "Technical Specification for DC Power Supply System Design of Power Engineering" DL / 5 5044-2014). In this case, the short-circuit current is 12V / (4.5mΩ + 100mΩ + 73.6mΩ) = 67.4A. It is evident that the short-circuit current mainly depends on the wire harness diameter and contact resistance, and the short-circuit current value is generally quite large, exceeding tens of A. Although the above method can accurately calculate the short-circuit current, it is not practically feasible. Therefore, the short-circuit current is generally determined to be 3 times the operating current. For a normal power module that consumes 100mA during normal operation, 300mA is considered a short circuit. Therefore, the second sampling resistor Rc2 is set to about 2Ω (0.6V / 300mA=2Ω), and the operating principle is the same as above.

[0084] In summary, since the first PNP transistor PNP1 and the second PNP transistor PNP2 will not conduct when no overcurrent / short circuit is detected, the current consumption of the current detection circuit is zero when the domain controller is in sleep mode and the constant power module is normal, thus achieving low power consumption of the domain controller. The turn-on voltage of the PNP transistors themselves is used as the criterion for overcurrent and short circuit detection, replacing the function of the comparator in existing technologies. Furthermore, the overcurrent trigger signal output by the first PNP transistor PNP1 and the short circuit trigger signal output by the second PNP transistor PNP2 are both derived from the power supply of the sleep power supply circuit, eliminating the need for an additional power supply device. Moreover, existing technologies that detect short circuits in the constant power module by sampling the current across the sampling resistor require selecting a small-value sampling resistor; however, the first sampling resistor Rc1 and the second sampling resistor Rc2 in this application can be larger-value resistors, thus reducing the size and cost of the first sampling resistor Rc1 and the second sampling resistor Rc2. On the other hand, the first sampling resistor Rc1 and the second sampling resistor Rc2 together are 7Ω. For a constant power module with a normal operating current of 100mA, the sampling detection circuit will generate a voltage drop of 0.7V. That is, when the constant power module is powered through the sleep power supply circuit, the supply voltage is 12V-0.7V=11.3V, which is in line with the automotive industry's 9V~16V power supply standard.

[0085] In a preferred embodiment, the current detection circuit further includes a first capacitor C1, a second capacitor C2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9.

[0086] The fourth resistor R4 and the fifth resistor R5 are connected in series. One end of the series circuit is connected to the second end of the first sampling resistor Rc1, and the other end of the series circuit is connected to the base of the first PNP transistor PNP1. The first capacitor C1 is connected between the first end of the first sampling resistor Rc1 and the common terminal of the fourth resistor R4 and the fifth resistor R5. One end of the sixth resistor R6 is connected to the collector of the first PNP transistor PNP1, and the other end of the sixth resistor R6 is the first output terminal of the current detection circuit used to output an overcurrent wake-up signal.

[0087] The seventh resistor R7 and the eighth resistor R8 are connected in series. One end of the series circuit is connected to the second end of the second sampling resistor Rc2, and the other end of the series circuit is connected to the base of the second PNP transistor PNP2. The first end of the second capacitor C2 is connected to the first end of the second sampling resistor Rc2, and the second end of the second capacitor C2 is connected to the common terminal of the seventh resistor R7 and the eighth resistor R8. One end of the ninth resistor R9 is connected to the collector of the second PNP transistor PNP2, and the other end of the ninth resistor R9 is the second output terminal of the current detection circuit used to output a short-circuit wake-up signal.

[0088] To further optimize the current detection circuit, this embodiment also includes a first capacitor C1, a second capacitor C2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The fourth resistor R4 and the fifth resistor R5 are the base current-limiting resistors for the first PNP transistor PNP1, and the seventh resistor R7 and the eighth resistor R8 are the base current-limiting resistors for the second PNP transistor PNP2, with a typical value of 2.2kΩ, used to prevent damage to the PNP transistors due to overcurrent when they are turned on. The first capacitor C1 and the second capacitor C2 are filter capacitors, with a typical value of 10nF, forming low-pass filters with the current resistors R4 and R7, respectively, to prevent the PNP transistors from abnormally turning on due to voltage glitches in the sleep power supply circuit itself. The sixth resistor R6 and the ninth resistor R9 are current-limiting resistors, with a typical value of 10kΩ. The typical values ​​of the above components are only for illustrative purposes; specific values ​​can be set according to actual needs, and this application does not impose any particular limitations on them.

[0089] In a preferred embodiment, the latching circuit includes a Schmitt trigger S1, an NPN transistor, a reverse protection diode D5, a first bias resistor Rp1, and a second bias resistor Rp2;

[0090] The input terminal of Schmitt trigger S1 is the input terminal of the latch circuit, and the output terminal of Schmitt trigger S1 is the output terminal of the latch circuit. The output terminal of Schmitt trigger S1 is connected to the anode of the reverse protection diode D5, and the input terminal of Schmitt trigger S1 is connected to the cathode of the reverse protection diode D5. Schmitt trigger S1 is used to output overcurrent and short-circuit latch signals when it receives overcurrent and short-circuit trigger signals at its input terminal. The overcurrent and short-circuit latch signals are used to control the sleep power supply circuit to stop supplying power to the constant power module and to control the high-side driver chip to supply power to the constant power module.

[0091] The collector of the NPN transistor is connected to the input of the Schmitt trigger S1. The first end of the first bias resistor Rp1 is connected to the base of the NPN transistor and the second end of the second bias resistor Rp2. The second end of the second bias resistor Rp2 and the emitter of the NPN transistor are both grounded. The second end of the first bias resistor Rp1 is used to receive the latch clear signal so that the Schmitt trigger S1 stops outputting overcurrent and short-circuit latch signals.

[0092] Specifically, the latching circuit provided in this embodiment includes a reverse protection diode D5, a Schmitt trigger S1, an NPN transistor, a first current-limiting resistor Rp1, and a second bias resistor Rp2. A self-locking circuit is formed by connecting the output and input terminals of the Schmitt trigger S1 through the reverse protection diode D5. Considering that the sleep power supply circuit 3 is in the default on state and only turns off upon receiving a turn-off signal, when a short circuit or overcurrent occurs in the constant power module, the current detection circuit outputs an overcurrent short-circuit trigger signal to the latching circuit. After self-locking by the Schmitt trigger S1, regardless of whether the overcurrent short-circuit trigger signal output by the current detection circuit disappears, the overcurrent short-circuit latching signal output by the Schmitt trigger S1 remains valid. Therefore, the turn-off signal received by the sleep power supply circuit 3 remains valid, thus controlling the sleep power supply circuit 3 to remain in the off state. Simultaneously, this overcurrent short-circuit latching signal controls the higher-side driver chip 2, which has a stronger driving force, to supply power to the constant power module.

[0093] The anti-reverse diode D5 in the latching circuit is used to form a positive feedback channel for the Schmitt trigger S1, thereby forming a signal self-lock. The NPN transistor NPN is used as a reset ground switch for the Schmitt trigger S1. The first current limiting resistor Rp1 is used for current limiting, and the second bias resistor Rp2 is used for biasing. The typical value can be 10kΩ.

[0094] In summary, since the input stage impedance of Schmitt trigger S1 is approximately infinite, the current consumed when Schmitt trigger S1 enters the self-locking state is 0mA (negligible at the μA level), further reducing power consumption while ensuring the normal operation of the domain controller.

[0095] In a preferred embodiment, the main control chip 1 is also used to detect whether the constant power module is abnormal when it receives an overcurrent wake-up signal or a short circuit wake-up signal, and when it is determined that the constant power module is not abnormal, it outputs a latch clear signal to the latch circuit 5 to control the latch circuit to exit the self-locking state.

[0096] In this embodiment, the main control chip 1 is also used to detect whether the constant power module is abnormal after being woken up by the current detection circuit 4. After detecting that the constant power module is not abnormal, it takes over the enable control of the high-side driver chip 2 from the latch circuit 5. After enabling the high-side driver chip 2, it clears the state of the latch circuit 5 by sending a clear signal to the latch circuit 5. The control of the high-side driver chip 2 and the sleep power supply circuit 3 is returned to the main control chip 1 to restore the normal power supply logic. When the main control chip 1 detects that the constant power module is not abnormal, it outputs a clear signal. It only needs to pull the input of the Schmitt trigger S1 low once to make the Schmitt trigger S1 exit the self-locking state, so that the sleep power supply circuit 3 and the high-side driver chip 2 can resume normal controlled logic.

[0097] This application also provides a vehicle including the aforementioned domain controller.

[0098] For a description of the automobile provided in this application, please refer to the above-described embodiment of the domain controller; further details will not be repeated here.

[0099] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0100] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A domain controller, characterized in that, It includes a main control chip, a high-side driver chip, and a sleep power supply circuit, wherein the sleep power supply circuit includes a first PMOS, a first resistor, and a shutdown circuit; The voltage input terminal of the high-side driver chip and the voltage input terminal of the sleep power supply circuit are both connected to the voltage output terminal of the first-level power supply circuit, and the voltage output terminal of the high-side driver chip and the voltage output terminal of the sleep power supply circuit are both connected to the power supply terminal of the constant power module. The main control chip is used to enable the high-side driver chip to supply power to the constant power module when a wake-up signal is received, and at the same time output a shutdown signal to the sleep power supply circuit so that the sleep power supply circuit stops supplying power to the constant power module; and to control the high-side driver chip to stop supplying power to the constant power module when a sleep signal is received, and at the same time stop outputting the shutdown signal to the sleep power supply circuit so that the sleep power supply circuit supplies power to the constant power module. The source of the first PMOS is the voltage input terminal of the sleep power supply circuit, the drain is the voltage output terminal of the sleep power supply circuit, the gate is connected to the first terminal of the first resistor and the output terminal of the shutdown circuit, the second terminal of the first resistor is grounded, and the shutdown circuit is used to turn off the first PMOS by pulling up the voltage of the gate of the first PMOS when the shutdown signal is received. It also includes a current detection circuit and a latching circuit; The current detection circuit is used to output an overcurrent wake-up signal to the main control chip and an overcurrent and short-circuit trigger signal to the latch circuit when the current flowing through the circuit connecting the sleep power supply circuit and the constant power module is greater than a preset overcurrent threshold; and to output a short-circuit wake-up signal to the main control chip and the overcurrent and short-circuit trigger signal to the latch circuit when the current flowing through the circuit connecting the sleep power supply circuit and the constant power module is greater than a preset short-circuit threshold. The latching circuit is used to enter a self-locking state when it receives the overcurrent and short-circuit trigger signals in order to output the shutdown signal to the sleep power supply circuit and enable the high-side driver chip to supply power to the constant power module. The main control chip is also used to enable the high-side driver chip to supply power to the constant power module when receiving the overcurrent wake-up signal, and output a latch clear signal to the latch circuit to make the latch circuit exit the self-locking state; and to output the latch clear signal to the latch circuit when receiving the short-circuit wake-up signal to make the latch circuit exit the self-locking state. The main control chip is also used to detect whether the constant power module is abnormal when it receives the overcurrent wake-up signal or the short-circuit wake-up signal, and when it is determined that the constant power module is not abnormal, it outputs a latch clear signal to the latch circuit to control the latch circuit to exit the self-locking state.

2. The domain controller as described in claim 1, characterized in that, The shutdown circuit includes a first NMOS and a second PMOS; The gate of the first NMOS is used to receive the shutdown signal, the source of the first NMOS is grounded, the drain of the first NMOS is connected to the gate of the second PMOS, the drain of the second PMOS is the output terminal of the shutdown circuit, and the source of the second PMOS is connected to the source of the first PMOS.

3. The domain controller as described in claim 2, characterized in that, The shutdown circuit also includes a second resistor, a third resistor, a tenth resistor, a first Zener diode, and a second Zener diode; The third resistor is connected between the gate and the source of the first NMOS, the second resistor is connected between the gate and the source of the second PMOS, the positive terminal of the second Zener diode is connected to the gate of the second PMOS, the negative terminal of the second Zener diode is connected to the source of the second PMOS, and the tenth resistor is connected between the source of the second PMOS and the voltage input terminal of the sleep power supply circuit. The common terminal of the gate of the first PMOS and the first resistor is connected to the positive terminal of the first Zener diode, and the negative terminal of the first Zener diode is connected to the source of the first PMOS.

4. The domain controller as described in claim 1, characterized in that, The main control chip is also used to obtain the current on the current feedback pin of the high-side driver chip after receiving the wake-up signal, and start timing when it is determined that the constant power module is overcurrent based on the current on the current feedback pin, and control the high-side driver chip to stop supplying power to the constant power module when the timing time is greater than a preset duration.

5. The domain controller as described in claim 4, characterized in that, The high-side driver chip is also used to stop supplying power to the constant power module when it is determined that the constant power module is short-circuited based on the current on its own current feedback pin.

6. The domain controller as claimed in claim 1, characterized in that, The current detection circuit includes a first sampling resistor, a second sampling resistor, a third diode, a fourth diode, a first PNP transistor, and a second PNP transistor, wherein the resistance value of the first sampling resistor is greater than the resistance value of the second sampling resistor. The first end of the first sampling resistor is connected to the output terminal of the sleep power supply circuit, the second end of the first sampling resistor is connected to the first end of the second sampling resistor, and the second end of the second sampling resistor is connected to the power supply terminal of the constant power module. The base of the first PNP transistor is connected to the second end of the first sampling resistor, the emitter is connected to the first end of the first sampling resistor, and the collector is the first output terminal of the current detection circuit used to output the overcurrent wake-up signal. The base of the second PNP transistor is connected to the second end of the second sampling resistor, the emitter is connected to the first end of the second sampling resistor, and the collector is the second output terminal of the current detection circuit used to output the short-circuit wake-up signal. The anode of the third diode is connected to the first output terminal of the current detection circuit, the anode of the fourth diode is connected to the second output terminal of the current detection circuit, and the cathode of the third diode is connected to the cathode of the fourth diode to form the third output terminal of the current detection circuit for outputting the overcurrent and short-circuit trigger signals.

7. The domain controller as claimed in claim 6, characterized in that, The current detection circuit also includes a first capacitor, a second capacitor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor; The fourth resistor and the fifth resistor are connected in series. One end of the series circuit is connected to the second end of the first sampling resistor, and the other end of the series circuit is connected to the base of the first PNP transistor. The first capacitor is connected between the first end of the first sampling resistor and the common terminal of the fourth and fifth resistors. One end of the sixth resistor is connected to the collector of the first PNP transistor, and the other end of the sixth resistor is the first output terminal of the current detection circuit used to output the overcurrent wake-up signal. The seventh resistor and the eighth resistor are connected in series. One end of the series circuit is connected to the second end of the second sampling resistor, and the other end of the series circuit is connected to the base of the second PNP transistor. The first end of the second capacitor is connected to the first end of the second sampling resistor, and the second end of the second capacitor is connected to the common terminal of the seventh and eighth resistors. One end of the ninth resistor is connected to the collector of the second PNP transistor, and the other end of the ninth resistor is the second output terminal of the current detection circuit used to output the short-circuit wake-up signal.

8. The domain controller as claimed in claim 1, characterized in that, The latching circuit includes a Schmitt trigger, an NPN transistor, a fifth diode, a first bias resistor, and a second bias resistor; The input terminal of the Schmitt trigger is the input terminal of the latch circuit, and the output terminal of the Schmitt trigger is the output terminal of the latch circuit. The output terminal of the Schmitt trigger is connected to the anode of the fifth diode, and the input terminal of the Schmitt trigger is connected to the cathode of the fifth diode. The Schmitt trigger is used to output an overcurrent and short-circuit latch signal when it receives the overcurrent and short-circuit trigger signal at its own input terminal. The overcurrent and short-circuit latch signal is used to control the sleep power supply circuit to stop supplying power to the constant power module and to control the high-side driver chip to supply power to the constant power module. The collector of the NPN transistor is connected to the input terminal of the Schmitt trigger. The first terminal of the first bias resistor is connected to the base of the NPN transistor and the second terminal of the second bias resistor. The second terminal of the second bias resistor and the emitter of the NPN transistor are both grounded. The second terminal of the first bias resistor is used to receive the latch clear signal so that the Schmitt trigger stops outputting the overcurrent and short-circuit latch signals.

9. A car, characterized in that, Includes the domain controller as described in any one of claims 1 to 8.

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