Display panel and display device

Abstract

The application relates to a display panel and a display device, the display panel comprising: a device layer comprising a first transistor located in a first display area and a second transistor located in a second display area, the first transistor comprising a first gate electrode, and the second transistor comprising a second gate electrode; a light-emitting layer stacked on one side of the device layer in a thickness direction of the device layer, comprising a plurality of first sub-pixels distributed in the first display area and second sub-pixels distributed in the second display area, the first sub-pixels comprising a first electrode electrically connected to the first transistor, and the second sub-pixels comprising a second electrode electrically connected to the second transistor, in the thickness direction, a normal projection of the first electrode at least partially overlaps a normal projection of the first gate electrode to form a first overlapping area; and a shielding layer arranged between a layer structure where the first gate electrode is located and a layer structure where the first electrode is located, the shielding layer covering the first overlapping area. The application can meet display requirements, has good brightness uniformity, and ensures display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] In the future, a transparent display device will be designed in the notch area of ​​the mobile phone, with the photosensitive components located under the transparent display panel to increase the screen-to-body ratio and achieve a true full-screen display.

[0003] Taking the display panel using organic light-emitting diode (OLED) as an example, since there are parasitic capacitances between the transistors and the electrodes of the corresponding sub-pixels in the area mainly used for display, the generation of parasitic capacitances will cause the brightness of different transparency areas of the display panel to be inconsistent, affecting the display effect of the organic light-emitting display panel. Summary of the Invention

[0004] This invention provides a display panel and a display device. The display panel can meet display requirements and has good brightness uniformity, thus ensuring display effect.

[0005] On one hand, according to an embodiment of the present invention, a display panel is provided, having a second display area and a first display area disposed at least partially surrounding the second display area, wherein the light transmittance of the second display area is greater than that of the first display area. The display panel includes: a device layer including a first transistor located in the first display area and a second transistor located in the second display area, the first transistor including a first gate electrode and the second transistor including a second gate electrode; a light-emitting layer, stacked on one side of the device layer in its thickness direction, the light-emitting layer including a plurality of first sub-pixels distributed in the first display area and a plurality of second sub-pixels distributed in the second display area, the first sub-pixels including a first electrode electrically connected to the first transistor and the second sub-pixels including a second electrode electrically connected to the second transistor, wherein in the thickness direction, the orthographic projection of the first electrode at least partially overlaps with the orthographic projection of the first gate electrode to form a first overlapping region; and a shielding layer disposed between the layer structure where the first gate electrode is located and the layer structure where the first electrode is located, the shielding layer being connected to a fixed potential and its orthographic projection in the thickness direction at least covering the first overlapping region.

[0006] According to one aspect of the present invention, the shielding layer includes arrayed shielding units, each shielding unit covering at least one first overlapping region formed by the first electrode and the first gate electrode.

[0007] According to one aspect of the present invention, at least three of the shielding units are interconnected and connected to the same potential.

[0008] According to one aspect of the present invention, the shielding unit is strip-shaped.

[0009] According to one aspect of the present invention, in the thickness direction, the second electrode and the second gate electrode are offset from each other by their orthogonal projections, and the shielding layer is located in the first display area.

[0010] According to one aspect of the present invention, the second display area includes a transparent display area and a transition display area located between the transparent display area and the first display area. The light transmittance of the first display area is less than that of the transparent display area. Each second transistor is disposed in the transition display area, and each second transistor is electrically connected to at least one second sub-pixel.

[0011] According to one aspect of the present invention, a second electrode located in the transparent display area is electrically connected to a second transistor via an electrode trace; in the thickness direction, the orthographic projection of the second electrode overlaps with the orthographic projection of the second gate electrode to form a second overlapping region, and a shielding layer is located between the second electrode and the second gate electrode and covers the second overlapping region; and / or, in the thickness direction, the orthographic projection of the electrode trace overlaps with the orthographic projection of the second electrode to form a third overlapping region, and a shielding layer is located between the electrode trace and the second electrode and covers the third overlapping region.

[0012] According to one aspect of the present invention, an insulating layer is formed between the device layer and the shielding layer, the insulating layer comprising an inorganic layer.

[0013] According to one aspect of the present invention, the inorganic layer includes at least one of silicon oxide and silicon nitride.

[0014] According to one aspect of the present invention, the device layer further includes a signal line, an opening is provided on the insulating layer, the signal line is exposed through a via, and the shielding layer is electrically connected to the signal line through the via.

[0015] According to one aspect of the present invention, the signal line includes one of a DC power supply signal line and a reference voltage signal line.

[0016] According to one aspect of the present invention, the shielding layer is a non-metallic layer structure.

[0017] According to one aspect of the present invention, the shielding layer comprises one of indium tin oxide and indium zinc oxide.

[0018] In another aspect, according to an embodiment of the present invention, a display device is provided, comprising the above-described display panel.

[0019] According to the embodiments of the present invention, the display panel and the display device include a device layer, a light-emitting layer and a shielding layer. The device layer includes a first transistor located in a first display area and a second transistor located in a second display area. The light-emitting layer includes a first sub-pixel distributed in the first display area and a second sub-pixel distributed in the second display area. Since the light transmittance of the second display area is greater than that of the first display area, the photosensitive component can be disposed on the back side of the second display area, which can realize full-screen display and ensure the light-sensing requirements of the photosensitive component.

[0020] Meanwhile, since the first display area is used for normal display, the first gate electrode and the first electrode will at least partially overlap in the thickness direction of the device layer to form a first overlapping area. By setting a shielding layer between the layer structure where the first gate electrode is located and the layer structure where the first electrode is located, the shielding layer is connected to a fixed potential and its orthogonal projection in the thickness direction at least covers the first overlapping area, the parasitic capacitance between the first electrode and the first gate electrode can be reduced or avoided, the brightness difference between the first display area and the second display area can be reduced, the uniformity can be good, and the display effect can be guaranteed. Attached Figure Description

[0021] The features, advantages and technical effects of exemplary embodiments of the present invention will now be described with reference to the accompanying drawings.

[0022] Figure 1 This is a top view of a display panel according to an embodiment of the present invention;

[0023] Figure 2 yes Figure 1 Enlarged view of point Q;

[0024] Figure 3 yes Figure 2 A cross-sectional view along the MM direction;

[0025] Figure 4 yes Figure 2 A cross-sectional view along the NN direction;

[0026] Figure 5 yes Figure 2 A cross-sectional view along the PP direction;

[0027] Figure 6 This is a top view schematic diagram of the shielding layer according to an embodiment of the present invention;

[0028] Figure 7 This is a top view of a display device according to an embodiment of the present invention;

[0029] Figure 8 yes Figure 7 A cross-sectional view along the WW direction.

[0030] in:

[0031] 100 - Display panel; AA1 - First display area; AA2 - Second display area; AA2a - Transparent display area; AA2b - Transition display area;

[0032] 11-First transistor; 111-First gate electrode; 12-Second transistor; 121-Second gate electrode; 13-Signal line;

[0033] 20 - Light-emitting layer; 21 - First sub-pixel; 211 - First electrode; 212 - First light-emitting element; 213 - Third electrode; 22 - Second sub-pixel; 221 - Second electrode; 222 - Second light-emitting element; 223 - Fourth electrode;

[0034] 30 - Shielding layer; 31 - Shielding unit;

[0035] 40 - Insulation layer;

[0036] 50 - First overlapping region; 60 - Second overlapping region; 70 - Electrode trace;

[0037] 200 - Photosensitive element.

[0038] X - Thickness direction.

[0039] In the accompanying drawings, the same parts use the same reference numerals. The drawings are not drawn to scale. Detailed Implementation

[0040] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. Numerous specific details are set forth in the following detailed description in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. In the accompanying drawings and the following description, at least some well-known structures and techniques have not been shown in order to avoid unnecessarily obscuring the invention; and, for clarity, the dimensions of some structures may be exaggerated. Furthermore, the features, structures, or characteristics described below may be combined in any suitable manner in one or more embodiments.

[0041] The directional terms used in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of the display panel and display device of the present invention. It should also be noted in the description of the present invention that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0042] In the future, a transparent display device will be designed in the notch area of ​​the mobile phone, with the photosensitive components located under the transparent display panel to increase the screen-to-body ratio and achieve a true full-screen display.

[0043] Taking Organic Light-Emitting Diode (OLED) displays as an example, OLEDs have gradually gained a foothold in the small-size display field due to their advantages such as thinness, flexibility, high contrast, and wide color gamut. Their basic structure includes an organic light-emitting unit (OLED) corresponding to each pixel area and a pixel driving circuit. The OLED includes two electrodes with opposite polarities and a light-emitting element located between them. When a voltage is applied to the two electrodes with opposite polarities, holes and electrons move to the light-emitting layer, recombine in the layer, and excitons in the light-emitting element migrate from the excited state to the ground state to emit light. With increasing application time, the potential of one electrode of the OLED rises. This change in the potential of the corresponding electrode causes a change in the potential on the metal structure of the pixel driving circuit in the overlapping area with the OLED, generating parasitic capacitance. This parasitic capacitance leads to inconsistent brightness in areas of different transparency on the display panel, affecting the display effect of the OLED display.

[0044] To address the aforementioned technical problems, embodiments of the present invention provide a display panel 100 and a display device that meet display requirements, exhibit good brightness uniformity, and ensure display quality. For a better understanding of the present invention, the following description is provided in conjunction with... Figures 1 to 8 The display panel and display device according to embodiments of the present invention will be described in detail.

[0045] like Figures 1 to 5As shown, the display panel 100 provided in this embodiment of the invention has a second display area AA2 and a first display area AA1 disposed at least partially around the second display area AA2. The light transmittance of the second display area AA2 is greater than that of the first display area AA1. The display panel 100 includes a device layer, a light-emitting layer 20 and a shielding layer 30. The device layer includes a first transistor 11 located in the first display area AA1 and a second transistor 12 located in the second display area AA2. The first transistor 11 includes a first gate electrode 111 and the second transistor 12 includes a second gate electrode 121. A light-emitting layer 20 is stacked on one side of the device layer in its thickness direction X. The light-emitting layer 20 includes a plurality of first sub-pixels 21 distributed in the first display area AA1 and second sub-pixels 22 distributed in the second display area AA2. The first sub-pixels 21 include a first electrode 211 electrically connected to the first transistor 11, and the second sub-pixels 22 include a second electrode 221 electrically connected to the second transistor 12. In the thickness direction X, the orthographic projection of the first electrode 211 at least partially overlaps with the orthographic projection of the first gate electrode 111 to form a first overlapping region 50. The first transistor 11 is used to drive the first sub-pixels 21, and the second transistor 12 is used to drive the second sub-pixels 22. A shielding layer 30 is disposed between the layer structure where the first gate electrode 111 is located and the layer structure where the first electrode 211 is located. The shielding layer 30 is connected to a fixed potential, and its orthographic projection in the thickness direction X at least covers the first overlapping region 50.

[0046] The first gate electrode 111 mentioned in the embodiments of the present invention refers to a gate potential layer that is not covered by other metal layers in the thickness direction X of the device layer, for example... Figure 3 The gate potential layer is located in the region of the first overlap region 50. Similarly, the second gate electrode 121 refers to the gate potential layer that is not covered by other metal layers in the thickness direction X, for example... Figure 4 The middle gate potential layer is located in the region of the second overlapping region 60.

[0047] The display panel 100 provided in this embodiment of the invention, since the light transmittance of the second display area AA2 is greater than that of the first display area AA1, can place photosensitive components and other devices on the back side of the second display area AA2, thereby achieving full-screen display while ensuring the light-sensing requirements of the photosensitive components 200. Meanwhile, since the first display area AA1 is used for normal display, the orthographic projections of its first gate electrode 111 and first electrode 211 in the thickness direction X of the device layer will at least partially overlap to form a first overlapping area 50. By providing a shielding layer 30 between the layer structure containing the first gate electrode 111 and the layer structure containing the first electrode 211, and by connecting the shielding layer 30 to a fixed potential and having its orthographic projection in the thickness direction X at least covering the first overlapping area 50, the formation of parasitic capacitance between the first electrode 211 and the first gate electrode 111 can be reduced or avoided, thereby reducing the brightness difference between the first display area AA1 and the second display area AA2, resulting in good uniformity and ensuring display performance.

[0048] Optionally, the display panel 100 provided in the embodiments of the present invention includes a second display area AA2 comprising a transparent display area AA2a and a transition display area AA2b located between the transparent display area AA2a and the second display area AA2, wherein the light transmittance of the first display area AA1 is less than that of the transparent display area AA2a.

[0049] Optionally, the light transmittance of the transparent display area AA2a is greater than or equal to 15%. To ensure that the light transmittance of the transparent display area AA2a is greater than 15%, or even greater than 40%, or even higher, in this embodiment, the light transmittance of each functional film layer of the display panel 100 is greater than 80%, and even at least some functional film layers have a light transmittance greater than 90%.

[0050] As an optional implementation, the display panel 100 provided in this embodiment of the invention may include a substrate, which may be made of a rigid material or a flexible substrate.

[0051] Optionally, the device layer is stacked on the substrate, and the device layer includes multiple first transistors 11 distributed in an array in the first display area AA1, and multiple second transistors 12 distributed in an array in the second display area AA2. In some optional embodiments, in order to ensure the light transmittance of the transparent display area AA2a, the array of second transistors 12 in the second display area AA2 can be distributed in the transition display area AA2b of the second display area AA2.

[0052] In some optional embodiments, the device layer may have a semiconductor layer, a multilayer metal layer and an interlayer insulating layer stacked and patterned along its own thickness direction X. The multilayer metal layer includes a gate potential layer. The patterned semiconductor layer, the multilayer metal layer and the interlayer insulating layer together form a first transistor 11 arrayed in the first display area AA1 and a second transistor 12 arrayed in the second display area AA2.

[0053] The first transistor 11 includes a first gate electrode 111 in the gate potential layer, and the second transistor 12 includes a second gate electrode 121 in the gate potential layer. Optionally, the first gate electrode 111 and the second gate electrode 112 are disposed in the same layer.

[0054] Optionally, the light-emitting layer 20 is stacked on the side of the device layer that faces away from the substrate in its thickness direction X. To ensure the flatness of the display panel 100, a planarization layer is also provided between the light-emitting layer 20 and the device layer.

[0055] The light-emitting layer 20 includes a pixel defining layer having a plurality of pixel openings, and the light-emitting layer 20 also includes sub-pixels distributed within the plurality of pixel openings. Optionally, the light-emitting layer 20 includes a first sub-pixel 21 distributed in the first display area AA1 and controlled by the first transistor 11 and a second sub-pixel 22 distributed in the second display area AA2 and controlled by the second transistor 12.

[0056] Optionally, the plurality of first sub-pixels 21 of the first display area AA1 may include a first red sub-pixel, a first blue sub-pixel, and a first green sub-pixel, and the plurality of second sub-pixels 22 of the second display area AA2 may include a second red sub-pixel, a second blue sub-pixel, and a second green sub-pixel.

[0057] Optionally, the first sub-pixel 21 includes a first electrode 211, a third electrode 213 disposed opposite to each other in the thickness direction X, and a first light-emitting element 212 located between the first electrode 211 and the third electrode 213. The second sub-pixel 22 includes a second electrode 221, a fourth electrode 223 disposed opposite to each other in the thickness direction X, and a second light-emitting element 222 located between the second electrode 221 and the fourth electrode 223. In some optional examples, the first electrode 211 and the second electrode 221 may be disposed in the same layer, and the third electrode 213 and the fourth electrode 223 may be disposed in the same layer. Optionally, the first electrode 211 and the second electrode 221 may be anodes, and the third electrode 213 and the fourth electrode 223 may be cathodes. Optionally, the third electrode 213 and the fourth electrode 223 may be a single layer and connected to a fixed potential.

[0058] Optionally, the first electrode 211 may be connected to one of the source and drain of the first transistor 11, and the second electrode 221 may be connected to one of the source and drain of the second transistor 12.

[0059] As an optional implementation, the display panel 100 provided in this embodiment of the invention may have a shielding layer 30 located between the device layer and the metal layer forming the first electrode 211 and the second electrode 221.

[0060] As an optional implementation, in the display panel 100 provided in this embodiment of the invention, the area of ​​the first display area AA1 can be much larger than the area of ​​the second display area AA2. The first display area AA1 is used for normal display and can also be referred to as the main display area. Since a first overlapping region 50 is formed between the first electrode 211 and the first gate electrode 111 in the first display area AA1, parasitic capacitance can be generated when the display panel 100 is working normally, resulting in a brightness difference between the first display area AA1 and the second display area AA2. To avoid the above situation, a shielding layer 30 can be distributed between the first electrode 211 and the first gate electrode 111 with the first overlapping region 50. The shielding layer 30 is used to shield the parasitic capacitance generated between the first electrode 211 and the first gate electrode 111, avoiding the parasitic capacitance from affecting the potential difference of the first gate electrode 111, reducing the brightness difference between the first display area AA1 and the second display area AA2, resulting in good uniformity and ensuring display effect.

[0061] Optionally, when a shielding layer 30 is provided between the first electrode 211 and the first gate electrode 111 forming the first overlapping region 50, whether or not a shielding layer 30 is provided between the second gate electrode 121 and the second electrode 221 in the second display area AA2 can be determined according to the specific circumstances.

[0062] As an optional implementation, the display panel 100 provided in this embodiment of the invention may have each second transistor 12 disposed in the transition display area AA2b, and each second transistor 12 is electrically connected to at least one second sub-pixel 22. That is, the second transistor 12 disposed in the transition display area AA2b controls the second sub-pixel 22 located in the transition display area AA2b and the transparent display area AA2a.

[0063] Optionally, in the thickness direction X of the device layer, the orthographic projection of the second electrode 221 of each second sub-pixel 22 in the second display area AA2 and the orthographic projection of the second gate electrode 121 can be staggered, which can effectively avoid the generation of parasitic capacitance between the second electrode 221 and the second gate electrode 121. In this case, the shielding layer 30 can be provided only in the first display area AA1.

[0064] like Figure 4As shown, in some optional embodiments, the orthographic projections of the second electrode 221 and the second gate electrode 121 in the thickness direction X of the device layer are not limited to being staggered. In some embodiments, the orthographic projection of the second electrode 221 may at least partially overlap with the orthographic projection of the second gate electrode 121 to form a second overlapping region 60. In this case, in order to reduce or avoid the generation of parasitic capacitance between the second electrode 221 and the second gate electrode 121, the shielding layer 30 may be located between the second electrode 221 and the second gate electrode 121 and cover the second overlapping region 60. With the above arrangement, the generation of parasitic capacitance between the second electrode 221 and the second gate electrode 121 can be reduced or avoided.

[0065] Optionally, since the shielding layer 30 is connected to a fixed voltage, that is, the portion of the shielding layer 30 located in the first display area AA1 and the portion located in the second display area AA2 are connected to a fixed voltage, the difference in parasitic capacitance formed between them is reduced, thereby reducing the brightness difference between the first display area AA1 and the second display area AA2.

[0066] As an optional implementation, the display panel 100 provided in this embodiment of the invention may have a shielding layer 30 that is a single, continuous layer. Of course, this is only one optional implementation.

[0067] like Figure 6 As shown, in some other examples, the shielding layer 30 may also include a plurality of shielding units 31 arranged in an array, each shielding unit 31 covering at least one first overlapping region 50 formed by the first electrode 211 and the first gate electrode 111. The display panel 100 provided in this embodiment of the invention, by configuring the shielding layer 30 as a plurality of arrayed shielding units 31, allows each shielding unit 31 to be connected to a fixed potential, thereby reducing the voltage drop across each shielding unit 31 and optimizing the shielding effect of the shielding layer 30.

[0068] In some alternative embodiments, at least three shielding units 31 are interconnected and connected to the same potential. Specifically, after the three shielding units 31 are interconnected, one of the shielding units 31 is connected to a signal line through a via to obtain a fixed potential. With the above arrangement, the number of vias can be reduced, and the impact of vias on the flatness of the surface of each sub-pixel of the light-emitting layer 20 can be avoided.

[0069] As an optional implementation, the display panel 100 provided in this embodiment of the invention may also cover one of the first overlapping regions 50 when the shielding layer 30 includes a plurality of shielding units 31 arranged in an array, so as to avoid the generation of parasitic capacitance between the first electrode 211 and the first gate electrode 111.

[0070] Of course, in some embodiments, each shielding unit 31 may cover two or more first overlapping areas 50 formed by the first electrode 211 and the first gate electrode 111. With the above arrangement, the number of shielding units 31 can be reduced, thereby reducing the number of vias when the shielding unit 31 is connected to a fixed potential, and avoiding the impact of vias on the flatness of the surface of each sub-pixel of the light-emitting layer 20.

[0071] In some optional embodiments, each shielding unit 31 may cover the first overlapping area 50 formed between the three first electrodes 211 and the first gate electrode 111. The three first sub-pixels 21 covered by each shielding unit 31 may include a first red sub-pixel, a first blue sub-pixel, and a first green sub-pixel. To meet display requirements, the multiple first sub-pixels 21 in the first display area AA1 are arranged according to a predetermined pattern. The first red sub-pixel, the first blue sub-pixel, and the first green sub-pixel are components of a pixel unit. By including the first red sub-pixel, the first blue sub-pixel, and the first green sub-pixel in the three first sub-pixels 21 covered by each shielding unit 31, the vias used for connection to a fixed potential in the shielding unit 31 can be easily staggered from the first light-emitting elements of each first sub-pixel 21, ensuring flatness and optimizing the display effect.

[0072] In some alternative embodiments, the display panel 100 provided in this embodiment of the invention may have a strip-shaped shielding unit 31, which is beneficial for covering the first overlapping area 50 and the second overlapping area 60.

[0073] like Figures 2 to 6 As shown, in an optional implementation, the display panel 100 provided in this embodiment of the invention has a second electrode 221 located in the transparent display area AA2a electrically connected to the second transistor 12 via an electrode trace 70. In the thickness direction X, the orthographic projection of the electrode trace 70 overlaps with the orthographic projection of the second electrode 221 to form a third overlapping region. A shielding layer 30 is located between the electrode trace 70 and the second electrode 221 and covers the third overlapping region. Through the above arrangement, the parasitic capacitance of the second display area AA2 can be further reduced, the difference in parasitic capacitance between the first display area AA1 and the second display area AA2 can be reduced, thereby reducing the brightness difference between the first display area AA1 and the second display area AA2, resulting in good uniformity and ensuring display performance.

[0074] Optionally, when a shielding layer 30 is provided within the second display area AA2, a single shielding layer 30 can cover the second overlapping region 60 and / or the third overlapping region in the second display area AA2. Alternatively, the shielding layer 30 can include shielding units 31, with each shielding unit 31 covering at least one second overlapping region 60 or a third overlapping region. In some embodiments, each shielding unit 31 can cover two or more second overlapping regions 60 formed by the second electrode 221 and the second gate electrode 121. This reduces the number of vias required when the shielding unit 31 is connected to a fixed potential, and avoids the impact of vias on the flatness of the surface of each sub-pixel of the light-emitting layer 20.

[0075] In some alternative embodiments, each shielding unit 31 may cover the second overlapping region 60 formed between the three second electrodes 221 and the second gate electrode 121, and the three second sub-pixels 22 covered by each shielding unit 31 may include a second red sub-pixel, a second blue sub-pixel and a second green sub-pixel.

[0076] Optionally, the portion of the shielding layer 30 located in the first display area AA1 and the portion located in the second display area AA2 are disposed on the same layer.

[0077] In some optional embodiments, the display panel 100 provided by the present invention has an insulating layer 40 formed between the device layer and the shielding layer 30. The insulating layer 40 includes an inorganic layer. By providing an insulating layer 40 between the device layer and the shielding layer 30, the safety performance of the device layer can be guaranteed. At the same time, by making the insulating layer 40 include an inorganic layer, the light transmittance of the insulating layer 40 can be improved, ensuring the transparency requirements of the second display area AA2.

[0078] As an optional implementation, the display panel 100 provided in this embodiment of the invention includes an inorganic layer comprising at least one of silicon oxide and silicon nitride. The inorganic layer may consist only of silicon oxide, or only of silicon nitride, or both silicon oxide and silicon nitride, to ensure the transparency requirements of the second display area AA2.

[0079] In some optional embodiments, the display panel 100 provided in this embodiment of the invention further includes a signal line 13 in the device layer, and a via is provided on the insulating layer 40. The signal line 13 is exposed in the via, and the shielding layer 30 is electrically connected to the signal line 13 through the via so that the shielding layer 30 can obtain a fixed potential.

[0080] As an optional implementation, the display panel 100 provided in this embodiment of the invention includes signal lines 13, which include either a DC power signal line or a reference voltage signal line. This configuration ensures that the shielding layer 30 has a fixed potential while allowing connection to existing signal lines on the display panel 100, reducing the impact on the structure and molding process of the display panel 100 and guaranteeing its performance requirements.

[0081] Optionally, an insulating layer 40 may also be included between the shielding layer 30 and the light-emitting layer 20. The insulating layer 40 has good light transmittance and can ensure the safe formation and molding requirements of the light-emitting layer 30.

[0082] As an optional implementation, the display panel 100 provided in this embodiment of the invention has a non-metallic shielding layer 30. By adopting a non-metallic shielding layer 30, the transparency of the shielding layer 30 can be improved, ensuring the transparency requirements of the second display area AA2 while meeting the shielding requirements of the shielding layer 30.

[0083] In some alternative embodiments, the shielding layer 30 may include one of indium tin oxide and indium zinc oxide, which can ensure both conductivity and transparency requirements.

[0084] like Figure 7 as well as Figure 8 As shown, in another aspect, embodiments of the present invention also provide a display device. As an optional implementation, embodiments of the present invention also provide a display device including the display panel 100 of any of the above embodiments. The display panel 100 includes a first surface S1 and a second surface S2 facing each other, wherein the first surface S1 is a display surface. The display device further includes a photosensitive component 200, which is located on the second surface S2 side of the display panel 100. Optionally, the photosensitive component 200 corresponds to the position of the transparent display area AA2a in the second display area AA1.

[0085] The photosensitive component 200 can be an image acquisition device used to acquire external image information. In this embodiment, the photosensitive component 200 can be a complementary metal-oxide-semiconductor (CMOS) image acquisition device. In other embodiments, the photosensitive component 200 can also be a charge-coupled device (CCD) image acquisition device or other forms of image acquisition device. It is understood that the photosensitive component 200 is not limited to an image acquisition device. For example, in some embodiments, the photosensitive component 200 can also be a light sensor such as an infrared sensor, a proximity sensor, an infrared lens, a flood illuminator, an ambient light sensor, and a dot projector. In addition, the display device can also integrate other components, such as a handset and a speaker, on the second surface of the display panel 100.

[0086] The display device provided in this embodiment includes the display panel 100 provided in the above embodiments. Since the light transmittance of the second display area AA2 is greater than that of the first display area AA1, the photosensitive component 200 can be disposed on the back side of the second display area AA2, which can achieve full-screen display and ensure the light-sensing requirements of the photosensitive component 200. Furthermore, the first display area AA1 of the display panel 100 is the area used for normal display. The orthographic projection of the first gate electrode 111 and the first electrode 211 in the thickness direction X of the device layer will at least partially overlap to form a first overlapping area 50. By setting a shielding layer 30 between the layer structure where the first gate electrode 111 is located and the layer structure where the first electrode 211 is located, and the shielding layer 30 is connected to a fixed potential and its orthographic projection in the thickness direction X at least covers the first overlapping area 50, the formation of parasitic capacitance between the first electrode 211 and the first gate electrode 111 can be reduced or avoided, thereby reducing the brightness difference between the first display area AA1 and the second display area AA2, resulting in good uniformity and ensuring display effect.

[0087] Although the invention has been described with reference to preferred embodiments, various modifications can be made and components can be replaced with equivalents without departing from the scope of the invention. In particular, the technical features mentioned in the various embodiments can be combined in any manner as long as there is no structural conflict. The invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A display panel, characterized by, The display panel includes a second display area and a first display area disposed at least partially surrounding the second display area, wherein the light transmittance of the second display area is greater than that of the first display area. The device layer includes a first transistor located in the first display area and a second transistor located in the second display area, wherein the first transistor includes a first gate electrode and the second transistor includes a second gate electrode; A light-emitting layer is stacked on one side of the device layer in its thickness direction. The light-emitting layer includes a plurality of first sub-pixels distributed in a first display area and a plurality of second sub-pixels distributed in a second display area. The first sub-pixels include a first electrode electrically connected to the first transistor, and the second sub-pixels include a second electrode electrically connected to the second transistor. In the thickness direction, the orthographic projection of the first electrode at least partially overlaps with the orthographic projection of the first gate electrode to form a first overlapping area. The shielding layer is connected to a fixed potential. The second display area includes a transparent display area and a transition display area located between the transparent display area and the first display area. The second electrode located in the transparent display area is electrically connected to the second transistor located in the transition display area through an electrode trace. In the thickness direction, the orthographic projection of the electrode trace overlaps with the orthographic projection of the second electrode to form a third overlapping area. The shielding layer includes a first portion located in the first display area and a second portion located in the transition display area. The first portion is disposed between the layer structure where the first gate electrode is located and the layer structure where the first electrode is located, and its orthographic projection in the thickness direction at least covers the first overlapping area. The second portion is located between the electrode trace and the second electrode and covers the third overlapping area.

2. The display panel according to claim 1, characterized in that, The shielding layer includes arrayed shielding units, each shielding unit covering at least one of the first overlapping regions formed by the first electrode and the first gate electrode.

3. The display panel according to claim 2, characterized in that, At least three of the shielding units are interconnected and connected to the same potential.

4. The display panel according to claim 2, characterized in that, The shielding unit is strip-shaped.

5. The display panel according to claim 1, characterized in that, In the thickness direction, the second electrode and the second gate electrode are offset from each other by their orthogonal projections, and the shielding layer is located in the first display area.

6. The display panel according to claim 1, characterized in that, The light transmittance of the first display area is less than that of the transparent display area. Each of the second transistors is disposed in the transition display area, and each of the second transistors is electrically connected to at least one of the second sub-pixels.

7. The display panel according to claim 6, characterized in that, In the thickness direction, the orthographic projection of the second electrode overlaps with the orthographic projection of the second gate electrode to form a second overlapping region, and the shielding layer is located between the second electrode and the second gate electrode and covers the second overlapping region.

8. The display panel according to claim 1, characterized in that, An insulating layer is formed between the device layer and the shielding layer, and the insulating layer includes an inorganic layer.

9. The display panel according to claim 8, characterized in that, The inorganic layer includes at least one of silicon oxide and silicon nitride.

10. The display panel according to claim 8, characterized in that, The device layer also includes signal lines, and the insulating layer has vias, through which the signal lines are exposed, and the shielding layer is electrically connected to the signal lines through the vias.

11. The display panel according to claim 10, characterized in that, The signal line includes either a DC power supply signal line or a reference voltage signal line.

12. The display panel according to claim 8, characterized in that, The shielding layer is a non-metallic layer structure.

13. The display panel according to claim 8, characterized in that, The shielding layer comprises one of indium tin oxide and indium zinc oxide.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

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