Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device, the display substrate has a display area and a cathode ring area surrounding the display area, wherein the display substrate comprises: a substrate; a light emitting device disposed on the substrate and located in the display area; the light emitting device comprises, in sequence from the direction away from the substrate: a first electrode, a light emitting layer and a second electrode; a power supply electrode embedded on the substrate and located in the cathode ring area; an insulating layer disposed on the substrate, the insulating layer is provided with a first via hole exposing the power supply electrode, and the first via hole is provided with a first conductive column; a connecting electrode located on the side of the insulating layer away from the substrate, the connecting electrode is in contact with the first conductive column and connected with the second electrode.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically to a display substrate and a display device. Background Technology

[0002] Micro-OLEDs (Micro-Organic Light-Emitting Diodes) are microdisplays that have emerged in recent years, with silicon-based OLEDs being one type. Silicon-based OLEDs are fabricated using mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology, offering advantages such as small size, high resolution (PPI), and high refresh rate. They are widely used in near-eye displays for virtual reality (VR) and augmented reality (AR). Summary of the Invention

[0003] This disclosure provides a display substrate having a display area and a cathode ring region surrounding the display area, wherein the display substrate includes:

[0004] Substrate;

[0005] A light-emitting device is disposed on the substrate and located in the display area; the light-emitting device includes a first electrode, a light-emitting layer and a second electrode arranged sequentially in a direction away from the substrate.

[0006] The power supply electrode is embedded on the substrate and located in the cathode ring region;

[0007] An insulating layer is disposed on the substrate, and a first via is disposed on the insulating layer to expose the power supply electrode, and a first conductive post is disposed in the first via;

[0008] A connecting electrode is located on the side of the insulating layer away from the substrate. The connecting electrode is in contact with the first conductive post and connected to the second electrode.

[0009] In some embodiments, the end of the first conductive post away from the power supply electrode extends beyond the surface of the insulating layer away from the power supply electrode, and the extended portion has a first height;

[0010] The thickness of the connecting electrode is greater than the first height.

[0011] In some embodiments, the first height is less than or equal to The thickness of the connecting electrode is greater than or equal to

[0012] In some embodiments, the end of the first conductive post away from the power supply electrode is not higher than the surface of the insulating layer away from the power supply electrode.

[0013] In some embodiments, the connecting electrode is integrally connected to the second electrode, and the material of the connecting electrode includes a transparent conductive material.

[0014] In some embodiments, the material of the first conductive post includes tungsten.

[0015] In some embodiments, the display substrate further includes: a pixel defining layer disposed on the substrate and located within the display area; the pixel defining layer has a pixel opening that exposes the surface of the first electrode, and the light-emitting layer is located in the pixel opening.

[0016] In some embodiments, the cathode ring region includes a plurality of nested sub-ring regions, each of which is provided with the power supply electrode, and a gap region is provided between two adjacent sub-ring regions;

[0017] In the interval region, the connecting electrode is in contact with the insulating layer.

[0018] In some embodiments, the insulating layer is provided with a plurality of first vias corresponding to the position of each of the power supply electrodes.

[0019] In some embodiments, the display substrate further includes a transistor embedded in the substrate, the first electrode is electrically connected to the transistor, and the power supply electrode is disposed on the same layer as the source and drain of the transistor.

[0020] In some embodiments, a second via is further provided on the insulating layer, the second via exposing the drain of the transistor, and a second conductive post is provided in the second via, through which the first electrode is connected to the drain of the transistor.

[0021] This disclosure also provides a display device, which includes the display substrate described above. Attached Figure Description

[0022] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0023] Figure 1 This is a plan view of a display substrate provided in one embodiment.

[0024] Figure 2 This is a schematic diagram of the display area of ​​a display substrate provided in one embodiment.

[0025] Figure 3 for Figure 1 A schematic diagram of the structure of the display substrate in the cathode ring region.

[0026] Figure 4 This is a schematic diagram showing the regional distribution of the display substrate provided in some embodiments of this disclosure.

[0027] Figure 5 This is a schematic diagram of the structure of a display substrate provided in some embodiments of this disclosure.

[0028] Figure 6 This is a schematic diagram of the first electrode in some embodiments of this disclosure.

[0029] Figure 7 This is a schematic diagram of a circuit principle provided in some embodiments of this disclosure.

[0030] Figure 8 The diagram shows the circuit implementation of the voltage control circuit and pixel driving circuit provided in some embodiments of this disclosure. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0032] The terminology used herein to describe embodiments of this disclosure is not intended to limit and / or restrict the scope of this disclosure. For example, unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense as would be understood by one of ordinary skill in the art to which this disclosure pertains. It should be understood that the terms “first,” “second,” and similar words used herein do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Unless the context clearly indicates otherwise, the singular forms “a,” “one,” or “the,” and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or similar words mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, but do not exclude other elements or objects. “Above,” “below,” “left,” “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0033] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, the embodiments of this disclosure are not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions.

[0034] Figure 1 This is a plan view of a display substrate provided in one embodiment, such as... Figure 1 As shown, the display substrate has a display area AA and a peripheral area surrounding the display area AA. The peripheral area may include: a dummy pixel area PADA, a cathode ring area EA, and a bonding area BA. The cathode ring area EA surrounds the display area AA, and the bonding area BA is located on one side of the display area AA. Multiple bonding electrodes PAD are disposed in the bonding area BA.

[0035] in, Figure 2 This is a schematic diagram of the display area of ​​a display substrate provided in one embodiment, such as... Figure 2 As shown, the display area AA includes multiple pixel areas PA. The display substrate includes a substrate 10 and a pixel driving circuit and a light-emitting device 20 disposed on the substrate 10. Each pixel area PA is provided with a pixel driving circuit and a light-emitting device 20. The pixel driving circuit is embedded in the substrate 10 and includes at least multiple transistors M. The light-emitting device 20 is disposed on the substrate 10 and includes a first electrode 21, a light-emitting layer 23, and a second electrode 22 arranged sequentially in a direction away from the substrate 10. The first electrode 21 is connected to the pixel driving circuit, and the second electrodes 22 of multiple light-emitting devices 20 can be connected into a single structure.

[0036] The display substrate also includes a pixel defining layer (PDL) and an insulating layer (30) disposed on the substrate 10. A second via is disposed on the insulating layer 30 corresponding to the position of the pixel driving circuit, and a second conductive post (32) is disposed within the second via. The first electrode 21 is connected to the pixel driving circuit through the second conductive post (32). The pixel defining layer (PDL) is located on the side of the insulating layer 30 away from the substrate 10. A first portion of the pixel defining layer (PDL) is located in the spacing region between the first electrodes 21, and a second portion is located on the side of the first electrodes 21 away from the substrate 10. Multiple pixel openings are formed on the pixel defining layer (PDL), with each pixel region (PA) corresponding to one pixel opening. The pixel openings expose the first electrode 21. The light-emitting layer (23) is located within the pixel openings.

[0037] Figure 3 for Figure 1 A schematic diagram of the display substrate in the cathode ring region is shown below. Figure 3As shown, the display substrate includes a power supply electrode 44 located in the cathode ring region EA, which is embedded in the substrate 10. The insulating layer 30 extends from the display region AA to the cathode ring region EA. A first via is provided on the insulating layer 30, exposing the power supply electrode 44, and a first conductive post 31 is provided in the first via. In addition, a first conductive electrode 41 and a second conductive electrode 42 are also provided in the cathode ring region EA. The first conductive electrode 41 is fabricated synchronously with the first electrode 21 of the light-emitting device 20, and the second conductive electrode 42 can be fabricated synchronously with the second electrode 22 of the light-emitting device 20, and the first conductive electrode 41 and the second conductive electrode 42 are in contact. Through the first conductive post, the first conductive electrode 41 and the second conductive electrode 42, the electrical signal on the power supply electrode 44 can be transmitted to the second electrode 22 of each light-emitting device 20.

[0038] like Figure 3 As shown, a filling layer 43 is also provided in the cathode ring region EA. At least a portion of the filling layer 43 is located in the gap region between the first conductive electrodes 41 to prevent the subsequently formed second conductive electrode 42 from breaking at the gap position between the first conductive electrodes 41. The filling layer 43 can be fabricated simultaneously with the pixel defining layer PDL.

[0039] In this design, the light-emitting device 20 is a top-emitting structure, and the first electrode 21 is a reflective electrode comprising multiple stacked sub-electrode layers. The first conductive electrode 41 has the same structure and material as the first electrode 21. For example, the multiple sub-electrode layers may include a titanium metal layer, an aluminum metal layer, another titanium metal layer, and an indium tin oxide (ITO) layer sequentially disposed. However, due to limitations in the process conditions, voids may appear on the deposited sub-electrode layers, and peeling may occur between the sub-electrode layers, leading to problems such as increased impedance and poor contact between the second conductive electrode 42 and the first conductive electrode 41. Furthermore, when fabricating the filling layer 43 using photolithography, etching residue is easily encountered, which can also lead to poor contact between the second conductive electrode 42 and the first conductive electrode 41, thus affecting product quality.

[0040] Figure 4 This is a schematic diagram showing the area distribution of the display substrate provided in some embodiments of this disclosure. Figure 5 This is a schematic diagram of the structure of a display substrate provided in some embodiments of this disclosure, such as... Figure 4 and Figure 5 As shown, the display substrate has a display area AA and a cathode ring area EA surrounding the display area AA. The display substrate includes: a substrate 10, a light-emitting device 20, a power supply electrode 44, an insulating layer 30, and a connecting electrode 45.

[0041] The substrate 10 is a silicon-based substrate. A light-emitting device 20 is disposed on the substrate 10 and located in the display area AA. The light-emitting device 20 may include, in a direction away from the substrate 10, a first electrode 21, a light-emitting layer 23, and a second electrode 22, arranged sequentially. The light-emitting layer 23 of each light-emitting device 20 can individually emit red, blue, or green light.

[0042] In some embodiments, the light-emitting device 20 adopts a top-emitting structure, the first electrode 21 is a reflective electrode, and the second electrode 22 is a transmissive electrode. Optionally... Figure 6 This is a schematic diagram of the first electrode in some embodiments of this disclosure, such as... Figure 5 and Figure 6 As shown, the first electrode 21 may include a first titanium metal layer 21a, an aluminum metal layer 21b, a second titanium metal layer 21c, and a transparent conductive layer 21d arranged sequentially along a direction away from the substrate 10. The first titanium metal layer 21a and the second titanium metal layer 21c can protect the aluminum metal layer 21b, and the transparent conductive layer 21d can be an indium tin oxide layer, which can play a role in hole injection.

[0043] The thickness of the first titanium metal layer 21a can be... Between, the thickness of aluminum metal layer 21b can be Between; the thickness of the second titanium metal layer 21c can be between; Between, the thickness of the transparent conductive layer 21d can be between.

[0044] In some embodiments, the first electrode 21 is the anode, the second electrode 22 is the cathode, and the second electrodes 22 of the plurality of light-emitting devices 20 can be connected as one unit. The light-emitting device 20 may also include a hole transport layer located between the first electrode 21 and the light-emitting layer 23, and an electron transport layer located between the light-emitting layer 23 and the second electrode 22.

[0045] like Figure 4 As shown, the power supply electrode 44 is embedded on the substrate 10 and located in the cathode ring region EA. The number of power supply electrodes 44 can be one or more.

[0046] An insulating layer 30 is disposed on the substrate 10. A first via is disposed on the insulating layer 30 corresponding to the position of each power supply electrode 44. The first via exposes the power supply electrode 44, and a first conductive post 31 is disposed within the first via. Optionally, the material of the insulating layer 30 may include one or more of silicon oxide (SiOx), silicon nitride (SiNx), and oxide nitride (SiON). The insulating layer 30 may be a single-layer structure or a multi-layer structure. It should be noted that, in this embodiment, a via exposing a structure means that the orthographic projection of the via on the substrate 10 overlaps with the orthographic projection of the structure on the substrate 10, thereby exposing at least a portion of the structure. It should also be noted that the first conductive post 31 disposed within the first via means that at least a portion of the first conductive post 31 is located within the first via.

[0047] The connecting electrode 45 is located on the side of the insulating layer 30 away from the substrate 10. The connecting electrode 45 is in direct contact with the first conductive post 31 and is connected to the second electrode 22 of each light-emitting device 20.

[0048] and Figure 3 Compared to the display substrate shown, Figure 5 In the display substrate shown, the connecting electrode 45 is in direct contact with the first conductive post 31, eliminating the need for a separate first conductive electrode 41. This prevents poor contact between the connecting electrode 45 and the first conductive post 31 due to defects such as holes or film separation in the first conductive electrode 41, thus improving the quality of the display substrate. Furthermore, since the first conductive electrode 41 is no longer present, the issues of increased resistance and voltage drop caused by it are avoided, which is beneficial for improving the display effect.

[0049] like Figure 4 As shown, the cathode ring region EA may include multiple nested sub-ring regions EA1, each sub-ring region EA1 having a power supply electrode 44. Each power supply electrode 44 can be a closed or semi-closed ring structure. A gap is provided between adjacent sub-ring regions EA1. The insulating layer 30 has multiple first vias corresponding to the position of each power supply electrode 44, and each first via contains a first conductive post 31. This ensures that each power supply electrode 44 is connected to the connecting electrode 45 through multiple first conductive posts 31, guaranteeing the electrical connection between the connecting electrode 45 and the power supply electrode 44. The multiple first vias corresponding to each power supply electrode 44 are evenly distributed, for example, arranged in multiple rows and columns, to ensure a more uniform current distribution on the connecting electrode 45.

[0050] In some embodiments, the material of the first conductive post 31 may include tungsten. Using tungsten metal can ensure the stability of the conductive path.

[0051] In some embodiments, the end of the first conductive post 31 away from the power supply electrode 44 (i.e., the top of the first conductive post 31) is not higher than the surface of the insulating layer 30 away from the power supply electrode 44 (i.e., the upper surface of the insulating layer 30). That is, the first conductive post 31 is entirely located in the first via, and the top of the first conductive post 31 is flush with the upper surface of the insulating layer 30, or the top of the first conductive post 31 is lower than the upper surface of the insulating layer 30.

[0052] In other embodiments, to ensure the reliability of the connection between the connecting electrode 45 and the first conductive post 31, such as... Figure 5 As shown, the top of the first conductive post 31 extends beyond the upper surface of the insulating layer 30, and the extended portion has a first height. Furthermore, the thickness of the connecting electrode 45 is greater than the first height to ensure the continuity of the connecting electrode 45.

[0053] In the fabrication process of the display substrate, a first via can be formed on the insulating layer 30, and then a first conductive post 31 can be formed within the first via. Afterwards, the first conductive post 31 and the insulating layer 30 are polished using a chemical mechanical polishing (CMP) process. Since the polishing rate varies for different materials, the polishing time can be controlled so that the top of the first conductive post 31 is flush with or slightly extends beyond the upper surface of the insulating layer 30. For example, the height of the extended portion (i.e., the aforementioned first height) is less than or equal to... For example, the first height is or or or or or

[0054] The connecting electrode 45 and the second electrode 22 of each light-emitting device 20 can be integrated. The connecting electrode 45 and the second electrode 22 can be made of magnesium-silver alloy. In this case, to ensure the light emission effect of the light-emitting device 20, the thickness of the connecting electrode 45 and the second electrode 22 needs to be relatively small. However, considering that the top of the first conductive post 31 extends beyond the upper surface of the insulating layer 30, if the thickness of the connecting electrode 45 is too small, it may break at the location of the first conductive post 31. Therefore, to ensure the continuity of the connecting electrode 45, in some embodiments, the thickness of the connecting electrode 45 is greater than or equal to... The connecting electrode 45 can be integrated with the second electrode 22 of the light-emitting device 20. In this case, the connecting electrode 45 and the second electrode 22 have the same material and thickness. For example, the thickness of the connecting electrode 45 is... The thickness of the connecting electrode 45 is such that, while ensuring the continuity of the connecting electrode 45, the light emission effect of the light-emitting device 20 can be guaranteed. For example, the thickness of the connecting electrode 45 is within a certain range. Between, or in Between, or in between.

[0055] When the thickness of connecting electrode 45 and the second electrode 22 is greater than or equal to To ensure the light emission effect of the light-emitting device 20, the connecting electrode 45 and the second electrode 22 can be made of a transparent conductive material, such as indium zinc oxide (IZO), indium tin oxide (ITO), or other transparent conductive materials. The connecting electrode 45 and the second electrode 22 can be formed using a sputtering process.

[0056] Figure 7 This is a schematic diagram of a circuit principle provided in some embodiments of this disclosure, such as... Figure 7 As shown, multiple pixel areas PA in the display area AA are arranged in multiple rows and columns. Each pixel area PA is provided with a pixel driving circuit and a light-emitting device 20 electrically connected to the pixel driving circuit. The pixel driving circuit includes multiple transistors, and the multiple transistors include at least a driving transistor. The control circuit includes at least multiple voltage control circuits 110, and each voltage control circuit 110 is connected to multiple pixel driving circuits 101. For example, one voltage control circuit 110 is connected to a row of pixel driving circuits 101. The first terminals of the driving transistors in the row of pixel driving circuits 101 are all connected to the voltage control circuit 110. The second terminal of each driving transistor is connected to the anode of the light-emitting device 20 of this display unit, and the cathode of the light-emitting device 20 is connected to the input terminal of the second power supply signal VSS. The voltage control circuit 110 is connected to the input terminal of the first power supply signal VDD, the input terminal of the initialization signal Vinit, the input terminal of the reset control signal RE, and the input terminal of the light emission control signal EM. The voltage control circuit 110 is configured to output the initialization signal Vinit to the first terminal of the driving transistor in response to the reset control signal RE, thereby controlling the corresponding light-emitting device 20 to reset. The voltage control circuit 110 is also configured to output a first power supply signal VDD to the first terminal of the driving transistor in response to the light emission control signal EM, thereby driving the light-emitting device 20 to emit light. By connecting the voltage control circuit 110 to the pixel driving circuit 101 in a display row, the structure of the pixel driving circuit 101 in the display area AA can be simplified, reducing the area occupied by the pixel driving circuit 101 in the display area AA. This allows for more pixel driving circuits 101 and light-emitting devices 20 to be set in the display area AA, achieving a high PPI display. Under the control of the reset control signal RE, the voltage control circuit 110 outputs an initialization signal Vinit to the first terminal of the driving transistor, controlling the corresponding light-emitting device 20 to reset. This avoids the influence of the voltage applied to the light-emitting device 20 during the previous frame's illumination on the illumination of the next frame, thus improving the ghosting phenomenon.

[0057] In an exemplary embodiment, three pixel areas PA of different colors constitute one pixel unit. The three pixel areas PA can be a red pixel area PA, a green pixel area PA, and a blue pixel area PA, respectively. In some examples, a voltage control circuit 110 can be connected to the pixel driving circuits 101 in two adjacent display units in the same row, or it can be connected to the pixel driving circuits 101 in three or more pixel areas PA in the same row, without limitation.

[0058] Figure 8 These are schematic diagrams illustrating the circuit implementation of the voltage control circuit and pixel driving circuit provided in some embodiments of this disclosure. For example... Figure 8 As shown, the first electrode 21 of the light-emitting device 20 is connected to the second electrode D of the driving transistor M0, and the second electrode 22 of the light-emitting device 20 is connected to the input terminal of the second power supply signal VSS. The voltage of the second power supply signal VSS is generally a negative voltage or a ground voltage, and the voltage of the initialization signal Vinit can also be set to a ground voltage. In some examples, the light-emitting device 20 may include an OLED (Organic Light-Emitting Diode), which can be a Micro-OLED or a Mini-OLED, which is beneficial for achieving high PPI displays.

[0059] In some examples, the voltage control circuit 110 is connected to two pixel driving circuits 101 in a row. Each pixel driving circuit 101 includes a driving transistor M0, a third transistor M3, a fourth transistor M4, and a storage capacitor Cst. The voltage control circuit 110 includes a first transistor M1 and a second transistor M2. The driving transistors M0, M1, M2, M3, and M4 are all metal-oxide-semiconductor (MOS) field-effect transistors fabricated on a silicon substrate. The gate of the first transistor M1 is connected to the input of the reset control signal RE, and its first terminal is connected to the input of the initialization signal Vinit, also for receiving the initialization signal Vinit. The second terminal of the first transistor M1 is connected to the first terminal S of the corresponding driving transistor M0 and the second terminal of the corresponding driving transistor M2. The gate of the second transistor M2 is connected to the input terminal of the light emission control signal EM, and is used to receive the light emission control signal EM. The first terminal of the second transistor M2 is connected to the input terminal of the first power supply signal VDD, and is used to receive the first power supply signal VDD. The second terminal of the second transistor M2 is connected to the first terminal S of the corresponding driving transistor M0 and the second terminal of the first transistor M1, respectively. In some examples, the first transistor M1 and the second transistor M2 may be of different types. For example, the first transistor M1 may be an N-type transistor and the second transistor M2 may be a P-type transistor, or the first transistor M1 may be a P-type transistor and the second transistor M2 may be an N-type transistor. In some possible implementations, the first transistor M1 and the second transistor M2 may be of the same type, which can be designed and determined according to the actual application environment, and is not limited here.

[0060] The pixel driving circuit 101 includes a driving transistor M0, a third transistor M3, a fourth transistor M4, and a storage capacitor Cst. The gate G of the driving transistor M0 and the first terminal S of the driving transistor M0 are connected to the second terminals of the first transistor M1 and the second transistor M2. The second terminal D of the driving transistor M0 is connected to the first electrode 21 of the light-emitting device 20. The gate of the third transistor M3 is connected to the input terminal of the first scan signal S1, for receiving the first scan signal S1. The first terminal of the third transistor M3 is connected to the input terminal of the data signal DA, for receiving the data signal DA. The second terminal of the third transistor M3 is connected to the gate G of the driving transistor M0. The gate of the fourth transistor M4 is connected to the input terminal of the second scan signal S2, for receiving the second scan signal S2. The first terminal of the fourth transistor M4 is connected to the input terminal of the data signal DA, for receiving the data signal DA. The second terminal of the fourth transistor M4 is connected to the gate G of the driving transistor M0. The first terminal of the storage capacitor Cst is connected to the gate G of the driving transistor M0, and the second terminal of the storage capacitor Cst is connected to the ground terminal GND.

[0061] Figure 5 The diagram only shows the driving transistor M0 in the pixel driving circuit. Taking the driving transistor as an example, the driving transistor M0 includes an active layer A, a gate G, a source S, a drain D, and a gate connection electrode G0. The active layer A of the driving transistor M0 can be formed on the silicon substrate by a doping process. The active layer A includes a source contact region A1, a drain contact region A2, and a channel region A0 located between the two. The source S is connected to the source contact region A1 through a corresponding conductive post 50, the drain D is connected to the drain contact region A2 through a corresponding conductive post 50, and the gate connection electrode G0 is connected to the gate G through a corresponding conductive post 50.

[0062] An insulating layer 30 is disposed on the substrate 10. A second via is disposed on the insulating layer 30 corresponding to the position of each driving transistor M0. The second via exposes the drain D of the driving transistor M0. A second conductive post 32 is disposed in the second via. The second conductive post 32 is a tungsten rod. The light-emitting device 20 is disposed on the side of the insulating layer 30 away from the substrate 10. The first electrode 21 of the light-emitting device 20 is connected to the drain D of the driving transistor M0 through the second conductive post 32.

[0063] like Figure 5 As shown, the display substrate further includes a pixel defining layer (PDL). The PDL can be made of inorganic materials, such as silicon oxide, silicon nitride, or oxynitride; or it can be made of organic materials, such as polyimide, acrylic, or polyethylene terephthalate. The PDL is disposed on the side of the insulating layer 30 away from the substrate 10 and is located within the display area AA. Pixel openings are formed on the PDL, exposing the surface of the first electrode 21. The light-emitting layer 23 of the light-emitting device 20 is located within the pixel openings.

[0064] In this embodiment, the orthographic projection of the pixel defining layer PDL onto the substrate 10 does not overlap with the orthographic projection of the cathode ring region EA onto the substrate 10. In the gap between adjacent sub-ring regions, the connecting electrode 45 is in direct contact with the insulating layer 30. That is, when forming the pixel defining layer PDL, an insulating material for fabricating the PDL is first formed on the substrate 10. Then, a pixel opening is formed on this insulating material using a photolithography patterning process, and all the insulating material of the cathode ring region EA is removed, leaving no residue. Figure 3 The filling portion 43 in the middle, that is, during the etching process of the insulating material, the etching area increases, which helps to reduce etching residue and thus improves the connection reliability between the connecting electrode 45 and the first conductive post 31.

[0065] In addition, since the connecting electrode 45 is connected to the top of the multiple first conductive pillars 31, and the top of the first conductive pillars 31 extends beyond the upper surface of the insulating layer 30, even if there is a small amount of insulating material residue during the preparation process, these residues will not cover the end face of the top of the first conductive pillars 31, thereby ensuring the reliability of the connection between the connecting electrode 45 and the first conductive pillars 31.

[0066] like Figure 4 As shown, the display substrate also has a bonding area BA and a metal trace area LA. The bonding area BA is located on one side of the display area AA, and the metal trace area LA is located between the bonding area BA and the cathode ring area EA. The display substrate also includes: a bonding electrode PAD located in the bonding area BA and metal traces located in the metal trace area LA, such as... Figure 5 As shown, the bonding electrode PAD and the metal trace are both embedded in the substrate 10. A third via V3 corresponding to the bonding electrode PAD is formed on the insulating layer 30, and the third via V3 exposes the bonding electrode PAD. The bonding electrode PAD, the metal trace, and the power supply electrode 44 can all be disposed on the same layer as the source S and drain D of the driving transistor M0.

[0067] In some embodiments, the display substrate may further include an encapsulation layer (not shown) covering the display area AA, the cathode ring area EA, and the metal trace area LA. The encapsulation layer may be a thin-film encapsulation structure.

[0068] In some embodiments, the display substrate may further include a cover plate (not shown), which is located on the side of the encapsulation layer away from the substrate 10, and is fixed to the substrate 10 on which the encapsulation layer is disposed by a sealant. The encapsulation layer, sealant, and cover plate may not cover the bonding area BA.

[0069] This disclosure also provides a display device, including the aforementioned display substrate. The display device can be a virtual reality device, an augmented reality device, or a near-eye display device, or it can be a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, or any other product or component with display function.

[0070] In the display substrate provided in this disclosure, the connecting electrode 45 is in direct contact with the first conductive post 31, and there is no need to provide the first conductive electrode 41. This avoids the situation where the connecting electrode 45 and the first conductive post 31 are in poor contact due to defects such as holes or film separation of the first conductive electrode 41, thereby improving the quality of the display substrate and thus improving the quality of the display device.

[0071] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate having a display area and a cathode ring region surrounding the display area, wherein, The display substrate includes: Substrate; A light-emitting device is disposed on the substrate and located in the display area; the light-emitting device includes a first electrode, a light-emitting layer and a second electrode arranged sequentially along a direction away from the substrate. The power supply electrode is embedded on the substrate and located in the cathode ring region; An insulating layer is disposed on the substrate, and a first via is disposed on the insulating layer to expose the power supply electrode, and a first conductive post is disposed in the first via; A connecting electrode is located on the side of the insulating layer away from the substrate. The connecting electrode is in contact with the first conductive post and connected to the second electrode. A pixel defining layer is disposed on the substrate and located within the display area; the pixel defining layer has a pixel opening that exposes the surface of the first electrode, and the light-emitting layer is located in the pixel opening; Wherein, the orthographic projection of the pixel defining layer on the substrate does not overlap with the orthographic projection of the cathode ring region on the substrate; The connecting electrode is integrated with the second electrode, and the material of the connecting electrode includes a transparent conductive material; The cathode ring region includes a plurality of nested sub-ring regions, each of which is provided with the power supply electrode, and a gap region is provided between two adjacent sub-ring regions; wherein, in the gap region, the connecting electrode is in contact with the insulating layer.

2. The display substrate according to claim 1, wherein, The end of the first conductive post away from the power supply electrode extends beyond the surface of the insulating layer away from the power supply electrode, and the extended portion has a first height; The thickness of the connecting electrode is greater than the first height.

3. The display substrate according to claim 2, wherein, The first height is less than or equal to 300 Å, and the thickness of the connecting electrode is greater than or equal to 800 Å.

4. The display substrate according to claim 1, wherein, The end of the first conductive post away from the power supply electrode is not higher than the surface of the insulating layer away from the power supply electrode.

5. The display substrate according to any one of claims 1 to 4, wherein, The material of the first conductive post includes tungsten.

6. The display substrate according to any one of claims 1 to 4, wherein, The insulating layer is provided with a plurality of first vias corresponding to the position of each of the power supply electrodes.

7. The display substrate according to any one of claims 1 to 4, wherein, The display substrate also includes a transistor embedded in the substrate, the first electrode is electrically connected to the transistor, and the power supply electrode is disposed on the same layer as the source and drain of the transistor.

8. The display substrate according to claim 7, wherein, The insulating layer is further provided with a second via, which exposes the drain of the transistor. A second conductive post is provided in the second via, and the first electrode is connected to the drain of the transistor through the second conductive post.

9. A display device, wherein, The display substrate includes any one of claims 1 to 8.

Images