Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes sub-pixels and a scan driving circuit. The scan driving circuit includes a multi-stage shift register and multiple clock signal lines. The multi-stage shift register includes a first shift register and a second shift register, and the multiple clock signal lines include a first sub-clock signal line and a second sub-clock signal line. The shift register includes a first sub-circuit. The first sub-clock signal line is electrically connected to the first sub-circuit in the first shift register, and the first sub-clock signal line is located in a first gap region adjacent to the first sub-circuit in the first shift register. The second sub-clock signal line is electrically connected to one of the first sub-circuit and the second sub-circuit in the second shift register, and the second sub-clock signal line is located in a first gap region adjacent to the sub-circuit electrically connected in the second shift register. The first sub-clock signal line and the second sub-clock signal line transmit the same clock signal, but they are located in different first gap regions.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] The scan drive circuit is an important component of a display device. It may include multiple cascaded shift registers, each electrically connected to a line in the display device. The scan drive circuit can sequentially input scan signals to multiple lines (e.g., gate lines or enable signal lines) in the display device, enabling the display device to display an image.

[0003] Incorporating a scanning drive circuit into a display device can effectively reduce costs and improve yield. Summary of the Invention

[0004] On one hand, a display panel is provided. The display panel has a display area, and includes: a plurality of sub-pixels located in the display area; and a scan driving circuit. The plurality of sub-pixels are arranged in multiple rows along a first direction and in multiple columns along a second direction; the display area includes a first gap region located between two adjacent columns of sub-pixels. The scan driving circuit includes a multi-level shift register and a plurality of clock signal lines located in the display area. The multi-level shift register includes a first shift register and a second shift register, and the plurality of clock signal lines include a first sub-clock signal line and a second sub-clock signal line. The shift register includes: a first sub-circuit and a second sub-circuit. The first sub-clock signal line is electrically connected to the first sub-circuit in the first shift register, and the first sub-clock signal line is located in the first gap region adjacent to the first sub-circuit in the first shift register. The second sub-clock signal line is electrically connected to one of the first sub-circuit and the second sub-circuit in the second shift register, and the second sub-clock signal line is located in the first gap region adjacent to the sub-circuit electrically connected in the second shift register. The first sub-clock signal line and the second sub-clock signal line transmit the same clock signal, but they are located in different first gap regions.

[0005] In some embodiments, the second sub-clock signal line is electrically connected to the first sub-circuit in the second shift register, and the spacing between the second sub-clock signal line and the first sub-circuit in the second shift register is smaller than the spacing between the first sub-clock signal line and the first sub-circuit in the first shift register. Alternatively, the second sub-clock signal line is electrically connected to the second sub-circuit in the second shift register, and the spacing between the second sub-clock signal line and the second sub-circuit in the second shift register is smaller than the spacing between the second sub-clock signal line and the first sub-circuit in the first shift register, and vice versa.

[0006] In some embodiments, when the second sub-clock signal line is electrically connected to the first sub-circuit in the second shift register, the first sub-clock signal line is located away from both the first sub-circuit in the first shift register and the first sub-circuit in the second shift register relative to the second sub-clock signal line. When the second sub-clock signal line is electrically connected to the second sub-circuit in the second shift register, the first sub-clock signal line is located between the first sub-circuit in the first shift register and the second sub-circuit in the second shift register, and the second sub-clock signal line is located away from the first sub-clock signal line relative to the second sub-circuit in the second shift register.

[0007] In some embodiments, the plurality of clock signal lines further includes a third sub-clock signal line and a fourth sub-clock signal line. The third sub-clock signal line is electrically connected to a second sub-circuit in the first shift register, and is located within a first gap region adjacent to the second sub-circuit in the first shift register. The fourth sub-clock signal line is electrically connected to the other of the first and second sub-circuits in the second shift register, and is located within a first gap region adjacent to the electrically connected sub-circuit in the second shift register. The third and fourth sub-clock signal lines transmit the same clock signal, but are located in different first gap regions.

[0008] In some embodiments, the first gap region where either the third sub-clock signal line or the fourth sub-clock signal line is located is different from the first gap region where either the first sub-clock signal line or the second sub-clock signal line is located.

[0009] In some embodiments, when the second sub-clock signal line is electrically connected to the first sub-circuit in the second shift register, and the fourth sub-clock signal line is electrically connected to the second sub-circuit in the second shift register, the spacing between the fourth sub-clock signal line and the second sub-circuit in the second shift register is smaller than the spacing between the third sub-clock signal line and the second sub-circuit in the first shift register. Furthermore, when the second sub-clock signal line is electrically connected to the second sub-circuit in the second shift register, and the fourth sub-clock signal line is electrically connected to the first sub-circuit in the second shift register, the spacing between the third sub-clock signal line and the second sub-circuit in the first shift register is smaller than the spacing between the third sub-clock signal line and the first sub-circuit in the second shift register, and the spacing between the fourth sub-clock signal line and the second sub-circuit in the second shift register is smaller than the spacing between the fourth sub-clock signal line and the second sub-circuit in the first shift register.

[0010] In some embodiments, when the second sub-clock signal line is electrically connected to the first sub-circuit in the second shift register, the third sub-clock signal line is located away from the second sub-circuit in the first shift register and the second sub-circuit in the second shift register relative to the fourth sub-clock signal line. When the second sub-clock signal line is electrically connected to the second sub-circuit in the second shift register, the fourth sub-clock signal line is located between the second sub-circuit in the first shift register and the first sub-circuit in the second shift register, and the third sub-clock signal line is located away from the fourth sub-clock signal line relative to the second sub-circuit in the first shift register.

[0011] In some embodiments, a first-level shift register is electrically connected to a row of subpixels. There are multiple first shift registers and multiple second shift registers. Multiple first shift registers are electrically connected to odd-numbered row subpixels, and multiple second shift registers are electrically connected to even-numbered row subpixels.

[0012] In some embodiments, the scan driving circuit further includes: a first bus electrically connected to the first sub-clock signal line and the second sub-clock signal line; the first bus is configured to transmit corresponding clock signals to the first sub-clock signal line and the second sub-clock signal line. When the plurality of clock signal lines further include a third sub-clock signal line and a fourth sub-clock signal line, the scan driving circuit further includes: a second bus electrically connected to the third sub-clock signal line and the fourth sub-clock signal line; the second bus is configured to transmit corresponding clock signals to the third sub-clock signal line and the fourth sub-clock signal line.

[0013] In some embodiments, the display panel further includes a bezel area located beside the display area. Both the first bus and the second bus are located within the bezel area and extend along the first direction.

[0014] In some embodiments, the first sub-circuit is electrically connected to a first clock signal terminal, a pull-up node, a pull-down node, and a first voltage signal terminal. The first sub-circuit is configured to transmit the first clock signal to the pull-down node under the control of the first clock signal transmitted at the first clock signal terminal; and to control the voltage of the pull-down node under the control of the voltage of the pull-up node. The second sub-circuit is electrically connected to a second clock signal terminal, the pull-up node, and an output signal terminal. The second sub-circuit is configured to transmit the second clock signal received at the second clock signal terminal to the output signal terminal under the control of the voltage of the pull-up node. The first sub-clock signal line is electrically connected to the first sub-circuit in the first shift register via the first clock signal terminal. The second sub-clock signal line is electrically connected to the first sub-circuit in the second shift register via the first clock signal terminal; or, the second sub-clock signal line is electrically connected to the second sub-circuit in the second shift register via the second clock signal terminal. When the plurality of clock signal lines further include a third sub-clock signal line and a fourth sub-clock signal line, the third sub-clock signal line is electrically connected to the second sub-circuit in the first shift register through the second clock signal terminal; the fourth sub-clock signal line is electrically connected to the second sub-circuit in the second shift register through the second clock signal terminal; or, the fourth sub-clock signal line is electrically connected to the first sub-circuit in the second shift register through the first clock signal terminal.

[0015] In some embodiments, the first sub-circuit includes: a first transistor and a second transistor. The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first clock signal terminal, and the second electrode of the first transistor is electrically connected to the pull-down node. The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the pull-down node, and the second electrode of the second transistor is electrically connected to the first voltage signal terminal. The second sub-circuit includes: a third transistor and a first capacitor. The control electrode of the third transistor is electrically connected to the pull-up node, the first electrode of the third transistor is electrically connected to the second clock signal terminal, and the second electrode of the third transistor is electrically connected to the output signal terminal. The first electrode of the first capacitor is electrically connected to the pull-up node, and the second electrode of the first capacitor is electrically connected to the output signal terminal. The first sub-clock signal line is electrically connected to the first transistor in the first shift register. The second sub-clock signal line is electrically connected to the first transistor in the second shift register; or, the second sub-clock signal line is electrically connected to the third transistor in the second shift register. When the plurality of clock signal lines further include a third sub-clock signal line and a fourth sub-clock signal line, the third sub-clock signal line is electrically connected to the third transistor in the first shift register; the fourth sub-clock signal line is electrically connected to the third transistor in the second shift register; or, the fourth sub-clock signal line is electrically connected to the first transistor in the second shift register.

[0016] In some embodiments, the first transistor includes a plurality of first sub-transistors arranged in parallel. And / or, the third transistor includes a plurality of third sub-transistors arranged in parallel. There are multiple first sub-clock signal lines; one first sub-transistor in the first shift register is electrically connected to one first sub-clock signal line. When the second sub-clock signal line is electrically connected to a first sub-circuit in the second shift register, there are multiple second sub-clock signal lines; one first sub-transistor in the second shift register is electrically connected to one second sub-clock signal line. When the second sub-clock signal line is electrically connected to a second sub-circuit in the second shift register, there are multiple second sub-clock signal lines, and one third sub-transistor in the second shift register is electrically connected to one second sub-clock signal line.

[0017] In some embodiments, the first gap regions where the multiple first sub-clock signal lines are located are different. The first gap regions where the multiple second sub-clock signal lines are located are also different.

[0018] In some embodiments, the plurality of clock signal lines, the first and second terminals of the first transistor, the first and second terminals of the second transistor, and the first and second terminals of the third transistor are arranged on the same layer. When the scan drive circuit further includes a first bus and a second bus, the first bus, the second bus, the control terminals of the first transistor, the second transistor, the third transistor, and the first terminal of the first capacitor are arranged on the same layer.

[0019] In some embodiments, the display area further includes a second gap region located between any two adjacent rows of sub-pixels. The shift register is located within the second gap region.

[0020] In some embodiments, along the second direction, a shift register electrically connected to any two adjacent rows of sub-pixels is located in the second gap region between the two adjacent rows of sub-pixels.

[0021] In some embodiments, a sub-pixel includes a pixel driving circuit and a light-emitting device disposed along the second direction. In two adjacent rows of sub-pixels, the light-emitting device is closer to the two-stage shift registers relative to the pixel driving circuit.

[0022] In some embodiments, the shift register further includes: an input circuit electrically connected to an input signal terminal, a second voltage signal terminal, and the pull-up node; the input circuit is configured to transmit a second voltage signal received at the second voltage signal terminal to the pull-up node in response to an input signal received at the input signal terminal; a first reset circuit electrically connected to the pull-down node, the pull-up node, and the first voltage signal terminal; the first reset circuit is configured to reset the pull-up node under the control of the voltage of the pull-down node; a second reset circuit electrically connected to the output signal terminal, the pull-down node, and the first voltage signal terminal; the second reset circuit is configured to reset the pull-down node under the control of the output signal transmitted at the output signal terminal; and a third reset circuit electrically connected to the pull-down node, the output signal terminal, and the first voltage signal terminal; the third reset circuit is configured to reset the output signal terminal under the control of the voltage of the pull-down node. A fourth reset circuit is electrically connected to the display reset signal terminal, the pull-up node, and the third voltage signal terminal; the fourth reset circuit is configured to reset the pull-up node under the control of the display reset signal transmitted at the display reset signal terminal. A fifth reset circuit is electrically connected to the global reset signal terminal, the pull-up node, and the first voltage signal terminal; the fifth reset circuit is configured to reset the pull-up node under the control of the global reset signal transmitted at the global reset signal terminal.

[0023] In some embodiments, the input circuit includes: a fourth transistor. The control electrode of the fourth transistor is electrically connected to the input signal terminal, the first electrode of the fourth transistor is electrically connected to the second voltage signal terminal, and the second electrode of the fourth transistor is electrically connected to the pull-up node. The first reset circuit includes: a fifth transistor. The control electrode of the fifth transistor is electrically connected to the pull-down node, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first voltage signal terminal. The second reset circuit includes: a sixth transistor. The control electrode of the sixth transistor is electrically connected to the output signal terminal, the first electrode of the sixth transistor is electrically connected to the pull-down node, and the second electrode of the sixth transistor is electrically connected to the first voltage signal terminal. The third reset circuit includes: a seventh transistor and a second capacitor. The control electrode of the seventh transistor is electrically connected to the pull-down node, the first electrode of the seventh transistor is electrically connected to the output signal terminal, and the second electrode of the seventh transistor is electrically connected to the first voltage signal terminal. The first electrode of the second capacitor is electrically connected to the pull-down node, and the second electrode of the second capacitor is electrically connected to the first voltage signal terminal. The fourth reset circuit includes: an eighth transistor. The control electrode of the eighth transistor is electrically connected to the display reset signal terminal, the first electrode of the eighth transistor is electrically connected to the pull-up node, and the second electrode of the eighth transistor is electrically connected to the third voltage signal terminal. The fifth reset circuit includes a ninth transistor. The control electrode of the ninth transistor is electrically connected to the global reset signal terminal, the first electrode of the ninth transistor is electrically connected to the pull-up node, and the second electrode of the ninth transistor is electrically connected to the first voltage signal terminal.

[0024] On the other hand, a display device is provided. The display device includes a display panel as described in any of the above embodiments. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be considered as schematic diagrams and are not intended to limit the actual dimensions, etc., of the products involved in the embodiments of this disclosure.

[0026] Figure 1 This is a structural diagram of a display device according to some embodiments of the present disclosure;

[0027] Figure 2 Here is a circuit diagram of a shift register according to some embodiments of this disclosure;

[0028] Figure 3 This is a circuit diagram of another shift register according to some embodiments of the present disclosure;

[0029] Figure 4 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0030] Figure 5 This is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0031] Figure 6 This is a structural diagram of another display panel according to some embodiments of the present disclosure;

[0032] Figure 7 This is a structural diagram of yet another display panel according to some embodiments of the present disclosure;

[0033] Figure 8 This is a structural diagram of yet another display panel according to some embodiments of the present disclosure;

[0034] Figures 9a-9c Here is a circuit diagram of a scan drive circuit according to some embodiments of this disclosure;

[0035] Figure 10 This is a structural diagram of a scanning drive circuit according to some embodiments of the present disclosure;

[0036] Figures 11a-11b This is a structural diagram of a sub-pixel and a scan driving circuit according to some embodiments of the present disclosure;

[0037] Figure 12 This is a partial structural diagram of a display panel according to one implementation method. Detailed Implementation

[0038] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0039] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0040] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0041] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0042] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0043] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0044] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0045] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0046] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0047] As used herein, “about” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0048] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0049] The transistors used in the circuits provided in the embodiments of this disclosure can be thin-film transistors, field-effect transistors (e.g., oxide thin-film transistors) or other switching devices with the same characteristics. The embodiments of this disclosure are all described using thin-film transistors as an example.

[0050] In some embodiments, the control electrode of each transistor used in the shift register is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be structurally symmetrical, they can be structurally indistinguishable; that is, the first and second electrodes of the transistor in the embodiments of this disclosure can be structurally indistinguishable. For example, in the case of a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, in the case of an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0051] In the circuits provided in the embodiments of this disclosure, nodes such as pull-up nodes and pull-down nodes do not represent actual existing components, but rather represent the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram.

[0052] In embodiments of this disclosure, the term "pull-up" refers to charging a node or an electrode of a transistor to raise the absolute value of the voltage level of that node or electrode, thereby enabling the operation of the corresponding transistor (e.g., turning it on). The term "pull-down" refers to discharging a node or an electrode of a transistor to lower the absolute value of the voltage level of that node or electrode, thereby enabling the operation of the corresponding transistor (e.g., turning it off).

[0053] In the circuits provided in the embodiments of this disclosure, all transistors are N-type transistors, which will be used as an example for explanation.

[0054] Some embodiments of this disclosure provide a display panel 100 and a display device 1000, which are described below.

[0055] Some embodiments of this disclosure provide a display device 1000, such as Figure 1As shown. The display device 1000 can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0056] In some examples, the aforementioned display device 1000 includes a frame, a display panel 100 disposed within the frame, a circuit board, a display driver IC (Integrated Circuit), and other electronic components.

[0057] The aforementioned display panel 100 may be, for example, an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a micro light-emitting diode (Micro LED) display panel, or a mini light-emitting diode (Mini LED), etc., and this disclosure does not specifically limit it.

[0058] The following description uses the above-mentioned display panel 100 as an OLED display panel as an example to illustrate some embodiments of this disclosure.

[0059] In some examples, such as Figure 2 As shown, the display panel 100 has a display area A, and of course, the display panel may also have a border area B. The border area B may be located next to the display area A.

[0060] For example, the aforementioned "side" refers to one side, two sides, three sides, or the perimeter of display area A. That is, border area B can be located on one side, two sides, or three sides of display area A, or it can be located around the perimeter of display area A, surrounding display area A.

[0061] In some examples, such as Figures 5-8As shown, the display panel 100 may include: a substrate 1, a plurality of sub-pixels 2, and a scanning drive circuit 3.

[0062] The types of substrate 1 mentioned above include various types, and can be selected and set according to actual needs.

[0063] For example, substrate 1 can be a rigid substrate. The rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0064] For example, substrate 1 can be a flexible substrate. This flexible substrate can be, for example, a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate, or a PI (Polyimide) substrate. In this case, display panel 100 can be a flexible display panel.

[0065] In some examples, such as Figures 5-8 As shown, the aforementioned plurality of sub-pixels 2 can be disposed on one side of the substrate 1 and located within the display area A. These plurality of sub-pixels 2 can, for example, be arranged in multiple rows along a first direction X and in multiple columns along a second direction Y. Each row of sub-pixels 2 may include multiple sub-pixels 2, and each column of sub-pixels 2 may include multiple sub-pixels 2. The number of sub-pixels 2 included in different rows and the number of sub-pixels 2 included in different columns can be selected and set according to actual needs (e.g., the shape of the display panel 100).

[0066] Here, the first direction X and the second direction Y intersect each other. The angle between the first direction X and the second direction Y can be selected and set according to actual needs. For example, the angle between the first direction X and the second direction Y can be 85°, 89° or 90°, etc.

[0067] There are multiple ways to arrange the aforementioned sub-pixels 2, and you can choose to set them according to your actual needs.

[0068] For example, such as Figure 7 As shown, the multiple sub-pixels 2 are relatively evenly distributed on one side of the substrate 1. The spacing between any two adjacent sub-pixels 2 is equal or approximately equal.

[0069] For example, at least two sub-pixels 2 constitute a group of sub-pixels, and multiple groups of sub-pixels are arranged in multiple rows along the first direction X and in multiple columns along the second direction Y. Four sub-pixels 2 constitute a group of sub-pixels, and these four sub-pixels 2 include, for example, a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0070] For example, such as Figures 5-8 As shown, each of the aforementioned multiple sub-pixels 2 may include a pixel driving circuit 21 and a light-emitting device 22 electrically connected to the pixel driving circuit 21. The pixel driving circuit 21 may provide a driving voltage to the light-emitting device 22 to control the light-emitting state of the light-emitting device 22.

[0071] The pixel driving circuit 21 described above has various structures, which can be selected and configured according to actual needs. For example, the structure of the pixel driving circuit 21 may include "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C", etc. Here, "T" represents a thin-film transistor, and the number before "T" indicates the number of thin-film transistors; "C" represents a storage capacitor, and the number before "C" indicates the number of storage capacitors. The pixel driving circuit 21 may include a switching transistor and a driving transistor.

[0072] For example, the light-emitting device 22 may include an anode, a light-emitting layer, and a cathode stacked sequentially. Furthermore, the light-emitting device 22 may also include, for example, a hole injection layer and / or a hole transport layer disposed between the anode and the light-emitting layer, and may also include an electron transport layer and / or an electron injection layer disposed between the light-emitting layer and the cathode. The pixel driving circuit 21 is electrically connected to the anode of the light-emitting device 22, for example.

[0073] For example, at least one of the anode and cathode is a light-transmitting layer. That is, at least one of the anode and cathode can be formed using a conductive material with high light transmittance.

[0074] For example, a conductive material with high light transmittance can be indium tin oxide (ITO).

[0075] When the anode is a transparent layer, the light emitted by the light-emitting device 22 can be emitted in the direction pointing towards the substrate 1. In this case, the display panel 100 can be a bottom-emitting display panel. When the cathode is a transparent layer, the light emitted by the light-emitting device 22 can be emitted in the direction away from the substrate 1. In this case, the display panel 100 can be a top-emitting display panel. When both the anode and cathode are transparent layers, the display panel 100 can emit light from both sides.

[0076] Furthermore, when the display panel 100 is a bottom-emitting display panel, the positional relationship between the pixel driving circuit 21 and the light-emitting device 22 can be as follows: Figure 11a and Figure 11bAs shown, the orthographic projections of the two on the substrate 1 do not overlap, ensuring that the display panel 100 has a high light transmittance. Of course, when the display panel 100 has a high light transmittance, the orthographic projections of the pixel driving circuit 21 and the light-emitting device 22 on the substrate 1 can also partially overlap, which is beneficial to improving the PPI (Pixels Per Inch) of the display panel 100.

[0077] When the display panel 100 is a top-emitting display panel, the orthographic projections of the pixel driving circuit 21 and the light-emitting device 22 on the substrate 1 can partially overlap, which helps to reduce the area occupied by the sub-pixel 2 on the substrate 1 and improves the PPI of the display panel 100.

[0078] In some examples, such as Figures 5-8 As shown, the display panel 100 may further include: a plurality of gate lines GL disposed on one side of the substrate 1 and extending along a first direction X, and a plurality of data lines DL disposed on one side of the substrate 1 and extending along a second direction Y. For example, the plurality of data lines DL are located on the side of the plurality of gate lines GL away from the substrate 1, and the plurality of data lines DL and the plurality of gate lines GL are insulated from each other.

[0079] For example, such as Figures 5-8 As shown, a gate line GL can be electrically connected to multiple pixel driving circuits 21 in the same row of sub-pixels 2, and a data line DL can be electrically connected to multiple pixel driving circuits 21 in the same column of sub-pixels 2. The number of gate lines GL electrically connected to multiple pixel driving circuits 21 in the same row of sub-pixels 2 can be set according to the structure of the pixel driving circuit 21. This disclosure uses the example of a row of sub-pixels 2 being electrically connected to a single gate line GL for illustrative purposes.

[0080] Of course, by way of example, the display panel 100 may further include: a plurality of enable signal lines disposed on one side of the substrate 1 and extending along a first direction X. By way of example, the plurality of enable signal lines may be disposed on the same layer as the plurality of gate lines GL; or, the plurality of enable signal lines may be located on a different layer from the plurality of gate lines GL and are insulated from each other.

[0081] For example, an enable signal line can be electrically connected to multiple pixel driving circuits 21 in the same row of sub-pixels 2. The configuration of the enable signal line can be determined according to the structure of the pixel driving circuit.

[0082] During the display process on the display panel 100, the pixel driving circuit 21 can receive scan signals from the corresponding gate line GL and data signals from the corresponding data line DL, form a driving voltage, and transmit the driving voltage to the light-emitting device 22 to drive the light-emitting device 22 to emit light. Alternatively, the pixel driving circuit 21 can receive scan signals from the corresponding gate line GL, data signals from the corresponding data line DL, and enable signals from the corresponding enable signal line, form a driving voltage, and transmit the driving voltage to the light-emitting device 22 to drive the light-emitting device 22 to emit light. By cooperating with the light-emitting devices 22 of multiple sub-pixels, the display panel 100 can display images.

[0083] In some examples, the scan driving circuit 3 and the plurality of sub-pixels 2 are located on the same side of the substrate 1. The scan driving circuit 3 may include a multi-stage shift register 31. The multi-stage shift register 31 may be cascaded.

[0084] The structure of the scanning drive circuit 3 described above includes various types, and can be selected and set according to actual needs.

[0085] For example, the scan driving circuit 3 can be a light emission control circuit. When the pixel driving circuit 21 is also electrically connected to the enable signal lines, the light emission control circuit can be electrically connected to the aforementioned multiple enable signal lines to provide enable signals to the corresponding pixel driving circuit 21 through these multiple enable signal lines.

[0086] For example, the scan driving circuit 3 can also be a scan driving circuit. This scan driving circuit can be electrically connected to the aforementioned multiple gate lines GL to provide scan signals to the corresponding pixel driving circuit 21 through the multiple gate lines GL.

[0087] The following describes the structure of the scanning driving circuit 3 and the pixel driving circuit 21 as follows: Figures 5-8 The “2T1C” structure shown is used as an example for illustrative explanation.

[0088] In some examples, the number of multi-stage shift registers 31 included in the scan drive circuit 3 described above, and the number of rows of sub-pixels 2, may be equal or unequal.

[0089] For example, such as Figures 5-8 and Figures 11a-11b As shown, the number of shift registers 31 can be equal to the number of rows of sub-pixels 2. Based on this, each level shift register 31 can be electrically connected to the pixel driving circuit 21 in the same row of sub-pixels 2 via a gate line GL. During display on the display panel 100, each level shift register 31 in the scan driving circuit 3 can transmit a scan signal to the pixel driving circuit 21 in the corresponding row of sub-pixels 2 via a corresponding gate line GL. Figures 11a-11bThe structure shown is a sequentially connected structure. Because it is difficult to show this structure in one figure, it has been divided into multiple figures.

[0090] For example, the number of shift registers 31 can be greater than the number of rows of sub-pixels 2. Based on this, a first-level shift register 31 can be electrically connected to the pixel driving circuit 21 in the same row of sub-pixels 2 via a gate line GL, while the output signal terminals Oput of the remaining shift registers 31 not electrically connected to the gate line GL... <n>It can be in a floating state. Regarding the output signal terminal Oput... <n>For further explanation, please refer to the description below; it will not be repeated here.

[0091] For example, the number of shift registers 31 can be less than the number of rows of sub-pixels 2. Based on this, a first-level shift register 31 can be electrically connected to multiple rows of sub-pixels 2. The first-level shift register 31 can be electrically connected to the pixel driving circuit 21 in the corresponding multiple rows of sub-pixels 2 via multiple gate lines GL. During display on the display panel 100, each shift register 31 in the scan driving circuit 3 can simultaneously transmit scan signals to the pixel driving circuit 21 in the corresponding multiple rows of sub-pixels 2 via the corresponding multiple gate lines GL. In this case, the output signal terminal Oput of some shift registers 31... <n>It can also be in a suspended state.

[0092] The shift register 31 described above has various structures, which can be selected and configured according to actual needs. The following is a schematic description of one structure of the shift register 31, but the structure of the shift register 31 in this disclosure is not limited to the example structure.

[0093] For example, the first voltage signal terminal VGL1 is configured to transmit a DC low-level signal (e.g., a portion of the clock signal lower than or equal to the low level of the clock signal); this DC low-level signal is referred to herein as the first voltage signal. The second voltage signal terminal VGH is configured to transmit a DC high-level signal (e.g., a portion of the clock signal higher than or equal to the high level of the clock signal); this DC high-level signal is referred to herein as the second voltage signal. The third voltage signal terminal VGL2 is configured to transmit a DC low-level signal (e.g., a portion of the clock signal lower than or equal to the low level of the clock signal); this DC low-level signal is referred to herein as the third voltage signal. The following embodiments are the same and will not be described again.

[0094] For example, the voltage value of the second voltage signal is greater than the voltage value of the first voltage signal, and the voltage value of the second voltage signal is greater than the voltage value of the third voltage signal. The voltage values ​​of the first voltage signal and the third voltage signal may be equal or unequal.

[0095] In some examples, such as Figures 2-4 and Figures 9a-9c As shown, the shift register 31 described above may include: an input circuit 311, a first sub-circuit 312 (also known as a control circuit), and a second sub-circuit 313 (also known as an output circuit). Among these, Figures 9a-9c The structure shown is a sequentially connected structure. Because it is difficult to show this structure in one figure, it has been divided into multiple figures.

[0096] For example, such as Figures 2-4 As shown, the input circuit 311 and the input signal terminal Input <n>(The attached image and the following text are all abbreviated as Iput) <n>), second voltage signal terminal VGH and pull-up node PU <n>Electrical connection. The input circuit 311 is configured to respond to the input signal terminal Iput. <n>The input signal received at the second voltage signal terminal VGH will be transmitted to the pull-up node PU. <n>Where N is a positive integer, representing the number of rows of sub-pixels.

[0097] For example, when the input signal level is high, the input circuit 311 can be turned on by the input signal and transmit the second voltage signal received at the second voltage signal terminal VGH to the pull-up node PU. <n>For the pull-up node PU <n>Charging is performed, causing the pull-up node PU to... <n>The voltage increases.

[0098] Optional, such as Figures 2-4 As shown, the input circuit 311 includes: a fourth transistor T4.

[0099] For example, such as Figure 3 and Figure 4 As shown, the control electrode of the fourth transistor T4 is connected to the input signal terminal Iput. <n>Electrical connections: The first terminal of the fourth transistor T4 is electrically connected to the second voltage signal terminal VGH, and the second terminal of the fourth transistor T4 is electrically connected to the pull-up node PU. <n>Electrical connection.

[0100] Here, when the input signal level is high, the fourth transistor T4 is turned on by the input signal. The fourth transistor T4 can receive the second voltage signal transmitted from the second voltage signal terminal VGH and transmit the received second voltage signal to the pull-up node PU. <n>This makes the pull-up node PU <n>The voltage increases.

[0101] For example, such as Figures 2-4 As shown, the first sub-circuit 312 is connected to the first clock signal terminal CLKA and the pull-up node PU. <n>Drop-down node PD <n>And electrically connected to the first voltage signal terminal VGL1. The first sub-circuit 312 is configured to, under the control of the first clock signal transmitted at the first clock signal terminal CLKA, transmit the first clock signal from CLKA to the pull-down node PD. <n>; and, at the pull-up node PU <n>Under the control of voltage, the pull-down node PD <n>The voltage is controlled.

[0102] For example, when the level of the first clock signal is high, the first sub-circuit 312 can be turned on under the action of the first clock signal, and transmit the first clock signal received at the first clock signal terminal CLKA to the pull-down node PD. <n>For the dropdown node PD <n>Charging is performed, causing the pull-down node PD to... <n>The voltage increases. At the pull-up node PU... <n>When the voltage is high, the first sub-circuit 312 can transmit the first voltage signal transmitted from the first voltage signal terminal VGL1 to the pull-down node PD. <n>, drop down the PD node <n>The voltage is pulled low at the pull-up node PU. <n>When the voltage is low, the first sub-circuit 312 may not transmit the first voltage signal to the pull-down node PD. <n>This makes the dropdown node PD <n>The voltage is maintained at a high level.

[0103] Optional, such as Figures 2-4 As shown, the first sub-circuit 312 includes: a first transistor T1 and a second transistor T2.

[0104] For example, such as Figures 2-4 As shown, the control terminal of the first transistor T1 is electrically connected to the first clock signal terminal CLKA, the first terminal of the first transistor T1 is electrically connected to the first clock signal terminal CLKA, and the second terminal of the first transistor T1 is connected to the pull-down node PD. <n>Electrical connection. The control electrode of the second transistor T2 is connected to the pull-up node PU. <n>Electrical connection: the first terminal of the second transistor T2 is connected to the pull-down node PD. <n>Electrical connection: The second terminal of the second transistor T2 is electrically connected to the first voltage signal terminal VGL1.

[0105] Here, when the level of the first clock signal is high, the first transistor T1 can be turned on under the action of the first clock signal, and transmit the first clock signal received at the first clock signal terminal CLKA to the pull-down node PD. <n>For the dropdown node PD <n>Charging is performed, causing the pull-down node PD to... <n>The voltage increases. Input circuit 311 is turned on, causing the pull-up node PU to... <n>When the voltage is high, the second transistor T2 can pull up the node PU. <n>Under the action of the transistor, the second transistor T2 can receive the first voltage signal transmitted from the first voltage signal terminal VGL1 and transmit the received first voltage signal to the pull-down node PD. <n>Pull down the PD node <n>The voltage at the pull-up node PU. <n>When the voltage is low, the second transistor T2 can pull up the node PU. <n>The action of shutting down the dropdown node PD will cause it to be disabled. <n>The voltage is maintained at a high level.

[0106] For example, such as Figures 2-4 As shown, the second sub-circuit 313 is connected to the second clock signal terminal CLKB and the pull-up node PU. <n>and output signal terminal Output <n>(The attached image and the following text are all abbreviated as Oput) <n>Electrical connection. The second sub-circuit 313 is configured to connect to the pull-up node PU. <n>Under the control of the voltage, the second clock signal received at the second clock signal terminal CLKB is transmitted to the output signal terminal Oput. <n>.

[0107] For example, when the second sub-circuit 311 is turned on, and the pull-up node PU is activated. <n>When the voltage is high, the second sub-circuit 313 can pull up the node PU. <n>It is turned on under the control of the voltage, and takes the second clock signal received at the second clock signal terminal CLKB as the output signal, and outputs it from the output signal terminal Oput. <n>Output.

[0108] In this example, the output signal Oput of the first-level shift register 31 <n>It can be electrically connected to at least one gate line GL, and the output signal terminal Oput <n>The output signal can be used as a scanning signal and transmitted via the at least one gate line GL to the pixel driving circuit 21 of the corresponding at least one row of sub-pixels 2.

[0109] Optional, such as Figures 2-4 As shown, the second sub-circuit 313 includes a third transistor T3 and a first capacitor C1.

[0110] For example, such as Figures 2-4 As shown, the control electrode of the third transistor T3 is connected to the pull-up node PU. <n>Electrical connections: The first terminal of the third transistor T3 is electrically connected to the second clock signal terminal CLKB, and the second terminal of the third transistor T3 is electrically connected to the output signal terminal Oput. <n>Electrical connection. The first terminal of the first capacitor C1 is connected to the pull-up node PU. <n>Electrical connection: The second terminal of the first capacitor C1 is connected to the output signal terminal Oput. <n>Electrical connection.

[0111] Here, the input circuit 311 is turned on, and the pull-up node PU is activated. <n>When the voltage is high, the third transistor T3 can pull up the node PU. <n>The transistor is turned on under the control of the voltage. The third transistor T3 can receive the second clock signal transmitted from the second clock signal terminal CLKB, and use the second clock signal as the output signal from the output signal terminal Oput. <n>Output.

[0112] Furthermore, when the input circuit 311 is turned on, the pull-up node PU is activated. <n>As the voltage increases, the first capacitor C1 is also charged. When the input circuit 311 is off, the first capacitor C1 can discharge, causing the pull-up node PU to... <n>Maintaining a high level allows the third transistor T3 to remain on. The third transistor T3 can continuously receive the second clock signal and output it from the Oput terminal. <n>Continuously output signal.

[0113] It should be noted that after cascading the multi-stage shift registers 31 to form the scan drive circuit 3, the output signal terminal Oput of a certain stage shift register 31... <n>For example, it can be connected to the input signal terminal Iput of the next-stage shift register 31. <n>Electrical connection. This allows the output signal terminal Oput of the stage-by-stage shift register 31 to be connected. <n>The output signal is used as the input signal in the next stage shift register 31. Of course, the cascading relationship of multiple shift registers 31 is not limited to this.

[0114] Among them, the input signal terminal Iput of part of the shift register 31 <n>It can be electrically connected to the start signal line 33 to receive the start signal transmitted by the start signal line 33 as an input signal. For details regarding the start signal line 35, please refer to the description below; it will not be repeated here.

[0115] The number of shift registers 31 electrically connected to the start signal terminal 33 is not limited and can be selected and set according to actual needs.

[0116] For example, the portion of shift register 31 electrically connected to the start signal line 33 can be the first-stage shift register 31 in the scan drive circuit 3, or it can be either the first-stage shift register 31 or the second-stage shift register 31, etc.

[0117] In some examples, such as Figure 3 and Figure 4 As shown, the shift register 31 may further include: a first reset circuit 314, a second reset circuit 315, a third reset circuit 316, a fourth reset circuit 317, and a fifth reset circuit 318.

[0118] For example, such as Figure 3 and Figure 4 As shown, the first reset circuit 314 and the pull-down node PD <n>Pull-up node PU <n>And the first voltage signal terminal VGL1 is electrically connected. The first reset circuit 314 is configured to, at the pull-down node PD <n>Under the control of voltage, the pull-up node PU <n>Perform a reset.

[0119] For example, in the dropdown node PD <n>When the voltage is high, the first reset circuit 314 can pull down the PD node. <n>It is turned on under the action of voltage. The first reset circuit 314 can receive the first voltage signal transmitted by the first voltage signal terminal VGL1 and transmit the first voltage signal to the pull-up node PU. <n>For the pull-up node PU <n>Perform a pull-down reset.

[0120] Optional, such as Figure 3 and Figure 4 As shown, the first reset circuit 314 includes a fifth transistor T5.

[0121] For example, such as Figure 3 and Figure 4 As shown, the control electrode of the fifth transistor T5 is connected to the pull-down node PD. <n>Electrical connection: The first terminal of the fifth transistor T5 is connected to the pull-up node PU. <n>Electrical connection: The second terminal of the fifth transistor T5 is electrically connected to the first voltage signal terminal VGL1.

[0122] Here, in the dropdown node PD <n>When the voltage is high, the fifth transistor T5 can pull down the PD node. <n>The fifth transistor T5 is turned on under the control of the voltage. It can transmit the first voltage signal from the first voltage signal terminal VGL1 to the pull-up node PU. <n>Pull up the PU node <n>The voltage is pulled down, affecting the pull-up node PU. <n>Perform a reset.

[0123] For example, such as Figure 3 and Figure 4 As shown, the second reset circuit 315 and the output signal terminal Oput <n>Drop-down node PD <n>And the first voltage signal terminal VGL1 is electrically connected. The second reset circuit 315 is configured to output signal terminal Oput. <n>Under the control of the transmitted output signal, the pull-down node PD is... <n>Perform a reset.

[0124] For example, when output circuit 313 is turned on and output signal terminal Oput is active... <n>When the level of the transmitted output signal is high (i.e., the level of the second clock signal is high), the second reset circuit 315 can be turned on by the output signal. The second reset circuit 315 can receive the first voltage signal transmitted from the first voltage signal terminal VGL1 and transmit the first voltage signal to the pull-down node PD. <n>For the dropdown node PD <n>Perform a pull-down reset.

[0125] Optional, such as Figure 3 and Figure 4 As shown, the second reset circuit 315 includes a sixth transistor T6.

[0126] For example, such as Figure 3 and Figure 4 As shown, the control electrode of the sixth transistor T6 is connected to the output signal terminal Oput. <n>Electrical connection: The first terminal of the sixth transistor T6 is connected to the pull-down node PD. <n>Electrical connection: The second terminal of the sixth transistor T6 is electrically connected to the first voltage signal terminal VGL1.

[0127] Here, the output circuit 313 is turned on, and the output signal terminal Oput is... <n>When the transmitted output signal level is high, the sixth transistor T6 can be turned on by the output signal. The sixth transistor T6 can then transmit the first voltage signal transmitted from the first voltage signal terminal VGL1 to the pull-down node PD. <n>, drop down the PD node <n>The voltage is pulled low, affecting the pull-down node PD. <n>Perform a reset.

[0128] For example, such as Figure 3 and Figure 4 As shown, the third reset circuit 316 is connected to the pull-down node and the output signal terminal Oput. <n>And the first voltage signal terminal VGL1 is electrically connected. The third reset line 316 is configured to connect to the pull-down node PD. <n>Under the control of the voltage, the output signal terminal Oput is... <n>Perform a reset.

[0129] For example, in the dropdown node PD <n>When the voltage is high, the third reset circuit 316 can pull down the PD node. <n>The circuit is turned on under the control of the voltage. The third reset circuit 316 can receive the first voltage signal transmitted from the first voltage signal terminal VGL1 and transmit the first voltage signal to the output signal terminal Oput. <n>For the output signal terminal Oput <n>Perform a pull-down reset.

[0130] Optional, such as Figure 3 and Figure 4 As shown, the third reset circuit 316 includes: a seventh transistor T7 and a second capacitor C2.

[0131] For example, such as Figure 3 and Figure 4 As shown, the control electrode of the seventh transistor T7 is connected to the pull-down node PD. <n>Electrical connection: The first terminal of the seventh transistor T7 is connected to the output signal terminal Oput. <n>Electrically connected, the second terminal of the seventh transistor T7 is electrically connected to the first voltage signal terminal VGL1. The first terminal of the second capacitor C2 is electrically connected to the pull-down node PD. <n>Electrically connected, the second terminal of the second capacitor C2 is electrically connected to the first voltage signal terminal VGL1.

[0132] Here, in the dropdown node PD <n>When the voltage is high, the seventh transistor T7 can pull down the PD node. <n>It is turned on under the control of the voltage. The seventh transistor T7 can transmit the first voltage signal transmitted from the first voltage signal terminal VGL1 to the output signal terminal Oput. <n>Output signal terminal Oput <n>The voltage is pulled low, affecting the output signal terminal Oput. <n>Perform a reset.

[0133] In addition, in the dropdown node PD <n>When the voltage is high, the second capacitor C2 will also be charged. During subsequent operation, the second capacitor C2 can also discharge, causing the pull-down node PD to... <n>Maintaining a high level allows the seventh transistor T7 to remain on. The seventh transistor T7 can continuously receive the first voltage signal and continuously pull the output signal terminal Oput low. <n>The voltage.

[0134] It should be noted that the third reset circuit 316 is used to control the output signal terminal Oput. <n>The process of resetting can also be called resetting the output signal terminal Oput. <n>The noise reduction process, specifically the third reset circuit 316, can also be called a noise reduction circuit. This is achieved by adjusting the output signal terminal Oput. <n>Noise reduction can avoid output signal input. <n>The residual output signal from the previous frame ensures the accuracy of the output signals from the shift register 31 and the scan drive circuit 3, thereby ensuring the display effect of the display panel 100.

[0135] For example, such as Figure 3 and Figure 4 As shown, the fourth reset circuit 317 is connected to the display reset signal terminal STD and the pull-up node PU. <n>And the third voltage signal terminal VGL2 is electrically connected. The fourth reset circuit 317 is configured to, under the control of the display reset signal transmitted at the display reset signal terminal STD, pull up the PU node. <n>Perform a reset.

[0136] For example, when the display reset signal is at a high level, the fourth reset circuit 317 can be turned on by the display reset signal. The fourth reset circuit 317 can receive the third voltage signal transmitted from the third voltage signal terminal VGL2 and transmit the third voltage signal to the pull-up node PU. <n>For the pull-up node PU <n>Perform a pull-down reset.

[0137] Optional, such as Figure 3 and Figure 4 As shown, the fourth reset circuit 317 includes: the eighth transistor T8.

[0138] For example, such as Figure 3 and Figure 4 As shown, the control terminal of the eighth transistor T8 is electrically connected to the display reset signal terminal STD, and the first terminal of the eighth transistor T8 is connected to the pull-up node PU. <n>Electrical connection: The second terminal of the eighth transistor T8 is electrically connected to the third voltage signal terminal VGL2.

[0139] Here, when the display reset signal level is high, the eighth transistor T8 can be turned on under the action of the display reset signal. The eighth transistor T8 can transmit the third voltage signal transmitted from the third voltage signal terminal VGL2 to the pull-up node PU. <n>Pull up the PU node <n>The voltage is pulled down, affecting the pull-up node PU. <n>Perform a reset.

[0140] It should be noted that after cascading the multi-stage shift registers 31 to form the scan drive circuit 3, the output signal terminal Oput of a certain stage shift register 31... <n>For example, it can be electrically connected to the display reset signal terminal STD of the previous stage shift register 31. This allows the output signal terminal Oput of the previous stage shift register 31 to be connected. <n>The output signal serves as the display reset signal in the previous stage shift register 31. Of course, the cascading relationship of multiple shift registers 31 is not limited to this.

[0141] The display reset signal terminal STD of part of the shift register 31 can be electrically connected to the display reset signal line 35, thereby receiving the signal transmitted by the display reset signal line 35 as the display reset signal. For details regarding the display reset signal line 35, please refer to the description below; it will not be repeated here.

[0142] The number of shift registers 31 electrically connected to the display reset signal line 35 is not limited and can be selected and set according to actual needs.

[0143] For example, the portion of shift register 31 electrically connected to the display reset signal line 35 can be the last stage shift register 31 in the scan drive circuit 3, or it can be the last stage shift register 31 and the penultimate stage shift register 31, etc.

[0144] For example, such as Figure 3 and Figure 4 As shown, the fifth reset circuit 318 is connected to the global reset signal terminal TRSR and the pull-up node PU. <n>And the first voltage signal terminal VGL1 is electrically connected. The fifth reset circuit 318 is configured to, under the control of the global reset signal transmitted by the global reset signal terminal TRSR, pull up the node PU. <n>Perform a reset.

[0145] For example, when the global reset signal is at a high level, the fifth reset circuit 318 can be turned on under the action of the global reset signal. The fifth reset circuit 318 can receive the first voltage signal transmitted from the first voltage signal terminal VGL1 and transmit the first voltage signal to the pull-up node PU. <n>For the pull-up node PU <n>Perform a pull-down reset.

[0146] Optional, such as Figure 3 and Figure 4 As shown, the fifth reset circuit 318 includes: the ninth transistor T9.

[0147] For example, such as Figure 3 and Figure 4 As shown, the control terminal of the ninth transistor T9 is electrically connected to the global reset signal terminal TRSR, and the first terminal of the ninth transistor T9 is connected to the pull-up node PU. <n>Electrical connection: The second terminal of the ninth transistor T9 is electrically connected to the first voltage signal terminal VGL1.

[0148] Here, when the global reset signal is high, the ninth transistor T9 can be turned on by the global reset signal. The ninth transistor T9 can then transmit the first voltage signal from the first voltage signal terminal VGL1 to the pull-up node PU. <n>Pull up the PU node <n>The voltage is pulled down, affecting the pull-up node PU. <n>Perform a reset.

[0149] In some examples, such as Figure 4 As shown, the shift register 31 may also include an abnormal power-down circuit 319.

[0150] For example, such as Figure 4 As shown, the abnormal power-down circuit 319 and the output signal terminal Oput <n>Drop-down node PD <n>The first voltage signal terminal VGL1 and the abnormal power-down signal terminal EN are electrically connected. The abnormal power-down circuit 319 is configured to turn on the pixel driving circuit 21 in the multiple sub-pixels 2 and release the remaining charge when the display panel 100 experiences an abnormal power-down.

[0151] For example, in the event of an abnormal power failure in the display panel 100, the abnormal power failure signal transmitted by the abnormal power failure signal terminal EN will be at a high level. The abnormal power failure circuit 319 can be turned on under the control of the abnormal power failure signal, transmitting the first voltage signal to the pull-down node PD. <n>And transmit the abnormal power failure signal to the output signal terminal Opt. <n>.

[0152] Optional, such as Figure 4 As shown, the abnormal power-down circuit 319 includes: the tenth transistor T10 and the eleventh transistor T11.

[0153] For example, such as Figure 4 As shown, the control terminal of the tenth transistor T10 is electrically connected to the abnormal power-down signal terminal EN, and the first terminal of the tenth transistor T10 is connected to the output signal terminal Oput. <n>Electrical connections: The second terminal of the tenth transistor T10 is electrically connected to the abnormal power-down signal terminal EN. The control terminal of the eleventh transistor T11 is electrically connected to the abnormal power-down signal terminal EN, and the first terminal of the eleventh transistor T11 is connected to the pull-down node PD. <n>Electrical connection: The second terminal of the eleventh transistor T11 is electrically connected to the first voltage signal terminal VGL1.

[0154] Here, in the event of an abnormal power failure in the display panel 100, the abnormal power failure signal transmitted at the abnormal power failure signal terminal EN is at a high level. The tenth transistor T10 and the eleventh transistor T11 can be turned on under the influence of this abnormal power failure signal. The eleventh transistor T11 can transmit the first voltage signal transmitted at the first voltage signal terminal VGL1 to the pull-down node PD. <n>The tenth transistor, T10, can transmit the abnormal power failure signal to the output signal terminal Oput. <n>This makes the output signal terminal Oput <n>An abnormal power failure signal is output, which controls the pixel driving circuit 21 of the corresponding row sub-pixel 2 in the display panel 100 to be turned on, so as to release the residual charge.

[0155] In some examples, such as Figures 5-8 As shown, the multi-stage shift register 31 included in the scan driving circuit 3 is located in the display area A. This avoids setting the shift register 31 in the bezel area B, reducing the area occupied by the scan driving circuit 3 in the bezel area B, and thus effectively reducing the size of the bezel area B, enabling the display panel 100 to achieve a narrow bezel, ultra-narrow bezel, or even bezel-less design.

[0156] In some examples, such as Figures 5-8 As shown, the scan drive circuit 3 also includes multiple clock signal lines 32. After cascading the multi-stage shift registers 31, the multi-stage shift registers 31 can be electrically connected to the multiple clock signal lines 32, and the multiple clock signal lines 32 can transmit clock signals to the corresponding shift registers 31.

[0157] For example, such as Figures 5-8 As shown, the multiple clock signal lines are located within the display area A. This reduces the number of clock signal lines 32 required in the bezel area B, or even eliminates the need for clock signal lines 32 in the bezel area B. This further reduces the area occupied by the scan drive circuit 3 in the bezel area B, and further reduces the size of the bezel area B, enabling the display panel 100 to achieve a narrow bezel, ultra-narrow bezel, or even bezel-less design.

[0158] Furthermore, such as Figures 5-8 As shown, display area A includes a first gap region A1 located between two adjacent columns of sub-pixels. The aforementioned multiple clock signal lines 32 can extend along the second direction Y. When a clock signal line 32 is located within display area A, that clock signal line 32 can be located within the first gap region A1.

[0159] In one implementation, such as Figure 12 As shown, in the display panel, the scan drive circuit includes multi-stage shift registers, a first clock signal line CK1, and a second clock signal line CK2. Each stage of the shift register corresponds to a row of sub-pixels. The first clock signal line CK1 is electrically connected to the first sub-circuit 312' of the odd-stage shift registers and the second sub-circuit 313' of the even-stage shift registers. The second clock signal line CK2 is electrically connected to the second sub-circuit 313' of the odd-stage shift registers and the first sub-circuit 312' of the even-stage shift registers. That is, the first clock signal line CK1 is electrically connected to all the shift registers in the scan drive circuit, and the second clock signal line CK2 is electrically connected to all the shift registers in the scan drive circuit. When the size of the display panel increases or the PPI increases, the number of shift registers in the scan drive circuit will increase, and the first clock signal line CK1 and the second clock signal line CK2 will need to be electrically connected to more shift registers. This increases the number of connection lines 4' connecting the first clock signal line CK1 to each stage of the shift register, and also increases the number of connection lines 4' connecting the second clock signal line CK2 to each stage of the shift register. This, in turn, increases the parasitic capacitance and resistance of the first clock signal line CK1 and the second clock signal line CK2, resulting in severe attenuation of the clock signal received by the shift register, thus affecting the display quality of the display panel.

[0160] Based on this, such as Figures 5-8 and Figure 11a , Figure 11b As shown, in some embodiments of the present disclosure, the multi-stage shift register 31 included in the scan driving circuit 3 may include a first shift register 31 and a second shift register 31. The multiple clock signal lines 32 included in the scan driving circuit 3 may include a first sub-clock signal line 321 and a second sub-clock signal line 322.

[0161] The number of first shift registers 31 and the number of second shift registers 31 can be at least one. The number of first shift registers 31 and the number of second shift registers 31 can be selected and set according to the structure of the display panel 100. The number of first sub-clock signal lines 321 and the number of second sub-clock signal lines 322 can be at least one. The number of first sub-clock signal lines 321 and the number of second sub-clock signal lines 322 can be selected and set according to the structure of the shift registers 31.

[0162] For example, the first shift register 31 and the second shift register 31 have the same structure. The at least one row of sub-pixels 2 connected to the first shift register 31 is different from the at least one row of sub-pixels 2 connected to the second shift register 31. That is, the output signal terminal Oput of the first shift register 31... <n>The output signal terminal Oput of the second shift register 31 <n>They are electrically connected to sub-pixels 2 in different rows respectively. The first shift register 31 and the second shift register 31 have different levels.

[0163] It should be noted that the multi-stage shift register 31 included in the scan drive circuit 3 may also include a third shift register 31 or a fourth shift register 31, etc. Correspondingly, the multiple clock signal lines 32 included in the scan drive circuit 3 may also include sub-clock signal lines electrically connected thereto, etc. This disclosure uses the scan drive circuit 3 including a first shift register 31 and a second shift register 31 as an example for illustrative explanation.

[0164] Here, there are multiple ways to set the first shift register 31 and the second shift register 31, and you can choose to set them according to your actual needs.

[0165] For example, the first-level shift register 31 is electrically connected to the multi-row sub-pixel 2.

[0166] For example, when there is one first shift register 31 and one second shift register 31, the first shift register 31 and the second shift register 31 can each be any level of shift register 31.

[0167] For example, when there are multiple first shift registers 31 and multiple second shift registers 31, at least a portion of the multiple first shift registers 31 can be odd-level shift registers, and at least a portion of the multiple second shift registers 31 can be even-level shift registers.

[0168] For example, such as Figures 5-8 and Figure 11a , Figure 11b As shown, the first-level shift register 31 is electrically connected to a row of sub-pixels 2.

[0169] For example, when there is one first shift register 31 and one second shift register 31, the first shift register 31 and the second shift register 31 can each be any level of shift register 31.

[0170] For example, when there are multiple first shift registers 31 and multiple second shift registers 31, the multiple first shift registers 31 can all be odd-level shift registers 31, and each can be electrically connected to the sub-pixels 2 of the odd-numbered rows; the multiple second shift registers 31 can all be even-level shift registers 31, and each can be electrically connected to the sub-pixels 2 of the even-numbered rows. Alternatively, the multiple first shift registers 31 can all be even-level shift registers 31, and each can be electrically connected to the sub-pixels 2 of the even-numbered rows; the multiple second shift registers 31 can all be odd-level shift registers 31, and each can be electrically connected to the sub-pixels 2 of the odd-numbered rows. Of course, the multiple first shift registers 31 and the multiple second shift registers 31 can be randomly arranged.

[0171] In some examples, such as Figures 5-8 As shown, the shift register 31 includes a first sub-circuit 312 and a second sub-circuit 313. The first sub-circuit 312 may have the following characteristics: Figures 2-4 The structure shown indicates that the second sub-circuit 313 can have the following characteristics: Figures 2-4 The structure shown is correct. Of course, the first sub-circuit 312 and the second sub-circuit 313 can also have other structures.

[0172] For example, the first sub-circuit 312 needs to receive a clock signal during operation. The second sub-circuit 313 also needs to receive a clock signal during operation. The clock signal received by the first sub-circuit 312 and the clock signal received by the second sub-circuit 313 can be the same or different.

[0173] For example, the clock signal received by the first sub-circuit 312 of the odd-level shift register is the same as the clock signal received by the second sub-circuit 313 of the even-level shift register.

[0174] For example, such as Figures 5-8 As shown, the first sub-clock signal line 321 is electrically connected to the first sub-circuit 312 in the first shift register 31, and the first sub-clock signal line 321 is located in the first gap region A1 adjacent to the first sub-circuit 312 in the first shift register 31.

[0175] Here, the first sub-clock signal line 321 and the first sub-circuit 312 in the first shift register 31 can be electrically connected through the first clock signal terminal CLKA.

[0176] When there are multiple first shift registers 31, the first sub-clock signal line 321 can be electrically connected to the first sub-circuit 312 of any of the multiple first shift registers 31, and the first sub-clock signal line 321 is located within a first gap region A1 adjacent to the multiple first sub-circuits 312 of the multiple first shift registers 31. That is, the first sub-circuit 312 of any of the multiple first shift registers 31 can be electrically connected to the first sub-clock signal line 321 through the corresponding first clock signal terminal CLKA.

[0177] Optional, such as Figures 5-8 As shown, a first connecting line 3211 can be provided between the first sub-clock signal line 321 and the first sub-circuit 312 in the first shift register 31. This first connecting line 3211 can be regarded as a branch of the first sub-clock signal line 321 and extends along the first direction X to connect the first sub-circuit 312 in the first shift register 31.

[0178] For example, "the first sub-clock signal line 321 is located in the first gap region A1 adjacent to the first sub-circuit 312 in the first shift register 31" can mean that, along the first direction X, the first gap region A1 where the first sub-clock signal line 321 is located is not provided with sub-pixels 2 between it and the first sub-circuit 312 in the first shift register 31, or that one or two columns of sub-pixels 2 are provided between it and the first sub-circuit 312 in the first shift register 31.

[0179] This allows for a smaller gap between the first sub-clock signal line 321 and the first sub-circuit 312 in the first shift register 31, effectively reducing the length of the first connection line 3211 between the first sub-clock signal line 321 and the first sub-circuit 312 in the first shift register 31, thereby reducing the parasitic capacitance and resistance of the first sub-clock signal line 321. Furthermore, since the first shift register 31 is a part of the plurality of shift registers 31 included in the scan drive circuit 3, the number of shift registers 31 electrically connected to the first sub-clock signal line 321 is effectively reduced, thereby effectively reducing the number of first connection lines 3211 electrically connected to the first sub-clock signal line 321. This further reduces the parasitic capacitance and resistance of the first sub-clock signal line 321.

[0180] For example, such as Figures 5-8 As shown, the second sub-clock signal line 322 is electrically connected to one of the first sub-circuit 312 and the second sub-circuit 313 in the second shift register 31, and the second sub-clock signal line 322 is located in the first gap region A1 adjacent to the sub-circuit electrically connected in the second shift register 31.

[0181] That is, such as Figure 5 and Figure 7 As shown, the second sub-clock signal line 322 can be electrically connected to the first sub-circuit 312 in the second shift register 31, and the second sub-clock signal line 322 is located within a first gap region A1 adjacent to the first sub-circuit 312 in the second shift register 31. Alternatively, as... Figure 6 and Figure 8 As shown, the second sub-clock signal line 322 can be electrically connected to the second sub-circuit 313 in the second shift register 31, and the second sub-clock signal line 322 is located in the first gap region A1 adjacent to the second sub-circuit 313 in the second shift register 31.

[0182] When there are multiple second shift registers 31, the aforementioned second sub-clock signal line 322 can be electrically connected to a first sub-circuit 312 in any of the multiple second shift registers 31, and the second sub-clock signal line 322 is located within a first gap region A1 adjacent to the multiple first sub-circuits 312 in the multiple second shift registers 31. Alternatively, the aforementioned second sub-clock signal line 322 can be electrically connected to a second sub-circuit 313 in any of the multiple second shift registers 31, and the second sub-clock signal line 322 is located within a first gap region A1 adjacent to the multiple second sub-circuits 313 in the multiple second shift registers 31.

[0183] Here, when the second sub-clock signal line 322 is electrically connected to the first sub-circuit 312 in the second shift register 31, the second sub-clock signal line 322 and the first sub-circuit 312 in the second shift register 31 can be electrically connected through the first clock signal terminal CLKA. In the aforementioned plurality of second shift registers 31, the first sub-circuit 312 of any second shift register 31 can be electrically connected to the second sub-clock signal line 322 through the corresponding first clock signal terminal CLKA.

[0184] Optional, such as Figure 5 and Figure 7 As shown, a second connecting line 3221 can be provided between the second sub-clock signal line 322 and the first sub-circuit 312 in the second shift register 31. This second connecting line 3221 can be regarded as a branch of the second sub-clock signal line 322 and extends along the first direction X to connect the first sub-circuit 312 in the second shift register 31.

[0185] For example, "the second sub-clock signal line 322 is located in the first gap region A1 adjacent to the first sub-circuit 312 in the second shift register 31" can mean that, along the first direction X, the first gap region A1 where the second sub-clock signal line 322 is located is not provided with sub-pixels 2 between it and the first sub-circuit 312 in the second shift register 31, or that one or two columns of sub-pixels 2 are provided between it and the first sub-circuit 312 in the second shift register 31.

[0186] This allows for a smaller gap between the second sub-clock signal line 322 and the first sub-circuit 312 in the second shift register 31, effectively reducing the length of the second connection line 3221 between the second sub-clock signal line 322 and the first sub-circuit 312 in the second shift register 31, thereby reducing the parasitic capacitance and resistance of the second sub-clock signal line 322. Furthermore, since the second shift register 31 is a subset of the multiple shift registers 31 included in the scan drive circuit 3, the number of shift registers 31 electrically connected to the second sub-clock signal line 322 is effectively reduced, thereby effectively reducing the number of second connection lines 3221 electrically connected to the second sub-clock signal line 322. This further reduces the parasitic capacitance and resistance of the second sub-clock signal line 322.

[0187] Here, when the second sub-clock signal line 322 is electrically connected to the second sub-circuit 313 in the second shift register 31, the second sub-clock signal line 322 and the second sub-circuit 313 in the second shift register 31 can be electrically connected through the second clock signal terminal CLKB. Among the aforementioned plurality of second shift registers 31, the second sub-circuit 313 of any second shift register 31 can be electrically connected to the second sub-clock signal line 322 through the corresponding second clock signal terminal CLKB.

[0188] Optional, such as Figure 6 and Figure 8 As shown, a third connecting line 3222 can be provided between the second sub-clock signal line 322 and the second sub-circuit 313 in the second shift register 31. This third connecting line 3222 can be regarded as a branch of the second sub-clock signal line 322 and extends along the first direction X to connect the second sub-circuit 313 in the second shift register 31.

[0189] For example, "the second sub-clock signal line 322 is located in the first gap region A1 adjacent to the second sub-circuit 313 in the second shift register 31" can mean that, along the first direction X, the first gap region A1 where the second sub-clock signal line 322 is located is not provided with sub-pixels 2 between it and the second sub-circuit 313 in the second shift register 31, or that one or two columns of sub-pixels 2 are provided between it and the second sub-circuit 313 in the second shift register 31.

[0190] This allows for a smaller gap between the second sub-clock signal line 322 and the second sub-circuit 313 in the second shift register 31, effectively reducing the length of the third connection line 3222 between the second sub-clock signal line 322 and the second sub-circuit 313 in the second shift register 31, thereby reducing the parasitic capacitance and resistance of the second sub-clock signal line 322. Furthermore, since the second shift register 31 is a subset of the multiple shift registers 31 included in the scan drive circuit 3, the number of shift registers 31 electrically connected to the second sub-clock signal line 322 is effectively reduced, thereby effectively reducing the number of third connection lines 3222 electrically connected to the second sub-clock signal line 322. This further reduces the parasitic capacitance and resistance of the second sub-clock signal line 322.

[0191] In some examples, the clock signals transmitted by the first sub-clock signal line 321 and the second sub-clock signal line 322 are the same.

[0192] For example, when the second sub-clock signal line 322 is electrically connected to the first sub-circuit 312 in the second shift register 31, the first clock signal received by the first sub-circuit 312 in the first shift register 31 is the same clock signal as the first clock signal received by the first sub-circuit 312 in the second shift register 31. Based on this, for example, the first sub-clock signal line 321 and the second sub-clock signal line 322 can be considered as two branches of a signal line electrically connected to the same clock signal terminal of different shift registers (where the clock signal received by that terminal is the same). This helps reduce the number of shift registers 31 electrically connected to the first sub-clock signal line 321, reducing the spacing between the first sub-clock signal line 321 and the corresponding first sub-circuit 312 of the shift register 31, and also reduces the number of shift registers 31 electrically connected to the second sub-clock signal line 322, reducing the spacing between the second sub-clock signal line 322 and the corresponding first sub-circuit 312 of the shift register 31.

[0193] For example, when the second sub-clock signal line 322 is electrically connected to the second sub-circuit 313 in the second shift register 31, the first clock signal received by the first sub-circuit 312 in the first shift register 31 and the second clock signal received by the second sub-circuit 313 in the second shift register 31 are the same clock signal. During the display process on the display panel 100, the same clock signal can be transmitted simultaneously to the first sub-clock signal line 321 and the second sub-clock signal line 322. Based on this, for example, the first sub-clock signal line 321 and the second sub-clock signal line 322 can be considered as two branches of the first clock signal line CK1 or the second clock signal line CK2 in one of the above implementations. This helps to reduce the number of shift registers 31 electrically connected to the first sub-clock signal line 321, reduce the spacing between the first sub-clock signal line 321 and the first sub-circuit 312 of the corresponding shift register 31, reduce the number of shift registers 31 electrically connected to the second sub-clock signal line 322, and reduce the spacing between the second sub-clock signal line 322 and the second sub-circuit 313 of the corresponding shift register 31.

[0194] In some examples, such as Figures 5-8 As shown, the first gap region A1 where the first sub-clock signal line 321 and the second sub-clock signal line 322 are located is different.

[0195] That is, when a clock signal line 32 is provided in the first gap region A1, the type of the clock signal line 32 is one (for example, a first sub-clock signal line 321 or a second sub-clock signal line 322). This can avoid signal crosstalk.

[0196] Therefore, the display panel 100 provided in some embodiments of this disclosure can reduce the area occupied by the scanning driving circuit 3 on the border area B by setting the multi-level shift register 31 and multiple clock signal lines 32 in the display area A, thereby reducing the size of the border area B and enabling the display panel 100 to achieve narrow border, ultra-narrow border or even borderless design.

[0197] Furthermore, this disclosure electrically connects the first sub-circuit 312 and the first sub-clock signal line 321 in the first shift register 31, and places the first sub-clock signal line 321 in a first gap region A1 adjacent to the first sub-circuit 312 in the first shift register 31. It also electrically connects the first sub-circuit 312 or the second sub-circuit 313 and the second sub-clock signal line 322 in the second shift register 31, and places the second sub-clock signal line 322 in a first gap region A1 adjacent to the first sub-circuit 312 or the second sub-circuit 313 in the second shift register 31. By ensuring that the first sub-clock signal line 321 and the second sub-clock signal line 322 transmit the same clock signal, this disclosure effectively reduces the number of shift registers 31 electrically connected to the first sub-clock signal line 321, and reduces the number of shift registers 31 electrically connected to the first sub-clock signal line 321. By reducing the spacing between the first sub-circuits 312 (i.e., reducing the length of the first connecting line 3211 between them), the parasitic capacitance and resistance of the first clock signal line 321 are reduced, thus improving the signal attenuation of the clock transmitted by the first clock signal line 321. This also effectively reduces the number of shift registers 31 electrically connected to the second clock signal line 322, and reduces the spacing between the second clock signal line 322 and the corresponding first sub-circuit 312 (i.e., reducing the length of the second connecting line 3221 between them) or the spacing between the second clock signal line 322 and the corresponding second sub-circuit 313 (i.e., reducing the length of the third connecting line 3222 between them). This further reduces the parasitic capacitance and resistance of the second clock signal line 322, improving the signal attenuation of the clock transmitted by the second clock signal line 322. In this way, the display quality of the display panel 100 can be effectively improved.

[0198] In some embodiments, such as Figure 5 and Figure 7 As shown, when the second sub-clock signal line 322 is electrically connected to the first sub-circuit 312 in the second shift register 31, the distance between the second sub-clock signal line 322 and the first sub-circuit 312 in the second shift register 31 is less than the distance between the first sub-clock signal line 321 and the first sub-circuit 312 in the first shift register 31.

[0199] In some examples, such as Figure 5 and Figure 7 As shown, along the second direction Y, the first sub-circuit 312 in the first shift register 31 and the first sub-circuit 312 in the second shift register 31 can be arranged in a row. This simplifies the wiring design and fabrication process of the shift register 31.

[0200] The distance between the first sub-clock signal line 321 and the first sub-circuit 312 in the first shift register 31 is greater than the distance between the second sub-clock signal line 322 and the first sub-circuit 312 in the second shift register 31. This means that the first sub-clock signal line 321 is farther away from the first sub-circuit 312 in the first shift register 31 and the first sub-circuit 312 in the second shift register 31 than the second sub-clock signal line 322.

[0201] There are multiple ways to configure the first sub-clock signal line 321, the second sub-clock signal line 322, and the first sub-circuit 312, which can be selected according to actual needs.

[0202] For example, the first sub-clock signal line 321 and the second sub-clock signal line 322 are located on both sides of the first sub-circuit 312. That is, the first sub-circuit 312 is located between the first sub-clock signal line 321 and the second sub-clock signal line 322, and the distance between the first sub-clock signal line 321 and the first sub-circuit 312 is greater than the distance between the second sub-clock signal line 322 and the first sub-circuit 312.

[0203] For example, such as Figure 5 and Figure 7 As shown, the first sub-clock signal line 321 and the second sub-clock signal line 322 are located on the same side of the first sub-circuit 312 (e.g., to the left or right of the first sub-circuit 312), and the second sub-clock signal line 322 is located between the first sub-clock signal line 321 and the first sub-circuit 312.

[0204] In some embodiments, such as Figure 6 and Figure 8 As shown, when the second sub-clock signal line 322 is electrically connected to the second sub-circuit 313 in the second shift register 31, the distance between the second sub-clock signal line 322 and the second sub-circuit 313 in the second shift register 31 is smaller than the distance between the second sub-clock signal line 322 and the first sub-circuit 312 in the first shift register 31. Similarly, the distance between the first sub-clock signal line 321 and the first sub-circuit 312 in the first shift register 31 is smaller than the distance between the first sub-clock signal line 321 and the second sub-circuit 313 in the second shift register 31.

[0205] Here, there are multiple ways to configure the first sub-clock signal line 322, the second sub-clock signal line 322, the first sub-circuit 312, and the second sub-circuit 313, which can be selected according to actual needs.

[0206] For example, the first sub-clock signal line 322 and the second sub-clock signal line 322 can both be located between the first sub-circuit 312 in the first shift register 31 and the second sub-circuit 313 in the second shift register 31. Compared with the second sub-circuit 313 in the second shift register 31, the first sub-clock signal line 322 is closer to the first sub-circuit 312 in the first shift register 31, and compared with the first sub-circuit 312 in the first shift register 31, the second sub-clock signal line 322 is closer to the second sub-circuit 313 in the second shift register 31.

[0207] For example, such as Figure 6 and Figure 8 As shown, the first sub-clock signal line 321 can be located between the first sub-circuit 312 in the first shift register 31 and the second sub-circuit 313 in the second shift register 31, and the second sub-clock signal line 322 is farther away from the first sub-clock signal line 321 relative to the second sub-circuit 313 in the second shift register 31.

[0208] Based on this, for example, along the first direction X, the first sub-circuit 312 in the first shift register 31 and the second sub-circuit 313 in the second shift register 31 are arranged sequentially, the first sub-clock signal line 321 can be located to the right of the first sub-circuit 312 in the first shift register 31, and the second sub-clock signal line 322 can also be located to the right of the second sub-circuit 313 in the second shift register 31.

[0209] It should be noted that in one of the above implementations, the first clock signal line CK1 is electrically connected to the first sub-circuit 312' of the odd-level shift register and the second sub-circuit 313' of the even-level shift register. The distance between the second clock signal line CK1 and the first sub-circuit 312' of the odd-level shift register is relatively large, and the distance between the first clock signal line CK1 and the first sub-circuit 312' of the odd-level shift register is several times or even more than ten times the distance between the first clock signal line CK1 and the second sub-circuit 313' of the even-level shift register. The second clock signal line CK2 is similar.

[0210] In this example, the first sub-clock signal line 321 and the second sub-clock signal line 322 can be regarded as two branches of the first clock signal line CK1 or the second clock signal line CK2 in one of the above implementations.

[0211] By configuring the first sub-clock signal line 321 and the second sub-clock signal line 322 as described above, the distance between the first sub-clock signal line 321 and the first sub-circuit 312 in the first shift register 31 can be effectively reduced. For example, compared to the above implementation, the distance between the first sub-clock signal line 321 and the first sub-circuit 312 in the first shift register 31 can be smaller than the distance between the first clock signal line CK1 and the control circuit 312' of the odd-level shift register. This helps to reduce the length of the first connecting line 3211 between the first sub-clock signal line 321 and the first sub-circuit 312 in the first shift register 31, effectively reducing the parasitic capacitance and resistance of the first sub-clock signal line 321 and improving the display quality of the display panel 100.

[0212] In some embodiments, such as Figure 7 and Figure 8 As shown, the scan drive circuit 3 includes multiple clock signal lines 32, including a third sub-clock signal line 323 and a fourth sub-clock signal line 324. The number of third sub-clock signal lines 323 and the number of fourth sub-clock signal lines 324 can be at least one. The number of third sub-clock signal lines 323 and the number of fourth sub-clock signal lines 324 can be selected and set according to the structure of the shift register 31.

[0213] In some examples, such as Figure 7 and Figure 8 As shown, the third sub-clock signal line 323 is electrically connected to the second sub-circuit 313 in the first shift register 31, and the third sub-clock signal line 323 is located in the first gap region A1 adjacent to the second sub-circuit 313 in the first shift register 31.

[0214] Here, the third sub-clock signal line 323 and the second sub-circuit 313 in the first shift register 31 can be electrically connected through the second clock signal terminal CLKB.

[0215] When there are multiple first shift registers 31, the aforementioned third sub-clock signal line 323 can be electrically connected to multiple second sub-circuits 313 in the multiple first shift registers 31, and the third sub-clock signal line 323 can be located within a first gap region A1 adjacent to the multiple second sub-circuits 313 in the multiple first shift registers 31. That is, in the multiple first shift registers 31, the second sub-circuit 313 of any first shift register 31 can be electrically connected to the third sub-clock signal line 323 through the corresponding second clock signal terminal CLKB.

[0216] Optional, such as Figure 7 and Figure 8 As shown, a fourth connecting line 3231 can be provided between the third sub-clock signal line 323 and the second sub-circuit 313 in the first shift register 31. This fourth connecting line 3231 can be regarded as a branch of the third sub-clock signal line 323 and extends along the first direction X to connect the second sub-circuit 313 in the first shift register 31.

[0217] For example, "the third sub-clock signal line 323 is located in the first gap region A1 adjacent to the second sub-circuit 313 in the first shift register 31" can mean that, along the first direction X, the first gap region A1 where the third sub-clock signal line 323 is located is not provided with sub-pixels 2 between it and the second sub-circuit 312 in the first shift register 31, or that one or two columns of sub-pixels 2 are provided between it and the second sub-circuit 312 in the first shift register 31.

[0218] This allows for a smaller gap between the third sub-clock signal line 323 and the second sub-circuit 313 in the first shift register 31, effectively reducing the length of the fourth connection line 3231 between the third sub-clock signal line 323 and the second sub-circuit 313 in the first shift register 31, thereby reducing the parasitic capacitance and resistance of the third sub-clock signal line 323. Furthermore, since the first shift register 31 is a subset of the multiple shift registers 31 included in the scan drive circuit 3, the number of shift registers 31 electrically connected to the third sub-clock signal line 323 is effectively reduced, thereby effectively reducing the number of fourth connection lines 3231 electrically connected to the third sub-clock signal line 323. This further reduces the parasitic capacitance and resistance of the third sub-clock signal line 323.

[0219] In some examples, the fourth sub-clock signal line 324 is electrically connected to another of the first sub-circuit 312 and the second sub-circuit 313 in the second shift register 31, and the fourth sub-clock signal line 324 is located in a first gap region A1 adjacent to the sub-circuit electrically connected in the second shift register 31.

[0220] That is, such as Figure 7 As shown, when the second sub-clock signal line 322 is electrically connected to the first sub-circuit 312 in the second shift register 31, the fourth sub-clock signal line 324 can be electrically connected to the second sub-circuit 313 in the second shift register 31, and the fourth sub-clock signal line 324 is located within the first gap region A1 adjacent to the second sub-circuit 313 in the second shift register 31. Alternatively, as... Figure 8 As shown, when the second sub-clock signal line 322 is electrically connected to the second sub-circuit 313 in the second shift register 31, the fourth sub-clock signal line 324 can be electrically connected to the first sub-circuit 312 in the second shift register 31.

[0221] When there are multiple second shift registers 31, the aforementioned fourth sub-clock signal line 324 can be electrically connected to multiple second sub-circuits 313 in the multiple second shift registers 31, and the fourth sub-clock signal line 324 is located within a first gap region A1 adjacent to the multiple second sub-circuits 313 in the multiple second shift registers 31. Alternatively, the aforementioned fourth sub-clock signal line 324 can be electrically connected to multiple first sub-circuits 312 in the multiple second shift registers 31, and the fourth sub-clock signal line 324 is located within a first gap region A1 adjacent to the multiple first sub-circuits 312 in the multiple second shift registers 31.

[0222] Here, when the fourth sub-clock signal line 324 is electrically connected to the second sub-circuit 313 in the second shift register 31, the fourth sub-clock signal line 324 and the second sub-circuit 313 in the second shift register 31 can be electrically connected through the second clock signal terminal CLKB. In the aforementioned plurality of second shift registers 31, the second sub-circuit 313 of any second shift register 31 can be electrically connected to the fourth sub-clock signal line 324 through the corresponding second clock signal terminal CLKB.

[0223] Optional, such as Figure 8 As shown, a fifth connecting line 3241 can be provided between the fourth sub-clock signal line 324 and the second sub-circuit 313 in the second shift register 31. This fifth connecting line 3241 can be regarded as a branch of the fourth sub-clock signal line 324 and extends along the first direction X to connect the second sub-circuit 313 in the second shift register 31.

[0224] For example, "the fourth sub-clock signal line 324 is located in the first gap region A1 adjacent to the second sub-circuit 313 in the second shift register 31" can mean that, along the first direction X, the first gap region A1 where the fourth sub-clock signal line 324 is located is not provided with sub-pixels 2 between it and the second sub-circuit 313 in the second shift register 31, or that one or two columns of sub-pixels 2 are provided between it and the second sub-circuit 313 in the second shift register 31.

[0225] This allows for a smaller gap between the fourth sub-clock signal line 324 and the second sub-circuit 313 in the second shift register 31, effectively reducing the length of the fifth connection line 3241 between the fourth sub-clock signal line 324 and the second sub-circuit 313 in the second shift register 31, thereby reducing the parasitic capacitance and resistance of the fourth sub-clock signal line 324. Furthermore, since the second shift register 31 is a subset of the multiple shift registers 31 included in the scan drive circuit 3, the number of shift registers 31 electrically connected to the fourth sub-clock signal line 324 is effectively reduced, thereby effectively reducing the number of fifth connection lines 3241 electrically connected to the fourth sub-clock signal line 324. This further reduces the parasitic capacitance and resistance of the fourth sub-clock signal line 324.

[0226] Here, when the fourth sub-clock signal line 324 is electrically connected to the first sub-circuit 312 in the second shift register 31, the fourth sub-clock signal line 324 and the first sub-circuit 312 in the second shift register 31 can be electrically connected through the first clock signal terminal CLKA. In the aforementioned plurality of second shift registers 31, the first sub-circuit 312 of any second shift register 31 can be electrically connected to the fourth sub-clock signal line 324 through the corresponding first clock signal terminal CLKA.

[0227] Optional, such as Figure 7 As shown, a sixth connecting line 3242 can be provided between the fourth sub-clock signal line 324 and the first sub-circuit 312 in the second shift register 31. This sixth connecting line 3242 can be regarded as a branch of the fourth sub-clock signal line 324 and extends along the first direction X to connect the first sub-circuit 312 in the second shift register 31.

[0228] For example, "the fourth sub-clock signal line 324 is located in the first gap region A1 adjacent to the first sub-circuit 312 in the second shift register 31" can mean that, along the first direction X, the first gap region A1 where the fourth sub-clock signal line 324 is located is not provided with sub-pixels 2 between it and the first sub-circuit 312 in the second shift register 31, or that one or two columns of sub-pixels 2 are provided between it and the first sub-circuit 312 in the second shift register 31.

[0229] This allows for a smaller gap between the fourth sub-clock signal line 324 and the first sub-circuit 312 in the second shift register 31, effectively reducing the length of the sixth connection line 3242 between the fourth sub-clock signal line 324 and the first sub-circuit 312 in the second shift register 31, thereby reducing the parasitic capacitance and resistance of the fourth sub-clock signal line 324. Furthermore, since the second shift register 31 is a part of the multiple shift registers 31 included in the scan drive circuit 3, the number of shift registers 31 electrically connected to the fourth sub-clock signal line 324 is effectively reduced, thereby effectively reducing the number of sixth connection lines 3242 electrically connected to the fourth sub-clock signal line 324. This effectively reduces the parasitic capacitance and resistance of the fourth sub-clock signal line 324.

[0230] In some examples, the clock signals transmitted by the third sub-clock signal line 323 and the fourth sub-clock signal line 324 are the same.

[0231] For example, when the second sub-clock signal line 322 is electrically connected to the first sub-circuit 312 in the second shift register 31, the fourth sub-clock signal line 324 is electrically connected to the second sub-circuit 313 in the second shift register 31. In this case, the second clock signal received by the second sub-circuit 313 in the first shift register 31 is the same clock signal as the second clock signal received by the second sub-circuit 313 in the second shift register 31. Based on this, for example, the third sub-clock signal line 323 and the fourth sub-clock signal line 324 can be considered as two branches of a signal line electrically connected to the same clock signal terminal of different shift registers (where the clock signal received by that terminal is the same). This helps reduce the number of shift registers 31 electrically connected to the third sub-clock signal line 323, reducing the spacing between the third sub-clock signal line 323 and the corresponding second sub-circuit 313 of the shift register 31, and reduces the number of shift registers 31 electrically connected to the fourth sub-clock signal line 324, reducing the spacing between the fourth sub-clock signal line 324 and the corresponding second sub-circuit 312 of the shift register 31.

[0232] For example, when the second sub-clock signal line 322 is electrically connected to the second sub-circuit 313 in the second shift register 31, the fourth sub-clock signal line 324 is electrically connected to the first sub-circuit 312 in the second shift register 31. At this time, the second clock signal received by the second sub-circuit 313 in the first shift register 31 and the first clock signal received by the first sub-circuit 312 in the second shift register 31 are the same clock signal. During the display process of the display panel 100, the same clock signal can be transmitted simultaneously to the third sub-clock signal line 323 and the fourth sub-clock signal line 324. Based on this, for example, the third sub-clock signal line 323 and the fourth sub-clock signal line 324 can be regarded as two branches of the first clock signal line CK1 or the second clock signal line CK2 in one of the above implementations. This helps to reduce the number of shift registers 31 electrically connected to the third sub-clock signal line 323, reduce the spacing between the third sub-clock signal line 321 and the second sub-circuit 313 of the corresponding shift register 31, reduce the number of shift registers 31 electrically connected to the fourth sub-clock signal line 324, and reduce the spacing between the fourth sub-clock signal line 324 and the first sub-circuit 312 of the corresponding shift register 31.

[0233] This disclosure effectively reduces the number of shift registers 31 electrically connected to the third sub-clock signal line 323 in the first shift register 32, and places the third sub-clock signal line 323 within a first gap region A1 adjacent to the second sub-circuit 313 in the first shift register 32. It also electrically connects the fourth sub-clock signal line 324 to either the second sub-circuit 313 or the first sub-circuit 312 in the second shift register 31, and places the fourth sub-clock signal line 324 within the first gap region A1 adjacent to either the second sub-circuit 313 or the first sub-circuit 312 in the second shift register 31. Furthermore, it ensures that the clock signals transmitted by the third sub-clock signal line 323 and the fourth sub-clock signal line 324 are identical. This reduces the number of shift registers 31 electrically connected to the third sub-clock signal line 323 and minimizes the interaction between the third sub-clock signal line 323 and the corresponding... The spacing between the second sub-circuits 313 (i.e., reducing the length of the fourth connecting line 3231 between them) helps to reduce the parasitic capacitance and resistance of the third sub-clock signal line 323, thus improving the signal attenuation of the clock transmitted by the third sub-clock signal line 323. It can also effectively reduce the number of shift registers 31 electrically connected to the fourth sub-clock signal line 324, and reduce the spacing between the fourth sub-clock signal line 324 and the corresponding second sub-circuit 313 (i.e., reducing the length of the fifth connecting line 3241 between them) or the spacing between the fourth sub-clock signal line 324 and the corresponding first sub-circuit 313 (i.e., reducing the length of the sixth connecting line 3242 between them). This further helps to reduce the parasitic capacitance and resistance of the fourth sub-clock signal line 324, improving the signal attenuation of the clock transmitted by the fourth sub-clock signal line 324. This effectively improves the display quality of the display panel 100.

[0234] In some examples, such as Figure 7 and Figure 8 As shown, the first gap region A1 where the third sub-clock signal line 323 and the fourth sub-clock signal line 324 are located are different.

[0235] That is, when a clock signal line 32 is provided in the first gap region A1, the type of the clock signal line 32 is one (for example, a third sub-clock signal line 323 or a fourth sub-clock signal line 324). This can avoid signal crosstalk.

[0236] In some embodiments, such as Figure 7 As shown, with the second sub-clock signal line 322 electrically connected to the first sub-circuit 312 in the second shift register 31, the fourth sub-clock signal line 324 is electrically connected to the second sub-circuit 313 in the second shift register 31. The spacing between the fourth sub-clock signal line 324 and the second sub-circuit 313 in the second shift register 31 is smaller than the spacing between the third sub-clock signal line 313 and the second sub-circuit 313 in the first shift register 31.

[0237] In some examples, such as Figure 7 As shown, along the second direction Y, the second sub-circuit 313 in the first shift register 31 and the second sub-circuit 313 in the second shift register 31 can be arranged in a row. This helps to simplify the wiring design of the shift register 31 and simplify the fabrication process of the shift register 31.

[0238] The distance between the third sub-clock signal line 323 and the second sub-circuit 313 in the first shift register 31 is greater than the distance between the fourth sub-clock signal line 324 and the second sub-circuit 313 in the second shift register 31. This means that the third sub-clock signal line 323 is farther away from the second sub-circuit 313 in the first shift register 31 than the fourth sub-clock signal line 324.

[0239] There are multiple ways to configure the third sub-clock signal line 323, the fourth sub-clock signal line 324 and the second sub-circuit 313, which can be selected according to actual needs.

[0240] For example, the third sub-clock signal line 323 and the fourth sub-clock signal line 324 are located on both sides of the second sub-circuit 313. That is, the second sub-circuit 313 is located between the third sub-clock signal line 323 and the fourth sub-clock signal line 324, and the distance between the third sub-clock signal line 323 and the second sub-circuit 313 is greater than the distance between the fourth sub-clock signal line 324 and the second sub-circuit 313.

[0241] For example, such as Figure 7 As shown, the third sub-clock signal line 323 and the fourth sub-clock signal line 324 are located on the same side of the second sub-circuit 313 (e.g., to the left or right of the second sub-circuit 313), and the fourth sub-clock signal line 324 is located between the third sub-clock signal line 323 and the second sub-circuit 313.

[0242] In some embodiments, such as Figure 8 As shown, with the second sub-clock signal line 322 electrically connected to the second sub-circuit 313 in the second shift register 31, the fourth sub-clock signal line 324 is electrically connected to the first sub-circuit 312 in the second shift register 31. The spacing between the third sub-clock signal line 323 and the second sub-circuit 313 in the first shift register 31 is smaller than the spacing between the third sub-clock signal line 323 and the first sub-circuit 312 in the second shift register 31. The spacing between the fourth sub-clock signal line 324 and the second sub-circuit 312 in the second shift register 32 is smaller than the spacing between the fourth sub-clock signal line 324 and the second sub-circuit 313 in the first shift register 32.

[0243] Here, there are multiple ways to configure the third sub-clock signal line 323, the fourth sub-clock signal line 324, the first sub-circuit 312, and the second sub-circuit 313, which can be selected according to actual needs.

[0244] For example, the third sub-clock signal line 323 and the fourth sub-clock signal line 324 can both be located between the second sub-circuit 314 in the first shift register 31 and the first sub-circuit 312 in the second shift register 31. Compared with the second sub-circuit 313 in the first shift register 31, the fourth sub-clock signal line 322 is closer to the second sub-circuit 313 in the second shift register 31, and compared with the first sub-circuit 312 in the second shift register 31, the third sub-clock signal line 323 is closer to the second sub-circuit 313 in the first shift register 31.

[0245] For example, such as Figure 8 As shown, the fourth sub-clock signal line 324 can be located between the second sub-circuit 313 in the first shift register 31 and the first sub-circuit 312 in the second shift register 31, and the third sub-clock signal line 323 is farther away from the fourth sub-clock signal line 324 relative to the second sub-circuit 313 in the first shift register 31.

[0246] Based on this, for example, along the first direction X, the first sub-circuit 312 and the second sub-circuit 313 in the second shift register 31 are arranged in sequence, the fourth sub-clock signal line 324 can be located to the right of the first sub-circuit 312 in the second shift register 31, and the third sub-clock signal line 323 can also be located to the right of the first sub-circuit 313 in the first shift register 31.

[0247] It should be noted that in one of the above implementations, the first clock signal line CK1 is electrically connected to the first sub-circuit 312' of the odd-level shift register and the second sub-circuit 313' of the even-level shift register. The distance between the second clock signal line CK1 and the first sub-circuit 312' of the odd-level shift register is relatively large, and the distance between the first clock signal line CK1 and the first sub-circuit 312' of the odd-level shift register is several times or even more than ten times the distance between the first clock signal line CK1 and the second sub-circuit 313' of the even-level shift register. The second clock signal line CK2 is similar.

[0248] In this example, the third sub-clock signal line 323 and the fourth sub-clock signal line 324 can be regarded as two branches of the first clock signal line CK1 or the second clock signal line CK2 in one of the above implementations.

[0249] By configuring the third sub-clock signal line 323 and the fourth sub-clock signal line 324 as described above, the distance between the third sub-clock signal line 323 and the second sub-circuit 313 in the first shift register 31 can be effectively reduced. For example, compared to the above implementation, the distance between the fourth sub-clock signal line 323 and the first sub-circuit 312 in the second shift register 31 can be smaller than the distance between the second clock signal line CK2 and the first sub-circuit 312' of the even-level shift register. This helps to reduce the length of the sixth connecting line 3242 between the fourth sub-clock signal line 324 and the first sub-circuit 312 in the second shift register 31, effectively reducing the parasitic capacitance and resistance of the fourth sub-clock signal line 324 and improving the display quality of the display panel 100.

[0250] In some embodiments, a sub-pixel 2 has a first size value along the first direction X. The first size value L of the sub-pixel 2 along the first direction X may refer to the distance between the centers of two adjacent sub-pixels 2 along the first direction X; or, the distance between the centers of the first gap regions A1 located on both sides of the sub-pixel 2 along the first direction X.

[0251] In some examples, the spacing between the first sub-circuit 312 and the first sub-clock signal line 321 in the first shift register 31 is less than or equal to four times the first size value L. That is, along the first direction X, there may be no sub-pixel 2 between the first sub-clock signal line 321 and the corresponding first sub-circuit 312, or there may be 1 to 4 columns of sub-pixels 2.

[0252] This effectively reduces the spacing between the first sub-clock signal line 321 and the corresponding first sub-circuit 312, reduces the parasitic capacitance and resistance of the first sub-clock signal line 321, improves the phenomenon of severe attenuation of the clock signal during transmission in the first sub-clock signal line 321, and thus improves the display quality of the display panel 100.

[0253] In some examples, the spacing between the second sub-output circuit 313 and the third sub-clock signal line 323 in the first shift register 31 is less than or equal to four times the first size value L. That is, along the first direction X, there may be no sub-pixel 2 between the third sub-clock signal line 323 and the corresponding second sub-circuit 313, or there may be 1 to 4 columns of sub-pixels 2.

[0254] This effectively reduces the spacing between the third sub-clock signal line 323 and the corresponding second sub-circuit 313, reduces the parasitic capacitance and resistance of the third sub-clock signal line 323, improves the severe attenuation phenomenon of the clock signal during transmission in the third sub-clock signal line 323, and thus improves the display quality of the display panel 100.

[0255] In some examples, when the second sub-clock signal line 322 is electrically connected to the first sub-circuit 312 in the second shift register 31, the fourth sub-clock signal line 324 is electrically connected to the second sub-circuit 313 in the second shift register 31. The spacing between the first sub-circuit 312 and the second sub-clock signal line 322 in the second shift register 31 is less than or equal to four times the first size value L. That is, along the first direction X, there may be no sub-pixel 2 between the second sub-clock signal line 322 and the corresponding first sub-circuit 312, or there may be 1 to 4 columns of sub-pixels 2. The spacing between the second sub-circuit 313 and the fourth sub-clock signal line 324 in the second shift register 31 is less than or equal to four times the first size value L. That is, along the first direction X, there may be no sub-pixel 2 between the fourth sub-clock signal line 324 and the corresponding second sub-circuit 313, or there may be 1 to 4 columns of sub-pixels 2.

[0256] This effectively reduces the spacing between the second sub-clock signal line 322 and the corresponding first sub-circuit 312, lowers the parasitic capacitance and resistance of the second sub-clock signal line 322, and mitigates the severe attenuation of the clock signal during transmission through the second sub-clock signal line 322, thereby improving the display quality of the display panel 100. Similarly, this effectively reduces the spacing between the fourth sub-clock signal line 324 and the corresponding second sub-circuit 313, lowers the parasitic capacitance and resistance of the fourth sub-clock signal line 324, and mitigates the severe attenuation of the clock signal during transmission through the fourth sub-clock signal line 324, thereby improving the display quality of the display panel 100.

[0257] In some examples, when the second sub-clock signal line 322 is electrically connected to the second sub-circuit 313 in the second shift register 31, the fourth sub-clock signal line 324 is electrically connected to the first sub-circuit 312 in the second shift register 31. The spacing between the second sub-circuit 313 and the second sub-clock signal line 322 in the second shift register 31 is less than or equal to four times the first size value L. That is, along the first direction X, there may be no sub-pixel 2 between the second sub-clock signal line 322 and the corresponding second sub-circuit 322, or there may be 1 to 4 columns of sub-pixels 2. The spacing between the first sub-circuit 312 and the fourth sub-clock signal line 324 in the second shift register 31 is less than or equal to four times the first size value L. That is, along the first direction X, there may be no sub-pixel 2 between the fourth sub-clock signal line 324 and the corresponding first sub-circuit 312, or there may be 1 to 4 columns of sub-pixels 2.

[0258] It should be noted that display area A includes multiple first gap regions A1. The number of clock signal lines 32 is less than the number of first gap regions A1. Specifically, some first gap regions A1 contain clock signal lines 32, while others do not.

[0259] In some embodiments, such as Figure 7 and Figure 8 As shown, either the first sub-clock signal line 321 or the second sub-clock signal line 322 is different from the first gap region A1 where either the third sub-clock signal line 323 or the fourth sub-clock signal line 324 is located.

[0260] That is, the first gap region A1 where the first sub-clock signal line 321 and the third sub-clock signal line 323 are located is different. The first gap region A1 where the first sub-clock signal line 321 and the fourth sub-clock signal line 324 are located is different. The first gap region A1 where the second sub-clock signal line 322 and the third sub-clock signal line 323 are located is different. The first gap region A1 where the second sub-clock signal line 322 and the fourth sub-clock signal line 324 are located is different.

[0261] In other words, when a clock signal line 32 is provided in the first gap region A1, the type of the clock signal line 32 is one (for example, the first sub-clock signal line 321, the second sub-clock signal line 322, the third sub-clock signal line 323 or the fourth sub-clock signal line 324).

[0262] In some examples, when a clock signal line 32 is provided in the first gap region A1, the number of clock signal lines 32 located in the same gap region A1 is one.

[0263] Here, the clock signal line 32 is relatively large along the first direction X. By setting only one clock signal line 32 in the first gap region A1, it is possible to avoid increasing the size of the first gap region A1 along the first direction X, thereby avoiding different sizes of different first gap regions A1 along the first direction X, which is beneficial to make the multiple sub-pixels 2 in the display panel 100 evenly distributed.

[0264] In some embodiments, the number of first sub-clock signal lines 321 can be determined according to the structure of the first transistor T1 in the first shift register 31. The number of third sub-clock signal lines 323 can be determined according to the structure of the third transistor T3 in the first shift register 31. The number of second sub-clock signal lines 322 can be determined according to the structure of the first transistor T1 or the third transistor T3 in the second shift register 31; correspondingly, the number of fourth sub-clock signal lines 324 can be determined according to the structure of the third transistor T3 or the first transistor T1 in the second shift register 31.

[0265] During the display process on the display panel 100, the first sub-clock signal line 321 and the second sub-clock signal line 322 transmit the same clock signal. There are various methods for transmitting the clock signal to the first sub-clock signal line 321 and the second sub-clock signal line 322, which can be selected and set according to actual needs.

[0266] In some examples, one end of the first sub-clock signal line 321 and one end of the second sub-clock signal line 322 can be led out to the frame area B and electrically connected to the port providing the corresponding clock signal through the corresponding signal transmission line.

[0267] In other examples, such as Figure 5 and Figure 6 As shown, the scan drive circuit 3 further includes a first bus 33. The first bus 33 is electrically connected to a first sub-clock signal line 321 and a second sub-clock signal line 322. The first bus 33 is configured to transmit corresponding clock signals to the first sub-clock signal line 321 and the second sub-clock signal line 322.

[0268] For example, the free end of the first bus 33 can be electrically connected to a port that provides the corresponding clock signal. In this way, the corresponding clock signal can be transmitted to the first sub-clock signal line 321 and the second sub-clock signal line 322 respectively through the first bus 33, so that the first sub-clock signal line 321 and the second sub-clock signal line 322 can receive the corresponding clock signal simultaneously.

[0269] By setting the first bus 33, it is beneficial to reduce the number of traces in the scan drive circuit 3, simplify the structure of the scan drive circuit 3, and reduce the area occupied by the scan drive circuit 3.

[0270] Furthermore, the multiple clock signal lines 32 in the scan drive circuit 3 may also include a third sub-clock signal line 323 and a fourth sub-clock signal line 324. During the display process on the display panel 100, the third sub-clock signal line 323 and the fourth sub-clock signal line 324 transmit the same clock signal. The methods for transmitting the clock signal to the third sub-clock signal line 323 and the fourth sub-clock signal line 324 can be varied and can be selected and set according to actual needs.

[0271] In some examples, one end of the third sub-clock signal line 323 and one end of the fourth sub-clock signal line 324 can be led out to the frame area B and electrically connected to the port providing the corresponding clock signal through the corresponding signal transmission line.

[0272] In other examples, such as Figure 7 and Figure 8 As shown, the scan drive circuit 3 further includes a second bus 34. The second bus 34 is electrically connected to the third sub-clock signal line 323 and the fourth sub-clock signal line 324. The second bus 34 is configured to transmit corresponding clock signals to the third sub-clock signal line 323 and the fourth sub-clock signal line 324.

[0273] For example, the free end of the second bus 34 can be electrically connected to a port that provides the corresponding clock signal. In this way, the corresponding clock signals can be transmitted to the third sub-clock signal line 323 and the fourth sub-clock signal line 324 through the second bus 34, so that the third sub-clock signal line 323 and the fourth sub-clock signal line 324 can receive the corresponding clock signals simultaneously.

[0274] By setting up the second bus 34, it is beneficial to reduce the number of traces in the scan drive circuit 3, simplify the structure of the scan drive circuit 3, and reduce the area occupied by the scan drive circuit 3.

[0275] In some examples, such as Figure 7 and Figure 8 As shown, both the first bus 33 and the second bus 33 extend along the first direction X and are located in the border area B.

[0276] By arranging the first bus 33 and the second bus 33 in the same direction, it is beneficial to reduce the area occupied by the first bus 33 and the second bus 33 in the display panel 100, which in turn helps to reduce the size of the remaining side bezel area B.

[0277] In some examples, the first and second terminals of the first transistor T1, the first and second terminals of the second transistor T1, and the first and second terminals of the third transistor T1 are arranged on the same layer. When the scan drive circuit 3 also includes a first bus 33 and a second bus 34, the first bus 33, the second bus 34, the control terminals of the first transistor T1, the second transistor T2, and the third transistor T3, and the first terminal of the first capacitor layer are arranged on the same layer.

[0278] Here, "same layer" as mentioned in this article refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same mask to form a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses. In this way, the first and second electrodes of the first transistor T1, the first and second electrodes of the second transistor T1, and the first and second electrodes of the third transistor T1 can be fabricated simultaneously in a single patterning process. It is also possible to simultaneously fabricate the first bus 33, the second bus 34, the control electrode of the first transistor T1, the control electrode of the second transistor T2, the control electrode of the third transistor T3, and the first electrode of the first capacitor layer in a single patterning process, which simplifies the fabrication process of the display panel 100.

[0279] In some embodiments, the first transistor T1 includes a plurality of first sub-transistors T11 arranged in parallel, and / or the third transistor T3 includes a plurality of third sub-transistors T31 arranged in parallel.

[0280] Based on this, the configuration of the first transistor T1 and the third transistor T3 can include: the first transistor T1 includes multiple first sub-transistors T11 connected in parallel, and the third transistor T3 is a complete transistor structure without being divided into multiple parallel sub-transistors; or, the first transistor T1 is a complete transistor structure without being divided into multiple parallel sub-transistors, and the third transistor T3 includes multiple third sub-transistors T31 connected in parallel; or, the first transistor T1 includes multiple first sub-transistors T11 connected in parallel, and the third transistor T3 includes multiple third sub-transistors T31 connected in parallel.

[0281] In some examples, the first transistor T1 includes a plurality of first sub-transistors T11 arranged in parallel.

[0282] For example, there can be multiple first sub-clock signal lines 321. One first sub-transistor T11 in the first shift register 31 can be electrically connected to one first sub-clock signal line 321. Correspondingly, one first sub-clock signal line 321 can be electrically connected to multiple first sub-transistors T11, each belonging to a different first shift register 31.

[0283] For example, the number of first sub-clock signal lines 321 can be equal to the number of multiple first sub-transistors T11 included in one first transistor T1 in the first shift register 31.

[0284] For example, when the second sub-clock signal line 322 is electrically connected to the first sub-circuit 312 in the second shift register 31, there can be multiple second sub-clock signal lines 322. Specifically, one first sub-transistor T11 in the second shift register 31 can be electrically connected to one second sub-clock signal line 322. Correspondingly, one second sub-clock signal line 322 can be electrically connected to multiple first sub-transistors T11, each belonging to a different second shift register 31.

[0285] For example, the number of second sub-clock signal lines 322 can be equal to the number of multiple first sub-transistors T11 included in one first transistor T1 in the second shift register 31.

[0286] In some examples, the third transistor T3 includes multiple third sub-transistors T31 arranged in parallel.

[0287] For example, when the second sub-clock signal line 322 is electrically connected to the second sub-circuit 313 in the second shift register 31, there can be multiple second sub-clock signal lines 322. A third sub-transistor T31 in the second shift register 31 can be electrically connected to one second sub-clock signal line 322. Correspondingly, one second sub-clock signal line 322 can be electrically connected to multiple third sub-transistors T31, each belonging to a different second shift register 31.

[0288] For example, the number of second sub-clock signal lines 322 can be equal to the number of multiple third sub-transistors T31 included in one third transistor T1 in the second shift register 31.

[0289] Here, the aforementioned multiple first sub-clock signal lines 321 can be located in different first gap regions A1, and the aforementioned multiple second sub-clock signal lines 322 can be located in different first gap regions A1. This ensures that when clock signal lines 32 are provided in the first gap region A1, the number of clock signal lines 32 provided is only one, thereby avoiding affecting the uniformity of the sub-pixels 2 and ensuring the display effect of the display panel 100.

[0290] It should be noted that when the scan drive circuit 3 includes multiple clock signal lines 32, and also includes a third sub-clock signal line 323 and a fourth sub-clock signal line 324, the number of third sub-clock signal lines 323 and the number of fourth sub-clock signal lines 324 can be multiple. The configuration of the third sub-clock signal line 323 and the fourth sub-clock signal line 324 can refer to the configuration of the first sub-clock signal line 321 and the second sub-clock signal line 322, and will not be repeated here.

[0291] In some embodiments, such as Figures 5-8 and Figure 11a , Figure 11b As shown, the display area A also includes a second gap region A2 located between any two adjacent rows of sub-pixels 2. The second gap region A2 extends along the first direction X.

[0292] The multi-stage shift register 31 included in the scan drive circuit 3 has multiple possible settings within the display area A, which can be selected according to actual needs.

[0293] In some examples, the multiple transistors and capacitors in each stage shift register 31 can be divided into multiple device groups, and each device group can be located between any two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2.

[0294] In other examples, such as Figures 5-8 and Figure 11a , Figure 11b As shown, each shift register 31 can be located within the second gap region A2. That is, each shift register 31 can be located between two adjacent rows of sub-pixels 2. In this case, the multiple transistors and capacitors included in the shift register 31 do not need to be grouped.

[0295] Here, the number of shift registers 31 set in the second gap region A2 can be selected and set according to actual needs.

[0296] For example, when the number of shift registers 31 is greater than or equal to the number of rows of sub-pixels, one shift register 31 can be set in each second gap region A2. In this case, along the second direction Y, each row of sub-pixels 2 and each level of shift register 31 are alternately set. Alternatively, in a plurality of second gap regions A2, some second gap regions A2 are not set with shift registers 31, while each second gap region A2 in another part of the second gap regions A2 is set with two shift registers 31.

[0297] For example, when the number of shift registers 31 is less than the number of rows of sub-pixels, in a portion of the multiple second gap regions A2, no shift registers 31 are provided, while in another portion of the multiple second gap regions A2, each second gap region A2 is provided with one shift register 31. Alternatively, in a portion of the multiple second gap regions A2, no shift registers 31 are provided, while in another portion of the multiple second gap regions A2, each second gap region A2 is provided with two shift registers 31.

[0298] For example, such as Figure 11a , Figure 11b As shown, taking the example of a first-level shift register 31 electrically connected to a row of sub-pixels 2. Along the second direction Y, the two-level shift register 31 electrically connected to any two adjacent rows of sub-pixels 2 is located in the second gap region A1 between the two adjacent rows of sub-pixels 2.

[0299] Take the four adjacent sub-pixels 2 along the second direction Y as an example.

[0300] The aforementioned four rows of sub-pixels 2 can be referred to as the first row of sub-pixels, the second row of sub-pixels, the third row of sub-pixels, and the fourth row of sub-pixels. The shift registers 31 electrically connected to the first row of sub-pixels and the second row of sub-pixels can be located within the second gap region A2 between the first and second rows of sub-pixels. Similarly, the shift registers 31 electrically connected to the third and fourth rows of sub-pixels can be located within the second gap region A2 between the third and fourth rows of sub-pixels. No shift register 31 is located within the second gap region A2 between the second and third rows of sub-pixels.

[0301] In some examples, such as Figure 11a , Figure 11b As shown, each sub-pixel 2 includes a pixel driving circuit 21 and a light-emitting device 22 disposed along the second direction Y. The pixel driving circuit 21 and the light-emitting device 22 are electrically connected, and the pixel driving circuit 21 is configured to provide a driving voltage to the light-emitting device 22 to control the light-emitting state of the light-emitting device 22.

[0302] In the case where the two-stage shift register 31, which is electrically connected to any two adjacent rows of sub-pixels 2 along the second direction Y, is located within the second gap region A1 between the two adjacent rows of sub-pixels 2, the light-emitting devices 22 in the two adjacent rows of sub-pixels 2 are all closer to the two-stage shift register 31 relative to the pixel driving circuit 21. For example, the aforementioned two adjacent rows of sub-pixels 2 can be symmetrically arranged with respect to the second gap region A2 between the two adjacent rows of sub-pixels 2.

[0303] Taking three adjacent rows of sub-pixels 2 along the second direction Y as an example. These three rows of sub-pixels 2 can be referred to as the first row of sub-pixels, the second row of sub-pixels, and the third row of sub-pixels. Two shift registers 31 are provided in the second gap region A2 between the first and second rows of sub-pixels, while no shift registers 31 are provided in the second gap region A2 between the second and third rows of sub-pixels. The light-emitting devices 22 in the first and second rows of sub-pixels are closer to the second gap region A2 between them relative to the pixel driving circuit 21, while the light-emitting devices 22 in the second and third rows of sub-pixels are farther away from the second gap region A2 between them relative to the pixel driving circuit 21.

[0304] This reduces the distance between the shift register 31 and the pixel driving circuit 21 in the corresponding row of sub-pixels 2, making it easier for the two to form an electrical connection. It also ensures that the light-emitting devices 22 in multiple sub-pixels 2 have a high degree of distribution uniformity, thereby ensuring that the display panel 100 has a good display effect.

[0305] It should be noted that this example only limits the placement of the sub-pixel driving circuit 21 and the light-emitting device 22 in each sub-pixel 2, and does not limit whether the structures of the pixel driving circuit 21 and the light-emitting device 22 are symmetrical. Since both the pixel driving circuit 21 and the light-emitting device 22 include multiple film layers, during the fabrication of these multiple film layers, unavoidable reasons such as process errors may lead to differences in the film layer sizes of different pixel driving circuits 21, or differences in the film layer sizes of different light-emitting devices 22. Therefore, it is not possible to ensure that the sub-pixel driving circuits 21 in two adjacent rows of sub-pixels 2 are strictly symmetrically arranged with respect to the second gap region A2 located between the two adjacent rows of sub-pixels 2, nor is it possible to ensure that the light-emitting devices 22 in two adjacent rows of sub-pixels 2 are strictly symmetrically arranged with respect to the second gap region A2 located between the two adjacent rows of sub-pixels 2.

[0306] In some embodiments, such as Figure 10 As shown, the scan drive circuit 3 may also include: a start signal line 35, a display reset signal line 36, a global reset signal line 37, and a DC voltage signal line 38. Figure 6 In the table, A1, A2, A3, ... AN represent the first-level shift register 31, the second-level shift register 31, the third-level shift register 31, ... the Nth-level shift register 31, respectively.

[0307] For example, such as Figure 10 As shown, after cascading the multi-stage shift registers 31, the input signal terminal Iput of the first-stage shift register 31... <n>It can be electrically connected to the start signal line 35 to receive the start signal transmitted by the start signal line 35 as an input signal.

[0308] For example, further, the input signal terminal Iput of the shift register 31 other than the first-stage shift register 31 (e.g., the second-stage shift register 31) <n>The output signal Oput of the previous stage shift register 31 is not connected. <n>Electrical connection, the input signal terminal Iput of this part of the shift register 31 <n>It can then be electrically connected to the start signal line 35 to receive the start signal transmitted by the start signal line 35 as an input signal.

[0309] For example, such as Figure 10 As shown, after cascading the multi-stage shift registers 31, the display reset signal terminal STD of the last stage shift register 31 can be electrically connected to the display reset signal line 36 to receive the signal transmitted by the display reset signal line 35 as the display reset signal.

[0310] For example, further, the display reset signal STD of some shift registers 31 (e.g., the penultimate shift register 31) other than the last shift register 31 is not connected to the output signal Oput of the next shift register 31. <n>Electrically connected, the display reset signal terminal STD of this shift register 31 can be electrically connected to the display reset signal line 36, receiving the signal transmitted by the display reset signal line 36 as the display reset signal.

[0311] For example, such as Figure 10 As shown, the global reset signal terminal TRSE of each shift register 31 can be electrically connected to the global reset signal line 37 and receive the signal transmitted by the global reset signal line 37 as the global reset signal.

[0312] For example, such as Figure 10 As shown, the second voltage signal terminal VGH of each shift register 31 can be electrically connected to the DC voltage signal line 38 and receive the DC voltage signal transmitted by the DC voltage signal line 38 as the second voltage signal.

[0313] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A display panel, characterized in that, The display panel has a display area; the display panel includes: The display area comprises a plurality of sub-pixels; the plurality of sub-pixels are arranged in multiple rows along a first direction and in multiple columns along a second direction; the display area includes a first gap region located between two adjacent columns of sub-pixels; and... The scanning driving circuit includes a multi-stage shift register and multiple clock signal lines located in the display area; the multi-stage shift register includes a first shift register and a second shift register, and the multiple clock signal lines include a first sub-clock signal line and a second sub-clock signal line; The shift register includes: a first sub-circuit and a second sub-circuit; The first sub-clock signal line is electrically connected to the first sub-circuit in the first shift register, and the first sub-clock signal line is located in a first gap region adjacent to the first sub-circuit in the first shift register. The second sub-clock signal line is electrically connected to one of the first sub-circuit and the second sub-circuit in the second shift register, and the second sub-clock signal line is located in a first gap region adjacent to the sub-circuit electrically connected in the second shift register; The first sub-clock signal line and the second sub-clock signal line transmit the same clock signal, but they are located in different first gap regions.

2. The display panel according to claim 1, characterized in that, The second sub-clock signal line is electrically connected to the first sub-circuit in the second shift register, and the distance between the second sub-clock signal line and the first sub-circuit in the second shift register is smaller than the distance between the first sub-clock signal line and the first sub-circuit in the first shift register. or, The second sub-clock signal line is electrically connected to the second sub-circuit in the second shift register. The distance between the second sub-clock signal line and the second sub-circuit in the second shift register is less than the distance between the second sub-clock signal line and the first sub-circuit in the first shift register. The distance between the first sub-clock signal line and the first sub-circuit in the first shift register is less than the distance between the first sub-clock signal line and the second sub-circuit in the second shift register.

3. The display panel according to claim 2, characterized in that, When the second sub-clock signal line is electrically connected to the first sub-circuit in the second shift register, the first sub-clock signal line is farther away from the first sub-circuit in the first shift register and the first sub-circuit in the second shift register relative to the second sub-clock signal line. When the second sub-clock signal line is electrically connected to the second sub-circuit in the second shift register, the first sub-clock signal line is located between the first sub-circuit in the first shift register and the second sub-circuit in the second shift register, and the second sub-clock signal line is farther away from the first sub-clock signal line relative to the second sub-circuit in the second shift register.

4. The display panel according to claim 1, characterized in that, The multiple clock signal lines also include a third sub-clock signal line and a fourth sub-clock signal line; The third sub-clock signal line is electrically connected to the second sub-circuit in the first shift register, and the third sub-clock signal line is located in a first gap region adjacent to the second sub-circuit in the first shift register; The fourth sub-clock signal line is electrically connected to the other of the first and second sub-circuits in the second shift register, and the fourth sub-clock signal line is located in a first gap region adjacent to the sub-circuit electrically connected in the second shift register. The third sub-clock signal line and the fourth sub-clock signal line transmit the same clock signal, but they are located in different first gap regions.

5. The display panel according to claim 4, characterized in that, The first gap region where either the third sub-clock signal line or the fourth sub-clock signal line is located is different from the first gap region where either the first sub-clock signal line or the second sub-clock signal line is located.

6. The display panel according to claim 4, characterized in that, When the second sub-clock signal line is electrically connected to the first sub-circuit in the second shift register, the fourth sub-clock signal line is electrically connected to the second sub-circuit in the second shift register, and the distance between the fourth sub-clock signal line and the second sub-circuit in the second shift register is less than the distance between the third sub-clock signal line and the second sub-circuit in the first shift register. When the second sub-clock signal line is electrically connected to the second sub-circuit in the second shift register, the fourth sub-clock signal line is electrically connected to the first sub-circuit in the second shift register. The distance between the third sub-clock signal line and the second sub-circuit in the first shift register is less than the distance between the third sub-clock signal line and the first sub-circuit in the second shift register. The distance between the fourth sub-clock signal line and the second sub-circuit in the second shift register is less than the distance between the fourth sub-clock signal line and the second sub-circuit in the first shift register.

7. The display panel according to claim 6, characterized in that, When the second sub-clock signal line is electrically connected to the first sub-circuit in the second shift register, the third sub-clock signal line is farther away from the second sub-circuit in the first shift register and the second sub-circuit in the second shift register relative to the fourth sub-clock signal line; When the second sub-clock signal line is electrically connected to the second sub-circuit in the second shift register, the fourth sub-clock signal line is located between the second sub-circuit in the first shift register and the first sub-circuit in the second shift register, and the third sub-clock signal line is farther away from the fourth sub-clock signal line relative to the second sub-circuit in the first shift register.

8. The display panel according to claim 1, characterized in that, The first-level shift register is electrically connected to a row of sub-pixels; There are multiple first shift registers and multiple second shift registers; Multiple first shift registers are electrically connected to odd-numbered row sub-pixels, and multiple second shift registers are electrically connected to even-numbered row sub-pixels.

9. The display panel according to any one of claims 1 to 8, characterized in that, The scanning drive circuit also includes: A first bus electrically connected to the first sub-clock signal line and the second sub-clock signal line; the first bus is configured to transmit corresponding clock signals to the first sub-clock signal line and the second sub-clock signal line. In the case where the plurality of clock signal lines also include a third sub-clock signal line and a fourth sub-clock signal line, The scanning drive circuit also includes: A second bus electrically connected to the third sub-clock signal line and the fourth sub-clock signal line; the second bus is configured to transmit corresponding clock signals to the third sub-clock signal line and the fourth sub-clock signal line.

10. The display panel according to claim 9, characterized in that, The display panel also has a border area located next to the display area; Both the first bus and the second bus are located in the border area and extend along the first direction.

11. The display panel according to claim 9, characterized in that, The first sub-circuit is electrically connected to a first clock signal terminal, a pull-up node, a pull-down node, and a first voltage signal terminal; the first sub-circuit is configured to transmit the first clock signal to the pull-down node under the control of the first clock signal transmitted at the first clock signal terminal; and to control the voltage of the pull-down node under the control of the voltage of the pull-up node. The second sub-circuit is electrically connected to the second clock signal terminal, the pull-up node, and the output signal terminal; the second sub-circuit is configured to transmit the second clock signal received at the second clock signal terminal to the output signal terminal under the control of the voltage of the pull-up node. The first sub-clock signal line is electrically connected to the first sub-circuit in the first shift register through the first clock signal terminal; The second sub-clock signal line is electrically connected to the first sub-circuit in the second shift register through the first clock signal terminal; or, the second sub-clock signal line is electrically connected to the second sub-circuit in the second shift register through the second clock signal terminal. In the case where the plurality of clock signal lines also include a third sub-clock signal line and a fourth sub-clock signal line, The third sub-clock signal line is electrically connected to the second sub-circuit in the first shift register through the second clock signal terminal; The fourth sub-clock signal line is electrically connected to the second sub-circuit in the second shift register through the second clock signal terminal; or, the fourth sub-clock signal line is electrically connected to the first sub-circuit in the second shift register through the first clock signal terminal.

12. The display panel according to claim 11, characterized in that, The first sub-circuit includes: a first transistor and a second transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first clock signal terminal, and the second electrode of the first transistor is electrically connected to the pull-down node. The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the pull-down node, and the second electrode of the second transistor is electrically connected to the first voltage signal terminal. The second sub-circuit includes: a third transistor and a first capacitor; The control electrode of the third transistor is electrically connected to the pull-up node, the first electrode of the third transistor is electrically connected to the second clock signal terminal, and the second electrode of the third transistor is electrically connected to the output signal terminal. The first terminal of the first capacitor is electrically connected to the pull-up node, and the second terminal of the first capacitor is electrically connected to the output signal terminal. The first sub-clock signal line is electrically connected to the first transistor in the first shift register; The second sub-clock signal line is electrically connected to the first transistor in the second shift register; or, the second sub-clock signal line is electrically connected to the third transistor in the second shift register. In the case where the plurality of clock signal lines also include a third sub-clock signal line and a fourth sub-clock signal line, The third sub-clock signal line is electrically connected to the third transistor in the first shift register; The fourth sub-clock signal line is electrically connected to the third transistor in the second shift register; or, the fourth sub-clock signal line is electrically connected to the first transistor in the second shift register.

13. The display panel according to claim 12, characterized in that, The first transistor includes a plurality of first sub-transistors arranged in parallel; and / or, the third transistor includes a plurality of third sub-transistors arranged in parallel; There are multiple first sub-clock signal lines; one first sub-transistor in the first shift register is electrically connected to one first sub-clock signal line. When the second sub-clock signal line is electrically connected to the first sub-circuit in the second shift register, there are multiple second sub-clock signal lines; one first sub-transistor in the second shift register is electrically connected to one second sub-clock signal line. When the second sub-clock signal line is electrically connected to the second sub-circuit in the second shift register, there are multiple second sub-clock signal lines, and a third sub-transistor in the second shift register is electrically connected to one second sub-clock signal line.

14. The display panel according to claim 13, characterized in that, The first gap regions where the multiple first sub-clock signal lines are located are different; The first gap regions where the multiple second sub-clock signal lines are located are different.

15. The display panel according to claim 12, characterized in that, The multiple clock signal lines, the first and second terminals of the first transistor, the first and second terminals of the second transistor, and the first and second terminals of the third transistor are arranged on the same layer; In the case where the scanning drive circuit further includes a first bus and a second bus, the first bus, the second bus, the control electrode of the first transistor, the control electrode of the second transistor, the control electrode of the third transistor, and the first electrode of the first capacitor are arranged on the same layer.

16. The display panel according to any one of claims 1 to 8, characterized in that, The display area also includes a second gap region located between any two adjacent rows of sub-pixels; The shift register is located within the second gap region.

17. The display panel according to claim 16, characterized in that, Along the second direction, a shift register electrically connected to any two adjacent rows of sub-pixels is located in the second gap region between the two adjacent rows of sub-pixels.

18. The display panel according to claim 17, characterized in that, The sub-pixel includes a pixel driving circuit and a light-emitting device disposed along the second direction; In the two adjacent rows of sub-pixels, the light-emitting devices are all closer to the shift register than the pixel driving circuit.

19. The display panel according to any one of claims 1 to 8, characterized in that, The shift register also includes: An input circuit is electrically connected to an input signal terminal, a second voltage signal terminal, and a pull-up node; the input circuit is configured to transmit a second voltage signal received at the second voltage signal terminal to the pull-up node in response to an input signal received at the input signal terminal. A first reset circuit is electrically connected to the pull-down node, the pull-up node, and a first voltage signal terminal; the first reset circuit is configured to reset the pull-up node under the control of the voltage of the pull-down node. The second reset circuit is electrically connected to the output signal terminal, the pull-down node, and the first voltage signal terminal; the second reset circuit is configured to reset the pull-down node under the control of the output signal transmitted at the output signal terminal. A third reset circuit is electrically connected to the pull-down node, the output signal terminal, and the first voltage signal terminal; the third reset circuit is configured to reset the output signal terminal under the control of the voltage of the pull-down node. A fourth reset circuit is electrically connected to the display reset signal terminal, the pull-up node, and the third voltage signal terminal; the fourth reset circuit is configured to reset the pull-up node under the control of the display reset signal transmitted at the display reset signal terminal; and, The fifth reset circuit is electrically connected to the global reset signal terminal, the pull-up node, and the first voltage signal terminal; the fifth reset circuit is configured to reset the pull-up node under the control of the global reset signal transmitted at the global reset signal terminal.

20. The display panel according to claim 19, characterized in that, The input circuit includes: a fourth transistor; The control electrode of the fourth transistor is electrically connected to the input signal terminal, the first electrode of the fourth transistor is electrically connected to the second voltage signal terminal, and the second electrode of the fourth transistor is electrically connected to the pull-up node. The first reset circuit includes: a fifth transistor; The control electrode of the fifth transistor is electrically connected to the pull-down node, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first voltage signal terminal. The second reset circuit includes: a sixth transistor; The control electrode of the sixth transistor is electrically connected to the output signal terminal, the first electrode of the sixth transistor is electrically connected to the pull-down node, and the second electrode of the sixth transistor is electrically connected to the first voltage signal terminal. The third reset circuit includes: a seventh transistor and a second capacitor; The control electrode of the seventh transistor is electrically connected to the pull-down node, the first electrode of the seventh transistor is electrically connected to the output signal terminal, and the second electrode of the seventh transistor is electrically connected to the first voltage signal terminal. The first terminal of the second capacitor is electrically connected to the pull-down node, and the second terminal of the second capacitor is electrically connected to the first voltage signal terminal. The fourth reset circuit includes: an eighth transistor; The control electrode of the eighth transistor is electrically connected to the display reset signal terminal, the first electrode of the eighth transistor is electrically connected to the pull-up node, and the second electrode of the eighth transistor is electrically connected to the third voltage signal terminal. The fifth reset circuit includes: a ninth transistor; The control terminal of the ninth transistor is electrically connected to the global reset signal terminal, the first terminal of the ninth transistor is electrically connected to the pull-up node, and the second terminal of the ninth transistor is electrically connected to the first voltage signal terminal.

21. A display device, characterized in that, The display device includes: a display panel as described in any one of claims 1 to 20.

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