Predicting load current and control current in a power converter using output voltage threshold with pre-seed target current value

Abstract

A system for controlling current in a power converter configured to generate an output voltage, the system can include a control loop having a plurality of comparators each having a respective reference voltage to which the output voltage is compared; a digital controller configured to calculate one or more pre-seed control parameters for the current; and an analog state machine configured to select a control parameter for controlling the current based on outputs of the plurality of comparators. The control parameter can be selected from the pre-seed control parameters, a control parameter for controlling the current to have a zero magnitude, and a control parameter for controlling the current to have a maximum magnitude.

Description

Technical Field

[0001] This disclosure generally relates to circuits for electronic devices, including but not limited to personal audio devices such as cordless phones and media players, and more specifically, to predicting load current and control current in power converters using output voltage thresholds. Background Technology

[0002] Personal audio devices (including cordless phones, such as mobile / cellular phones, MP3 players, and other consumer audio devices) are widely used. Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers. This circuitry typically includes a speaker driver that includes a power amplifier for driving the audio output signal to the headphones or speakers. Typically, a power converter can be used to supply power voltage to the power amplifier in order to amplify the signal driven to the speakers, headphones, or other transducers. A switching power converter is an electronic circuit that converts a power supply from one direct current (DC) voltage level to another DC voltage level. Examples of such switching DC-DC converters include, but are not limited to, boost converters, buck converters, buck-boost converters, inverting buck-boost converters, and other types of switching DC-DC converters. Therefore, using a power converter, DC voltage, such as that provided by a battery, can be converted to another DC voltage to power a power amplifier.

[0003] A power converter can be used to provide a power voltage rail to one or more components in a device. Therefore, it may be desirable to regulate the output voltage of the power converter with minimal ripple in the presence of time-varying currents and power loads. Summary of the Invention

[0004] Based on the teachings of this disclosure, one or more disadvantages and problems associated with existing methods for regulating the output voltage of power converters can be reduced or eliminated.

[0005] According to embodiments of this disclosure, a system for controlling current in a power converter may include: an external control loop configured to use an external set of output voltage thresholds for the output voltage generated by the power converter to provide hysteretic control of the current; and an internal control loop configured to use an internal set of output voltage thresholds for the output voltage to provide continuous control of the current, the internal control loop also being configured to measure the duration required for the output voltage to exceed a single pair of two output voltage thresholds of the internal set of output voltage thresholds to determine an input reference estimate of the current load of the power converter, and to set a peak current threshold and a valley current threshold based on the input reference estimate of the current load.

[0006] According to these and other embodiments of the present disclosure, a system may include: an inductive power converter configured to receive an input voltage and generate an output voltage; and a switching controller for controlling the switching of the inductive power converter to define a charging state and a delivery state of the inductive power converter, wherein the switching controller includes a plurality of comparators, each comparator having a respective reference voltage for comparison with the output voltage, and wherein the plurality of comparators are used to control the inductive power converter in one or both of a hysteresis control mode and a continuous control mode.

[0007] According to these and other embodiments of the present disclosure, a method for controlling current in a power converter may include: applying an external control loop configured to use an external set of output voltage thresholds for an output voltage generated by the power converter to provide hysteretic control of the current; and applying an internal control loop configured to use an internal set of output voltage thresholds for an output voltage to provide continuous control of the current, the internal control loop being further configured to measure the duration required for the output voltage to exceed a single pair of two output voltage thresholds of the internal set of output voltage thresholds to determine an input reference estimate of the current load of the power converter, and setting a peak current threshold and a valley current threshold based on the input reference estimate of the current load.

[0008] According to these and other embodiments of the present disclosure, a method may include controlling the switching of an inductor power converter to define a charging state and a delivery state of the inductor power converter, wherein the power converter is configured to receive an input voltage and generate an output voltage, and wherein the control includes using a plurality of comparators for controlling the inductor power converter in one or both of a hysteresis control mode and a continuous control mode, each comparator having a respective reference voltage for comparison with the output voltage.

[0009] According to these and other embodiments of this disclosure, a system for controlling current in a power converter configured to generate an output voltage may include a control loop having a plurality of comparators, each comparator having a respective reference voltage for comparison with the output voltage, a digital controller configured to calculate one or more pre-seeded control parameters for the current, and an analog state machine configured to select control parameters for controlling the current based on the outputs of the plurality of comparators. The control parameters may be selected from pre-seeded control parameters, control parameters for controlling the current with zero amplitude, and control parameters for controlling the current with maximum amplitude.

[0010] According to these and other embodiments of this disclosure, a method for controlling current in a power converter configured to generate an output voltage may include using a control loop having a plurality of comparators, each comparator having a respective reference voltage for comparison with the output voltage, a digital controller configured to calculate one or more pre-seed control parameters for the current, and an analog state machine configured to select control parameters for controlling the current based on the outputs of the plurality of comparators. The control parameters may be selected from pre-seed control parameters, control parameters for controlling the current with zero amplitude, and control parameters for controlling the current with maximum amplitude.

[0011] According to these and other embodiments of the present disclosure, a method for randomizing inductor current in at least one of a plurality of parallel-coupled peak / valley current-controlled power converters may include comparing inductor current with a threshold to generate a comparison signal, delaying the comparison signal by a plurality of delay amounts to generate a plurality of delayed versions of the comparison signal, and randomly selecting one of the plurality of delayed versions of the comparison signal for controlling the inductor current during one or both of a charging state and a delivery state of at least one of the plurality of parallel-coupled peak / valley current-controlled power converters.

[0012] According to these and other embodiments of the present disclosure, a method for randomizing inductor current in at least one of a plurality of parallel-coupled peak / valley current-controlled power converters may include randomly selecting an offset current parameter, adding the offset current parameter to a reference current parameter to generate a modified reference current parameter, and comparing the inductor current with the modified reference current parameter to control the inductor current during one or both of a charging state and a transfer state of at least one of the plurality of parallel-coupled peak / valley current-controlled power converters.

[0013] According to these and other embodiments of the present disclosure, a system for randomizing inductor current in at least one of a plurality of parallel-coupled peak / valley current-controlled power converters may include: a comparator configured to compare inductor current with a threshold to generate a comparison signal; a delay element configured to delay the comparison signal by a plurality of delay amounts to generate a plurality of delayed versions of the comparison signal; and selection logic configured to randomly select one of the plurality of delayed versions of the comparison signal for controlling the inductor current during one or both of a charging state and a delivery state of at least one of the plurality of parallel-coupled peak / valley current-controlled power converters.

[0014] According to these and other embodiments of the present disclosure, a system for randomizing inductor current in at least one of a plurality of parallel-coupled peak / valley current-controlled power converters may include: selection logic configured to randomly select an offset current parameter; a combiner configured to add the offset current parameter to a reference current parameter to generate a modified reference current parameter; and a comparator configured to compare the inductor current with the modified reference current parameter to control the inductor current during one or both of a charging state and a transfer state of at least one of the plurality of parallel-coupled peak / valley current-controlled power converters.

[0015] According to these and other embodiments of the present disclosure, a system may include: a power converter configured to receive an input voltage and generate an output voltage; and a controller configured to control the operation of the power converter based on a comparison of the output voltage with at least one output voltage threshold, and to set at least one output voltage threshold based on the input voltage.

[0016] According to these and other embodiments of the present disclosure, a method may include controlling the operation of a power converter configured to receive an input voltage and generate an output voltage, such control being based on a comparison of the output voltage with at least one output voltage threshold; and setting at least one output voltage threshold based on the input voltage.

[0017] According to these and other embodiments of this disclosure, a system may include: a power converter configured to receive an input voltage and generate an output voltage; and a controller configured to control the operation of the power converter based on a comparison of a current associated with the power converter with a threshold current, and to control the threshold current according to the input voltage.

[0018] According to these and other embodiments of the present disclosure, a method may include controlling the operation of a power converter configured to receive an input voltage and generate an output voltage, such control being based on a comparison of a current associated with the power converter with a threshold current, and controlling the threshold current according to the input voltage.

[0019] The technical advantages of this disclosure will be apparent to those skilled in the art from the accompanying drawings, description, and claims included herein. The objects and advantages of the embodiments will be realized and obtained, at least by means of the elements, features, and combinations particularly pointed out in the claims.

[0020] It should be understood that both the foregoing general description and the following detailed description are illustrative and explanatory, and are not intended to limit the claims set forth in this disclosure. Attached Figure Description

[0021] A more complete understanding of this embodiment and its advantages can be obtained by referring to the following description taken in conjunction with the accompanying drawings, wherein similar reference numerals indicate similar features, and wherein:

[0022] Figure 1 An example mobile device according to an embodiment of the present disclosure is shown;

[0023] Figure 2 A block diagram of selected components inside a mobile device according to an embodiment of the present disclosure is shown;

[0024] Figure 3A A block diagram of selected components of an example boost converter having multiple operating modes according to an embodiment of the present disclosure is shown, depicting operation in bypass mode;

[0025] Figure 3B A block diagram of selected components of an example boost converter having multiple operating modes according to an embodiment of the present disclosure is shown, depicting operation in boost activation mode;

[0026] Figure 3C A block diagram of selected components of an example boost converter having multiple operating modes according to an embodiment of the present disclosure is shown, depicting operation in a boost inactive mode;

[0027] Figure 4 A graph showing the inductor current through a phase of a boost converter and the control signal of the phase switch over time is shown according to an embodiment of the present disclosure.

[0028] Figure 5 A block diagram of selected components of an example control circuit for a boost converter according to an embodiment of the present disclosure is shown;

[0029] Figure 6 The following is shown in accordance with this disclosure: Figures 3A-3C Example graph of the power supply voltage generated by the boost converter over time;

[0030] Figure 7 The waveforms of the power supply voltage generated by the power converter over a period of time and the waveforms of the inductor current in the power converter over the same period of time are shown according to the present disclosure.

[0031] Figure 8 An embodiment according to this disclosure is shown. Figure 5 A block diagram of selected components of the external control loop subsystem of the current controller shown.

[0032] Figure 9 Example waveforms depicting an external loop control of a boost converter according to embodiments of the present disclosure are shown.

[0033] Figure 10 An embodiment according to this disclosure is shown. Figure 5 A block diagram of selected components of the internal control loop subsystem of the current controller shown.

[0034] Figure 11 Example waveforms depicting an example of internal loop control of a boost converter according to an embodiment of the present disclosure are shown;

[0035] Figure 12 Example waveforms depicting an example of internal loop control of a boost converter under light load conditions, according to embodiments of the present disclosure, are shown.

[0036] Figure 13 A block diagram of selected components of another example control circuit for a boost converter according to an embodiment of the present disclosure is shown;

[0037] Figure 14 An embodiment according to this disclosure is shown. Figure 13 A block diagram of selected components of the internal control loop subsystem of the current controller shown.

[0038] Figure 15 An embodiment according to this disclosure is shown. Figure 13 A block diagram of selected components of the external control loop subsystem of the current controller shown.

[0039] Figure 16 A block diagram of selected components of an example peak / valley controller according to an embodiment of the present disclosure is shown;

[0040] Figures 17A-17C Graphs of various example waveforms of battery current, boost converter inductor current, and boost converter control signal over time are shown according to embodiments of the present disclosure.

[0041] Figure 18 A block diagram of selected components of an example peak / valley controller having a circuit for performing time-domain phase randomization of inductor currents in a boost converter, according to an embodiment of the present disclosure, is shown.

[0042] Figure 19 A graph showing an example waveform of the inductor current of a boost converter with time-domain phase randomization according to an embodiment of the present disclosure is provided.

[0043] Figure 20 A block diagram of selected components of an example peak / valley controller having a circuit for performing level-domain phase randomization of inductor current in a boost converter, according to an embodiment of the present disclosure, is shown.

[0044] Figure 21A graph showing an example waveform of the inductor current of a boost converter with level-domain phase randomization according to an embodiment of the present disclosure is provided.

[0045] Figure 22 Graphs of various example waveforms of load current delivered from the boost converter, power supply voltage generated by the boost converter, and inductor current of a phase of the boost converter, according to embodiments of the present disclosure, are shown.

[0046] Figure 23 Graphs of various example waveforms of the load current delivered from the boost converter, the threshold voltage for regulating the power supply voltage generated by the boost converter, the power supply voltage, and the sensed voltage at the input of the boost converter are shown according to embodiments of the present disclosure.

[0047] Figure 24 Selected components of a control subsystem according to an embodiment of the present disclosure are shown to provide voltage domain hysteresis control of a threshold voltage to regulate a power supply voltage generated by a boost converter;

[0048] Figure 25 Graphs of various example waveforms of the sensed voltage at the input of the boost converter and the flag for switching the threshold voltage to adjust the power supply voltage generated by the boost converter are shown according to embodiments of the present disclosure.

[0049] Figure 26 Selected components of a control subsystem according to embodiments of the present disclosure are shown to provide time-domain hysteresis control of a threshold voltage to regulate a power supply voltage generated by a boost converter;

[0050] Figure 27 Graphs of various example waveforms of the sensed voltage at the input of the boost converter and the flag for switching the threshold voltage to adjust the power supply voltage generated by the boost converter are shown according to embodiments of the present disclosure.

[0051] Figure 28 Selected components of a control subsystem provided according to embodiments of the present disclosure for controlling a threshold voltage to regulate a power supply voltage generated by a boost converter are shown.

[0052] Figure 29 The diagram shows graphs of the sensed voltage at the input of the boost converter, a flag for switching the threshold voltage to adjust the power supply voltage generated by the boost converter, and various example waveforms of the power supply voltage according to embodiments of the present disclosure.

[0053] Figure 30 Graphs showing various example waveforms of the power supply voltage generated by the boost converter and the inductor current of the phase of the boost converter according to embodiments of the present disclosure; and

[0054] Figure 31 Graphs of various example waveforms of the power supply voltage generated by the boost converter, the inductor current of the phase of the boost converter, and the sensed voltage at the input of the boost converter are shown according to embodiments of the present disclosure. Detailed Implementation

[0055] Figure 1 An example mobile device 1 according to an embodiment of the present disclosure is shown. Figure 1 A mobile device 1 is described, which is coupled to an earphone 3 in the form of a pair of earbud speakers 8A and 8B. Figure 1 The earphone 3 described herein is merely an example, and it is understood that the mobile device 1 can be connected to and used with various audio transducers, including but not limited to earphones, earbuds, in-ear headphones, and external speakers. The plug 4 provides an electrical terminal connection between the earphone 3 and the mobile device 1. The mobile device 1 can provide a display to the user and receive user input using a touchscreen 2, or alternatively, a standard liquid crystal display (LCD) can be combined with various buttons, sliders, and / or dials disposed on the surface and / or sides of the mobile device 1.

[0056] Figure 2 A block diagram is shown illustrating selected components integrated into a mobile device 1 according to an embodiment of the present disclosure. Figure 2 As shown, the mobile device 1 may include a boost converter 20, which is configured to boost the battery voltage V BAT The voltage is boosted to generate a power supply voltage V for multiple downstream components 18 of the mobile device 1. SUPPLY Downstream components 18 of mobile device 1 may include any suitable functional circuitry or devices of mobile device 1, including but not limited to processors, audio encoders / decoders, amplifiers, display devices, etc. Figure 2 As shown, the mobile device 1 may also include a battery charger 16 for charging the battery 22.

[0057] In some embodiments of the mobile device 1, the boost converter 20 and the battery charger 16 may be the only components of the mobile device 1 electrically coupled to the battery 22, and the boost converter 20 may be electrically connected between the battery 22 and all downstream components of the mobile device 1. However, in other embodiments of the mobile device 1, some downstream components 18 may be directly electrically coupled to the battery 22.

[0058] Figure 3A A block diagram of selected components of an example boost converter 20 having multiple operating modes according to an embodiment of the present disclosure is shown, depicting operation in bypass mode. Figure 3AAs shown, the boost converter 20 may include a battery 22, multiple inductive boost phases 24, a sensing capacitor 26, a sensing resistor 28, a bypass switch 30, and a control circuit 40. Figure 3A As shown, each inductor boost phase 24 may include a power inductor 32, a charging switch 34, a rectifier switch 36, and an output capacitor 38.

[0059] although Figures 3A-3C A boost converter 20 with three inductor boost phases 24 is depicted, but embodiments of the boost converter 20 may have any suitable number of inductor boost phases 24. In some embodiments, the boost converter 20 may include three or more inductor boost phases 24. In other embodiments, the boost converter 20 may include fewer than three phases (e.g., single-phase or two-phase).

[0060] The boost converter 20 can supply power at the voltage V generated by the boost converter 20. SUPPLY The minimum voltage V is greater than the threshold. MIN It operates in bypass mode. In some embodiments, this threshold minimum voltage V MIN It can be a function of the monitored current (e.g., the current through sensing resistor 28). In some embodiments, this threshold minimum voltage V MIN It can change according to the monitored changes in current, so as to change from the power supply voltage V SUPPLY The power supply components provide the desired headroom. Control circuitry 40 can be configured to sense the power supply voltage V. SUPPLY and power supply voltage V SUPPLY With threshold minimum voltage V MIN Comparison. At power supply voltage V SUPPLY The voltage VDD_SENSE across sensing capacitor 26 is greater than the threshold minimum voltage V MIN In this case, control circuit 40 can activate (e.g., enable, close, turn on) bypass switch 30 and one or more rectifier switches 36 and deactivate (e.g., disable, open, turn off) charging switch 34. In this bypass mode, the resistors of rectifier switch 36, power inductor 32, and bypass switch 30 can be combined to minimize the voltage difference between battery 22 and power supply voltage V. SUPPLY The total effective resistance of the path between them.

[0061] Figure 3B A block diagram of selected components of an example boost converter 20 according to an embodiment of the present disclosure is shown, depicting its operation in boost activation mode. When the supply voltage V... SUPPLY Insufficient to reduce the power supply voltage V SUPPLY Maintain at the threshold minimum voltage V MINWhen above, the boost converter 20 can operate in boost activation mode. In boost activation mode, the control circuit 40 can deactivate (e.g., disable, disconnect, turn off) the bypass switch 30, and generate appropriate control signals P1, P2, P3 and The charging switch 34 of the inductor boost phase 24 (e.g., during the charging state of phase 24) and the rectifier switch 36 (e.g., during the passing state of phase 24) are periodically commutated (as described in more detail below) to transfer current I. BAT and boost battery voltage V BAT Delivered to a higher supply voltage V SUPPLY In order to supply voltage V SUPPLY The electrical nodes provide the programmed (or servo-driven) desired current (e.g., average current) while maintaining the supply voltage V. SUPPLY The minimum voltage above the threshold V MIN In boost activation mode, the voltage VDD_SENSE may drop below the threshold minimum voltage V. MIN Furthermore, in boost activation mode, boost converter 20 can operate as a single-phase boost converter or a multi-phase boost converter.

[0062] In boost activation mode, control circuit 40 can operate boost converter 20 by operating inductor boost phase 24 in peak and valley detection operations, as described in more detail. The switching frequency generated by charging switch 34 and rectifier switch 36 of inductor boost phase 24 can be determined by the sensed voltage VDD_SENSE and the supply voltage V SUPPLY The inductance and programmed ripple parameters of the power inductor 32A (e.g., the configuration of the target current ripple in the power inductor 32A) are determined.

[0063] Figure 3C A block diagram of selected components of a boost converter 20 according to an embodiment of the present disclosure is shown, depicting its operation in boost inactive mode. When the power supply voltage V generated by the boost converter 20... SUPPLY Rise above the minimum threshold voltage V MIN and hysteresis voltage V HYST The sum of these values, and the sensed voltage VDD_SENSE remains below the threshold minimum voltage V MIN When the boost converter 20 is in a boost inactive mode, the control circuit 40 can deactivate (e.g., disable, disconnect, or turn off) the bypass switch 30, the charging switch 34, and the rectifier switch 36. Therefore, when the sensed voltage VDD_SENSE remains below the threshold minimum voltage V... MINAt this time, the control circuit 40 prevents the boost converter 20 from entering bypass mode so as not to draw voltage from the power supply V. SUPPLY Restore power to battery 22. Additionally, if the power supply voltage V... SUPPLY It should drop below the minimum threshold voltage V MIN Then the control circuit 40 can make the boost converter 20 re-enter the boost activation mode so as to make the power supply voltage V SUPPLY Increase to the threshold minimum voltage V MIN and hysteresis voltage V HYST sum.

[0064] As described above, when the boost converter 20 operates in boost activation mode, the control circuit 40 can provide inductor current I through power inductors 32A, 32B, and 32C, respectively. L1 I L2 and I L3 Lag current control. Figure 4 An inductor current I according to an embodiment of the present disclosure is shown. L1 Example curves of control signal P1 over time. Figure 4 As shown, the control circuit 40 can generate a control signal P1 of phase 24A and So that: (a) when the inductor current I L1 Drops below the valley current threshold I val1 When the inductor current I is reached, the control circuit 40 can activate the charging switch 34A and deactivate the rectifier switch 36A; and (b) when the inductor current I is reached... L1 Increase to above the peak current threshold I pk1 At this time, control circuit 40 can deactivate charging switch 34A and activate rectifier switch 36A. Therefore, control circuit 40 can provide control over inductor current I. L1 The hysteresis control makes the inductor current I... L1 At the approximate valley current threshold I val1 and approximate peak current threshold I pk1 The inductor current I varies between these values. L1 With average current I avg1 and ripple current I ripple , so that:

[0065] and

[0066]

[0067] Control circuit 40 can also generate control signals P2 for phases 24B and 24C. P3 and To provide the inductor current I L2 and I L3 Similar or identical controls.

[0068] Figure 5 A block diagram of selected components of a control circuit 40 according to an embodiment of the present disclosure is shown. Figure 5 As shown, the control circuit 40 may include multiple comparators 42A, 42B, 42C, and 42D, each comparator being configured to convert the power supply voltage V... SUPPLY Each voltage is compared with its respective threshold voltages V1, V2, V3 and V4, and a comparison signal C1, C2, C3 and C4 is generated.

[0069] Based on comparison signals C1, C2, C3, and C4, the load estimator 44 of the control circuit 40 can implement an internal control loop to estimate the load seen at the output of the boost converter 20 and, based on it, generate the battery current I. BAT Target average current I avg The internal control loop can be said to provide control over the inductor current I. L Continuous control. Furthermore, based on comparison signals C1, C2, and C4, and the target average current I... avg The current controller 46 of the control circuit 40 can implement an external control loop. Both the internal and external control loops can be used to set the valley current threshold I. val Peak current threshold I pk And a control signal ENABLE for selectively enabling or disabling the boost activation mode of boost converter 20. During operation, the internal control loop can maximize the efficiency of boost converter 20 and minimize the voltage V. SUPPLY The ripple on the power supply can be limited by an external control circuit, while the external control circuit can limit the power supply voltage V. SUPPLY Maximum ripple. Based on the valley current threshold I. val and peak current threshold I pk The peak / valley controller 48 of the control circuit 40 can generate control signals for controlling the power converter 20.

[0070] Figure 6 The power supply voltage V according to this disclosure is shown. SUPPLY Example graphs over time. (e.g.) Figure 6 As shown, threshold voltages V1, V2, V3, and V4 can reduce the power supply voltage V SUPPLY The size is divided into five different regions: A, B, C, D, and E. Figure 6 This demonstrates how the load estimator 44 can adjust the target average current I in each of the five different regions A, B, C, D, and E. avg .

[0071] Region A can be referred to as the MAX region. In this region, the supply voltage V... SUPPLYThe voltage is below the undervoltage threshold represented by the threshold voltage V1. Therefore, in region A, the load estimator 44 can determine the target average current I. avg Set it to its maximum value to result in as much inductor current I as possible. L (For example, I) L1 I L2 I L3 To minimize the power supply voltage V SUPPLY The decline.

[0072] Region B can be referred to as the INCREMENT region. Within this region between the threshold voltages V1 and V2, the load estimator 44 can recursively increase the target average current I. avg To increase the current delivered by the boost converter 20, thereby increasing the supply voltage V. SUPPLY The load estimator 44 can use multiplicative recursion (e.g., I...). avg(i+1) =I avg(i) x a1, where a1>1), addition recursion (e.g., I avg(i+1) =I avg(i) +a2, where a2>0) or any other recursive method to increase the target average current I avg .

[0073] Region C can be referred to as the measurement region, where V SUPPLY Between threshold voltages V2 and V3. In region C, load estimator 44 can measure the power supply voltage V. SUPPLY The time taken to exceed threshold voltages V2 and V3, and the target average current I can be updated accordingly. avg As described in more detail below.

[0074] Region D can be referred to as the decrement region. Within this region between the threshold voltages V3 and V4, the load estimator 44 can recursively decrement the target average current I. avg To reduce the current delivered by the boost converter 20, thereby reducing the supply voltage V. SUPPLY The load estimator 44 can use multiplicative recursion (e.g., I...). avg(i+1) =I avg(i) x a1, where a1<1), addition recursion (e.g., I avg(i+1) =I avg(i) +a2, where a2<0) or any other recursive method to decrease the target average current I. avg .

[0075] Region E can be referred to as the hold region. In this region above the threshold voltage V4, the load estimator 44 can hold or maintain the decreasing target average current I.avg value (e.g., I avg(i+1) = I avg(i) ).

[0076] As discussed above, when in region C, load estimator 44 measures power supply voltage V SUPPLY the time it takes to exceed threshold voltages V2 and V3, and this measurement can be used to update the target average current I avg . For illustration, reference is made to Figure 7 , which depicts the power supply voltage V SUPPLY over a period of time and the inductor current I L (e.g., inductor current I L1 , I L2 , I L3 ) over the same period. As Figure 7 shows, load estimator 44 can measure the time Δt1 that it takes for power supply voltage V SUPPLY to increase from threshold voltage V2 to threshold voltage V3. The change in voltage from threshold voltage V2 to threshold voltage V3 divided by the time Δt1 can define a slope s1. Similarly, load estimator 44 can measure the time Δt2 that it takes for power supply voltage V SUPPLY to decrease from threshold voltage V3 to threshold voltage V2. The change in voltage from threshold voltage V3 to threshold voltage V2 divided by the time Δt2 can define a slope s2. During a rising edge of power supply voltage V SUPPLY , the average inductor current I through the single power inductor 32 avg(i) can be defined as rising current I R , while during a falling edge of power supply voltage V SUPPLY , the average inductor current I through the single power inductor 32 avg(i) can be defined as falling current I F .

[0077] Using the charge balance relationship of the output capacitor 38 coupled to power supply voltage V SUPPLY , load estimator 44 can update the target average current I drawn from the battery 22 avg . For example, using the measurement of rising current I R , the target average current I avg can be updated according to the following:

[0078]

[0079] where D' i is equal to 1 minus the duty cycle of inductor current I L , and C out is the capacitance of the output capacitor 38. the quotient It can be unknown or uncertain, but it can be estimated. For example, in some embodiments, the load estimator 44 can use a fixed-value estimator. However, if the input voltage is known (e.g., voltage VDD_SENSE), then D′ i The reciprocal of the power supply voltage V can be approximated as equal to the power supply voltage V. SUPPLY Divide by the quotient of this input voltage. Therefore, the target average current I is used to update the... avg The aforementioned formula can be written as:

[0080]

[0081] However, due to the output capacitor C out The approximation and the assumption of a lossless boost converter 20 mean that this relationship may have uncertainties. However, by using the rising current I given by the following formula... R and the falling current I F These two measurements can eliminate this uncertainty:

[0082]

[0083] If we assume that the voltage increase from threshold voltage V2 to threshold voltage V3 is quantitatively equal to the voltage decrease from threshold voltage V3 to threshold voltage V2, then the target average current I is used to update... avg The aforementioned formula can be written as:

[0084]

[0085] The above is used to update the target average current I avg Both methods likely have their own advantages and disadvantages. For example, updating based on a current measurement might be better at detecting large, fast transients, but this is less effective due to the influence of duty cycle and output capacitance C. out The assumptions made may be inaccurate, and it also assumes that voltage changes and current measurements are known precisely. Updates based on the two current measurements may be more robust to offsets in voltage changes and current measurements, but this approach assumes that the load on the power converter 20 is constant across both measurements, which may not be the case, especially in the presence of large transients. Therefore, in some embodiments, a hybrid approach may be used, where a single measurement method is used if only one measurement is available, or if the single measurement is larger (or smaller) than the dual measurement method by more than the uncertainty range of the single measurement method, and otherwise a dual measurement method is used.

[0086] Figure 8 A block diagram of selected components of the external loop control subsystem 50 of the current controller 46 according to an embodiment of the present disclosure is shown. Figure 8As shown, the current controller 46 can be implemented using logic inverters 52A and 52B, set-reset latches 54A and 54B, and multiplexers 56A and 56B.

[0087] The logic inverter 52A inverts the comparison signal C2, and the set-reset latch 54A generates the control signal ENABLE with a delay, so that the power supply voltage V... SUPPLY When the voltage drops below the threshold voltage V2, the control signal ENABLE is activated (asserted), and the power supply voltage V... SUPPLY When the voltage rises above the threshold voltage V4, the control signal ENABLE is deasserted. When the control signal ENABLE is deasserted, the control circuit 40 can disable the charging switch 34 and the rectifier switch 36, and the power converter 20 can operate in boost inactive mode.

[0088] Furthermore, inverter 52B can invert the comparison signal C1, and set-reset latch 54B can generate the control signal MAX_ENABLE with hysteresis, which indicates whether the control circuit 40 should generate the target average current I. avg The maximum value. Receiving the control signal RESET_MAX can disable the control signal MAX_ENABLE, thereby reducing the threshold value of the peak current I. pk Valley current threshold I val The control is returned to the internal control loop. The 56A multiplexer can be configured based on the control signal MAX_ENABLE and the peak current threshold I. pk The maximum value and target peak current threshold I pk (For example, the target average current I calculated by the load estimator 44) avg Export), generate peak current threshold I pk Similarly, the multiplexer 56B can be based on the control signal MAX_ENABLE, the valley current threshold I... val Maximum value and target valley current threshold I val (For example, the target average current I calculated by the load estimator 44) avg Export), generate valley current threshold I val .

[0089] To further illustrate the control via the external loop of the current controller 46, refer to... Figure 9 .like Figure 9 As shown, in region I of the waveform, the power supply voltage V SUPPLYIf the threshold voltage V4 is exceeded, the boost converter 20 can be placed in boost inactive mode because the set-reset latch 54A may cause the control signal ENABLE to fail, resulting in high impedance for the boost converter 20. Therefore, in region I, the load on the boost converter 20 may cause the supply voltage V to be affected. SUPPLY The decrease.

[0090] When the power supply voltage V SUPPLY When the voltage drops below the threshold voltage V2, the set-reset latch 54A enables the control signal ENABLE, and the boost converter 20 can enter boost activation mode. Figure 9 In region II of the waveform shown, the load estimator 44 can actually achieve the target average current I performed by the load estimator 44. avg The estimation is used to control the peak current threshold I. pk Valley current threshold I val However, in Figure 9 In the specific example shown, the load estimator 44 may not be able to "turn around" the supply voltage V quickly enough. SUPPLY And the power supply voltage V SUPPLY It may continue to decrease.

[0091] Therefore, the power supply voltage V SUPPLY The voltage may drop below the threshold voltage V1, causing the set-reset latch 54B to be set, activating the control signal MAX_ENABLE, and forcing the peak current I... pk and target valley current I val exist Figure 9 They reach their maximum values ​​(maximum peak current I) in region III. pk-max and the maximum valley current I avg-max ). At power supply voltage V SUPPLY After sufficient increase, the set-reset latch 54B can reset and disable the control signal MAX_ENABLE, and the load estimator 44 can regain control, as shown in region IV of the waveform. If the power supply voltage V SUPPLY If the voltage is increased further beyond the threshold voltage V4, the set-reset latch 54A can disable the control signal ENABLE again, causing the boost converter 20 to enter the boost inactive mode.

[0092] Therefore, the external loop implemented by the current controller 46 can switch the boost converter 20 between maximum current and high impedance states, and change the power supply voltage V. SUPPLY The ripple is limited to approximately between the threshold voltages V1 and V4, even though the internal loop control of the load estimator 44 cannot regulate the power supply voltage V. SUPPLY hour.

[0093] Figure 10 A block diagram of selected components of the internal control loop subsystem 60 of the current controller 46 according to an embodiment of the present disclosure is shown. Figure 11 Example waveforms depicting an example of the internal loop control of a boost converter 20 according to an embodiment of the present disclosure are shown.

[0094] like Figure 10 As shown, the internal control loop subsystem 60 can receive the target average current I calculated by the load estimator 44. avg This target average current I avg Divide by the number n of phases 24 present in boost converter 20, and apply each of the positive offset +Δ and negative offset –Δ to the target average current I through offset blocks 62A and 62B respectively. avg The results from offset blocks 62A and 62B can be saturated to minimum values ​​by saturation blocks 64A and 64B respectively, to generate rising currents I. R and the falling current I F Adder blocks 68A and 68B can reduce the ripple current I. ripple Half of it is added to the rising current I R and the falling current I F Each of them, and adder blocks 70A and 70B can draw from the rising current I R and the falling current I F Subtract the ripple current I from each of the values ​​in the equation. ripple Half of it. Based on comparison signals C2 and C3, latch 66 can selectively enable and disable control signal TOGGLE to switch the selection of multiplexers 72A and 72B so that:

[0095] • Due to the power supply voltage V SUPPLY When the voltage drops below the threshold voltage V2 and the control signal TOGGLE is active, an intermediate peak current threshold I is generated. pk ′ and intermediate valley current threshold I val ′, making I pk ′=I R +I ripple / 2 and I val ′=I R -I ripple / 2, and the average inductor current is the rising current I R .

[0096] • Due to the power supply voltage V SUPPLY When the voltage is increased above the threshold voltage V3 and the control signal TOGGLE fails, an intermediate peak current threshold I is generated. pk ′ and intermediate valley current threshold I val′, making I pk ′=I F +I ripple / 2 and I val ′=I F -I ripple / 2, and the average inductor current is the decreasing current I. F .

[0097] As above Figure 8 As shown, the intermediate peak current threshold I pk ′ and intermediate valley current threshold I val The peak current threshold I can be generated by the external loop control subsystem 50. pk Valley current threshold I val .

[0098] Therefore, switching the control signal TOGGLE can maintain V. SUPPLY Adjustment between threshold voltage V2 and threshold voltage V3. For example, when the control signal TOGGLE is high, the average value of the current per phase can be set to the rising current I. R Because this current value is different from the target average current I avg The offset is positive by +Δ, which may cause the power supply voltage V to be affected. SUPPLY The current increases. On the other hand, when the control signal TOGGLE is low, the average value of the current per phase can be set to the decreasing current I. F Because this current value is different from the target average current I avg The offset is negative by -Δ, which may cause the supply voltage V to be affected. SUPPLY decline.

[0099] Sometimes, load variations at the output of power converter 20 may cause the target average current I to change. avg Changes, such as in Figure 11 As shown at time t0, in this case, the load estimator 44 can modify the target average current I as described above. avg .

[0100] Figure 12 Example waveforms depicting an example of internal loop control of the boost converter 20 under light load conditions are shown according to embodiments of the present disclosure. For light load, the target average current I calculated by the load estimator 44... avg It can be greater than the minimum target average current I applied by saturation blocks 64A and 64B. avg_min Because the rising current I R and the falling current I F In this situation, the inductor current I may be saturated. L The current may be greater than that required for the steady-state operation of the boost converter 20, forcing the supply voltage V to...SUPPLY exist Figure 12 Regions I and III have positive slopes. When the power supply voltage V SUPPLY When the threshold voltage V4 is exceeded, the set-reset latch 54A from the external loop control subsystem 50 may cause the boost converter 20 to enter the boost inactive region, thereby forcing the power supply voltage V4 to be lowered due to the high impedance state of the boost converter 20. SUPPLY exist Figure 12 Regions II and IV have negative slopes. Under light load conditions, the peak current threshold I is utilized. pk Valley current threshold I val The fixed saturation threshold can maximize power efficiency by switching between the boost active state and the boost inactive state.

[0101] In a simplified implementation of the control circuit 40, the control circuit 40 can be implemented as a digital control system, which is configured for the peak current threshold I. pk Valley current threshold I val The control parameters include the control signal ENABLE and the number n of enabled phases 24. However, due to the sample-and-hold circuitry and existing processing delays that may be employed in this digital implementation, a delay of several clock cycles may occur between the switching of comparator 42 and the determination of new control parameters. This delay may contribute to the power supply voltage V generated by power converter 20. SUPPLY Overshoot and undershoot can cause the power supply voltage V to... SUPPLY Undesirable ripple and excessive voltage drop. Compared to what a fully digital implementation of control circuitry 40 can support, it may be desirable to have less supply voltage V. SUPPLY It has a faster response to rapid load transients.

[0102] Figure 13 A block diagram of selected components of a control circuit 40A according to an embodiment of the present disclosure is shown. The control circuit 40A may be functionally and / or structurally compatible with… Figure 5 The control circuit 40 shown is similar in many respects, with the main difference being that the current controller 46A is divided into a digital calculation block 82 and an analog circuit 84. As described in more detail below, the analog circuit 84 can minimize the delay that would exist in a fully digital implementation by using pre-seed values ​​of control parameters generated by the digital calculation block 82 and selecting from these pre-seed values ​​through the analog circuit 84 to generate control parameters that are transmitted to the peak / valley controller 48 and the boost converter 20. The analog circuit 84 can be directly driven by the comparator 42 such that when the comparator 42 switches, the analog circuit 84 immediately changes its state and selects the peak current threshold I. pk Valley current threshold I valThe new control parameters are generated by the control signal ENABLE and the number n of enabled phases 24. This method of changing the state and updating the control parameters can create a low-latency path from comparator 42 to the new, updated control parameters. On the other hand, the digital computation block 82 can be configured to calculate the pre-seed parameters based on the comparator output and its internal control algorithm.

[0103] Figure 14 A block diagram of selected components of the internal control loop subsystem 60A of a current controller 46A according to an embodiment of the present disclosure is shown. The internal loop control subsystem 60A may be functionally and / or structurally integrated with... Figure 10 The internal loop control subsystem 60 shown is similar in many respects, except that multiplexers 72A and 72B and a portion of the analog state machine 80 can be implemented by analog circuitry 84, and other components of the internal loop control subsystem 60A can be implemented by digital computing block 82. Figure 14 As shown, the digital computing block 82 can generate a pre-seed value based on all comparison signals C1, C2, C3, and C4, and the analog state machine 86 can be configured to control the selection of this pre-seed value based on comparison signals C2 and C3 using multiplexers 72A and 72B to generate the intermediate peak current threshold I. pk ′ and intermediate valley current threshold I val ′.

[0104] Figure 15 A block diagram of selected components of an external loop control loop subsystem 50A of a current controller 46A according to an embodiment of the present disclosure is shown. The external loop control subsystem 50A may be functionally and / or structurally integrated with... Figure 8 The external loop control subsystem 50 shown is similar in many respects, except that multiplexers 56A and 56B and a portion of the analog state machine 86 can be implemented by analog circuitry 84. Figure 15 As shown, the analog state machine 86 can be configured to: based on the comparison signal C1 and the control signal RESET_MAX generated by the digital computing block 82, in one aspect, the maximum peak current threshold I... pk_max and the maximum valley current threshold I val_max The pre-seed value and the intermediate peak current threshold I generated by the internal control loop subsystem 60A on the other hand. pk ′ and intermediate valley current threshold I val The selection of the pre-seed value is controlled. Furthermore, the analog state machine 86 can be configured to control the ENABLE signal of the power converter 20 based on the comparison signals C2 and C4.

[0105] In the boost converter 20 with multiple phases 24, all phases 24 can use the peak current threshold I. pkValley current threshold I val The same setpoint, and lookup tables or other suitable methods can be used based on the target average current I. avg This determines how many phases 24 are active. Furthermore, this lookup table or other suitable method can have hysteresis to prevent over-enabled and over-disabled individual phases 24. Additionally, a lookup table or another lookup table can be used to determine the maximum current state of the power converter 20 (e.g., supply voltage V). SUPPLY How many phases 24 should be enabled under the threshold voltage V1?

[0106] Although the preceding discussion has taken into account the current control and voltage regulation of the boost converter 20, it is understood that similar or identical methods can be applied to other types of inductor-based power converters, including but not limited to buck converters and buck-boost converters.

[0107] Return to reference Figures 3A-3C Each power inductor 32 in each phase 24 can draw its own inductor current I. L (For example, I) L1 I L2 and I L3 Furthermore, because all phases 24 can use the peak current threshold I as described above. pk Valley current threshold I val Since the impedance of each phase 24 is the same, the inductor current I is at the same set point. L1 I L2 and I L3 All are expected to be in phase with each other. However, in practical implementations, if the impedances of each phase 24 are different but close in value, the corresponding inductor current I will be... L1 I L2 and I L3 They may slowly move in and out of phase. But when the inductor current I... L1 I L2 and I L3 When two or more of them are in phase with each other, there may be a relatively long period.

[0108] Figure 16 A block diagram of selected components of a peak / valley controller 48A according to an embodiment of the present disclosure is shown. In some embodiments, the peak / valley controller 48A may be used to implement... Figure 5 The peak / valley controller 48 is shown. (As shown...) Figure 16 As shown, the peak / valley controller 48A may include comparators 90A and 90B and a latch 92. Comparator 90A can be configured to input the inductor current I... L With valley current threshold I valThe comparison is performed, and comparator 90B can be configured to compare the inductor current I. L With peak current threshold I pk A comparison is made. Latch 92 (which can be implemented as a set-reset latch or other suitable circuitry or logic device) can generate a control signal P. x (For example, control signals P1, P2, P3, etc.) and (e.g., control signals) (etc.), used to control such as Figure 5 The switch of the boost converter 20 is shown. For example, when the inductor current I... L Drop to the valley current threshold I val The latch 92 can make the control signal P... x Effective and enable control signals Failure, and when the inductor current I L Drop to the valley current threshold I val The latch 92 can make the control signal P... x Failure and control signal Effective.

[0109] Figures 17A-17C The use of a peak / valley controller 48A according to an embodiment of the present disclosure is illustrated, with battery current I... BAT Inductor current I L1 and I L2 And graphs of various example waveforms of control signals P1 and P2 over time. For clarity and illustration purposes, in Figures 17A-17C Only the currents I of the two inductors are shown. L1 and I L2 And two control signals P1 and P2, although the boost converter 20 may include more than two phases 24 in addition to 17A- Figure 17C Other inductor currents and control signals besides those shown. For example... Figures 17A-17B As shown, when the current I of a single inductor L1 and I L2 When they are in phase or nearly in phase, it may affect the battery current I. BAT Large ripple is generated (e.g., approximately equal to the current I in a single inductor). L Ripple current I present in ripple (twice). If there exists an in-phase inductor current I L If there are N phases (24), then the battery current I... BAT The ripple on the current I in a single inductor can be due to... L Ripple current I present in ripple N times.

[0110] For many reasons, battery current IBAT Such ripple can be problematic, especially if it occurs at high frequencies. For example, this ripple can reduce the efficiency of the boost converter 20, making it difficult to sense the battery current I. BAT Or it may parasitically couple into surrounding circuitry, causing electromagnetic interference. Furthermore, this current ripple may appear on the input voltage of the boost converter 20 and the supply voltage V. SUPPLY Above, the interference control circuit 40 controls the boost converter 20 (e.g., depending on the power supply voltage V). SUPPLY The interference of feedback control in the control circuit 40 (the value of the interference).

[0111] To overcome the current I of the in-phase inductor L The related issues can be addressed by the peak / valley controller 48A. Figure 16 Modify as shown to perform one or both of time-domain phase randomization or level-domain phase randomization, as described in more detail below.

[0112] Figure 18 An embodiment of the present disclosure is shown having an inductor current I for performing a boost converter 20. L A block diagram of selected components of an example peak / valley controller 48B for time-domain phase randomization circuitry. In some embodiments, the peak / valley controller 48B can be used to implement... Figure 5 The peak / valley controller 48 is shown. Furthermore, the peak / valley controller 48B can be used in many ways with... Figure 16 The peak / valley controller 48B is similar to or the same as the peak / valley controller 48A, with the main difference being that the peak / valley controller 48B may include additional circuitry mated between the set input of comparator 90A and latch 92, so as to respond to the inductor current I. L With valley current threshold I val The comparison performs time-domain phase randomization. For example... Figure 18 As shown, the output of comparator 90A can be received by tapped delay line 94, which can generate one or more outputs, each delaying the output of comparator 90A by a corresponding amount. Furthermore, multiplexer 96 can receive the undelayed output of comparator 90A and one or more outputs of delay line 94, and, based on a random number n... rand Select one of these outputs such that the comparator signal received by the set input of latch 92 is delayed by a random amount of time. Therefore, as... Figure 19 As shown, random number n rand The output transition of latch 92 from Q=0 to Q=1 can be randomly delayed. This may delay the transition from the pass state of phase 24 to the charging state of phase 24, and therefore also delay the inductor current I in phase 24. LThe occurrence of a trough. Also, for example... Figure 19 As shown, this delay can also cause the output transition of the random delay latch 92 from Q=1 to Q=0, which may delay the transition from the charging state of phase 24 to the passing state of phase 24, and therefore also delay the inductor current I in phase 24. L The peak value appears. This randomization can minimize the occurrence of the individual inductor current I in phase 24. L Phase alignment.

[0113] Additional circuitry for providing time-domain phase randomization (e.g., delay line 94 and multiplexer 96) can be implemented as a delay inductor current I. L With valley current threshold I val The comparison results (e.g., such as) Figure 18 As shown), to delay the inductor current I L With peak current threshold I pk The comparison result, or both. This additional randomization circuitry can be replicated for some or all of phases 24. In other words, in some embodiments, one or more phases 24 can be controlled by a corresponding peak / valley controller 48A, while one or more other phases 24 can each provide control over the inductor current I in some, but not all, of the phases 24. L The corresponding peak / valley controller 48B controls the time-domain randomization; and in other embodiments, phase 24 can each freely provide the inductor current I in all phases 24. L The corresponding peak / valley controller 48B controls the time-domain randomization.

[0114] Figure 20 An embodiment of the present disclosure is shown having an inductor current I for performing a boost converter 20. L A block diagram of selected components of an example peak / valley controller 48C for level-domain phase randomization circuitry. In some embodiments, the peak / valley controller 48C can be used to implement... Figure 5 The peak / valley controller 48 is shown. Furthermore, the peak / valley controller 48C can be used in many ways with... Figure 16 The peak / valley controller 48A is similar to or the same as the peak / valley controller 48C, with the main difference being that the peak / valley controller 48C may include a valley current threshold I. val Additional circuitry connected in the path to execute one or more individual inductor currents I L Phase randomization in the level domain. For example... Figure 20 As shown, the multiplexer 98 can receive multiple level adjustments (e.g., -Δ, 0, +Δ, etc.) to modify the valley current threshold I. val The level and based on a random number n randSelect one of these outputs. Then, combiner 99 can adjust the level of this selection to match the valley current threshold I. val The combination allows the modified valley current threshold I received by latch 92 to be combined. val Including random level adjustment. The result, such as... Figure 21 As shown, random number n rand The output transition of latch 92 from Q=0 to Q=1 can be randomly delayed (or advanced). This delays the transition from the pass state of phase 24 to the charging state of phase 24, and therefore also delays the inductor current I in phase 24. L The occurrence of a trough. Also, for example... Figure 21 As shown, this delay can also cause the output transition of the random delay latch 92 from Q=1 to Q=0, which may delay the transition from the charging state of phase 24 to the passing state of phase 24, and therefore also delay the inductor current I in phase 24. L The peak value appears. This randomization can minimize the occurrence of the individual inductor current I in phase 24. L Phase alignment.

[0115] Additional circuitry (e.g., multiplexer 98 and combiner 99) for providing level-domain phase randomization can be implemented to adjust the valley current threshold I. val Apply level adjustment (e.g., such as) Figure 20 As shown), for the peak current threshold I pk Apply level adjustment, or both. This additional randomization circuitry can be replicated for some or all of phases 24. In other words, in some embodiments, one or more phases 24 can be controlled by their respective peak / valley controllers 48A, while one or more other phases 24 can each provide the inductor current I in some, but not all, of the phases 24. L The corresponding peak / valley controller 48C controls the level domain randomization; and in other embodiments, phase 24 can each freely provide the inductor current I in all phases 24. L The corresponding peak / valley controller 48C controls the time-domain randomization.

[0116] In many instances, the foregoing description can provide the power supply voltage V. SUPPLY Appropriate adjustment. However, the load current I drawn from the boost converter 20... LOAD In the case of a significant increase, the power supply voltage V SUPPLY It may drop excessively below the threshold voltage V1, such as Figure 22 As shown. Figure 22 This shows the load current I at time t1. LOAD The large step change. At a later time t2, the supply voltage V SUPPLYThe voltage can drop below the threshold voltage V1, which may cause the control circuit 40 to enable additional phases 24 of the boost converter 20 (e.g., increasing the number of enabled phases 24 from one to more than one). When these additional phases 24 are enabled, they can begin in their respective charging states. In the charging state, the inductor current I of the newly enabled phase 24... L It may increase, but during the state of charging, no current can be transferred from these phases to the load current I. LOAD Therefore, the power supply voltage V SUPPLY It may decrease. Each newly activated phase 24 can remain in its charging state until their inductor current I... L To achieve the target peak current I pk So far. Therefore, each newly activated phase 24 reaches the target peak current I. pk The longer the time taken, the lower the power supply voltage V. SUPPLY The more it decreases, the more likely it is to drop. Inductor current I L The rate of increase in current can be given by the following formula:

[0117]

[0118] Where L is the inductance of power inductor 32. It is worth noting that, due to the internal impedance of battery 22, the resistance of sensing resistor 28, and the parasitic impedance of the trace between battery 22 and boost converter 20, according to Ohm's law, the sensed voltage VDD_SENSE may vary with the battery current I. BAT The increase from the battery voltage V BAT decline.

[0119] Figure 22 The power supply voltage V for newly activated phase 24 is shown in the following two cases. SUPPLY and inductor current I L (i) Case marked "A" on the waveform, where the sensed voltage VDD_SENSE is relatively high; and (ii) Case marked "B" on the waveform, where the sensed voltage VDD_SENSE is relatively low. In case A, the charging state time of the newly activated phase 24 may be shorter due to the higher sensed voltage VDD_SENSE, while in case B, the charging state time of the newly activated phase 24 may be longer due to the lower sensed voltage VDD_SENSE.

[0120] To overcome this problem, another component of the control circuit 40, boost converter 20, or power delivery system 1 can be configured to consider the sensing voltage VDD_SENSE to be sufficiently low (e.g., below the threshold sensing voltage V). THRESH When this occurs, selectively increase the voltage thresholds V1, V2, V3, and V4, such as... Figure 23 As shown. Figure 23 As shown, in response to the sensing voltage VDD_SENSE decreasing to the threshold sensing voltage V THRESH The control circuit 40 can increase the voltage thresholds V1, V2, V3, and V4 by the same amount (e.g., as shown in the figure). Figure 23 The controlled ramp method shown is as follows: Figure 23 As shown by midpoint A. Therefore, if in Figure 23 Load current I occurs at point B as shown. LOAD A large step change, while the sensed voltage VDD_SENSE is low, then the supply voltage V SUPPLY It can descend to Figure 23 Point C is shown, but since voltage thresholds V1 and V2 have already increased, this decrease may be minimal. Furthermore, if the sensed voltage VDD_SENSE increases again to the threshold sensed voltage V... THRESH The above (in Figure 23 (as shown at point D) or if the boost converter 20 enters its bypass mode, the control circuit 40 can cause the voltage thresholds V1, V2, V3, and V4 to decrease to their original levels (e.g., as shown at point D). Figure 23 (Controlled ramp method shown). Boolean flag RAISE_V x _FLAG Figure 23 As shown, it can indicate the state of voltage thresholds V1, V2, V3, and V4 (e.g., RAISE_V in the default state). x _FLAG=0, RAISE_V increases as voltage thresholds V1, V2, V3, and V4 increase. x _FLAG=1).

[0121] use Figure 23 The technology shown has a power supply voltage V. SUPPLY The absolute decrease can be minimized, but the amount of time spent by the boost converter 20 in its bypass mode remains unaffected, thus maintaining efficiency.

[0122] To prevent response to near-threshold sensing voltage V THRESH The control circuit 40 may include hysteresis control to perform frequent switching of voltage thresholds V1, V2, V3, and V4 based on the sensed voltage VDD_SENSE. Figure 23 The technology shown. For example. Figure 24 Selected components (e.g., which may be implemented wholly or partially by control circuitry 40) of a control subsystem 100 providing voltage domain hysteresis control of threshold voltages V1, V2, V3, and V4 according to embodiments of the present disclosure are shown. Figure 24 As shown, comparator 102 can compare the sensed voltage VDD_SENSE with the threshold sensed voltage V THRESHA comparison is performed, and the result of this comparison can be received by the set input of the set-reset latch 108 when the sensed voltage VDD_SENSE drops to the threshold sensed voltage V. THRESH The following causes the flag RAISE_V to be affected. x _FLAG takes effect, such as Figure 25 As shown. Furthermore, comparator 104 can compare the sensed voltage VDD_SENSE with a higher threshold sensed voltage V. THRESH-HI A comparison is performed, and the result of this comparison can be used with an indication of whether the boost converter 20 is in its bypass mode, via a logical OR operation through OR gate 106. The output of OR gate 106 can be received by the reset input of set-reset latch 108 when the sensed voltage VDD_SENSE increases to a higher threshold sensed voltage V THRESH-HI The following occurs, or if the boost converter 20 enters its bypass mode, causing the RAISE_V flag to be displayed. x _FLAG is discarded, such as Figure 25 As shown. Conversely, the flag RAISE_V x The _FLAG can be received by the select input of the multiplexer 110, which can be based on the flag RAISE_V. x The value of _FLAG selects an amount (e.g., 0 or ΔV) to add to each of the threshold voltages V1, V2, V3, and V4. Therefore, when the sensing voltage VDD_SENSE increases to a higher threshold sensing voltage V... THRESH-HI When the threshold voltages V1, V2, V3, and V4 are reduced to their default values ​​V1′, V2′, V3′, and V4′, and when the sensing voltage VDD_SENSE is reduced to the threshold sensing voltage V THRESH-HI The threshold voltages V1, V2, V3, and V4 can be increased to V1′+ΔV, V2′+ΔV, V3′+ΔV, and V4′+ΔV, respectively.

[0123] For the purposes of clarity and explanation, Figure 24 The ramps used to induce threshold voltages V1, V2, V3, and V4 are not described in the text (e.g., as shown in the image). Figure 23 Components (such as filters, ramp generators, etc.) shown may exist in the control subsystem 100, but they can still exist in the control subsystem 100.

[0124] As another example, Figure 26 Selected components (e.g., which may be implemented wholly or partially by control circuitry 40) of a control subsystem 120 providing time-domain hysteresis control of threshold voltages V1, V2, V3, and V4 according to embodiments of the present disclosure are shown. Figure 26 As shown, comparator 122 can compare the sensed voltage VDD_SENSE with the threshold sensed voltage V THRESHA comparison is performed, and the result of this comparison can be received by the input of an instant-set delay-release timer 124 when the sensed voltage VDD_SENSE drops to the threshold sensed voltage V. THRESH The following causes the flag RAISE_V to be affected. x _FLAG takes effect, such as Figure 27 As shown. Timer 124 can then hold the flag RAISE_V. x _FLAG remains active until the sensed voltage VDD_SENSE increases to the threshold sensed voltage V THRESH This continues until the minimum duration of the program is reached. For example, such as... Figure 27 The period A shown can be shorter than the programmed minimum duration, therefore the sensed voltage VDD_SENSE for period A is higher than the threshold sensed voltage V. THRESH The increase may not be sufficient to make the RAISE_V flag active for timer 124. x The _FLAG is invalid. However, as... Figure 27 The period B shown can be equal to the programmed minimum duration, therefore the sensed voltage VDD_SENSE for period B is higher than the threshold sensed voltage V. THRESH The increase may be sufficient to make the RAISE_V flag for timer 124. x The _FLAG flag is disabled. Additionally, if boost converter 20 enters its bypass mode, timer 124 can be reset and cause the RAISE_V flag to be disabled. x The _FLAG flag is invalidated. Conversely, the RAISE_V flag is invalidated. x The _FLAG can be received by the select input of the multiplexer 130, which can be based on the flag RAISE_V. x The value of _FLAG selects an amount (e.g., 0 or ΔV) to add to each of the threshold voltages V1, V2, V3, and V4. Therefore, when the sensed voltage VDD_SENSE decreases to the threshold sensed voltage V... THRESH-HI In the following cases, threshold voltages V1, V2, V3, and V4 can be increased to V1′+ΔV, V2′+ΔV, V3′+ΔV, and V4′+ΔV, respectively, in response to the boost converter 20 entering its bypass mode or in response to the sensing voltage VDD_SENSE increasing to the threshold sensing voltage V. THRESH The minimum duration for continuous programming is reduced to the default values ​​V1′, V2′, V3′, and V4′.

[0125] For the purposes of clarity and explanation, Figure 26 The ramps used to induce threshold voltages V1, V2, V3, and V4 are not described in the text (e.g., as shown in the image). Figure 23 Components (such as filters, ramp generators, etc.) shown may exist in the control subsystem 120, but they can still exist in the control subsystem 120.

[0126] As another example, Figure 28 Selected components of a control subsystem 140, which provides control over threshold voltages V1, V2, V3, and V4 according to embodiments of the present disclosure, are shown (e.g., it may be implemented wholly or partially by control circuitry 40). Figure 28 As shown, comparator 142 can compare the sensed voltage VDD_SENSE with the threshold sensed voltage V THRESH The comparison is performed, and the result of this comparison can be received by the first input of the logic AND gate 146. Additionally, comparator 144 can output the power supply voltage V. SUPPLY The value is compared with the threshold voltage V3, and the result of this comparison can be received by the second input of the logic AND gate 146. Therefore, the logic AND gate 146 can trigger the set input of the set-reset latch 147, making the value at VDD_SENSE... <V THRESH And V SUPPLY When >V3, the set-reset latch 147 sets the flag RAISE_V. x _FLAG takes effect, such as Figure 29 As shown. Additionally, the output of comparator 142 can be inverted by logic inverter 149 and trigger the reset input of set-reset latch 147, making VDD_SENSE > V THRESH When, make the flag RAISE_V x The _FLAG is invalid.

[0127] Conversely, the flag RAISE_V x The _FLAG can be received by the select input of the multiplexer 150, which can be based on the flag RAISE_V. x The value of _FLAG selects a quantity (e.g., 0 or ΔV) to add to each of the threshold voltages V1, V2, V3, and V4. Therefore, when VDD_SENSE... <V THRESH And V SUPPLY When the threshold voltages are greater than V3, the threshold voltages V1, V2, V3 and V4 can be increased to V1′+ΔV, V2′+ΔV, V3′+ΔV and V4′+ΔV respectively, or they may be reduced to their default values ​​V1′, V2′, V3′ and V4′.

[0128] The desired advantage is that, as the threshold voltages V1, V2, V3, and V4 are increased, it can minimize the supply voltage V. SUPPLY The risk of the power supply dropping below threshold voltages V1 and V2. To illustrate, if the power supply voltage V... SUPPLY If the voltage drops below the threshold voltage V2, the control circuit 40 can rapidly increase the load current I delivered by the boost converter 20. LOAD Furthermore, if the power supply voltage VSUPPLY If the voltage is below the threshold voltage V1, the control circuit 40 can reduce the load current I. LOAD Set to its maximum value. Any of these events can cause the battery current I... BAT Undesirable disturbances and spikes on the screen. However, the control implemented by the control subsystem 140 can reduce or eliminate this drawback.

[0129] For the purposes of clarity and explanation, Figure 28 The ramps used to induce threshold voltages V1, V2, V3, and V4 are not described in the text (e.g., as shown in the image). Figure 23 Components (such as filters, ramp generators, etc.) shown may exist in the control subsystem 140, but they can still exist in the control subsystem 140.

[0130] In some embodiments, control circuitry 40 may implement one of control subsystems 100, 120, and 140 to control threshold voltages V1, V2, V3, and V4. In other embodiments, control circuitry 40 may combine two or more of control subsystems 100, 120, and 140 in any suitable combination to control threshold voltages V1, V2, V3, and V4.

[0131] As described above, the load current I drawn from the boost converter 20 LOAD A significant increase in power supply voltage V may lead to SUPPLY The decline. Figure 30 Graphs of various example waveforms according to embodiments of the present disclosure are shown, illustrating responses to load current I. LOAD The step voltage of the power supply V SUPPLY The varying degrees of decrease were also depicted, and the inductor current I of phase 24 of the boost converter 20 was also described. L As previously stated, when this drop occurs, the supply voltage V... SUPPLY The voltage may drop below the threshold voltage V1, which could cause the control circuit 40 to enable additional phases 24 of the boost converter 20 (e.g., increasing the number of enabled phases 24 from one to more than one). When these additional phases 24 are enabled, they can begin in their respective charging states. In the charging state, the inductor current I of the newly enabled phase 24... L It may increase, but during the state of charging, no current can be transferred from these phases to the load current I. LOAD Therefore, the power supply voltage V SUPPLY It may decrease. Each newly activated phase 24 can remain in its charging state until their inductor current I... L To achieve the target peak current I pk So far. Therefore, each newly activated phase 24 reaches the target peak current I. pkThe longer the time taken, the lower the power supply voltage V. SUPPLY The more it decreases, the better. Also, as mentioned above, the inductor current I... L The rate of increase in current can be given by the following formula:

[0132]

[0133] Figure 30 The target peak current I for phase 24 is depicted. pk There are three possible settings. In the first case, the target peak current I... pk It can be in the value I pk-lo At this value I pk-lo At this location, the inductor current I of the newly activated phase 24 L To quickly reach the target peak current I pk And thus, it begins to rapidly supply current to the load of boost converter 20. However, the target peak current value I pk-lo It may not be enough to overcome the power supply voltage V SUPPLY The decrease may have a waveform V SUPPLY-LO The characteristics shown.

[0134] In the second case, the target peak current I pk It can be at the optimal value I pk-opt It can represent the target peak current I sufficient to support the load. pk The minimum value. In this case, the inductor current I of one or more newly activated phases 24. L It may quickly reach the target peak current I. pk And it is also sufficient to support the load, thus allowing the power supply voltage V SUPPLY (It may have a waveform V) SUPPLY-OPT The characteristics shown effectively overcome the decline.

[0135] In the third case, the target peak current I pk It can be in the value I pk-hi At this value I pk-hi At this point, the inductor current I of one or more newly activated phases 24 L Slowly reach the target peak current I pk And thus, it begins to slowly supply current to the load of the boost converter 20. Therefore, although the target peak current value I... pk-hi It may be sufficient to overcome the power supply voltage V SUPPLY (It may have a waveform V) SUPPLY-HI The characteristic shown decreases over time, but there may be excessive decreases until one or more newly enabled phases 24 begin to deliver current.

[0136] Therefore, it might be desirable to use the optimal value I. pk-opt It is large enough to support a given maximum load current I LOAD At the same time, it should be small enough to minimize the duration of the charging state of the newly added one or more phases 24, and thus keep the supply voltage V SUPPLY The decrease in voltage is minimized. However, this optimal value can vary over time, depending on the state of the boost converter 20 and the power delivery system in which the boost converter 20 is located. Therefore, this optimal value I is chosen. pk-opt It may prove to be challenging.

[0137] In order to generate the target peak current I pk (and valley peak current I) val The optimal value of the target average current I can be set by control circuit 40 (or its components, such as load estimator 44 or current controller 46) based on the sensed voltage VDD_SENSE. avg For illustration, assume that the known maximum power consumption P from the output of boost converter 20 is... MAX Then the power consumption P MAX Instantaneous target average current I avg-max It can be given as:

[0138]

[0139] Where n is an approximation of the power efficiency of the boost converter 20. Maximum target peak current I pk-max and the maximum target valley current I val-max It can be calculated as follows:

[0140]

[0141]

[0142] Maximum target peak current I pk-max and the maximum valley current I val-max These values ​​can be as follows Figure 8 and Figure 15 As shown and as described above, it is used to calculate the target peak current I. pk Valley current I val . Figure 31 The power supply voltage V generated by the boost converter 20 according to an embodiment of the present disclosure is shown. SUPPLY The inductor current I of one or more newly activated phases 24 L And graphs of various example waveforms of the sensed voltage VDD_SENSE. Specifically, Figure 31 The diagram describes how the maximum target peak current I is changed according to the sensed voltage VDD_SENSE under the control of the control circuit 40.pk-max .exist Figure 31 In the middle, the power supply voltage V SUPPLY The voltage can drop below the threshold voltage V1 at point A, which can trigger the control circuit 40 to enable one or more additional phases 24. Additionally, the power supply voltage V... SUPPLY Reducing the voltage to below the threshold voltage V1 can cause the control circuit 40 to reduce the target peak current I. pk Set to the maximum target peak current I pk-max (and the target valley current I) val Set to the maximum target valley current I pk-val Furthermore, as the sensing voltage VDD_SENSE decreases, the maximum target peak current I... pk-max (and the maximum target valley current I) pk-val This can be increased based on the sensed voltage VDD_SENSE. Therefore, the boost converter 20 can utilize... Figure 31 Point B in the diagram indicates a lower initial peak current requirement so that the boost converter 20 can begin delivering current to its output more quickly, thereby preventing the supply voltage V from surging. SUPPLY Excessive decrease. Maximum target peak current I pk-max (and the maximum target valley current I) pk-val It can be increased to a steady-state level, such as Figure 31 Point C is shown in the diagram.

[0143] As used herein, when two or more elements are referred to as being “coupled” to each other, the term indicates that such two or more elements are in electronic or mechanical communication, whether, where applicable, they are indirectly or directly connected, with or without intermediate elements.

[0144] This disclosure covers all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that will be understood by those skilled in the art. Similarly, where appropriate, the appended claims cover all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that will be understood by those skilled in the art. Furthermore, references in the appended claims to a device or system or a component of a device or system that are adapted, arranged, capable, configured, enabled, operable, or effectively perform a particular function cover that device, system, or component, whether or not it or the particular function is activated, switched on, or unlocked, provided that the device, system, or component is so adapted, arranged, capable, configured, enabled, operable, or effective. Therefore, modifications, additions, or omissions can be made to the systems, devices, and methods described herein without departing from the scope of this disclosure. For example, components of a system and device may be integrated or separated. Furthermore, the operation of the systems and devices disclosed herein may be performed by more, fewer, or other components, and the described methods may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used herein, “each” means each member of a set or each member of a subset of a set.

[0145] Although exemplary embodiments are shown in the accompanying drawings and described below, the principles of this disclosure can be implemented using any number of techniques, whether currently known or not. This disclosure should not be limited in any way to the exemplary embodiments and techniques shown in the drawings and described above.

[0146] Unless otherwise specified, the items depicted in the accompanying drawings are not necessarily drawn to scale.

[0147] All examples and conditional language described herein are intended for educational purposes to help the reader understand the content and concepts of this disclosure contributed by the inventors to advance the art, and are to be construed as not being limited to these specific examples and conditions. Although embodiments of this disclosure have been described in detail, it should be understood that various changes, substitutions, and modifications can be made thereto without departing from the spirit and scope of this disclosure.

[0148] While specific advantages have been listed above, various embodiments may include some, none, or all of the listed advantages. Furthermore, other technical advantages may become apparent to those skilled in the art after reading the foregoing figures and description.

[0149] In order to help the Patent Office and any reader of any patent issued under this application interpret the claims appended herein, the applicants wish to note that they do not intend for any appended claim or claim element to reference 35 U.S.SC §112(f) unless the words “means” or “step” are expressly used in a particular claim.

Claims

1. A system for controlling current in a power converter configured to generate an output voltage, the system comprising a control loop having: Multiple comparators, each having a corresponding reference voltage to be compared with the output voltage; A digital controller configured to calculate one or more pre-seed control parameters for the current based on the output of the comparator and the internal control algorithm of the digital controller; as well as An analog state machine is configured to select control parameters for controlling the current based on the outputs of the plurality of comparators, the control parameters being selected from: The pre-seed control parameters; Control parameters used to control the current to have zero amplitude; as well as Control parameters used to control the current to have the maximum amplitude.

2. The system according to claim 1, wherein, The digital controller is configured to set the peak current threshold and valley current threshold based on the input reference estimation of the current load.

3. The system according to claim 2, wherein, The analog state machine is also configured to cooperate with the digital controller: If the output voltage is lower than a first threshold, then the peak current threshold and valley current threshold of the current are set to a first pre-calculated value, wherein the first pre-calculated value is higher than the input reference estimate of the current load; and If the output voltage is higher than the first threshold, the peak current threshold and valley current threshold of the current are set to a second pre-calculated value, wherein the second pre-calculated value is lower than the input reference estimate of the current load.

4. The system according to claim 1, wherein, The analog state machine is configured to disable the power converter when the output voltage is higher than a first threshold, and to enable the power converter when the output voltage is lower than a second threshold, wherein the second threshold is lower than the first threshold.

5. The system according to claim 4, wherein, The digital controller is also configured to set the current to its maximum value if the output voltage is less than a third threshold, wherein the third threshold is lower than the second threshold.

6. The system according to claim 5, wherein, The digital controller is configured to set the current based on an input reference estimate of the current load when the output voltage is between the first threshold and the second threshold.

7. The system according to claim 5, wherein: The power converter includes a multiphase power converter, which includes multiple phases; Each phase includes a separate phase power converter; and The analog state machine is configured to determine the number of individual phase power converters to be enabled based on the maximum current of each phase when the output voltage is below the third threshold.

8. A method for controlling current in a power converter configured to generate an output voltage, the method comprising using a control loop having: Multiple comparators, each having a corresponding reference voltage to be compared with the output voltage; A digital controller configured to calculate one or more pre-seed control parameters for the current based on the output of the comparator and the internal control algorithm of the digital controller; as well as An analog state machine is configured to select control parameters for controlling the current based on the outputs of the plurality of comparators, the control parameters being selected from: The pre-seed control parameters; Control parameters used to control the current to have zero amplitude; as well as Control parameters used to control the current to have the maximum amplitude.

9. The method according to claim 8, wherein, The digital controller is configured to set the peak current threshold and valley current threshold based on the input reference estimation of the current load.

10. The method according to claim 9, wherein, The analog state machine is also configured to cooperate with the digital controller: If the output voltage is lower than a first threshold, then the peak current threshold and valley current threshold of the current are set to a first pre-calculated value, wherein the first pre-calculated value is higher than the input reference estimate of the current load; and If the output voltage is higher than the first threshold, the peak current threshold and valley current threshold of the current are set to a second pre-calculated value, wherein the second pre-calculated value is lower than the input reference estimate of the current load.

11. The method according to claim 10, wherein, The analog state machine is configured to disable the power converter when the output voltage is higher than a first threshold, and to enable the power converter when the output voltage is lower than a second threshold, wherein the second threshold is lower than the first threshold.

12. The method according to claim 11, wherein, The digital controller is also configured to set the current to its maximum value if the output voltage is less than a third threshold, wherein the third threshold is lower than the second threshold.

13. The method according to claim 12, wherein, The digital controller is configured to set the current based on an input reference estimate of the current load when the output voltage is between the first threshold and the second threshold.

14. The method according to claim 12, wherein: The power converter includes a multiphase power converter, which includes multiple phases; Each phase includes a separate phase power converter; and The analog state machine is configured to determine the number of individual phase power converters to be enabled based on the maximum current of each phase when the output voltage is below the third threshold.

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