Integrated assembly and method of forming an integrated assembly

Abstract

Some embodiments include an integrated assembly having a source structure. The source structure includes, in ascending order, a first conductively-doped semiconductor material, one or more first insulating layers, a second conductively-doped semiconductor material, one or more second insulating layers, and a third conductively-doped semiconductor material. The source structure includes a block extending through the second conductively-doped semiconductor material. A conductive level is over the source structure. A channel material extends vertically along the conductive level and into the source structure to be in direct contact with the second conductively-doped semiconductor material. One or more memory cell materials are between the channel material and the conductive level. Some embodiments include methods of forming an integrated assembly.

Description

[0001] Relevant patent data

[0002] This application claims priority and benefit to U.S. Patent Application No. 16 / 890,296, filed June 2, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] A method for forming an integrated assembly (e.g., an integrated memory device). Integrated assembly. Background Technology

[0004] Memory provides data storage for electronic systems. Flash memory is a type of memory with numerous applications in modern computers and devices. For example, modern personal computers may have a BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to use flash memory in solid-state drives instead of conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide remote upgrade devices to enhance features.

[0005] NAND can be the basic architecture for flash memory and can be configured to include vertically stacked memory cells.

[0006] Before describing NAND in detail, it may be helpful to describe more generally the relationship of the memory array within an integrated arrangement. Figure 1 shows a block diagram of a prior art device 1000, which includes a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns, access lines 1004 (e.g., word lines for conducting signals WL0 to WLm) and first data lines 1006 (e.g., bit lines for conducting signals BL0 to BLn). The access lines 1004 and the first data lines 1006 are used to transfer information to and from the memory cells 1003. Row decoders 1007 and column decoders 1008 decode address signals A0 to AX on address lines 1009 to determine which of the memory cells 1003 to be accessed. Sensing amplifier circuitry 1015 is used to determine the value of the information read from the memory cells 1003. I / O circuitry 1017 transmits information values ​​between memory array 1002 and input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O lines 1005 represent values ​​of information read from or to be written to memory cells 1003. Other devices may communicate with device 1000 via I / O lines 1005, address lines 1009, or control lines 1020. Memory control unit 1018 controls memory operations to be performed on memory cells 1003, utilizing signals on control line 1020. Device 1000 may receive supply voltage signals Vcc and Vss on first power supply line 1030 and second power supply line 1032, respectively. Device 1000 includes selection circuitry 1040 and input / output (I / O) circuitry 1017. Selection circuit 1040 can respond to signals CSEL1 to CSELn via I / O circuit 1017 to select signals on first data line 1006 and second data line 1013 that represent information to be read from or programmed into memory cell 1003. Column decoder 1008 can selectively activate CSEL1 to CSELn signals based on address signals A0 to AX on address line 1009. Selection circuit 1040 can select signals on first data line 1006 and second data line 1013 to provide communication between memory array 1002 and I / O circuit 1017 during read and program operations.

[0007] The memory array 1002 of Figure 1 may be a NAND memory array, and Figure 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that can be used with the memory array 1002 of Figure 1. Device 200 includes multiple charge storage device strings. In a first direction (Z-Z'), each charge storage device string may include, for example, thirty-two charge storage devices stacked on top of each other, wherein each charge storage device corresponds to, for example, one of thirty-two layers (e.g., layers 0 to 31). The charge storage devices in the respective strings may share a common channel region, for example, a channel region formed in a respective pillar of a semiconductor material (e.g., polysilicon), around which the charge storage device string is formed. In a second direction (X-X'), each first group of, for example, sixteen strings may include, for example, eight strings sharing multiple (e.g., thirty-two) access lines (i.e., “global control gate (CG) lines”, also called word lines WL). Each of the access lines may couple a charge storage device within a layer. When each charge storage device includes a cell capable of storing two bits of information, charge storage devices coupled to the same access line (and therefore corresponding to the same layer) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In a third direction (Y-Y'), each of eight second groups of multiple strings may include sixteen strings coupled to corresponding ones of eight data lines (e.g., BLs). The size of a memory block may include 1,024 pages and approximately 16 MB in total (e.g., 16 WL × 32 layers × 2 bits = 1,024 pages / block, block size = 1,024 pages × 16 KB / page = 16 MB). The number of strings, layers, access lines, data lines, first groups, second groups, and / or pages may be greater than or less than the number of strings, layers, access lines, data lines, first groups, second groups, and / or pages shown in Figure 2.

[0008] Figure 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of Figure 2 in the X-X' direction, which contains fifteen strings of charge storage devices from one of the sixteen first groups of strings described in Figure 2. The multiple strings of memory blocks 300 may be grouped into multiple subsets 310, 320, 330 (e.g., block columns), such as block columns. I Block List j and block list KEach subset (e.g., a tile column) comprises a “partial block” (sub-block) of memory block 300. A global drain-side select-gate (SGD) line 340 may be coupled to multiple strings of SGDs. For example, the global SGD line 340 may be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via one of multiple (e.g., three) sub-SGD drivers 332, 334, 336, each sub-SGD line corresponding to a corresponding subset (e.g., a tile column). Each of the sub-SGD drivers 332, 334, 336 may couple or disconnect the SGDs of the corresponding partial block (e.g., a tile column) of strings in parallel, independently of those SGDs of other partial blocks. A global source-side select-gate (SGS) line 360 ​​may be coupled to multiple strings of SGSs. For example, a global SGS line 360 ​​may be coupled to a plurality of sub-SGS lines 362, 364, 366 via a corresponding one of a plurality of sub-SGS drivers 322, 324, 326, where each sub-SGS line corresponds to a corresponding subset (e.g., a tile column). Each of the sub-SGS drivers 322, 324, 326 may couple or cut off the SGS of the corresponding sub-block (e.g., a tile column) string in parallel, independently of the SGS of other sub-blocks. A global access line (e.g., a global CG line) 350 may be coupled to the charge storage device corresponding to the corresponding layer of each of the plurality of strings. Each global CG line (e.g., global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding one of a plurality of sub-string drivers 312, 314, 316. Each of the substring drivers can be coupled or disconnected in parallel with the charge storage devices corresponding to the respective sub-block and / or layer, independently of those charge storage devices in other sub-blocks and / or layers. The charge storage devices corresponding to the respective subset (e.g., a sub-block) and the respective layer may include a “partial layer” (e.g., a single “pattern”) of charge storage devices. A string corresponding to the respective subset (e.g., a sub-block) can be coupled to one of the corresponding sub-sources 372, 374, and 376 (e.g., “pattern source”), where each sub-source is coupled to a corresponding power source.

[0009] Alternatively, the NAND memory device 200 can be described with reference to the schematic illustration of Figure 4.

[0010] Memory array 200 includes word lines 2021 to 202 N And bit lines 2281 to 228 M .

[0011] Memory array 200 also includes NAND strings 2061 to 206 M Each NAND string contains 2081 to 208 charge storage transistors. NCharge storage transistors can use floating gate materials (e.g., polysilicon) to store charge, or they can use charge trapping materials (e.g., silicon nitride, metal nanodots, etc.) to store charge.

[0012] Charge storage transistor 208 is located at the intersection of word line 202 and string 206. Charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistor 208 of each NAND string 206 is connected in series from source to drain between a source select device (e.g., source-side selected gate, SGS) 210 and a drain select device (e.g., drain-side selected gate, SGD) 212. Each source select device 210 (e.g., 2101, 210...) M The first selection device 210 is located at the intersection of string 206 and source selection line 214, while each drain selection device 212 is located at the intersection of string 206 and drain selection line 215. Selection devices 210 and 212 can be any suitable access device and are generally shown as blocks in FIG4.

[0013] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 corresponding to the NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 corresponding to the NAND string 2061. The source select device 210 is connected to the source select line 214.

[0014] The drain of each drain selector 212 is connected to the bit line (i.e., digital line) 228 at its drain contact. For example, the drain of drain selector 2121 is connected to bit line 2281. The source of each drain selector 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain selector 2121 is connected to the charge storage transistor 208 of the corresponding NAND string 2061. N The drain electrode.

[0015] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistor 208 couples its control gate 236 to a word line 202. The charge storage transistor 208 is a column of transistors within the NAND string 206 coupled to a given positioning line 228. The charge storage transistor 208 behaves in conjunction with those transistors coupled to a given word line 202.

[0016] The vertically stacked memory cells of the three-dimensional NAND architecture can be erased by generating hole carriers underneath them and then using an electric field to sweep the hole carriers upwards along the memory cells.

[0017] A gated structure of the transistor can be used to provide gate-induced drain current (GIDL), which generates holes for block erasure of memory cells. The transistor can be a source-side selected (SGS) device as described above. The channel material associated with the memory cell string can be configured as channel material pillars, and regions of such pillars can be gated and coupled to the SGS device. The gated coupling portion of the channel material pillar is the portion overlapping the gate of the SGS device.

[0018] It may be necessary to heavily dope at least some of the gated coupling portions of the channel material pillars. In some applications, it may be necessary for the gated coupling portions to include both a heavily doped lower region and a lightly doped upper region; both regions overlapping with the gate of the SGS device. Specifically, the overlap with the lightly doped region provides the SGS device with non-leakage "off" characteristics, and the overlap with the heavily doped region provides the SGS device with leakage GIDL characteristics. The terms "heavily doped" and "lightly doped" are used relative to each other, not relative to a particular conventional meaning. Thus, a "heavily doped" region is more heavily doped than a neighboring "lightly doped" region and may or may not be heavily doped in a conventional sense. Similarly, a "lightly doped" region is less heavily doped than a neighboring "heavily doped" region and may or may not be lightly doped in a conventional sense. In some applications, the term "lightly doped" refers to having a density of less than or equal to about 10 18 Semiconductor materials with dopant concentrations of 10 atoms per cubic centimeter, and the term "heavily doped" refers to semiconductor materials with dopant concentrations greater than or equal to about 10 atoms per cubic centimeter. 22 Semiconductor materials with dopants of 1 atom / cubic centimeter.

[0019] Initially, the channel material can be lightly doped, and then a heavily doped region can be formed by diffusion from the underlying doped semiconductor material.

[0020] There is a need to develop improved methods for forming integrated memories (e.g., NAND memory). There is also a need to develop improved memory devices. Attached Figure Description

[0021] Figure 1 shows a block diagram of a prior art memory device having a memory array containing memory cells.

[0022] Figure 2 shows a schematic diagram of a prior art memory device in the form of a 3D NAND memory device, as shown in Figure 1.

[0023] Figure 3 shows a cross-sectional view of the prior art 3D NAND memory device of Figure 2 in the X-X' direction.

[0024] Figure 4 is a schematic diagram of a conventional NAND memory array.

[0025] Figure 5 and5A A schematic cross-sectional side view of an instance integration assembly during the instance processing phase of an instance embodiment method for forming an instance memory device. Figure 5 ) and illustrations from top to bottom ( Figure 5A ). Figure 5 The cross-sectional side view is along Figure 5A Line 5-5.

[0026] Figure 6 and 6A To continue Figure 5 and 5A The instance processing phase following the processing phase Figure 5 and 5A A schematic cross-sectional side view of an example integrated assembly. Figure 6 ) and illustrations from top to bottom ( Figure 6A ). Figure 6 The cross-sectional side view is along Figure 6A Line 6-6.

[0027] Figure 7 To continue Figure 6 The instance processing phase following the processing phase Figure 5 A schematic cross-sectional side view of an example integrated assembly.

[0028] Figure 8 and 8A To continue Figure 7 The instance processing phase following the processing phase Figure 5 and 5A A schematic cross-sectional side view of an example integrated assembly. Figure 8 ) and illustrations from top to bottom ( Figure 8A ). Figure 8 The cross-sectional side view is along Figure 8A Line 8-8.

[0029] Figures 9 to 11 To continue Figure 8 Instances following the processing phase are processed sequentially in the next phase. Figure 5 A schematic cross-sectional side view of an example integrated assembly.

[0030] Figure 11A for Figure 11 A schematic cross-sectional side view of area A.

[0031] Figures 12 to 19 To continue Figure 11 Instances following the processing phase are processed sequentially in the next phase. Figure 5 A schematic cross-sectional side view of an example integrated assembly. Figure 19 This can be considered as demonstrating an instance memory device.

[0032] Figure 19A For along Figure 19 The diagram of the layers is shown from top to bottom. Figure 19 The cross-sectional side view is along Figure 19A Line 19-19.

[0033] Figure 20 A schematic cross-sectional side view of an integrated assembly for another example. Detailed Implementation

[0034] Some embodiments include novel methods for forming memory devices. The memory device may have a vertically stacked hierarchy of memory cells above a conductive electrode structure. Sacrificial material may be provided in regions of the conductive electrode structure, and support blocks may be provided within the sacrificial material. The sacrificial material may be removed to leave voids, and the support blocks may be retained to provide support for the structure above the voids. Conductive doped semiconductor material may subsequently be formed within the voids. Some embodiments include integrated assemblies having support blocks of conductive doped semiconductor material extending through the conductive electrode structure. Reference Figures 5 to 20 Describe an example implementation.

[0035] refer to Figure 5 The integrated assembly 10 includes an insulating material 14 on top of the substrate 12.

[0036] Substrate 12 may include semiconductor materials and may include, for example, single-crystal silicon (Si), substantially composed of, or composed of. Substrate 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction that includes semiconductor materials, including but not limited to bulk semiconducting materials, such as semiconducting wafers (alone or in a combination of other materials) and layers of semiconducting materials (alone or in a combination of other materials). The term "substrate" means any support structure that includes, but is not limited to, the semiconductor substrates described above. In some applications, substrate 12 may correspond to a semiconductor substrate comprising one or more materials associated with integrated circuit manufacturing. Such materials may include one or more of, for example, refractory metals, barrier materials, diffusion materials, insulating materials, etc.

[0037] A gap is provided between the substrate 12 and the insulating material 14 to indicate that other materials, devices, etc. may exist between the substrate 12 and the insulating material 14.

[0038] The insulating material 14 may include any suitable composition, such as one or more of silicon dioxide, silicon nitride, aluminum oxide, etc.

[0039] Stack 16 is formed over insulating material 14. Stack 16 includes a first material 18, layers 20a to 20c above the first material, and a second material 22 above the layers.

[0040] The first material 18 is conductive and may include any suitable composition. In some embodiments, the first material 18 may include a conductive doped semiconductor material; and may include, for example, conductive doped silicon, be substantially composed of, or be composed of. Silicon may be in any suitable crystalline form (e.g., one or more of single crystal, polycrystalline, amorphous, etc.). The conductive doped silicon may include a concentration of at least about 10. 20 Dopant per atom per cubic centimeter, with examples of dopant including one or more of phosphorus, arsenic, boron, etc.

[0041] The first material 18 can be formed to any suitable thickness, and in some embodiments it can be formed to a thickness in the range of about 100 nanometers (nm) to about 300 nm.

[0042] Layers 20a to 20c may comprise any suitable material. In some embodiments, layers 20a to 20c may be electrically insulating. For example, outer layers 20a and 20c may comprise, substantially comprise, or comprise silicon nitride; and the central layer 20b may comprise, substantially comprise, or comprise silicon dioxide. Layers 20a to 20c may be formed with a total overall thickness in the range of about 5 nm to about 20 nm.

[0043] Layers 20a to 20c are examples of layers that can be formed between materials 18 and 22. During subsequent processing stages, regions of the second material 22 are removed, and layers 20a to 20c provide an interface over material 18, allowing material 22 to be removed without harmful etching into material 18. In some embodiments, layers 20a to 20c may be fewer than the three layers shown, and in some embodiments, more than the three layers shown. In some embodiments, layers 20a to 20c may be omitted if materials 22 and 18 comprise a suitable composition that allows material 22 to be removed without damaging material 18.

[0044] The second material 22 may comprise any suitable composition, such as one or more semiconductor materials. In some embodiments, the second material 22 may comprise, consist substantially of, or be composed of silicon. The silicon within the second material 22 may include, or exclude, dopants such that such silicon is not electrically doped. For example, the dopant concentration within the second material 22 may be less than or equal to about 10. 16 One atom per cubic centimeter.

[0045] The channel material pillars will ultimately be supported by the regions of stack 16, and slots will be provided between the channel material pillars to divide the pillars between the first set associated with the first memory block and the second set associated with the second memory block. Instance locations of the channel material pillars are illustrated at region 24, and instance locations of the slots are illustrated at region 26.

[0046] Figure 5A exhibit Figure 5 The top view of assembly 10 shows an example arrangement of channel material column position 24 and slit position 26.

[0047] refer to Figure 6 The masking material 28 is patterned into a blocking region 30 above the second material 22. The masking material 28 may include any suitable composition; and in some embodiments may include a photolithographically patterned photoresist. The blocking region 30 is located below the channel material pillar location 24 and the slit location 26.

[0048] The opening 32 extends through the masking material 28. In some embodiments, the blocking area 30 may be considered as blocking a first area 34 of the material 22 while exposing a second area 36 of the material 22 through the opening 32.

[0049] Figure 6A exhibit Figure 6 The top view of assembly 10 shows an example arrangement of blocking area 30 and opening 32.

[0050] refer to Figure 7 Dopant 38 is injected into the second region 36 of material 22, while masking material 28 prevents the dopant from entering the first region 34 of material 22. The dopant in region 36 is illustrated using a dotted diagram.

[0051] Dopant 38 may include one or more elements selected from groups 13 to 15 of the periodic table, and may be provided in region 36 up to approximately 1 × 10⁻⁶. 18 From atoms per cubic centimeter to approximately 1 × 10⁻⁶ 21 The total concentration is in the range of atoms per cubic centimeter. In some embodiments, the dopant 38 may comprise, consist substantially of, or be composed of carbon, and may be about 1 × 10⁻⁶. 18 From atoms per cubic centimeter to approximately 1 × 10⁻⁶ 21 A concentration in the range of atoms per cubic centimeter is provided to region 36. In some embodiments, dopant 38 may include, be substantially composed of, or be composed of boron, and may be provided in region 36 at a concentration of about 1 × 10⁻⁶. 18 From atoms per cubic centimeter to approximately 1 × 10⁻⁶ 21 Concentration in the range of atoms per cubic centimeter.

[0052] In some embodiments, the undoped region 34 of material 22 may correspond to a sacrificial material that can be selectively removed relative to layer 20c and the doped region 36. For the purposes of this disclosure and the appended claims, if one material is etched at a faster rate than another material, then that material is considered to be selectively removable relative to the other material.

[0053] In some embodiments, material 22 may include silicon. In such embodiments, the doped region 36 is resistant to etching with tetramethylammonium hydroxide (TMAH), while the undoped region 34 remains susceptible to such etching. If such activation improves the resistance of the doped region 36 to TMAH-containing etchants, then the assembly 10 can withstand heat treatment and / or other conditions suitable for activating the dopant within the doped region 36.

[0054] After doping region 36, remove masking material 28 to leave Figure 8 The assembly components. Figure 8A exhibit Figure 8 The image shows a top view of assembly 10 in the processing stage, and shows an undoped region 34 of material 22 extending laterally around a doped region 36 of material 22. The undoped region 34 can be considered as forming bridging regions 40 (some of which are labeled) extending between the doped regions 36.

[0055] refer to Figure 9 The second layer 42a to 42c is formed above the second material 22, and the third material 44 is formed above the layers 42a to 42c.

[0056] The third material 44 is conductive and may include any suitable composition. In some embodiments, the third material 44 may include a conductive doped semiconductor material and may include, consist substantially of, or be composed of conductive doped silicon. Silicon may be in any suitable crystalline form (e.g., one or more of single crystal, polycrystalline, amorphous, etc.). The third material may be formed to any suitable thickness, and in some embodiments may be formed to a thickness in the range of about 100 nm to about 300 nm. The conductive doped silicon may include a concentration of at least about 10 20 The dopant is present in atoms per cubic centimeter, and examples of dopant include one or more of phosphorus, arsenic, boron, etc. The third material 44 may or may not include the same composition as the first material 18.

[0057] Layers 42a to 42c may comprise any suitable material. In some embodiments, layers 42a to 42c may be electrically insulating. For example, outer layers 42a and 42c may comprise, substantially comprise, or comprise silicon nitride; and central layer 42b may comprise, substantially comprise, or comprise silicon dioxide. Layers 42a to 42c may be formed with a total overall thickness in the range of about 5 nm to about 20 nm.

[0058] Layers 42a to 42c are examples of layers that can be formed between materials 44 and 22. Undoped regions 34 of the second material 22 are removed during subsequent processing stages, and layers 42a to 42c provide an interface that allows these regions to be removed without damaging material 44. In some embodiments, layers 42a to 42c may be fewer than the three layers shown, and in some embodiments, more than the three layers shown. In some embodiments, layers 42a to 42c may be omitted if materials 22 and 44 comprise a suitable composition that allows the undoped regions of material 22 to be removed without damaging material 44.

[0059] Layers 42a to 42c can be referred to as the second layer, to distinguish them from the first layer 20a to 20c.

[0060] Layers 42a to 42c and material 44 can be considered as part of stack 16.

[0061] A second stack 46 is formed over a first stack 16. The second stack 46 has alternating first levels 48 and second levels 50. The first level 48 includes material 52, and the second level 50 includes material 54. Materials 52 and 54 may include any suitable composition. In some embodiments, material 52 may include, substantially consist of, or be composed of silicon nitride; and material 54 may include, substantially consist of, or be composed of silicon dioxide.

[0062] refer to Figure 10 In the illustrated embodiment, opening 56 is formed to extend through the first stack 16 and the second stack 46, and opening 56 terminates in the insulating material 14. Opening 56 is located in the above reference. Figure 5 and 5A The described channel material column is located at position 24. Opening 56 can be referred to as the first opening.

[0063] refer to Figure 11 Semiconductor material (channel material) 58 is formed within the opening 56. The semiconductor material 58 is configured as a channel material pillar 60.

[0064] Semiconductor material 58 may include any suitable composition; and in some embodiments may include one or more of, substantially composed of or composed of: silicon, germanium, group III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term group III / V semiconductor material refers to semiconductor materials comprising elements selected from groups III and V of the periodic table (where group III and V are older nomenclature and are now referred to as groups 13 and 15). In some embodiments, semiconductor material 58 may include suitably doped silicon, substantially composed of or composed of.

[0065] In the illustrated embodiment, the channel material column 60 is an annular ring (e.g., Figure 19A As shown in the top-down view, such annular rings surround the insulating material 62. This configuration of the channel material pillars can be considered to correspond to a “hollow” channel configuration, wherein the insulating material 62 is provided within the hollow portion of the channel material pillar. In other embodiments, the channel material 58 may be configured as a solid pillar.

[0066] The channel material pillar 60 is separated from the materials 52 and 54 of the stack 46 by the intervention region 64. Region 64 includes one or more cell materials (memory cell materials) formed within the opening 56 prior to the channel material 58. The cell materials of region 64 may include tunneling material 66, charge storage material 68, charge blocking material 70, and dielectric barrier material 72, such as... Figure 11A As shown.

[0067] The tunneling material 66 (also known as the gate dielectric material) may include any suitable composition, and in some embodiments may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, etc.

[0068] The charge storage material 68 may include any suitable composition, and in some embodiments may include a floating gate material (e.g., polysilicon) or a charge trapping material (e.g., one or more of silicon nitride, silicon oxynitride, conductive nanodots, etc.).

[0069] The charge blocking material 70 may include any suitable composition, and in some embodiments may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, etc.

[0070] The dielectric barrier material 72 may include any suitable composition, and in some embodiments may include one or more of alumina, hafnium oxide, zirconium oxide, etc.

[0071] In some embodiments, it can be considered that in Figure 11 Unit materials 66, 68, 70 and 72 are formed within the opening 56 to line the opening, and then channel material 58 can be formed within such lined openings. Figure 11A The channel material 58 is separated from the charge storage material 68 by an insulating material (tunneling material) 66.

[0072] refer to Figure 12 The second opening 74 is formed to travel through the second stack 46 and reach one of the first regions 34 of the second material 22. The opening 74 may or may not penetrate into the second material 22.

[0073] In some embodiments, opening 56 is a cylindrical opening (see reference). Figure 19A (understood from a top-down view), and opening 74 is relative to... Figure 12 The cross-section extends into grooves (slits) both inside and outside the page (see also [reference]). Figure 19A (Understanding from top to bottom).

[0074] Opening 74 has a sidewall surface 73 extending along the materials 52 and 54 of stack 46. In the illustrated embodiment, the sidewall surface 73 is generally vertical; the term "generally vertical" means vertical within reasonable manufacturing and measurement tolerances. In other embodiments, the sidewall surface 73 may be tapered.

[0075] refer to Figure 13 The protective material 76 is formed within the opening (slit) 74 and along the sidewall surface 73. In some embodiments, the protective material 76 may be considered as lining the sidewall surface 73.

[0076] The protective material 76 may comprise any suitable composition. In some embodiments, the protective material 76 may comprise, substantially comprise, or comprise only silicon, and specifically may comprise effectively undoped silicon (e.g., including intrinsic dopant concentrations, and in some embodiments including less than or equal to about 10). 16 (Dopant concentration of atoms per cubic centimeter). In some embodiments, the protective material 76 may include one or more of the following: metals (e.g., tungsten, titanium, etc.), metal-containing materials (e.g., metal silicides, metal nitrides, metal carbides, metal borides, etc.), and semiconductor materials (e.g., silicon, germanium, etc.).

[0077] The protective material 76 may or may not extend through the upper surface of the assembly 10.

[0078] refer to Figure 14 One or more etching operations are used to create an opening (slit) 74 at the bottom of the protective material 76 to expose one or more of the undoped first regions 34 of the material 22. In the illustrated embodiment, the etching partially penetrates the material 22. In other embodiments, the etching may stop at the upper surface of the material 22. In other specific embodiments, the etching may completely penetrate the material 22 to stop at the surface of layer 20c.

[0079] refer to Figure 15 The first zone 34 selectively removes material 22 relative to the second zone 36. Figure 14 This forms a catheter 78 that travels around the second zone 36. Catheter 78 is referenced above. Figure 8AThe described bridging region 40 extends laterally around the second region 36. The first region 34 can be selectively removed relative to the second region 36 by any suitable method. In some embodiments, region 34 comprises undoped silicon (or at least substantially undoped silicon), and region 36 comprises doped silicon; and region 34 is selectively removed using an etchant containing TMAH. For the purposes of this disclosure and the appended claims, if the removal rate of the first material is faster than that of the second material, then the first material is considered to be selectively removed relative to the second material, which may include, but is not limited to, a condition of 100% selectivity with respect to the second material over the first material.

[0080] Catheter 78 extends to the reference above. Figure 11A The described dielectric barrier material 72. In some embodiments, the conduit 78 may be indicated as extending into the unit material provided within the region 64 (e.g., extending into...). Figure 11A (One or more of the unit materials 66, 68, 70 and 72 shown). In some embodiments, the dielectric barrier material 72 may be omitted from the material formed in region 64, and the conduit 78 may instead extend to the charge barrier material 70.

[0081] refer to Figure 16 The conduit 78 extends through the cell material within region 64 to expose the sidewall surface 79 of the semiconductor material (channel material) 58.

[0082] refer to Figure 17 Conductive doped semiconductor material 80 is formed inside the conduit 78. Figure 16 Semiconductor material 80 may comprise any suitable composition, and in some embodiments may comprise, substantially comprise, or comprise one or more of the following: silicon, germanium, group III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc. In some embodiments, semiconductor material 80 may comprise silicon heavily doped with an n-type dopant (e.g., doped to at least about 10). 22 (Concentration per atom per cubic centimeter).

[0083] The doped semiconductor material 80 directly contacts the channel material 58 along the sidewall 79.

[0084] refer to Figure 18 Materials 76 and 80 are removed from the opening (slit) 74. Materials 76 and 80 can be removed to any suitable extent within the slit 74.

[0085] The dopant diffuses outward from the conductive doped semiconductor material 80 into the semiconductor material (channel material) 58 to form a heavily doped region 82 within the lower portion of the channel material pillar 60. The approximate upper boundary of the dopant within the heavily doped region 82 is indicated by line 83.

[0086] The outward diffusion from the doped material 80 to the semiconductor material 58 can be accomplished by any suitable process, including, for example, a suitable heat treatment (e.g., a heat treatment at a temperature exceeding about 300°C for at least about two minutes).

[0087] refer to Figure 19 , the first level of material 48 52 ( Figure 18 The conductive material 84 is removed and replaced with conductive material 84. Although conductive material 84 is shown to completely fill the first layer 48, in other embodiments, at least some of the materials provided within the first layer 48 may be insulating materials (e.g., dielectric barrier materials). If dielectric barrier material is provided along the first layer 48, then it can be referred to above. Figure 11A The described unit material omits dielectric barrier material 72.

[0088] The conductive material 84 may include any suitable composition, and in some embodiments may include a tungsten core at least partially surrounded by titanium nitride.

[0089] Figure 19 The first layer 48 is a conductive layer, and the stack 46 can be considered to include alternating insulating layers 50 and conductive layers 48.

[0090] After the conductive material 84 is formed along layer 48, an insulating material 86 is formed within slit 74. The insulating material 86 may include any suitable composition, and in some embodiments may include, consist substantially of, or be composed of silicon dioxide.

[0091] Figure 19 Assembly 10 is shown as a memory device including memory cell 90 and select device (SGS device) 92. The lowest conductive layer in conductive layers 48 is designated 48a, and a doped region 82 extends into said conductive layer 48a. Conductive layer 48a includes the SGS device 92. In the illustrated embodiment, the dopant extends partially over layer 48a to achieve a desired balance between the non-leakage disconnect characteristics and the leakage GIDL characteristics of the SGS device.

[0092] Although only one of the conductive layers is shown as being incorporated into the SGS device, in other embodiments, multiple conductive layers may be incorporated into the SGS device. The conductive layers may be electrically coupled (connected together) to each other for incorporation into the long-channel SGS device. If multiple conductive layers are incorporated into the SGS device, then outwardly diffusing dopant may extend upward over two or more of the conductive layers 48 incorporated into the SGS device.

[0093] Memory cells 90 (e.g., NAND memory cells) are stacked vertically on top of each other. Each memory cell includes a region of semiconductor material (channel material) 58 and a region of conductive layer 48 (control gate region). Regions of conductive layer 48 not included by memory cell 90 can be considered word line regions (selection regions) that couple the control gate region to driver circuitry and / or other suitable circuitry. Memory cell 90 includes cell material (e.g., tunneling material, charge storage material, dielectric barrier material, and charge blocking material) within region 64.

[0094] In some embodiments, the conductive level 48 associated with the memory cell 90 may be referred to as a word line / control gate level (or memory cell level) because it contains word lines and control gates associated with the vertically stacked memory cells of the NAND string. The NAND string may include any suitable number of memory cell levels. For example, a NAND string may have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, etc.

[0095] Conductive materials 18, 44, and 80 together form the source structure 94 (i.e., Figure 19 The stack 16 can be considered to correspond to the source structure. The source structure may be similar to the source structure 216 described in the "Background Art" section. The source structure is shown as being coupled to a control circuitry system (e.g., CMOS) 96. The control circuitry system may be below the source structure 94 (as shown) or may be located at any other suitable location. The conductive material of the source structure 94 may be coupled to the control circuitry system (e.g., CMOS 96) at any suitable processing stage.

[0096] Figure 19 The source structure 94 includes a conductive material 18 (which may be a conductive doped semiconductor material and may be referred to as a first conductive doped semiconductor material), includes one or more of the first layers 20, includes a conductive doped semiconductor material 80 (which may be referred to as a second conductive doped semiconductor material), includes one or more of the second layers 42, and includes a conductive material 44 (which may be a conductive doped semiconductor material and may be referred to as a third conductive doped semiconductor material).

[0097] The source structure 94 also includes a block 98 that extends through the conductive doped semiconductor material 80 and corresponds to the doped region 36 of the material 22.

[0098] In some embodiments, materials 18, 80, and 44 may be the same composition as each other and may include, for example, conductive doped silicon, be substantially composed of, or be composed of. In some embodiments, at least one of materials 18, 80, and 44 may be a composition different from each other relative to materials 18, 80, and 44.

[0099] In the illustrated embodiment, the source structure 94 includes layers 20a to 20c and layers 42a to 42c. These layers may be insulating and may be kept thin enough not to significantly reduce the conductivity of the source structure 94. Furthermore, one or more layers may be omitted, and in some embodiments, all layers may be omitted so that the conductive materials 18, 80, and 44 are in direct contact with each other (e.g., ...). Figure 20 (As shown). Alternatively, one or more of layers 20a to 20c and 42a to 42c may be conductive, thereby enhancing the conductivity of the source structure 94.

[0100] In some embodiments, the channel material pillars 60 may be considered to represent a large number of substantially identical channel material pillars extending on the assembly 10; the term “substantially identical” means identical within reasonable tolerances of manufacture and measurement. Figure 19A The top-down view shows pillars 60 arranged within a matrix (in the illustrated embodiment, pillars 60 are hexagonally encapsulated), and shows slits 74 extending through the matrix of channel material pillars. In some embodiments, slits 74 may divide the pillars between a first block region 102 and a second block region 104. Thus, memory cells 90 on one side of slits 74 may be considered to be within the first block region 102, and memory cells 90 on the other side of slits 74 may be considered to be within the second block region 104. Block regions 102 and 104 may be similar to memory blocks (or memory sub-blocks) described in the "Background Art" section of this disclosure.

[0101] The advantage of the processing described in this article is that it removes... Figure 18 During the process of replacing material 52 with conductive material 84, support blocks 98 can help support various materials and structures provided above such blocks. This can advantageously mitigate bending, tipping, compression and / or other unwanted physical changes that would otherwise occur without support blocks 98.

[0102] In some embodiments, Figure 19 and 20 The assembly 10 can be considered an example of a memory device (i.e., a flash memory device, a NAND memory array, a NAND memory configuration, etc.).

[0103] The assemblies and structures discussed above can be used within integrated circuits (where the term "integrated circuit" refers to electronic circuitry supported by a semiconductor substrate) and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting fixtures, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0104] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0105] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The use of the term “dielectric” in some instances and the term “insulating” (or “electrically insulating”) in others provides a linguistic variation within this disclosure to simplify the premises of the appended claims and is not intended to indicate any significant chemical or electrical differences.

[0106] The terms "electrical connection" and "electrical coupling" may be used in this disclosure. These terms are considered synonymous. Using one term in some cases and another in others provides linguistic variation within this disclosure to simplify the presuppositions of the appended claims.

[0107] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The descriptions provided herein and the appended claims relate to any structure having the described relationships between various features, regardless of whether the structure is in a particular orientation in the drawings or rotated relative to that orientation.

[0108] Unless otherwise indicated, the cross-sectional views accompanying the drawings show only the features within the plane of the cross-section, and not the material behind the plane of the cross-section, in order to simplify the illustration.

[0109] When a structure is mentioned above as "on," "adjacent to," or "against" another structure, it may be directly on top of the other structure or there may be intervening structures. In contrast, when a structure is mentioned as "directly above," "directly adjacent to," or "directly against" another structure, there are no intervening structures. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless explicitly stated otherwise), but instead indicate upright alignment.

[0110] A structure (e.g., a layer, material, etc.) may be referred to as “vertically extending” to indicate that the structure extends generally upward from the underlying substrate (e.g., a base plate). A vertically extending structure may or may not extend substantially orthogonally relative to the upper surface of the substrate.

[0111] Some embodiments include an integrated assembly having a source structure. The source structure includes, in ascending order, a first conductive doped semiconductor material, one or more first insulating layers, a second conductive doped semiconductor material, one or more second insulating layers, and a third conductive doped semiconductor material. The source structure further includes a block extending through the second conductive doped semiconductor material. Vertically stacked conductive layers are above the source structure. The conductive layers include memory cell layers. A channel material extends vertically along the memory cell layers and into the source structure to directly contact the second conductive doped semiconductor material. One or more memory cell materials are located between the channel material and the vertically stacked conductive layers.

[0112] Some embodiments include a method of forming an integrated assembly. A first stack of a second material is formed, comprising a first material on top of a first material. The first material is conductive. A second region of the second material is doped while a first region of the second material remains undoped. The first region extends laterally around the second region. A second stack is formed above the first stack. The second stack has alternating first and second levels. A first opening is formed to extend through the first and second stacks. Cell material is formed within the first opening to line the opening. The cell material comprises a charge storage material and an insulating material. A channel material is formed within the lined first opening, and the channel material is separated from the charge storage material by the insulating material. A second opening is formed to travel through the second stack and reach the first region of the second material. The first region is selectively removed relative to the second region. The removal of the first region forms a conduit traveling around the second region and from the second opening to the cell material. The conduit extends through the cell material and into the channel material. A doped semiconductor material is formed within the extended conduit. A dopant is diffused outward from the doped semiconductor material into the channel material. The outwardly diffused dopant extends upwards to at least one of the first layers. A conductive material is formed within the first layer.

[0113] Some embodiments include a method of forming an integrated assembly. A first stack is formed, the first stack including a first material, at least one first layer above the first material, and a second material above the at least one first layer. The first material is conductive. A second region of the second material is doped while the first region of the second material remains undoped. The first region extends laterally around the second region. At least one second layer is formed above the second material, and a third material is formed above the at least one second layer. The first stack includes the third material and the at least one second layer. The third material is conductive. A second stack is formed above the first stack. The second stack has alternating first and second layers. A first opening is formed to extend through the first stack and the second stack. Cell material is formed within the first opening to line the first opening. The cell material includes a charge storage material and an insulating material. A channel material is formed within the lined first opening, and the channel material is separated from the charge storage material by the insulating material. A second opening is formed to travel through the second stack and reach the first region of the second material. The first region of the second material is selectively removed relative to the second region of the second material. The removal of the first region of the second material forms a conduit to the cell material. The conduit extends through the unit material and into the channel material. A doped semiconductor material is formed within the extended conduit. A dopant is diffused outward from the doped semiconductor material into the channel material. The diffused dopant extends upward into at least one of the first layers. A conductive material is formed within the first layer.

[0114] As per the regulations, the disclosed subject matter has been described in language that is more or less specific to structural or methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims should be given a full literal scope and properly interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly comprising: A source structure includes a first conductive doped semiconductor material, one or more first insulating layers above the first conductive doped semiconductor material, a second conductive doped semiconductor material above the one or more first insulating layers, one or more second insulating layers above the second conductive doped semiconductor material, and a third conductive doped semiconductor material above the one or more second insulating layers; the source structure further includes a block extending through the second conductive doped semiconductor material. Vertically stacked conductive layers are positioned above the source structure; the conductive layers include memory cell layers. The channel material extends vertically along the memory cell hierarchy and into the source structure to directly contact the second conductive doped semiconductor material; and One or more memory cell materials are disposed between the channel material and the vertically stacked conductive layers.

2. The integrated assembly according to claim 1, wherein the upper conductive layer of the vertically stacked conductive layers is the memory cell layer, and wherein the lower conductive layer of the vertically stacked conductive layers is the selection device layer.

3. The integrated assembly according to claim 1, wherein the first conductive doped semiconductor material, the second conductive doped semiconductor material, and the third conductive doped semiconductor material are the same composition as each other.

4. The integrated assembly of claim 3, wherein the first conductive doped semiconductor material, the second conductive doped semiconductor material and the third conductive doped semiconductor material comprise conductive doped silicon.

5. The integrated assembly of claim 1, wherein the block comprises doped silicon.

6. The integrated assembly of claim 1, wherein the block comprises silicon doped with one or more elements selected from groups 13 to 15 of the periodic table.

7. The integrated assembly according to claim 6, wherein the one or more elements selected from groups 13 to 15 of the periodic table are in units of 1 × 10⁻⁶. 18 From atoms per cubic centimeter to 1 × 10⁻⁶ 21 The total concentration exists in the range of atoms per cubic centimeter.

8. The integrated assembly of claim 1, wherein the block comprises boron-doped silicon.

9. The integrated assembly of claim 1, wherein the block comprises carbon-doped silicon.

10. The integrated assembly of claim 1, wherein the conductive layer comprises a metal.

11. The integrated assembly of claim 10, wherein the conductive layers are spaced apart from each other by intervention layers comprising silicon dioxide.

12. A method of forming an integrated assembly, comprising: A first stack of a second material, which is conductive, is formed on top of a first material. The second region of the second material is doped while the first region of the second material remains undoped; the first region extends laterally around the second region. A second stack is formed on top of the first stack; The second stack has alternating first and second levels; A first opening is formed to extend through the first stack and the second stack; A unit material is formed within the first opening to line the first opening, the unit material comprising a charge storage material and an insulating material; A channel material is formed within the lined first opening, and the channel material is separated from the charge storage material by the insulating material; A second opening is formed to allow passage through the second stack and to reach the first area of ​​the second material; The first region is selectively removed relative to the second region; the removal of the first region forms a conduit that travels around the second region and from the second opening to the unit material; The conduit extends through the unit material and into the channel material; Doped semiconductor material is formed within the extended conduit; The dopant is diffused outward from the doped semiconductor material into the channel material, and the outwardly diffused dopant extends upward to at least one of the first layers; and Conductive material is formed within the first layer.

13. The method of claim 12, further comprising forming a memory cell along the first layer, wherein the memory cell includes a region of the channel material; wherein the integrated assembly includes a memory device including the memory cell; and wherein the first material and the doped semiconductor material together form at least a portion of the source structure of the memory device.

14. The method of claim 13, further comprising forming a source selection device to include at least one of the first layers.

15. The method of claim 12, wherein the first material and the second material comprise semiconductor materials.

16. The method of claim 12, wherein the first material comprises conductive doped silicon, and wherein the second material comprises unconductive doped silicon.

17. The method of claim 16, wherein the first stack comprises one or more insulating layers between the first material and the second material.

18. The method of claim 17, wherein the insulating layer comprises a layer comprising silicon dioxide and a layer comprising silicon nitride.

19. The method of claim 17, wherein the insulating layer comprises a first composition sandwiched between two second compositions.

20. The method of claim 19, wherein the first composition comprises silicon dioxide, and wherein the second composition comprises silicon nitride.

21. The method of claim 16, wherein the doping of the second region of the second material comprises doping with one or more elements selected from groups 13 to 15 of the periodic table.

22. The method of claim 21, wherein the one or more elements selected from groups 13 to 15 of the periodic table are provided in a 1 × 10⁻⁶ matrix. 18 From atoms per cubic centimeter to 1 × 10⁻⁶ 21 The total concentration is within the range of atoms per cubic centimeter.

23. The method of claim 16, wherein the doping of the second region of the second material comprises doping with boron.

24. The method of claim 16, wherein the doping of the second region of the second material comprises doping with carbon.

25. A method of forming an integrated assembly, comprising: A first stack is formed, the first stack comprising a first material, at least one first layer above the first material, and a second material above the at least one first layer; the first material is conductive; The second region of the second material is doped while the first region of the second material remains undoped; the first region extends laterally around the second region. At least one second layer is formed on top of the second material, and a third material is formed on top of the at least one second layer; the first stack includes the third material and the at least one second layer; The third material is conductive; A second stack is formed on top of the first stack; The second stack has alternating first and second levels; A first opening is formed to extend through the first stack and the second stack; A unit material is formed within the first opening to line the first opening, the unit material comprising a charge storage material and an insulating material; A channel material is formed within the lined first opening, and the channel material is separated from the charge storage material by the insulating material; A second opening is formed to allow passage through the second stack and to reach the first area of ​​the second material; The first region of the second material is selectively removed relative to the second region of the second material; the removal of the first region of the second material forms a conduit into the unit material; The conduit extends through the unit material and into the channel material; Doped semiconductor material is formed within the extended conduit; The dopant is diffused outward from the doped semiconductor material into the channel material, and the outwardly diffused dopant extends upward to at least one of the first layers; and Conductive material is formed within the first layer.

26. The method of claim 25, wherein the charge storage material is a charge trapping material.

27. The method of claim 25, wherein the unit material comprises a dielectric barrier material and a charge barrier material.

28. The method of claim 25, wherein the first material and the third material are the same composition as each other.

29. The method of claim 28, wherein both the first material and the third material comprise conductive doped silicon.

30. The method of claim 29, wherein the second material comprises unconductively doped silicon.

31. The method of claim 30, wherein the doping of the second region of the second material comprises doping with one or more elements selected from groups 13 to 15 of the periodic table.

32. The method of claim 31, wherein the one or more elements selected from groups 13 to 15 of the periodic table are provided in a 1 × 10⁻⁶ matrix. 18 From atoms per cubic centimeter to 1 × 10⁻⁶ 21 The total concentration is within the range of atoms per cubic centimeter.

33. The method of claim 30, wherein the doping of the second region of the second material comprises doping with boron.

34. The method of claim 30, wherein the doping of the second region of the second material comprises doping with carbon.

35. The method of claim 25, wherein the at least one first layer is electrically insulating.

36. The method of claim 25, wherein the at least one first layer comprises a silicon dioxide layer and a silicon nitride layer.

37. The method of claim 25, wherein the at least one second layer is electrically insulating.

38. The method of claim 25, wherein the at least one second layer comprises a silicon dioxide layer and a silicon nitride layer.

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