Three-dimensional memory and methods of making three-dimensional memory

Abstract

The application provides a three-dimensional memory and a preparation method of the three-dimensional memory. The three-dimensional memory comprises a layer stack, a channel structure and a storage structure. The layer stack comprises conductor layers and dielectric layers which are alternately stacked. The channel structure penetrates the layer stack. The conductor layers comprise conductive materials. The storage structure is in the conductor layers, is formed on a surface of the channel structure and is between the channel structure and the conductive materials. The storage structure of the three-dimensional memory is in the conductor layers and is formed on the surface of the channel structure, so that when the three-dimensional memory is manufactured, the influence of process deviation on the performance of the three-dimensional memory caused by the removal of the sacrificial material can be avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and in particular to three-dimensional memory and methods for fabricating three-dimensional memory. Background Technology

[0002] Three-dimensional (3D) memory has attracted widespread attention due to its high storage capacity and low production cost.

[0003] A three-dimensional memory comprises a stacked structure formed on a substrate, a channel structure penetrating the stacked structure, and memory layers located on the surface of the channel structure. The stacked structure includes alternating conductor layers and dielectric layers. The conductive material in each conductor layer of the stacked structure is obtained by replacing a sacrificial material. During the replacement of the sacrificial material, etching deviations may occur, resulting in over-etching or under-etching of the sacrificial material in the horizontal direction for one or more conductor layers, affecting the transistor's performance parameters. Over-etching may even destroy the memory structure located on the surface of the channel structure, rendering the transistor corresponding to that conductor layer unable to store data, thus causing the memory cell to fail. Summary of the Invention

[0004] This application provides a three-dimensional memory that can improve the reliability of the memory.

[0005] In a first aspect, a three-dimensional memory is provided, comprising a stacked structure, a channel structure, and a storage structure. The stacked structure includes alternately stacked conductor layers and dielectric layers; the channel structure extends through the stacked structure. The conductor layers include a conductive material. The storage structure is formed within the conductor layers, on the surface of the channel structure, and located between the channel structure and the conductive material.

[0006] The storage structure of the three-dimensional memory is located in the conductor layer and formed on the surface of the channel structure. Therefore, when manufacturing the three-dimensional memory, the performance of the three-dimensional memory is improved by avoiding the impact of excessive or insufficient etching due to process errors during the removal of sacrificial materials.

[0007] In conjunction with the first aspect, in some possible implementations, the channel structure comprises a single-crystal semiconductor material.

[0008] Single-crystal semiconductor materials have high electron mobility, and using single-crystal semiconductor materials in the channel structure can improve the performance of three-dimensional memory.

[0009] In conjunction with the first aspect, in some possible implementations, the dielectric layer includes a protective structure located on the surface of the channel structure.

[0010] Channel structures can be formed using selective epitaxial growth (SEG) technology. During the formation of the channel structure, elements (such as nitrogen) in the sacrificial layer of the stacked structure may diffuse into the single-crystal semiconductor of the channel structure, affecting the performance of the 3D memory.

[0011] By placing a protective layer on the surface of the channel structure, the diffusion of elements in the sacrificial layer of the stacked structure can be reduced or even eliminated. Removing the protective layer at the site of the removed sacrificial layer on the surface of the channel structure before forming the memory structure can prevent process variations during etching from affecting the transistor's performance parameters.

[0012] In conjunction with the first aspect, in some possible implementations, the material of the channel structure is monocrystalline silicon; the material of each protective structure is amorphous silicon.

[0013] Amorphous silicon has a significantly lower hardness than crystalline silicon and is more chemically reactive. Therefore, monocrystalline silicon can be used as an etching stop layer to reduce the difficulty of the etching process.

[0014] In conjunction with the first aspect, in some possible implementations, the surface of the channel structure in the conductive layer includes grooves, and the storage structure is located in the grooves.

[0015] By creating grooves on the surface of the channel structure and placing the storage structure within the grooves, the number of defects in the single-crystal silicon channel structure can be reduced, thereby mitigating the impact of defects on the performance of the 3D memory.

[0016] In conjunction with the first aspect, in some possible implementations, the material of the channel structure is single-crystal silicon with a "001" lattice direction along the channel structure and penetrating the stacked structure.

[0017] Single-crystal silicon with a lattice orientation of "001" grows faster. By creating grooves at the locations of the conductive layer on the channel structure surface, the number of defects can be reduced. Therefore, the height of the channel structure can be increased while still meeting the required mobility. As the channel structure height increases, the growth time of the single-crystal silicon remains constant. Using single-crystal silicon with a lattice orientation of "001" for the channel structure allows for faster single-crystal silicon growth, shortening the fabrication time of 3D memory and reducing manufacturing costs.

[0018] In conjunction with the first aspect, in some possible implementations, the storage structure includes a tunneling layer, a charge trapping layer, and a blocking layer arranged sequentially along a direction away from the channel structure.

[0019] In a second aspect, a method for fabricating a three-dimensional memory is provided, comprising: forming a stacked structure on a substrate, the stacked structure comprising alternately stacked sacrificial layers and dielectric layers; forming a channel structure that extends through the stacked structure and through sacrificial material in the sacrificial layers; removing the sacrificial material; forming a memory structure at the location on the surface of the channel structure where the sacrificial material has been removed; and depositing a conductive material to replace the removed sacrificial material.

[0020] The memory structure is formed after the sacrificial material in the stacked structure is removed, which avoids the impact on the performance of the 3D memory due to over-etching or under-etching caused by process errors during the removal of the sacrificial layer, thereby improving the performance of the 3D memory.

[0021] In conjunction with the second aspect, in some possible implementations, the channel structure is made of a single-crystal semiconductor material.

[0022] In conjunction with the second aspect, in some possible implementations, forming the channel structure includes: forming a storage via that penetrates the stacked structure and passes through the sacrificial material; forming a protective layer on the sidewall of the storage via to which the protective layer is formed; and growing a single-crystal semiconductor material in the storage via to form the channel structure.

[0023] During the formation of the channel structure, elements (such as nitrogen) in the sacrificial material of the stacked structure may diffuse into the single-crystal semiconductor of the channel structure, affecting the performance of the 3D memory. By setting a protective layer on the surface of the channel structure, the diffusion of elements in the sacrificial layer of the stacked structure can be reduced or even eliminated, thereby improving the performance of the 3D memory.

[0024] In conjunction with the second aspect, in some possible implementations, the method further includes: removing the protective layer at the location of each sacrificial layer on the surface of the channel structure.

[0025] Before forming the memory structure, removing the protective layer located on the surface of the channel structure at the removed sacrificial layer can avoid the impact of process deviations in the etching process on the transistor's performance parameters.

[0026] In conjunction with the second aspect, in some possible implementations, the material of the channel structure is monocrystalline silicon; the material of each protective structure is amorphous silicon.

[0027] In conjunction with the second aspect, in some possible implementations, removing the protective layer at the location of the sacrificial material on the surface of the channel structure includes: using an etching process to remove the protective layer at the location of the sacrificial material on the surface of the channel structure, wherein the semiconductor material grown in the memory hole is an etching stop layer.

[0028] When removing sacrificial material, using the semiconductor material grown in the memory hole (i.e., the material of the channel structure) as an etch stop layer can reduce the time accuracy requirements of the etching process and reduce the difficulty of the etching process.

[0029] In conjunction with the second aspect, in some possible implementations, the semiconductor material grown in the storage hole is monocrystalline silicon; the material of the protective layer is amorphous silicon.

[0030] Amorphous silicon has a significantly lower hardness than crystalline silicon and is more chemically reactive. Therefore, monocrystalline silicon can be used as an etching stop layer to reduce the difficulty of the etching process.

[0031] In conjunction with the second aspect, in some possible implementations, the channel structure comprises a single-crystal semiconductor material. The method further includes forming a groove at a location on the surface of the channel structure where the sacrificial material has been removed. Forming a storage structure at the location on the surface of the channel structure where the sacrificial material has been removed includes forming the storage structure within the groove.

[0032] By creating grooves at the location of the conductive layer on the surface of the channel structure (i.e., the location of the removed sacrificial material), the number of defects in the single-crystal silicon channel structure can be reduced, thereby reducing the impact of defects on the performance of the 3D memory.

[0033] In conjunction with the second aspect, in some possible implementations, forming a groove at each location on the surface of the channel structure where the sacrificial layer is removed includes: forming an oxide at the location on the surface of the channel structure where the sacrificial material is removed; and removing the oxide to form the groove.

[0034] The channel structure is typically made of monocrystalline or polycrystalline silicon, while the dielectric layer is usually made of silicon oxide. Etching the channel structure may affect the structure of the dielectric layer.

[0035] By forming and removing oxides at each location on the surface of the channel structure where the sacrificial layer is removed, grooves can be formed, thus avoiding any impact on the structure of the dielectric layer.

[0036] In conjunction with the second aspect, in some possible implementations, the material of the channel structure is single-crystal silicon with a single-crystal lattice direction of "001" along the direction of the channel structure away from the substrate.

[0037] Single-crystal silicon with a lattice orientation of "001" grows faster. By creating grooves at the locations of the conductive layer on the channel structure surface, the number of defects can be reduced. Therefore, the height of the channel structure can be increased while still meeting the required mobility. As the channel structure height increases, the growth time of the single-crystal silicon remains constant. Using single-crystal silicon with a lattice orientation of "001" for the channel structure allows for faster single-crystal silicon growth, shortening the fabrication time of 3D memory and reducing manufacturing costs.

[0038] In conjunction with the second aspect, in some possible implementations, forming a storage structure at the location where the sacrificial layer is removed on the surface of the channel structure includes: sequentially forming a tunneling layer, a charge trapping layer, and a blocking layer stacked in the storage structure at the location where the sacrificial layer is removed on the surface of the channel structure.

[0039] Thirdly, an electronic device is provided, including the three-dimensional memory described in the first aspect. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of a NAND string circuit structure.

[0041] Figure 2 This is a schematic diagram of a three-dimensional memory structure.

[0042] Figure 3 This is a schematic structural diagram of a portion of a three-dimensional memory.

[0043] Figure 4 This is a schematic structural diagram of a three-dimensional memory provided in an embodiment of this application.

[0044] Figure 5 This is a schematic diagram of the crystal structure of single-crystal silicon.

[0045] Figure 6 This is a schematic flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of this application.

[0046] Figures 7 to 19 This is a schematic diagram of the fabrication process of a three-dimensional memory provided in an embodiment of this application.

[0047] Figure 20 This is a schematic structural diagram of a three-dimensional memory and control circuit provided in an embodiment of this application.

[0048] Figure 21 This is a schematic flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of this application. Detailed Implementation

[0049] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0050] As used herein, the terms “above,” “over,” “to,” “between,” and “on” can refer to the relative position of a layer with respect to other layers. A layer being “above,” “over,” or “on” another layer, or being connected or bonded “to” another layer or “in contact” with another layer, can mean directly contacting other layers or having one or more interstitial layers. A layer being “between” multiple layers can mean directly contacting those multiple layers or having one or more interstitial layers.

[0051] Compared with traditional two-dimensional (2D) memory, three-dimensional (3D) memory has higher storage capacity and lower production cost, and has attracted widespread attention.

[0052] Figure 1 It is a schematic circuit topology diagram of a three-dimensional NAND series. Figure 2 This is a schematic diagram of a three-dimensional memory structure.

[0053] NAND is an operation that returns zero if and only if all operands are 1; otherwise, the result is 1. The Boolean operator for NAND is NAND. NAND strings can also be called NAND strings. Three-dimensional memory can include multiple NAND strings.

[0054] Each NAND string can include multiple transistors arranged in series. Taking four transistors Q0, Q1, Q2, and Q3 arranged in series as an example, this will be explained.

[0055] A NAND string comprises transistors with storage capabilities. Each transistor with storage capabilities has a control gate (CG) and a charge storage region (CSR). The CSR may include, for example, a charge trapping layer. For example, transistors Q1 and Q2 have storage capabilities. The select gate of transistor Q1 is connected to word line (WL)0, and the select gate of transistor Q2 is connected to WL1. Each transistor can be understood as a memory cell.

[0056] The NAND string can also include other transistors. For example, the gate of transistor Q3 can be connected via the select line SGS to control the on or off state of transistor Q3, thereby controlling whether the NAND string is connected to bit line (BL) 111. The gate of transistor Q0 can also be connected via the select line SGD to control the on or off state of transistor Q0, thereby controlling whether the NAND string is connected to common source line 128. Transistors Q0 and Q3 can also include charge storage regions; however, during use, no charge is stored in the charge storage regions of transistors Q0 and Q3.

[0057] For transistors with storage capabilities, the charge storage region can utilize a non-conductive dielectric material to store charge in a non-volatile manner. The charge storage region can be a three-layer dielectric consisting of an oxide layer, a nitride layer, and an oxide-nitride-oxide (ONO) layer sandwiched between the control gate and the transistor channel. For example, ONO can be silicon oxide (SiO2)-silicon nitride (Si3N4)-silicon oxide, or ONO can be aluminum oxide (Al2O3)-Si3N4-SiO2, etc.

[0058] like Figure 2 As shown in (C), the charge trapping layer 243 is sandwiched between the barrier layer 244 and the tunneling layer 242.

[0059] From the control gate to the center of the channel structure 240, the first oxide layer is a barrier layer 244 for blocking electron tunneling from the charge trapping layer 243 to the control gate or from the control gate to the charge trapping layer 243. The barrier layer 244 may be a stack of dielectrics; for example, in one embodiment, the barrier layer may be a stack of dielectric Al2O3-SiO2.

[0060] From the control gate to the center of the channel structure 240, the second oxide layer is a tunneling layer 242, through which electrons can tunnel from the channel to the charge trapping layer 243 during programming. This tunneling of electrons from the channel through the tunneling layer 242 to the charge trapping layer 243 can also be referred to as electron injection into the charge trapping layer 243.

[0061] By injecting electrons from channel structure 240 into the nitride of charge trapping layer 243, a transistor with storage capability can be programmed, in which electrons are trapped and stored in a limited area of ​​charge trapping layer 243.

[0062] The charge stored in the charge trapping layer 243 can change the threshold voltage of the transistor. For example, the threshold voltage of the transistor is VT1 when no electrons are injected into the charge trapping layer 243, and the threshold voltage of the transistor is VT2 after electrons are injected into the charge trapping layer 243. When the voltage of the control gate of the transistor is between VT1 and VT2, the on and off states of the transistor can represent "1" and "0" in digital logic, respectively, thereby realizing the storage of data.

[0063] Data stored in a transistor can be erased by injecting holes into the charge-trapping layer 243 formed by nitride, and then recombinating the injected holes with electrons. Alternatively, data can be erased by extracting electrons from the nitride, for example, by applying an electric field to cause electrons to tunnel from the charge-trapping layer 243 formed by nitride into the channel. Of course, both mechanisms can be used simultaneously for data erasure.

[0064] like Figure 2 As shown in (A), an insulating film 220 is disposed on the substrate 210, a metal layer is disposed on the insulating film 220, and a common source line SL0 is disposed in the metal layer.

[0065] A stacked structure is provided on the metal layer. The stacked structure includes alternately stacked metal layers and insulating layers. A channel structure 240 is provided in the stacked structure. Figure 2 The NAND string shown in (A) is linear, and the two channel structures 240 correspond to NAND string C0 and NAND string C1 respectively.

[0066] Figure 2 (B) in the middle is Figure 2 A magnified schematic diagram of a local area (A) in the diagram. Figure 2 (C) in the middle is Figure 2 The cross-sectional view of (B) along line BB'. Figure 2 (B) in the middle is Figure 2 The cross-sectional view of (C) along the line CC'.

[0067] The channel structure 240 includes a semiconductor channel 241, a tunneling layer 242, a charge trapping layer 243, and a barrier layer 244 arranged sequentially outward from the center of the channel structure 240.

[0068] Semiconductor channel 241 can be a semiconductor, that is, a material whose conductivity at room temperature is between that of a conductor and an insulator. Barrier layer 244 can be an oxide, such as Al2O3, SiO2, or a stack of Al2O3-SiO2. Charge trapping layer 243 can be a nitride, such as Si3N4. Tunneling layer 242 can be an oxide, such as SiO2.

[0069] It should be understood that the semiconductor channel 241 is a solid cylinder, while the tunneling layer 242, charge trapping layer 243, and barrier layer 244 are all hollow cylinders. The horizontal cross-section of the cylinder can be circular, elliptical, square, or other shapes. The horizontal cross-section of the cylinder may deviate from a perfect circle or ellipse.

[0070] In the fabrication of a three-dimensional memory, the stacked structure may include alternating sacrificial layers and insulating layers. Through-holes are formed throughout the stacked structure, and channel structures 240 are formed within these through-holes. Subsequently, the sacrificial layer material in the stacked structure is replaced with a metallic material, thereby achieving electrical connections between the gates of the individual transistors in the three-dimensional memory. Figure 2 As shown in (A), in the formed three-dimensional memory, insulating layers D0 to D4 are alternately stacked with metal layers SGS, WL0, WL1, and SGD. Before the metal material replaces the sacrificial layer material, the locations of the metals in the metal layers SGS, WL0, WL1, and SGD serve as the sacrificial layer material. The sacrificial layer material can be, for example, silicon nitride.

[0071] like Figure 2 As shown in (B), the contact point between the metal material layer and the barrier layer 244 in the CSR can be understood as the gate of the transistor. The contact point between the metal material layer WL1 and the barrier layer 244 can be understood as the gate of transistor Q2, the contact point between the metal material layer WL1 and the barrier layer 244 can be understood as the control gate of transistor Q2, and the contact point between the metal material layer SGD and the barrier layer 244 can be understood as the gate of transistor Q3.

[0072] Figure 3 Yes, yes Figure 2 A magnified schematic diagram of a local area (A) in the diagram.

[0073] When replacing the sacrificial layer material in a multilayer structure with a metallic material, the sacrificial layer in the multilayer structure needs to be removed first. This can be done using an etching process.

[0074] During the etching process, due to process deviations, over-etching may occur in the horizontal direction for one or more sacrificial layers, affecting transistor performance parameters such as erase / write operation voltage, erase / write lifetime, and data retention time. It may even damage the charge trapping layer, causing the memory cell to fail, that is, the transistor will not have the ability to store data.

[0075] Generally, the etching of the sacrificial layer that is far from the substrate is faster, while the etching of the sacrificial layer that is close to the substrate is slower.

[0076] Excessive etching of the sacrificial layer at the location of the metal layer 310, which is far from the substrate, causes the metal layer 310 to extend into the channel structure 240, resulting in memory cell failure.

[0077] Insufficient etching of the sacrificial layer at the location of the metal layer 320 near the substrate results in sacrificial layer material existing between the metal layer 320 and the channel structure 240. The large distance between the metal layer 320 and the channel structure 240 affects transistor performance parameters such as erase / write operation voltage and threshold voltage, and may even prevent effective control of transistor turn-on and turn-off, leading to memory cell failure.

[0078] Furthermore, as the number of layers in the stacked structure increases, the height of the channel structure 240 also increases. When the semiconductor channel 241 uses a single-crystal semiconductor material, the distance from the substrate 210 increases, resulting in a greater number of defects per unit volume in the semiconductor channel 241. Therefore, increasing the number of layers in the stacked structure leads to a decrease in the electron mobility of the transistor.

[0079] According to the structure of 3D memory, the performance of a NAND string is determined by the performance of the transistor with the lowest electron mobility within the NAND string. Therefore, as the number of layers in the stacked structure increases, the performance of 3D memory decreases.

[0080] To address the aforementioned issues, embodiments of this application provide a three-dimensional memory.

[0081] Figure 4 This is a schematic structural diagram of a three-dimensional memory provided in an embodiment of this application.

[0082] The three-dimensional memory includes a substrate 210, a stacked structure, a channel structure 440, and a storage structure 450.

[0083] The stacked structure may be located on the substrate 210, and the stacked structure includes alternating stacked conductor layers 430 and dielectric layers 420. Generally, the stacked structure includes multiple conductor layers 430 and multiple dielectric layers 420.

[0084] In some embodiments, the three-dimensional memory may also exclude the substrate 210. The three-dimensional memory can be fabricated on the substrate 210, and the substrate can then be removed.

[0085] The channel structure is a 440-degree through-layer structure.

[0086] The conductive layer 430 includes the conductive material.

[0087] The storage structure 450 is formed in the conductor layer on the surface of the channel structure and is located between the channel structure 440 and the conductive material.

[0088] Each memory structure 450 and its corresponding channel structure 440 constitute a transistor. A conductive material connects to the memory structure, and the signal from the conductive material serves as the control gate (CG) signal for that transistor.

[0089] Each storage structure 450 is located on the surface of the channel structure 440 and is in contact with the conductive material in the conductor layer 430 corresponding to the storage structure 450.

[0090] Because the memory structure is located on the conductor layer and formed on the surface of the channel structure, it is formed after the sacrificial layer is removed. Therefore, the memory structures 450 located on different conductor layers do not contact each other. Or, on the surface of the channel structure 440, the memory structures 450 located on different conductor layers do not contact each other.

[0091] In a NAND string, the storage structure 450 in the upper and lower conductor layers is separated from the channel structure 440 by the dielectric layer 420, such as... Figure 4 As shown.

[0092] Or, such as Figure 16 As shown, the storage structure 450 includes a tunneling layer 732, a charge trapping layer 733, and a barrier layer 734. The storage structure 450 in the upper and lower conductor layers is protected by a structure (i.e., a barrier layer) on the surface of the channel structure 440. Figure 16 The protective layer 710 shown is separated.

[0093] The conductive layer 430 in the stacked structure is obtained by replacing the sacrificial material in the sacrificial layer with a conductive material. After forming the channel structure 440 that penetrates the stacked structure, the sacrificial material in the sacrificial layer is removed, and a memory structure 450 is formed on the surface of the channel structure 440. Then, conductive material is deposited to form the conductive layer 430. This avoids the impact of over-etching or under-etching due to process errors during sacrificial layer removal on the performance of the 3D memory, thus improving the performance of the 3D memory.

[0094] The dielectric layer 420 can be made of insulating materials such as silicon oxide. The sacrificial layer can be made of silicon nitride. The conductive layer can be made of metal or other conductive materials (such as graphene or polymer compounds).

[0095] The channel structure 440 can be made of a semiconductor material. For example, it can be a polycrystalline semiconductor or a single-crystal semiconductor. Using a single-crystal semiconductor in the channel structure 440 results in fewer defects, which can improve the performance of the three-dimensional memory.

[0096] The three-dimensional memory may also include a protective layer located on the surface of the channel structure. Before forming the memory structure, the protective layer at the location of the conductive layer on the surface of the channel structure 440 can be removed to form multiple protective structures.

[0097] In other words, the three-dimensional memory may also include a protective structure within the dielectric layer 420, located on the surface of the channel structure 440. This means the protective structure is in contact with the electrolyte material within the dielectric layer.

[0098] To prevent elements in the sacrificial layer from diffusing into the semiconductor of the channel structure 440 during semiconductor growth and affecting the performance of the three-dimensional memory, a protective layer can be formed on the sidewall of the storage hole before the channel structure 440 is formed in the storage hole that penetrates the stacked structure.

[0099] When removing the sacrificial material, process variations may cause the protective layer to be etched in whole or in part. If the protective layer is part of the memory structure, such as as a tunneling layer or as part of a tunneling layer, the thickness of the protective layer after removing the sacrificial material affects the transistor's performance parameters.

[0100] Therefore, the protective layer at the location of the surface sacrificial layer of the channel structure 440 can be removed. The protective layer is divided into multiple protective structures. Each protective structure corresponds one-to-one with the dielectric layer 420. Each protective structure is located on the surface of the channel structure 440 and is in contact with the dielectric layer 420 corresponding to that protective structure.

[0101] By removing the protective layer located on the surface of the channel structure 440 at the removed sacrificial layer, the impact of etching process deviations on transistor performance parameters can be avoided.

[0102] In each transistor of the 3D memory, the storage structure is located between the gate and the channel structure 440. The storage structure has two stable states, allowing the transistor to be in both on and off states when an equal gate voltage is provided. Data is stored by adjusting these two stable states. The storage structure can be a charge trapping structure (ONO), including a tunneling layer, a charge trapping layer, and a blocking layer. The storage structure can also be a ferroelectric storage structure, etc. This application does not limit the specific implementation of this structure.

[0103] The channel structure 440 can be made of a single-crystal semiconductor. For example, the channel structure 440 can be made of single-crystal silicon. The protective layer can be made of an amorphous semiconductor, such as amorphous silicon. Amorphous silicon has a significantly lower hardness than crystalline silicon and is chemically more reactive, therefore the single-crystal silicon in the channel structure 440 can be used as an etching stop layer. When removing the amorphous silicon protective layer, an etchant with a lower etching rate on the silicon oxide dielectric layer can be selected. Using amorphous silicon as the protective layer can reduce the difficulty of the etching process.

[0104] Before forming the memory structure 450, a groove can be formed on the surface of the channel structure 440 at the location where the sacrificial layer is removed. The memory structure 450 is formed in the groove, and then a conductive material is deposited to replace the sacrificial layer, forming a conductive layer 430.

[0105] In other words, in each conductive layer 430, the surface of the channel structure 440 includes a groove, and the storage structure corresponding to the conductive layer 430 is located in the groove.

[0106] As the number of layers in the stacked structure increases, the height of the channel structure 440 also increases. When the semiconductor channel 241 uses a single-crystal semiconductor material, the greater the distance from the substrate 210, i.e., the higher the growth height of the single-crystal silicon, the more defects there are per unit volume in the channel structure 440. By setting a groove at the location of the conductive layer 430 on the surface of the channel structure 440 (i.e., the location of the removed sacrificial layer), the number of defects can be reduced, thereby reducing the impact of defects on the performance of the three-dimensional memory.

[0107] The material for channel structure 440 can be monocrystalline silicon. Monocrystalline silicon has a face-centered cubic crystal structure, such as... Figure 5 As shown, Si atoms are located at the center of the six faces of the cube and at the eight vertices of the cube.

[0108] In the crystal structure of single-crystal silicon, points A, B, C, and D each contain four Si atoms, located at the four vertices of a cube. Specifically, A, B, and C are three vertices on the same face of the cube; AB is one edge of the cube; BC is another edge; and AD is the body diagonal. The direction along the side length of the face-centered cubic structure (e.g., along edge length AB) is the lattice direction "001"; the direction along the diagonal of one face of the face-centered cubic structure (e.g., along line AC) is the lattice direction "110"; and the direction along the diagonal of the face-centered cubic structure (e.g., along line AD) is the lattice direction "111". The lattice direction can also be called the crystal orientation. Single-crystal silicon can be grown along lattice directions "001", "110", or "111". Preferably, the channel structure uses single-crystal silicon with a lattice direction of "001" along the direction away from the substrate.

[0109] Single-crystal silicon with a lattice orientation of "110" grows more slowly but has fewer defects, thus achieving better charge mobility and improving the performance of three-dimensional memory.

[0110] Single-crystal silicon with a lattice orientation of "001" grows faster. By creating grooves at the locations of the conductive layer 430 on the surface of the channel structure 440, the number of defects can be reduced. Therefore, the height of the channel structure 440 can be increased while still meeting the mobility requirements. As the height of the channel structure 440 increases, the growth time required for single-crystal silicon remains constant. Using single-crystal silicon with a lattice orientation of "001" in the channel structure 440 allows for faster single-crystal silicon growth, shortening the fabrication time of three-dimensional memory and reducing manufacturing costs.

[0111] Figure 6 This is a schematic flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of this application.

[0112] Prior to S501, one or more metal layers in a stacked structure can be formed on the substrate 201. The metal layers may include patterned metals, thereby enabling the formation of various circuits on the substrate 201. For example, a metal layer for transmitting power signals, control signals for a three-dimensional memory, and other signals can be formed.

[0113] Alternatively, circuitry can be formed on other chips and then bonded to the 3D memory for signal transmission. For details, please refer to... Figure 20 Explanation.

[0114] The substrate 210 can be made of semiconductor materials such as silicon (Si), germanium (Ge), or gallium arsenide. When multiple metal layers are formed, the materials of the multiple metal layers can be the same or different.

[0115] The following explanation will be based on the example of a substrate 210 made of silicon.

[0116] S501, a stacked structure is formed on substrate 210.

[0117] A stacked structure consists of multiple sacrificial (SAC) layers and multiple dielectric layers stacked alternately. For example... Figure 7 As shown, the multiple sacrificial layers are SAC0, SAC1, SAC2, and SAC3. The multiple dielectric layers are D0, D1, D2, D3, and D4.

[0118] The sacrificial material in the sacrificial layer will be replaced by a conductive material in subsequent processes to form the gate signal transmission lines of each transistor, such as word lines WL0, WL1, etc. The sacrificial material can be, for example, silicon nitride.

[0119] The dielectric layer is used for insulation between word lines. The material of the dielectric layer can be an insulator such as silicon oxide (SiO2).

[0120] Layered structures can be formed through deposition processes. For example, chemical vapor deposition can be used to generate layered structures.

[0121] Chemical vapor deposition (CVD) is a process in which a gaseous reactant containing elements that make up a thin film is introduced into a reaction chamber, where a chemical reaction occurs on the wafer surface, thereby generating the desired solid film and depositing it on the surface.

[0122] S502, etch a memory hole (MH) through the stacked structure.

[0123] The storage hole passes through the sacrificial material in the sacrificial layer.

[0124] Etching technology is mainly divided into dry etching and wet etching.

[0125] Dry etching involves exposing the silicon wafer surface to plasma generated in a gaseous state. The plasma passes through windows created in the photoresist and undergoes a physical or chemical reaction (or both) with the silicon wafer, thereby removing the exposed surface material. Dry etching can also be called reactive ion etching (RIE) or photolithography.

[0126] Wet etching primarily utilizes chemical reagents to react with the material being etched. It is also used to etch certain layers on silicon wafers or to remove residues left after dry etching.

[0127] Storage vias can be formed using reactive ion etching (RIE). RIE technology offers the advantage of faster etching speeds in the vertical direction.

[0128] The storage via extends vertically through alternating sacrificial and insulating layers. The storage via may extend downwards to substrate 210.

[0129] It should be understood that the size of the storage aperture can vary from the top away from the substrate 210 to the bottom near the substrate 210. For example, the size of the storage aperture can gradually decrease from the top to the bottom.

[0130] Figure 7 The diagram shows the structure formed after S502.

[0131] S503, a protective layer 710 is deposited in the storage hole to form Figure 8 The structure shown.

[0132] Preferably, the protective layer 710 can be formed using atomic layer deposition (ALD) at a temperature below 400°C. The thickness of the protective layer 710 can be 5 to 20 angstroms (Å). The protective layer 710 can be, for example, amorphous silicon. It should be understood that the thicknesses of the sacrificial layer and dielectric layer follow industry standards, and the thickness of the protective layer 710 is much smaller than the thicknesses of the sacrificial layer and dielectric layer.

[0133] Atomic layer deposition (ALD), also known as single-atom layer deposition, is a method that deposits material onto a substrate surface layer by layer in the form of single-atom films. ALD shares similarities with conventional chemical deposition. However, in ALD, the chemical reaction of the new atomic layer is directly related to the previous layer, ensuring that only one atomic layer is deposited per reaction.

[0134] The process temperature for atomic layer deposition can be less than 400 degrees Celsius (°C).

[0135] S504, the protective layer 710 on the surface of the substrate 210 is removed by etching.

[0136] Reactive ion etching technology has the advantage of faster etching speed in the vertical direction. The protective layer 710 at the bottom of the storage hole can be removed by hydrogen plasma, exposing the surface of the substrate 210.

[0137] like Figure 9 As shown, the storage hole passes vertically through the stacked structure, and the sidewall of the storage hole is covered with a protective layer 710.

[0138] S505, grows single-crystal silicon in the memory hole to form channel structure 440.

[0139] Selective epitaxial growth (SEG) technology can be used to grow single-crystal silicon in memory holes.

[0140] Selective epitaxial growth refers to epitaxial growth performed within a defined area on a substrate.

[0141] The substrate 210 is made of silicon and can be used as a single-crystal seed to grow single-crystal silicon in the memory hole. It should be understood that the crystal orientation of the single-crystal silicon grown in the memory hole is the same as that of the substrate 210. Crystal orientation refers to the lattice direction.

[0142] It should be understood that step S504 is optional. Using a clean single-crystal silicon substrate as the single-crystal seed for SEG is an effective way to perform SEG. Of course, other methods can also be used for the single-crystal seed for SEG, and this application does not limit the specific methods described in the embodiments.

[0143] The lattice orientation of the single-crystal silicon channel structure 440 can be "110" or "001", etc. With a lattice orientation of "110", the grown single-crystal silicon has fewer defects and better charge mobility, thus improving the performance of the 3D memory. With a lattice orientation of "001", the single-crystal silicon grows faster, shortening the fabrication time of the 3D memory and reducing manufacturing costs.

[0144] A wafer with a lattice orientation of "001" can be used as substrate 210.

[0145] Single-crystal silicon can be grown in memory vias using various epitaxial growth techniques. Generally, the temperature range for the SEG process is 400-1000℃, with the specific temperature selection depending on the semiconductor material being grown.

[0146] During the SEG process, due to the high temperature, atoms such as nitrogen (N) in the dielectric layer may diffuse into the monocrystalline silicon, affecting its performance. The protective layer 710 placed on the sidewall of the memory via prevents atoms from the dielectric layer from diffusing into the monocrystalline silicon within the memory via.

[0147] Before S505, the bottom of the storage hole, i.e. the surface of the substrate 210 in the storage hole, can be pre-cleaned.

[0148] It should be understood that in multiple storage holes, single-crystal silicon grows synchronously upward from the surface of substrate 210. Figure 10 The structure after S505 is shown.

[0149] S506, Remove the sacrificial material in the sacrificial layer and the protective layer 710 on the surface of the channel structure where the sacrificial material is located.

[0150] Since the storage hole passes through the generated material, after the sacrificial material is removed, the protective layer 710 on the surface of the channel structure at the location of the sacrificial material is exposed, and the protective layer 710 at that location can be removed.

[0151] Choose an etchant that can etch the sacrificial layer, has low corrosivity to the dielectric layer, and has low corrosivity to monocrystalline silicon.

[0152] If the etchant is highly corrosive to the sacrificial layer but less corrosive to amorphous silicon, the amorphous silicon can be used as an etching stop layer. Then, an etchant that is highly corrosive to amorphous silicon but less corrosive to monocrystalline silicon is selected to remove the protective layer 710 on the surface of the channel structure 440 at the location of the sacrificial layer.

[0153] If the etchant is highly corrosive to the sacrificial layer and amorphous silicon, but less corrosive to monocrystalline silicon, the channel structure 440 can serve as an etch stop layer. In other words, the etchant has weak etching properties for the dielectric layer and monocrystalline silicon. Therefore, during etching, the material of the sacrificial layer (such as nitrides) will be etched away, and the amorphous silicon sidewalls, which act as the protective layer 710, will be over-etched. Finally, the etching stops at the surface of the monocrystalline silicon, which has higher hardness and is less prone to etching.

[0154] The method of stopping etching by using an etch stop layer can be called a self-limited recess process. This etch stop layer can also be called a self-limited recess etch stop layer.

[0155] Because the etching rate is higher at the top of the substrate than at the bottom of the substrate during the etching process, the etching time needs to be controlled to avoid completely removing the protective layer 710 on the sidewall of the single crystal silicon.

[0156] If the protective layer 710 is completely removed, it will be difficult to fill the space left by the removed protective layer 710 due to its small thickness, which will have an adverse effect on the performance of the three-dimensional memory.

[0157] The selection of the material and etchant for the protective layer 710 should ensure that removing the protective layer 710 from the surface of the channel structure at the location of the sacrificial layer avoids damage to the dielectric layer structure and the channel structure 440 in the stacked structure. In other words, by employing a self-limited recess process, using single-crystal silicon as the etch stop layer to remove the silicon oxide layer 731 on the silicon surface, damage to the dielectric layer structure and the channel structure 440 in the stacked structure can be avoided, and the process difficulty can be reduced.

[0158] Figure 11 The structure after S506 is shown. Figure 12 Yes Figure 11 A magnified view of the dashed area in the image. The sacrificial layer has been removed. The protective layer 710 has been etched into separate rings surrounding the pillars of the channel structure 440.

[0159] S507, etch a groove at the location of the sacrificial layer removed from the surface of channel structure 440.

[0160] Specifically, prior to S507a, the surface of the channel structure 440 at the location of the removed sacrificial layer is pre-cleaned.

[0161] S507a can grow a silicon oxide layer 731 on the surface of the channel structure 440 at the location of the removed sacrificial layer through oxidation processes such as wet oxidation and dry oxidation. Figure 13 As shown.

[0162] Since the protective layer 710 is also made of silicon, silicon oxide will also be grown on the surface of the protective layer 710. That is to say, the silicon oxide layer 731 is located on the surface of the channel structure 440 and the protective layer 710 at the location of the sacrificial layer.

[0163] During the growth of the oxide layer on the surface of channel structure 440, silicon atoms on the surface of channel structure 440 undergo a chemical reaction to generate silicon oxide, thus forming the oxide layer. Therefore, during oxide layer formation, the surface of channel structure 440 at the location of the sacrificial layer—that is, the interface between single-crystal silicon and silicon oxide—gradually moves towards the center of channel structure 440. Because oxide layer growth is non-directional, while the surface of channel structure 440 moves towards the center of channel structure 440 in a direction parallel to the substrate surface, it also moves towards the center of the dielectric layer in a direction perpendicular to the substrate surface.

[0164] S507b uses an etching process to remove the silicon oxide layer 731 on the surface of the channel structure 440.

[0165] Removing the silicon oxide layer 731 from the surface of the channel structure 440 exposes the surface of the channel structure 440.

[0166] Wet etching can be used. Wet etching does not affect the lattice of single-crystal silicon. Since the etching rate of wet etching is non-directional, meaning the etching rate is essentially the same in all directions, etching the silicon oxide layer 731 on the surface of the channel structure 440 can also be understood as removing the silicon oxide layer 731. In the process of generating the silicon oxide layer 731 through oxidation, all or part of the silicon element in the silicon oxide layer 731 originates from the single-crystal silicon in the channel structure 440. That is, when growing the silicon oxide layer 731 using oxidation, the silicon on the surface of the channel structure 440 and the protective layer 710 at the location of the sacrificial layer undergoes a chemical reaction to form the silicon oxide in the silicon oxide layer 731. Therefore, through S507a to S507b, an oxide layer is grown on the surface of the channel structure 440 at the location of the sacrificial layer, and then the oxide layer is etched, forming a groove on the surface of the channel structure 440 at the location of the sacrificial layer, such as... Figure 14 and Figure 15 As shown. Figure 15 It is a 3D image. Figure 14 This is a cross-sectional view.

[0167] Due to the changes in the channel structure 440 surface during the growth of the oxide layer, the width of the groove is generally slightly larger than the width (or thickness) of the sacrificial layer.

[0168] Before S507b, it can be cleaned again.

[0169] It should be understood that the dielectric layer material can also be silicon oxide. During S507b, a portion of the dielectric layer surface is also removed. To avoid compromising the insulating effect of the dielectric layer, the duration of S507b should be controlled to remove the silicon oxide from the surface of the monocrystalline silicon without affecting the insulating function of the dielectric layer.

[0170] In single-crystal silicon grown using the SEG process, the number of defects per unit volume of single-crystal silicon increases with the increase in growth height. In other words, in a single-crystal silicon channel structure, the number of defects at the top (the part away from the substrate) of the channel structure is greater than that at the bottom (the part closer to the substrate).

[0171] Therefore, in a channel structure, the number of defects per unit volume of single-crystal silicon increases with the distance from the center of the channel structure. In other words, in a single-crystal silicon channel structure, there are more surface defects than internal defects.

[0172] An increase in the number of defects leads to a decrease in charge mobility and a reduction in memory cell performance.

[0173] The etching rate at the top of the channel structure is greater than that at the bottom of the channel structure.

[0174] By using S507, growing and etching an oxide layer on the surface of the channel structure 440 at the location of the sacrificial layer to form a groove can effectively reduce the number of defects at the memory cells within the vertical channel, minimizing the impact of the SEG process on the performance of the memory cells, thereby improving the capacity and performance of the 3D memory. Under the same transistor performance requirements, by setting the groove, the number of sacrificial and dielectric layers in the stacked structure can be increased, i.e., the number of transistors per unit area can be increased, effectively improving the capacity of the 3D memory.

[0175] S508, a storage structure is formed in the groove.

[0176] The storage structure can be a ferroelectric storage structure. That is to say, through... Figure 6 The method shown can be used to fabricate three-dimensional ferroelectric memory.

[0177] Ferroelectric memory is a type of non-volatile memory produced using a special process. It is formed from artificially synthesized lead-zirconium-titanium (PZT) or hafnium-zirconium oxide (HfZrOx) materials to create the memory crystal. When an electric field is applied to a ferroelectric transistor, the central atoms move in the direction of the field and remain in a low-energy state (I). Conversely, when the electric field is reversed and applied to the same ferroelectric transistor, the central atoms move in the direction of the field and remain in another low-energy state (II). The movement and coupling of numerous central atoms within the crystal unit cell forms ferroelectric domains, which then generate polarization charges under the influence of the electric field. The polarization charges generated by ferroelectric domains reversing under an electric field are higher, while those generated without reversal are lower. This binary stability of ferroelectric materials allows them to be used as memory.

[0178] In particular, when the electric field is removed, the central atom remains stationary in a low-energy state, and the state of the memory is preserved. Therefore, the state of the memory cell can be determined by whether the ferroelectric domains reverse under an electric field to form a high-polarization charge or not reverse to form a low-polarization charge. The reversal of ferroelectric domains does not require a high electric field; a normal operating voltage is sufficient to change the state of the memory cell to "1" or "0". Furthermore, no charge pump is needed to generate high-voltage data erasure, thus eliminating write / erase delays. This characteristic allows ferroelectric memory to continue retaining data after power loss, offers fast write speeds, has an unlimited write lifespan, and is less prone to damage.

[0179] The storage structure can also be a charge trapping structure ONO, etc. The charge trapping structure ONO includes a tunneling layer 732, a charge trapping layer 733, and a barrier layer 734, such as... Figure 16 As shown.

[0180] A tunneling layer 732, a charge trapping layer 733, and a barrier layer 734 are sequentially deposited within the groove.

[0181] Charge trapping structures can be formed through chemical vapor deposition or atomic layer deposition. The charge trapping structure includes a tunneling layer 732, a charge trapping layer 733, and a barrier layer 734.

[0182] Atomic layer deposition (ALD) is a method that deposits material onto a substrate surface layer by layer in the form of single-atom films. ALD is similar to conventional chemical deposition. However, in ALD, the chemical reaction of the new atomic layer is directly related to the previous layer, ensuring that only one atomic layer is deposited per reaction.

[0183] In some embodiments, the thickness of the charge trapping structure can be less than 50 Å, which reduces the erase / write voltage to 5 volts (V), speeds up memory cell access, increases erase / write lifetime, and reduces data retention time.

[0184] It should be understood that during S508, tunneling layer, charge trapping layer, and barrier layer materials are also grown on the surface of the dielectric layer. Since the tunneling layer, charge trapping layer, and barrier layer materials are all insulators, the tunneling layer, charge trapping layer, and barrier layer materials on the surface of the dielectric layer can also be understood as part of the dielectric layer, used to replace the insulation between the metal layers of the sacrificial layer.

[0185] S509, a conductive material is deposited at the site of the removed sacrificial layer to form a conductive layer 430.

[0186] The conductive layer 430 can be formed using a standard 3D NAND replace gate process.

[0187] In other words, a conductive material is used to replace the removed sacrificial layer. The conductive layer 430 can be formed by chemical vapor deposition or atomic layer deposition. The conductive material can be a metal, such as nickel (Ni), titanium (Ti), cobalt (Co), or tungsten (W).

[0188] The structure after S509 is as follows Figure 17 As shown. Figure 18 yes Figure 17 A magnified view of the area within the dashed line region. Figure 19 yes Figure 18 The top view of the structure shown. Figure 18 yes Figure 19 The structure shown is a cross-sectional view along line AA'.

[0189] The sacrificial layer SAC0 is replaced with the selection line SGS, SAC1 is replaced with the word line WL0, SAC2 is replaced with the word line WL1, and SAC3 is replaced with the selection line SGD.

[0190] Figure 19 One possible pattern for a storage hole is shown. Figure 19 The storage holes shown are staggered, but this is not the only possible pattern. For example, the storage holes do not need to be staggered as shown. Figure 19 The diagram shows an alternating pattern.

[0191] Figure 19 The storage hole shown has a circular cross-section in the horizontal direction. The storage hole can also be other shapes, and this application does not limit this.

[0192] It should be understood that the size of the storage vias may differ in different layers. For example, the storage vias in layers closer to substrate 210 may be smaller.

[0193] After S509, the substrate can be removed to reduce the thickness of the 3D memory.

[0194] Figure 20This is a schematic structural diagram of a three-dimensional memory and control circuit provided in an embodiment of this application.

[0195] A three-dimensional memory can be formed on the substrate of the chip to form a three-dimensional memory chip 1901.

[0196] Circuits can be formed on the substrate of the chip to form circuit chip 1902.

[0197] The three-dimensional memory chip 1901 can be bonded to the circuit chip 1902.

[0198] For example, a face-to-face bonding process can be used to form a bonding interface between the upper surfaces of the 3D memory chip 1901 and the circuit chip 1902, so that the upper surfaces of the 3D memory chip 1901 and the circuit chip 1902 are electrically connected. The two wafers are stacked together, and signals are transmitted through the circuit chip 1902 to control the 3D memory chip 1901.

[0199] To improve the growth rate of the three-dimensional memory in the three-dimensional memory chip 1901, the substrate of the three-dimensional memory chip 1901 can be made of single-crystal silicon with a single-crystal lattice orientation of "001".

[0200] To improve the performance of the circuit chip 1902, the substrate of the circuit chip 1902 can be made of single-crystal silicon with a single-crystal lattice orientation of "110".

[0201] Of course, technologies such as wafer-level molding can also be used to achieve electrical connection between the 3D memory chip 1901 and the circuit chip 1902.

[0202] Figure 21 This is a schematic flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of this application.

[0203] In S601, a stacked structure is formed, the stacked structure comprising alternately stacked sacrificial layers and dielectric layers.

[0204] A multilayer structure can be formed on the substrate.

[0205] In S602, a channel structure is formed that extends through the stacked structure and through the sacrificial material in the sacrificial layer.

[0206] In S603, the sacrificial material in the sacrificial layer is removed.

[0207] The sacrificial layer includes a sacrificial material, which may be silicon nitride or the like. The sacrificial layer may or may not include other materials, and this application does not limit this.

[0208] In S604, a storage structure is formed at the location on the surface of the channel structure where the sacrificial material is removed.

[0209] In S605, a conductive material is deposited instead of the removed sacrificial material.

[0210] Optionally, the channel structure is made of a single-crystal semiconductor material.

[0211] Optionally, in S602, a storage hole may be formed that penetrates the stacked structure and passes through the sacrificial material.

[0212] A protective layer is formed on the sidewall of the storage hole.

[0213] The storage hole is filled with single-crystal semiconductor material to form the channel structure.

[0214] During the formation of the channel structure, elements (such as nitrogen) in the sacrificial material of the stacked structure may diffuse into the single-crystal semiconductor of the channel structure, affecting the performance of the 3D memory. By setting a protective layer on the surface of the channel structure, the diffusion of elements in the sacrificial layer of the stacked structure can be reduced or even eliminated.

[0215] Prior to S604, the protective layer at the location of the sacrificial material on the surface of the channel structure can be removed to expose the location of each sacrificial layer on the surface of the channel structure.

[0216] Therefore, the protective layer is divided into multiple protective structures, and each protective structure can correspond one-to-one with a dielectric layer in the laminated structure.

[0217] Before forming the memory structure, removing the protective layer located on the surface of the channel structure at the removed sacrificial layer can avoid the impact of process deviations in the etching process on the transistor's performance parameters.

[0218] Optionally, the semiconductor material filling the storage hole can be monocrystalline silicon, and the material of the protective layer can be amorphous silicon.

[0219] Amorphous silicon has a significantly lower hardness than crystalline silicon and is more chemically reactive. Therefore, monocrystalline silicon can be used as an etching stop layer to reduce the difficulty of the etching process.

[0220] Optionally, after S603, a groove is formed at each location of the removed sacrificial material on the surface of the channel structure.

[0221] By creating grooves at the location of the conductive layer on the surface of the channel structure (i.e., the location of the removed sacrificial material), the number of defects in the single-crystal silicon channel structure can be reduced, thereby reducing the impact of defects on the performance of the 3D memory.

[0222] Specifically, oxides can be formed at each location on the surface of the channel structure where sacrificial material can be removed. The oxides can then be removed to form the grooves.

[0223] In S604, a storage structure is formed in the groove on the surface of the channel structure.

[0224] Optionally, the material of the channel structure is single-crystal silicon with a single-crystal lattice direction of "001" along the direction away from the substrate.

[0225] Single-crystal silicon with a lattice orientation of "001" grows faster. By creating grooves at the locations of the conductive layer 430 on the surface of the channel structure 440, the number of defects can be reduced. Therefore, the height of the channel structure 440 can be increased while still meeting the mobility requirements. As the height of the channel structure 440 increases, the growth time required for single-crystal silicon remains constant. Using single-crystal silicon with a lattice orientation of "001" in the channel structure 440 allows for faster single-crystal silicon growth, shortening the fabrication time of three-dimensional memory and reducing manufacturing costs.

[0226] Optionally, at the location on the surface of the channel structure where the sacrificial layer is removed, a tunneling layer, a charge trapping layer, and a blocking layer stacked in the storage structure are sequentially formed.

[0227] This application provides an electronic device, including the three-dimensional memory mentioned above.

[0228] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, or the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0229] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0230] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A three-dimensional memory, characterized in that, include: Layered structure, channel structure, storage structure; The stacked structure includes alternating conductor layers and dielectric layers; The channel structure extends through the stacked structure; The conductor layer includes a conductive material; The storage structure is formed in the conductor layer on the surface of the channel structure and is located between the channel structure and the conductive material, wherein the surface of the channel structure includes a groove and the storage structure is located in the groove; The three-dimensional memory also includes a protective structure located on the surface of the channel structure and between the dielectric layer and the channel structure, wherein the memory structures in adjacent conductor layers are separated by the protective structure on the surface of the channel structure.

2. The three-dimensional memory according to claim 1, characterized in that, The channel structure includes a single-crystal semiconductor material.

3. The three-dimensional memory according to claim 1 or 2, characterized in that, The channel structure is made of monocrystalline silicon; the protective structure is made of amorphous silicon.

4. The three-dimensional memory according to claim 1 or 2, characterized in that, The material of the channel structure is single-crystal silicon with a single-crystal lattice direction of "001" along the direction of the channel structure penetrating the stacked structure.

5. The three-dimensional memory according to claim 1 or 2, characterized in that, The storage structure includes a tunneling layer, a charge trapping layer, and a blocking layer arranged sequentially in a direction away from the channel structure.

6. An electronic device, characterized in that, The three-dimensional memory includes any one of claims 1-5.

7. A method for fabricating a three-dimensional memory, characterized in that, include: A stacked structure is formed, the stacked structure comprising alternately stacked sacrificial layers and dielectric layers; A channel structure is formed, which penetrates the stacked structure and passes through the sacrificial material in the sacrificial layer; Remove the sacrificial material; A storage structure is formed at the location on the surface of the channel structure where the sacrificial material is removed; A conductive material is deposited to replace the removed sacrificial material; The formation of the channel structure includes: A storage hole is formed, which penetrates the stacked structure and passes through the sacrificial material; A protective layer is formed on the sidewall of the storage hole; Semiconductor material is grown in the memory hole where the protective layer is formed to form the channel structure; The method further includes removing the protective layer at the location of the sacrificial material on the surface of the channel structure.

8. The method according to claim 7, characterized in that, The channel structure includes a single-crystal semiconductor material.

9. The method according to claim 7 or 8, characterized in that, The protective layer for removing the sacrificial material from the surface of the channel structure includes: a protective layer for removing the sacrificial material from the surface of the channel structure using an etching process, wherein the semiconductor material grown in the memory hole is an etching stop layer.

10. The method according to claim 7 or 8, characterized in that, The semiconductor material grown in the storage hole is monocrystalline silicon; the material of the protective layer is amorphous silicon.

11. The method according to claim 7 or 8, characterized in that, The channel structure comprises a single-crystal semiconductor material. The method further includes: forming a groove on the surface of the channel structure at the location where the sacrificial material is removed; The formation of a storage structure at the location on the surface of the channel structure where the sacrificial material is removed includes: forming the storage structure in the groove.

12. The method according to claim 11, characterized in that, The method of forming a groove at the location where the sacrificial layer is removed on the surface of the channel structure includes: Oxides are formed at the locations on the surface of the channel structure where the sacrificial material is removed; The oxide is removed to form the groove.

13. The method according to claim 11, characterized in that, The material of the channel structure is single-crystal silicon with a "001" lattice direction along the direction away from the substrate.

14. The method according to claim 7 or 8, characterized in that, The storage structure is formed at the location on the surface of the channel structure where the sacrificial layer is removed, including: At the location on the surface of the channel structure where the sacrificial layer is removed, a tunneling layer, a charge trapping layer, and a blocking layer, which are stacked in the storage structure, are formed in sequence.

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