A millimeter wave radar general processing chip

Abstract

The application provides a millimeter wave radar general processing chip, which comprises an input interface module, a distance FFT module, a cache module, a speed FFT module, a CFAR detection module, a processor bus system, an embedded processor core and an output interface module; the input interface module receives millimeter wave radar AD sampling data and sends the data to the distance FFT module, and then the data are sent to the cache module for caching; when a complete radar frame data is received, the cache module sends the cached data to the speed FFT module for processing; the processing result is sent to the CFAR detection module for detection, and a detection target result is obtained; the embedded processor core controls and monitors each module through the processor bus system, and controls the output interface module to send the radar processing result out; and the millimeter wave radar general processing chip provided by the application can meet the application scene demand of high cost requirement, low power consumption requirement and high processing real-time requirement.

Description

Technical Field

[0001] This invention belongs to the field of radar signal processing technology, specifically relating to a general-purpose processing chip for millimeter-wave radar. Background Technology

[0002] Since 2015, international analog chip giants such as TI, NXP, and Maxim Integrated have successively launched integrated millimeter-wave radar chips with frequencies above 60GHz. These chips integrate millimeter-wave front-end components (including power amplifiers, frequency sources, low-noise amplifiers, and receiver mixers), AD sampling, radar signal processing, and system control, enabling them to perform all the functions of a single millimeter-wave radar and ultimately directly output radar processing results such as point clouds and target information. Currently, these chips have been widely used in fields such as autonomous driving, smart homes, medical testing, and security monitoring.

[0003] As applications become more in-depth and extensive, the aforementioned highly integrated millimeter-wave radar chips have also revealed some problems, mainly the following two:

[0004] a. High cost, accounting for a large proportion of the cost of the final product.

[0005] Because highly integrated millimeter-wave radar chips offer extremely powerful functionality, an entire end product is often built around this chip. This results in millimeter-wave radar chips accounting for a very high percentage of the cost of end products. As competition intensifies, end product manufacturers will eventually face a vicious cycle of zero or extremely low profit margins.

[0006] b. Inflexible use, greatly restricting product development.

[0007] Highly integrated millimeter-wave radar chips have largely fixed radar processing functions and methods, which can only be adjusted through configuration parameters. This limits product development using these chips, restricting flexibility and significantly limiting product possibilities. This is a major reason for the limited application of millimeter-wave radar chips at present.

[0008] Some manufacturers have recognized the two issues mentioned above and have therefore made appropriate cuts to their existing highly integrated millimeter-wave radar chips, removing the radar processing component while integrating the millimeter-wave radar antenna. This further integrates and optimizes the functionality of the millimeter-wave radar chip, increasing processing flexibility and reducing chip costs. This allows application vendors to flexibly develop custom radar processing algorithms based on their specific application needs. Simultaneously, due to the absence of a radar processing component, the cost of the new generation of millimeter-wave radar chips is significantly reduced, to approximately two-thirds of that of highly integrated millimeter-wave radar chips. The remaining one-third profit margin creates conditions for application vendors to leverage their capabilities and develop attractive application technologies. For example, Infineon's newly launched BGT60TR13C chip costs only around 160 yuan (compared to TI's highly integrated millimeter-wave chip IWR6843 with similar performance, which costs over 230 yuan). Paired with an M7 microcontroller costing around 40 yuan, a series of products comparable to the IWR6843 can be developed, offering greater flexibility and significantly lower costs.

[0009] To use next-generation unprocessed millimeter-wave radar chips, a processing chip must be used in conjunction with them. Generally speaking, the following types of processing chips can be considered: microcontrollers, PC systems, DSPs, embedded GPUs, FPGAs, etc.

[0010] PC systems are bulky and consume a lot of power, making them unsuitable for mainstream millimeter-wave radar applications such as automotive, smart homes, and security monitoring. However, medical monitoring is one possible application area.

[0011] DSPs, embedded GPUs, and FPGAs offer high computing power and flexibility, making them suitable for applications in automotive, smart homes, security monitoring, and medical surveillance. However, their higher cost and relatively higher power consumption make them unsuitable for low-cost products and devices requiring ultra-low power consumption.

[0012] Microcontrollers have extremely low power consumption and very low cost, making them an ideal processor to pair with next-generation millimeter-wave radar chips. However, microcontrollers are not designed for radar processing. The processing algorithms required for radar processing cannot be implemented through hardware acceleration, resulting in slow processing time, poor computational efficiency, and unsuitability for applications with high real-time requirements.

[0013] Therefore, it is evident that the three types of processors mentioned above cannot meet the requirements of an application scenario that demands high cost, low power consumption, and high real-time processing. Similar scenarios are quite common in practical applications, such as fall detection for the elderly. Millimeter-wave radar used for fall detection needs to operate silently and around the clock, requiring extremely low power consumption. Furthermore, the widespread application of this type of radar necessitates extremely tight cost control. Since a fall is an instantaneous event, and the time from the fall to triggering an alarm should be as fast as possible, this places extremely high demands on the system's real-time processing performance. In such application scenarios, the three types of processors mentioned above are practically inadequate. Summary of the Invention

[0014] The purpose of this invention is to provide a novel general-purpose millimeter-wave radar processing chip that can meet the application scenarios with high cost requirements, low power consumption requirements, and high real-time processing requirements.

[0015] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0016] This invention provides a general-purpose millimeter-wave radar processing chip, including an input interface module, a range FFT module, a cache module, a velocity FFT module, a CFAR detection module, a processor bus system, an embedded processor core, and an output interface module;

[0017] The processor bus system is bidirectionally connected to the input interface module, distance FFT module, cache module, speed FFT module, CFAR detection module, embedded processor core, and output interface module; the input interface module, distance FFT module, cache module, speed FFT module, and CFAR detection module are sequentially unidirectionally connected.

[0018] The input interface module is used to receive external millimeter-wave radar AD sampling data and send it to the range FFT module;

[0019] The caching module is used to cache radar sampling point data processed by the range FFT module. When a complete radar frame data is received, the caching module sends the cached data to the velocity FFT module for processing.

[0020] The CFAR detection module is used to perform CFAR detection on the radar sampling point data processed by the velocity FFT module to obtain the target detection result.

[0021] The output interface module is used to output the detection results of the target to the outside world;

[0022] The embedded processor core controls and monitors the input interface module, distance FFT module, cache module, speed FFT module, and CFAR detection module through the processor bus system, and simultaneously controls the output interface module to send radar processing results to the outside world through the processor bus system.

[0023] The input interface module is used to receive RAW data sampled by millimeter-wave radar AD and convert it into internal parallel port data. The input interface module can be adapted to, but is not limited to, SPI, I2C, and CAN buses. The output interface module is used to convert the internal parallel port data into SPI interface output.

[0024] The embedded processor core and processor bus system may be, but are not limited to, ARM series processors, MIPS instruction set processors, RISC-V or OpenRisc processing cores.

[0025] The buffer module includes a one-to-N selector MUX0, N FIFOs with a depth of 2×M, and an N-to-one selector MUX1, where N is the number of pulses in a radar frame and M is the number of sampling points in a radar pulse.

[0026] The input of MUX0 is connected to the output of the distance FFT module, the output of MUX0 is connected to the input of N FIFOs, the output of N FIFOs is connected to the input of MUX1, and the output of MUX1 is connected to the input of the speed FFT module.

[0027] The radar sampling points processed by the range FFT module are input into MUX0. During gating, the gating path of MUX0 is switched once for each radar pulse; the first radar pulse selects path 1, and the radar sampling point is input into FIFO 0; the second radar pulse selects path 2, and the radar sampling point is input into FIFO 1; and so on, until the (N+1)th radar pulse selects path 1 again, and the radar sampling point is input into FIFO 0. The above loop is repeated to ensure that each FIFO buffers a complete radar sampling pulse.

[0028] For FIFO output, MUX1 performs gating as follows: the first radar sampling point selects path 1, outputting the radar sampling point buffered in FIFO 0; the second radar sampling point selects path 2, outputting the radar sampling point buffered in FIFO 1; and so on, until the (N+1)th radar sampling point selects path 1 again, outputting the radar sampling point buffered in FIFO 0. This loop is repeated to ensure that the radar sampling points are sequentially output to the velocity FFT module for processing.

[0029] The CFAR detection module includes a register group, an averaging module, and a comparison module. The velocity FFT module inputs the processed radar sampling points into the register group. After shifting and storing, the register group outputs a reference point to the averaging module and simultaneously outputs the detected point to the comparison module for comparison. The averaging module averages the input reference points to obtain the CFAR threshold and inputs it into the comparison module. The comparison module compares the detected point, the fixed threshold, and the CFAR threshold to determine whether the detected point is a target marker. If it is, it is reported; otherwise, it is not reported.

[0030] The register group includes N columns and R rows of radar sampling point registers connected in series. The register group is divided into N-column region and S-column region vertically. The S-column R-row region is the CFAR detection window. N is the number of radar pulses in one frame, R is the number of rows in the detection window, and S is the number of columns in the detection window.

[0031] For each radar sampling point input into the register group, the center point of the CFAR detection window is used as the detected point and output to the comparison module; the remaining points of the CFAR detection window are used as reference points and output to the averaging module.

[0032] The averaging module includes an adder, a latch, and a shifter. Reference points are input into the averaging module circuit, and the adder accumulates the reference points within the CFAR detection window. When all reference points within the CFAR detection window have been accumulated, the latch LA is opened, and the accumulated value is sent to the shifter for right shifting. Right shifting means dividing the accumulated value by 2^shift value to obtain the average value of the reference values ​​within the CFAR detection window. This average value is the CFAR threshold.

[0033] The comparison module includes two greater than circuits and one AND circuit. One greater than circuit compares the detected point with the CFAR threshold. When the detected point > the CFAR threshold, it outputs a logic 1; otherwise, it outputs a logic 0. The other greater than circuit compares the detected point with a fixed threshold. When the detected point > the fixed threshold, it outputs a logic 1; otherwise, it outputs a logic 0. The outputs of the two greater than circuits are fed into the AND circuit. After logical operation, a target marker is output. That is, when the detected point > the CFAR threshold and the detected point > the fixed threshold, the comparison module outputs a target marker of 1; otherwise, it outputs a target marker of 0.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0035] Current general-purpose processors cannot meet the demands of specialized applications requiring low cost, low power consumption, and high real-time processing performance. Therefore, this invention proposes a general-purpose processing chip for millimeter-wave radar using Application-Specific Integrated Circuit (ASIC) technology. This processing chip, when paired with a new generation of processorless millimeter-wave radar chips, can meet the needs of applications with high cost requirements, low power consumption requirements, and high real-time processing requirements.

[0036] Microcontrollers, PC systems, DSPs, embedded GPUs, FPGAs, and other computing systems are all general-purpose computer systems, not systems customized for implementing radar processing algorithms. Therefore, to run these computing systems, a large amount of resources unrelated to radar processing algorithms must be provided, with most of the power consumption and computing time consumed in non-radar processing.

[0037] This invention employs ASIC technology to custom-design integrated circuits (chips) based on radar processing algorithms. Each circuit component in this chip serves the radar processing algorithm, enabling the algorithm to be implemented using a minimal number of logic gates, thereby saving resources and reducing power consumption. Furthermore, because the radar processing algorithm circuitry is fully customized, there are no redundant bus data transmission processes during implementation. Once one module completes its calculation, the result can be directly transmitted to the next module via the circuit, significantly reducing the intermediate switching waiting time. This reduces computational latency and greatly improves real-time performance. Therefore, this invention can meet the needs of application scenarios with high cost requirements, low power consumption requirements, and high real-time processing requirements. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the module of the millimeter-wave radar universal processing chip of the present invention;

[0039] Figure 2 This is a structural block diagram of the cache module in this invention;

[0040] Figure 3 This is a structural block diagram of the CFAR detection module in this invention;

[0041] Figure 4 This is a structural diagram of the register group in this invention;

[0042] Figure 5 This is a block diagram illustrating the principle of the averaging module in this invention.

[0043] Figure 6 This is a block diagram illustrating the principle of the comparison module in this invention. Detailed Implementation

[0044] The present invention will be further described below with reference to the accompanying drawings. The following examples are only used to describe the present invention and are not intended to limit the scope of use of the present invention. All equivalent modifications of the present invention by those skilled in the art are included within the scope of the claims of the present invention.

[0045] like Figure 1 As shown, this invention provides a novel general-purpose chip (Radar Signal Processing, or RSP) specifically designed for millimeter-wave radar signal processing, which includes:

[0046] 1. Input Interface Module

[0047] 2. Distance FFT module

[0048] 3. Caching module

[0049] 4. Speed ​​FFT Module

[0050] 5. CFAR detection module

[0051] 6. Processor Bus System (AHB)

[0052] 7. Embedded processor core (ARM-M0)

[0053] 8. Output Interface Module

[0054] The processor bus system (AHB) is bidirectionally connected to the input interface module, range FFT module, cache module, speed FFT module, CFAR detection module, embedded processor core, and output interface module; the input interface module, range FFT module, cache module, speed FFT module, and CFAR detection module are sequentially unidirectionally connected. The input interface module is used to receive external millimeter-wave radar AD sampling data, and the output interface module is used to output radar processing results.

[0055] After sampling by the millimeter-wave radar, the data is transmitted to the RSP chip via the SPI interface. The input interface module inside the RSP chip receives the sampled data and sends it to the range FFT module, then buffers it in the buffer module. Once a complete radar frame is received, the buffer module sends the buffered data to the velocity FFT module for processing. The processed result is then sent to the CFAR detection module for CFAR detection to obtain the final target detection result. All of the above modules can upload the result data to the embedded processor core via the processor bus system (AHB bus) for further display. The embedded processor core can also control and monitor the above modules via the AHB bus, and simultaneously control the output interface module to send out the RSP output results.

[0056] The following is a detailed introduction to each module:

[0057] 1. Input interface module, output interface module, processor bus system, embedded processor core

[0058] The input interface module is primarily used to receive RAW data sampled by the millimeter-wave radar's AD converter and convert the SPI interface data transmitted by the millimeter-wave radar chip into internal parallel port data. The output interface module primarily converts parallel port data into SPI interface output. Both the input and output interface modules can be adapted to, but are not limited to, SPI, I2C, CAN, and other buses. The SPI interface is a mature interface in the industry, and the technology for converting the SPI interface to a parallel interface is well-known to professionals in this field and will not be elaborated upon here.

[0059] The RAW data sampled by the millimeter-wave radar AD can be obtained through, but is not limited to, the following methods:

[0060] A. Millimeter-wave radar chips. For example, TI's IWR6843 and Infineon's BGT60TR13C.

[0061] B. Millimeter-wave radar systems assembled from discrete components.

[0062] The embedded processor core (one or more general-purpose reduced instruction set processor cores) and processor bus system can be, but are not limited to, ARM series processors, MIPS instruction set processors, RISC-V, OpenRisc, and other processing cores. This technology is well-known to those skilled in the art, and numerous published patents are available for searching; therefore, it is not the core content of this patent and will not be elaborated upon here.

[0063] 2. Distance FFT module

[0064] The distance-based FFT module is a circuit module that implements FFT operations using circuit elements. Under the control of an embedded processor core, it can quickly complete FFT calculations in hardware. This technology is a well-known and mature technology in the industry and is not the focus of this invention.

[0065] 3. Caching module

[0066] The buffer module consists of N FIFOs with a depth of 2×M, where N is the number of pulses in a radar frame and M is the number of sampling points in a radar pulse.

[0067] The specific design of the cache module is as follows: Figure 2As shown, the radar sampling points processed by the range FFT module are input into MUX0. MUX0 is a 1-to-N selector. During selection, the selection path of MUX0 is switched once for each radar pulse. That is: for the first radar pulse, path 1 is selected, and the radar sampling point is input into FIFO 0; for the second radar pulse, path 2 is selected, and the radar sampling point is input into FIFO 1; and so on, until the (N+1)th radar pulse, at which point the selector returns to path 1, and the radar sampling point is input into FIFO 0, and then the above cycle is repeated. This ensures that each FIFO buffers a complete radar sampling pulse.

[0068] On the other hand, the FIFO output is also connected to an N-to-1 MUX1 selector. Unlike the MUX0 selector, the MUX1 selector works as follows: for the first radar sampling point, path 1 is selected, and the radar sampling point buffered in FIFO 0 is output; for the second radar sampling point, path 2 is selected, and the radar sampling point buffered in FIFO 1 is output; and so on, until the (N+1)th radar sampling point, at which point the selector returns to path 1, outputting the radar sampling point buffered in FIFO 0, and then the above loop is repeated. The result of this control is that the radar sampling points are output sequentially to subsequent modules for processing in a "vertical" manner.

[0069] 4. Speed ​​FFT module

[0070] The speed FFT module (designed identically to the distance FFT module) is a circuit module that implements FFT operations using circuit elements. This technology is a well-known and mature technology in the industry and is not the focus of this invention.

[0071] 5. CFAR detection module

[0072] The CFAR detection module, also known as the constant false alarm rate (CFAR) detection module, employs the CFAR algorithm from radar processing to achieve target detection. Specifically designed for CFAR detection, this module can rapidly implement CFAR detection in hardware under the control of an embedded processor core. The detailed circuit implementation of the CFAR detection module is shown below. Figure 3 As shown, the circuit consists of three main modules: a register group, an averaging module, and a comparison module. The velocity FFT module inputs the processed radar sampling points into the register group. After shifting and registering, the register group outputs a reference point to the averaging module; simultaneously, it outputs the monitored point to the comparison module for comparison. The averaging module averages the input reference points to obtain the CFAR threshold, which is then input into the comparison module. The comparison module compares the monitored point, the fixed threshold, and the CFAR threshold to ultimately determine whether the monitored point is a target. If it is, a target detection is reported; otherwise, no report is made.

[0073] The fixed threshold can be obtained through the following method: First, based on the scenario requirements, the approximate range of the fixed threshold is calculated through design. Then, through physical testing, the specific value of the fixed threshold is continuously adjusted to observe the detection probability of the radar. Finally, the fixed threshold value is obtained and stored in the chip.

[0074] The three main modules are described in detail below.

[0075] 1) Register set

[0076] The specific design of the register group circuit is as follows: Figure 4 As shown in the diagram, "D" represents a radar sampling point register. The specific number of bits depends on the radar sampling point width, typically ranging from 12 to 32 bits. N represents the number of radar pulses in one frame. R and S represent the CFAR detection window size, with R indicating the number of rows and S indicating the number of columns.

[0077] The register set consists of N columns and R rows, divided vertically into NS column regions and S column regions. Figure 4 The area enclosed by the solid line frame (the part in the middle). The S-column and R-row area enclosed by the solid line frame is also called the CFAR detection window.

[0078] For each radar sampling point input into the register group, the center point of the CFAR detection window is used as the detected point and output to the comparison module. The remaining points in the CFAR detection window are used as reference points and output to the averaging module.

[0079] 2) Average module

[0080] The specific circuit of the average module is as follows: Figure 5 As shown in the figure, "+" represents an adder, "LA" represents a latch, and ">>" represents a shifter.

[0081] The reference points are input to the averaging module circuit, where an adder accumulates the reference points within the CFAR detection window. Once all reference points within the CFAR detection window have been accumulated, the latch LA opens, sending the accumulated value to a shifter for right shifting. Right shifting represents dividing the accumulated value by 2^the shift value. Therefore, by appropriately designing the values ​​of R and S, the CFAR detection window can approximate a power of 2. The average value of the reference values ​​within the CFAR detection window can then be quickly calculated using the above method. This average value is the CFAR threshold.

[0082] 3) Comparison Module

[0083] The specific circuit of the comparison module is as follows: Figure 6 As shown in the figure, the symbol ">" represents a greater than circuit, which outputs logic 1 when the input a>b, otherwise it outputs logic 0; the symbol "&" represents a logic AND circuit.

[0084] The comparison module indicates that when the detected point is greater than the CFAR threshold and the detected point is greater than the fixed threshold, the comparison module outputs a target marker of 1; otherwise, it outputs a target marker of 0.

[0085] In summary, the millimeter-wave radar general-purpose processing chip provided by this invention is a chip technology implemented using application-specific integrated circuit (ASIC) technology for processing RAW data sampled by millimeter-wave radar AD. The RSP chip of this invention has the following characteristics:

[0086] 1) The RSP chip has one or more general-purpose reduced instruction processing cores. This core can be, but is not limited to, ARM, RISC-V, OpenRisc, etc.

[0087] 2) The RSP chip has an internal input interface module for receiving RAW data sampled by millimeter-wave radar AD. The interface can be adapted to, but is not limited to, SPI, I2C, CAN, and other buses.

[0088] 3) The RSP chip has dedicated hardware circuitry for implementing FFT, which can quickly complete FFT calculations in hardware under the control of the processing kernel.

[0089] 4) The RSP chip has a dedicated hardware circuit for implementing constant false alarm rate (CFAR) detection, which can be quickly implemented in hardware under the control of the processing kernel.

[0090] 5) RSP chips are implemented using ASIC technology and can be manufactured using, but are not limited to, modern CMOS manufacturing processes.

[0091] This invention uses Application-Specific Integrated Circuit (ASIC) development technology to propose a general-purpose processing chip for millimeter-wave radar. This processing chip, when paired with a new generation of unprocessed millimeter-wave radar chips, can meet the application scenarios with high cost requirements, low power consumption requirements, and high real-time processing requirements.

[0092] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation on the present invention. Any simple modifications, alterations, or equivalent structural transformations made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A general-purpose processing chip for millimeter-wave radar, characterized in that: It includes an input interface module, a distance FFT module, a cache module, a speed FFT module, a CFAR detection module, a processor bus system, an embedded processor core, and an output interface module; The processor bus system is bidirectionally connected to the input interface module, distance FFT module, cache module, speed FFT module, CFAR detection module, embedded processor core, and output interface module; the input interface module, distance FFT module, cache module, speed FFT module, and CFAR detection module are sequentially unidirectionally connected. The input interface module is used to receive external millimeter-wave radar AD sampling data and send it to the range FFT module; The caching module is used to cache radar sampling point data processed by the range FFT module. When a complete radar frame data is received, the caching module sends the cached data to the velocity FFT module for processing. The CFAR detection module is used to perform CFAR detection on the radar sampling point data processed by the velocity FFT module to obtain the target detection result. The output interface module is used to output the detection results of the target to the outside world; The embedded processor core controls and monitors the input interface module, distance FFT module, cache module, speed FFT module, and CFAR detection module through the processor bus system, and at the same time controls the output interface module to send radar processing results to the outside world through the processor bus system. The buffer module includes a one-to-N selector MUX0, N FIFOs with a depth of 2×M, and an N-to-one selector MUX1, where N is the number of pulses in a radar frame and M is the number of sampling points in a radar pulse. The input of MUX0 is connected to the output of the distance FFT module, the output of MUX0 is connected to the input of N FIFOs, the output of N FIFOs is connected to the input of MUX1, and the output of MUX1 is connected to the input of the speed FFT module. The radar sampling points processed by the range FFT module are input into MUX0. During gating, the gating path of MUX0 is switched once for each radar pulse; the first radar pulse selects path 1, and the radar sampling point is input into FIFO 0; the second radar pulse selects path 2, and the radar sampling point is input into FIFO 1; and so on, until the (N+1)th radar pulse selects path 1 again, and the radar sampling point is input into FIFO 0. The above loop is repeated to ensure that each FIFO buffers a complete radar sampling pulse. For FIFO output, MUX1 performs gating as follows: the first radar sampling point selects path 1 and outputs the radar sampling point cached in FIFO0; the second radar sampling point selects path 2 and outputs the radar sampling point cached in FIFO1; and so on, until the N+1th radar sampling point selects path 1 again and outputs the radar sampling point cached in FIFO0. The above loop is repeated to ensure that the radar sampling points are output sequentially to the velocity FFT module for processing.

2. The millimeter-wave radar general-purpose processing chip according to claim 1, characterized in that: The input interface module is used to receive RAW data sampled by millimeter-wave radar AD and convert it into internal parallel port data. The input interface module can be adapted to, but is not limited to, SPI, I2C, and CAN buses. The output interface module is used to convert the internal parallel port data into SPI interface output.

3. The millimeter-wave radar general-purpose processing chip according to claim 1, characterized in that: The embedded processor core and processor bus system are ARM series processors, MIPS instruction set processors, RISC-V or OpenRisc processing cores.

4. The millimeter-wave radar general-purpose processing chip according to claim 1, characterized in that: The CFAR detection module includes a register group, an averaging module, and a comparison module. The velocity FFT module inputs the processed radar sampling points into the register group. After shifting and storing, the register group outputs a reference point to the averaging module and simultaneously outputs the detected point to the comparison module for comparison. The averaging module averages the input reference points to obtain the CFAR threshold and inputs it into the comparison module. The comparison module compares three values: the detected point, the fixed threshold, and the CFAR threshold to determine whether the detected point is a target marker. If it is, it is reported; otherwise, it is not reported.

5. The millimeter-wave radar general-purpose processing chip according to claim 4, characterized in that: The register group includes N columns and R rows of radar sampling point registers connected in series. The register group is divided into N-column region and S-column region vertically. The S-column R-row region is the CFAR detection window. N is the number of radar pulses in one frame, R is the number of rows in the detection window, and S is the number of columns in the detection window. For each radar sampling point input into the register group, the center point of the CFAR detection window is used as the detected point and output to the comparison module; the remaining points of the CFAR detection window are used as reference points and output to the averaging module.

6. The millimeter-wave radar general-purpose processing chip according to claim 5, characterized in that: The averaging module includes an adder, a latch, and a shifter. Reference points are input into the averaging module circuit, and the adder accumulates the reference points within the CFAR detection window. When all reference points within the CFAR detection window have been accumulated, the latch LA is opened, and the accumulated value is sent to the shifter for right shifting. Right shifting means dividing the accumulated value by 2^shift value to obtain the average value of the reference values ​​within the CFAR detection window. This average value is the CFAR threshold.

7. The millimeter-wave radar general-purpose processing chip according to any one of claims 4-6, characterized in that: The comparison module includes two greater than circuits and one AND circuit. One greater than circuit compares the detected point with the CFAR threshold. When the detected point > the CFAR threshold, it outputs logic 1; otherwise, it outputs logic 0. The other greater than circuit compares the detected point with a fixed threshold. When the detected point > the fixed threshold, it outputs logic 1; otherwise, it outputs logic 0. The outputs of the two greater than circuits are fed into the AND circuit. After logical operation, a target marker is output. That is, when the detected point > the CFAR threshold and the detected point > the fixed threshold, the comparison module outputs a target marker of 1. Otherwise, the output target is marked as 0.

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