An artificial intelligence-based FPGA chip radar signal processing device

Abstract

The application relates to the fields of pulse radar, FPGA and unmanned aerial vehicles, in particular to an FPGA chip radar signal processing device based on artificial intelligence, which comprises hardware devices for supporting real-time processing information installed on an unmanned aerial vehicle and low-power devices, the hardware devices for supporting real-time processing information installed on the unmanned aerial vehicle execute corresponding instructions by adopting an FPGA+ARM heterogeneous architecture without changing original unmanned aerial vehicle control data transmission and a control link; the low-power devices are used for optimizing logic and prolonging unmanned aerial vehicle cruising time; in the application, a core computing unit FPGA device can directly perform program burning, only needs to send a configuration instruction to the FPGA through an upper computer when the FPGA is in an idle state, and the FPGA turns into an updating state after receiving the instruction, receives new model data transmitted by the upper computer, reconstructs an internal algorithm model, and can also dynamically modify model classification numbers through parameter configuration.

Description

Technical Field

[0001] This invention relates to the fields of pulse radar, FPGA and drones, specifically to an artificial intelligence-based FPGA chip radar signal processing device. Background Technology

[0002] Radar signal processing is an extremely important component of radar systems. The development of modern radar technology increasingly relies on signal processing. Radar signal processing not only greatly improves the radar's ability to detect targets in complex backgrounds, but also provides more information. Therefore, radar signal processing is one of the most active and rapidly progressing parts of current radar technology research. Pulse radar is a type of precision tracking radar. Each time it transmits a pulse, the antenna can simultaneously form several beams. By comparing the amplitude and phase of the echo signals from each beam, when the target is on the antenna axis, the amplitude and phase of the echo signals from each beam are equal, and the signal difference is zero. When the target is not on the antenna axis, the amplitude and phase of the echo signals from each beam are unequal, generating a signal difference, which drives the antenna to turn towards the target until the antenna axis is aligned with the target. In this way, the elevation and azimuth angles of the target can be measured. The sum of the signals received from each beam can be used to measure the distance to the target, thereby realizing the measurement and tracking of the target. The pulse measurement radar obtains the target's distance information by measuring the round-trip time delay of the pulse electromagnetic wave, measures the target's radial velocity based on the Doppler frequency in the received pulse carrier, and obtains the target's azimuth and elevation angle data using the equal signal method.

[0003] Pulse measurement radar has three operating modes: ① Reflection mode: The radar receives the reflected signal from the target. This mode is often used for tracking short-range targets, obtaining information about rocket propulsion stages and the characteristics of reentry targets. ② Responder mode: The radar receives signals relayed by the transponder on the aircraft. This mode has strong signal transmission, long radar range, and strong anti-jamming capability, and is used for measuring long-range targets. Responder mode can be further divided into coherent and non-coherent response modes. When using coherent response mode, the transmit and receive frequencies of the transponder maintain a strict multiple relationship. ③ Beacon mode: The radar only receives signals transmitted by the beacon on the aircraft and cannot measure distance; it is only used to acquire targets. To expand the measurement range of the flight area, multiple radars are often deployed in a longitudinal column along the flight area to achieve relay tracking and measurement of targets, called a radar chain. This means that before the current radar can no longer track or "cannot see" the target, the next radar has already acquired it. All radars work synchronously, providing real-time intercept data. Pulse measurement radar is a radio device used for tracking and precise measurement of aircraft. It provides measurement information for spacecraft orbit determination and target characteristic measurement. Commonly used pulse measurement radars include conical scanning radar and monopulse radar. It is a type of tracking radar. The antenna simultaneously transmits several beams and then receives their sum and difference signals. The sum signal determines the distance information, the difference signal determines the angle information, and the phase difference between the difference signal and the sum signal determines the direction of the angular error, thereby driving the antenna to track the target.

[0004] Traditional radar signal processing systems are characterized by large equipment quantities, complex structures, low reliability, and high costs. However, with the continuous development of integrated circuits, the shrinking of device sizes, the increasing integration density, and the rapid advancements in various process technologies, it has become possible to integrate the entire radar signal processing system onto a single circuit board.

[0005] Pulse measurement radar is widely used in radio equipment for tracking and precision measurement of aircraft. It provides measurement information for spacecraft orbit determination and target characteristic measurement, and has the advantages of low cost. However, the information obtained by radar is also limited and cannot obtain deeper information. Therefore, under the condition of operating with limited payload, UAVs need to design a hardware device that can support UAVs to process information in real time. Summary of the Invention

[0006] The purpose of this invention is to provide an FPGA chip-based radar signal processing device based on artificial intelligence to solve the problems mentioned in the background art.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0008] An FPGA chip radar signal processing device based on artificial intelligence, characterized in that the processing device includes hardware devices that support real-time information processing installed on a drone and low-power devices;

[0009] The hardware device that supports real-time information processing on the drone adopts an FPGA+ARM heterogeneous architecture to execute corresponding instructions without changing the original drone control data transmission and control link.

[0010] The low-power device determines the specific FPGA model based on the algorithm and frame rate requirements to be ported, and optimizes the logic to reduce power consumption and extend the drone's cruise time.

[0011] Furthermore, the method for executing corresponding instructions without altering the original UAV control data transmission and control link includes the following steps:

[0012] S1.11. Set the parameters of the core computing unit according to the power consumption and weight / volume parameters of the UAV; wherein, in this invention, the core computing unit uses an FPGA chip of model JFM7VX690T20;

[0013] S1.21. Process the data according to the internal algorithm of the core computing unit, and use the processed data as the input of the RJ45 interface;

[0014] S1.31. Perform data preprocessing and FPGA hyperparameter calculation based on the input data. The data preprocessing and FPGA hyperparameter calculation are performed by ARM. In this invention, an AMR core processing chip with a model of 4Core ARM Cortex-A53 is used.

[0015] S1.41. Initialize the instruction set according to the Command driver and input the parameters and input data into the DataBuffer;

[0016] S1.51. Decision-making commands are transmitted via RS232 serial port to achieve the goal of not changing the original UAV control data transmission and control link.

[0017] This invention addresses the limitations of UAV takeoff weight and pod space, as well as constraints on power consumption, weight, and volume. The core computing chip of this invention employs an FPGA+ARM heterogeneous architecture, whose size meets the UAV pod requirements, and whose low power consumption satisfies the UAV's operational needs. The complete device workflow is as follows: the core computing unit uses an FPGA device; data processed by the FPGA is input via an RJ45 interface; data preprocessing and FPGA hyperparameter calculation are performed by the ARM; the instruction set is initialized by the Command driver; and finally, parameters and input data are input into the DataBuffer. Without altering the original UAV control data transmission and control link, decision-making commands are executed via RS232 serial port transmission.

[0018] Furthermore, the method for data processing by the internal algorithm of the core computing unit includes the following steps:

[0019] S2.1. Obtain input data and cache the data using a FIFO. While caching, call the zero-padding module to process the data.

[0020] S2.2 Obtain the number of channels in the input feature map of this layer and perform zero-padding operation;

[0021] S2.3 Obtain the zero-padding data through calculation and output the feature data through FIFO;

[0022] S2.4 Read weight data through FPGA Conv 1*3;

[0023] S2.5. After assembling the feature data into a 1*3 window, perform convolution calculation together with the weight data and output the result.

[0024] The core computing unit of this invention is an FPGA, and the core logic part is an artificial intelligence algorithm. For different convolution kernels in the algorithm, a module reuse design is adopted. The 1*3 window is zero-padded and convolved into 3*3 (0 is padded to the empty positions of the window). The rest of the process is the same, including input zero-padded, feature map window assembly, weight caching and weighted convolution calculation. The input data first needs to be cached in FIFO and the zero-padded module is notified to start. Zero-padded operation is performed according to the number of channels of the input feature map of the layer. After the operation is completed, the FIFO is controlled to output feature data. The feature data is assembled into a 1*3 window and then convolved with the weight data to obtain the output result.

[0025] Furthermore, the method for obtaining the number of channels of the input feature map of this layer and performing zero-padding includes the following steps:

[0026] S3.1 Analyze the input data and perform zero-padding;

[0027] S3.2. Obtain a window size of 1*3. According to the present invention, the convolution stride of the algorithm model is set to be uniformly 1. Add 0 padding values ​​to the 1*3 window to ensure that all data can be traversed.

[0028] S3.3, According to the formula The output data dimension values ​​are obtained, where W represents the dimension of the input data, P represents the padding value, and S is the step size.

[0029] S3.4 Calculate the matrix inner product of the input data and the weight data, and add the calculation result to the corresponding bias value one by one to obtain the corresponding row and column values ​​in the 3*3 output matrix.

[0030] This invention acquires input data and then pads it with zeros. The acquisition window is 1*3, the convolution stride is 1, and zero padding values ​​are added to the 1*3 window. The data dimension value is obtained through a formula. After the data is input, it is directly multiplied and accumulated with the weight data, and the result is output.

[0031] Furthermore, the method for optimizing the logic includes the following steps:

[0032] S1.12. Obtain input data, read weight data, and directly multiply and accumulate the input data with the weight data.

[0033] S1.22. Perform 8-bit quantization on the FPGA calculation results and convert fixed-point numbers to floating-point numbers using the Softmax operator;

[0034] S1.32. Quantize highly discrete data within the scope of big data;

[0035] S1.42. Merge the operators in the neural network algorithm and output the results.

[0036] Furthermore, the method for converting fixed-point numbers to floating-point numbers using the Softmax operator includes the following steps:

[0037] S5.11, The probability that a sample belongs to category i is: According to the formula We obtain the first C1 parameters, that is

[0038] S5.21. Add a C-1 dimensional column vector T(y), y = 1, 2, 3, ..., C-1. If a sample belongs to the i-th class, then the element in the i-th row is 1, and the rest are 0.

[0039] S5.31. According to class y∈1, that is, when y≠K, only one element in T(y) is 1 and the rest are 0. Then the expected value of y is:

[0040] S5.41, According to the formula get

[0041] S5.51, according to Substitute into the formula From

[0042] S5.61. Replace i with C in the denominator to obtain... Right now

[0043] S5.71. Convert the data obtained from FPGA processing to fixed-point numbers using the Softmax operator.

[0044] This invention calculates the convolution result using an FPGA to obtain 8-bit quantized data. The fixed-point data obtained from the FPGA calculation is then converted to floating-point numbers using the Softmax operator. The calculation process uses floating-point numbers, and the corresponding output is also a floating-point number.

[0045] Furthermore, the 8-bit quantization method includes the following steps:

[0046] S5.12. When acquiring feature maps, the training focus should be on scale parameters and offset parameters.

[0047] S5.22, According to the formula Treating the skewed activation distribution, where It is a quantified value. These are the inverse quantized values, (x, n, p) is the scale, z represents the offset parameter, and s represents the scale;

[0048] S5.32, According to the formula Update the gradient of parameter s;

[0049] S5.42, According to the formula Update the gradient of parameter z;

[0050] S5.52. By employing symmetric signed quantization, layer weights can be observed to have a zero-based symmetric distribution, thus achieving weight quantization. Therefore, compared to dual-stack quantization, activated asymmetric quantization incurs additional costs during inference because the additional offset terms can be pre-calculated and incorporated into the bias at compile time, according to the formula... Four possible parameters for the relative quantization scheme are obtained. Without applying offset parameters, it follows the learnable symmetric quantization separation proposed in LSQ. Since it uses the unsigned range of the stacked quantization scheme, it completely corresponds to the parameterization proposed in LSQ for activation quantization. This represents the inverse quantization value of the weight. This represents the weight quantization value.

[0051] S5.62: Quantizes large datasets with highly discrete distributions based on an 8-bit quantization scheme.

[0052] The focus of this invention is to quantize highly discrete data within a large dataset based on the above core quantization principles, while also meeting hardware deployment requirements. The algorithm is ported and deployed on hardware devices. The specific quantization process is handled by the Soffmax operator and quantization formula. The output of the convolution part is a 24-bit fixed-point number. The Soffmax operator can quantize the 24-bit fixed-point number to 8 bits. Furthermore, the original algorithm's BN, ReLU, and Scale (operators in neural network algorithms) parts are merged to provide data references for subsequent results.

[0053] Furthermore, the method for quantizing large-scale, highly discrete data based on an 8-bit quantization scheme includes the following steps:

[0054] S7.1 Obtain the quantized data value from S5.62;

[0055] S7.2 Output a 24-bit fixed-point number through a convolution function, and quantize the 24-bit fixed-point number to 8 bits according to the Softmax operator;

[0056] S7.3 Merge the operators in the original neural network algorithm and output the result.

[0057] In this invention, the core computing unit FPGA device does not require disassembling the drone for program burning. Instead, when the FPGA is idle, a configuration command is sent from a host computer (PC) to the FPGA. Upon receiving the command, the FPGA enters an update state, receives new model data from the host computer, reconstructs its internal algorithm model, and can dynamically modify the number of model classifications through parameter configuration. Algorithm detection is not possible in the update state. After the update is complete, the FPGA transitions from the update state to an idle or working state, where it can receive new input monitoring data and use the new model for detection. The FPGA can be developed according to requirements, adapting to different algorithm model weights through external input parameters. In this invention, the FPGA starts the pre-trained detection model upon power-up, requiring no configuration and only needing to input detection data to output detection results. Attached Figure Description

[0058] Figure 1 This is a flowchart of the FPGA Conv 1*3 module of an FPGA chip radar signal processing device based on artificial intelligence according to the present invention;

[0059] Figure 2 This is a flowchart of the FPGA Conv 1*1 module of an FPGA chip radar signal processing device based on artificial intelligence according to the present invention;

[0060] Figure 3 This is a flowchart of the FPGA Quantization module of an FPGA chip radar signal processing device based on artificial intelligence according to the present invention;

[0061] Table 1 is a list of main components of an FPGA chip radar signal processing device based on artificial intelligence according to the present invention. Detailed Implementation

[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] Please see Figures 1-3 The present invention provides the following technical solution:

[0064] An FPGA chip radar signal processing device based on artificial intelligence, characterized in that the processing device includes hardware devices that support real-time information processing installed on a drone and low-power devices;

[0065] The hardware device that supports real-time information processing on the drone adopts an FPGA+ARM heterogeneous architecture to execute corresponding instructions without changing the original drone control data transmission and control link.

[0066] The low-power device determines the specific FPGA model based on the algorithm and frame rate requirements to be ported, and optimizes the logic to reduce power consumption and extend the drone's cruise time.

[0067] The method for executing corresponding instructions without altering the original UAV control data transmission and control link includes the following steps:

[0068] S1.11. Set the parameters of the core computing unit according to the power consumption and weight / volume parameters of the UAV; wherein, in this invention, the core computing unit uses an FPGA chip of model JFM7VX690T20;

[0069] S1.21. Process the data according to the internal algorithm of the core computing unit, and use the processed data as the input of the RJ45 interface;

[0070] S1.31. Perform data preprocessing and FPGA hyperparameter calculation based on the input data. The data preprocessing and FPGA hyperparameter calculation are performed by ARM. In this invention, an AMR core processing chip with a model of 4Core ARM Cortex-A53 is used.

[0071] S1.41. Initialize the instruction set according to the Command driver and input the parameters and input data into the DataBuffer;

[0072] S1.51. Transmit decision commands via RS232 serial port to achieve the goal of not changing the original UAV control data transmission and control link (as shown in Table 1, which is a list of main components).

[0073] The method for data processing by the internal algorithm of the core computing unit includes the following steps:

[0074] S2.1. Obtain input data and cache the data using a FIFO. While caching, call the zero-padding module to process the data.

[0075] S2.2 Obtain the number of channels in the input feature map of this layer and perform zero-padding operation;

[0076] S2.3 Obtain the zero-padding data through calculation and output the feature data through FIFO;

[0077] S2.4, Read weight data via FPGA Conv 1*3 (e.g.) Figure 1 The diagram shown is a flowchart of FPGA Conv 1*3.

[0078] S2.5. After assembling the feature data into a 1*3 window, perform convolution calculation together with the weight data and output the result.

[0079] The method for obtaining the number of channels in the input feature map of this layer and performing zero-padding includes the following steps:

[0080] S3.1 Analyze the input data and perform zero-padding;

[0081] S3.2. Obtain a window size of 1*3. According to the present invention, the convolution stride of the algorithm model is set to be uniformly 1. Add 0 padding values ​​to the 1*3 window to ensure that all data can be traversed.

[0082] S3.3, According to the formula The output data dimension values ​​are obtained, where W represents the dimension of the input data, P represents the padding value, and S is the step size.

[0083] S3.4 Calculate the inner product of the input data and weight data, and add the result to the corresponding bias value to obtain the corresponding row and column values ​​in the 3*3 output matrix (e.g., ...). Figure 2 The diagram shown is a flowchart of FPGA Conv 1*1.

[0084] The method for optimizing the logic includes the following steps:

[0085] S1.12. Obtain input data, read weight data, and directly multiply and accumulate the input data with the weight data.

[0086] S1.22. Perform 8-bit quantization on the FPGA calculation results and convert fixed-point numbers to floating-point numbers using the Softmax operator;

[0087] S1.32. Quantize highly discrete data within the scope of big data;

[0088] S1.42. Merge the operators in the neural network algorithm and output the results.

[0089] The method for converting fixed-point numbers to floating-point numbers using the Softmax operator includes the following steps:

[0090] S5.11, The probability that a sample belongs to category i is: According to the formula We obtain the first C-1 parameters, that is

[0091] S5.21. Add a C-1 dimensional column vector T(y), y = 1, 2, 3, ..., C-1. If a sample belongs to the i-th class, then the element in the i-th row is 1, and the rest are 0, i.e., (T(i)). i =1;

[0092] S5.31. According to class y∈1, that is, when y≠K, only one element in T(y) is 1 and the rest are 0. Then the expected value of y is:

[0093] S5.41, According to the formula get

[0094] S5.51, according to the Substitute into the formula From

[0095] S5.61. Replace i with C in the denominator to obtain Right now

[0096] S5.71. Convert the data obtained from FPGA processing to fixed-point numbers using the Softmax operator.

[0097] The 8-bit quantization method includes the following steps:

[0098] S5.12. When acquiring feature maps, the training process should focus on scale parameters and offset parameters.

[0099] S5.22, According to the formula Treating the skewed activation distribution, where It is a quantified value. These are the inverse quantized values, (x, n, p) is the scale, z represents the offset parameter, and s represents the scale;

[0100] S5.32, According to the formula Update the gradient of parameter s;

[0101] S5.42, According to the formula Update the gradient of parameter z;

[0102] S5.52. By employing symmetric signed quantization, layer weights can be observed to have a zero-based symmetric distribution, thus achieving weight quantization. Therefore, compared to dual-stack quantization, activated asymmetric quantization incurs additional costs during inference because the additional offset terms can be pre-calculated and incorporated into the bias at compile time, according to the formula... Four possible parameters for the relative quantization scheme are obtained. Without applying offset parameters, it follows the learnable symmetric quantization separation proposed in LSQ. Since it uses the unsigned range of the stacked quantization scheme, it completely corresponds to the parameterization proposed in LSQ for activation quantization. This represents the inverse quantization value of the weight. This represents the weight quantization value.

[0103] S5.62: Quantizes large datasets with highly discrete distributions based on an 8-bit quantization scheme.

[0104] The method for quantizing large-scale, highly discrete data based on an 8-bit quantization scheme includes the following steps:

[0105] S7.1 Obtain the quantized data value from S5.62;

[0106] S7.2 Output a 24-bit fixed-point number through a convolution function, and quantize the 24-bit fixed-point number to 8 bits according to the Soffmax operator;

[0107] S7.3 Combine the operators in the original neural network algorithm and output the result (e.g.) Figure 3 The diagram shown is a flowchart of FPGA Quantization.

[0108] In this embodiment, the computer program is run and initialized by the algebraic instruction set (Command) driver. The parameters and input data are input into the DataBuffer. The control parameters will automatically select the computation logic (Convolution, BN, Scale, ReLU, Eltwisee) and computation order of the entire device for operation. After the operation is completed, it returns to DDR to complete the Memory to Memory (data memory to memory exchange) operation.

[0109] PE units represent the important convolutional operation units in CNNs, while Assist Calculation represents the non-convolutional operation units. The operation flow of convolution and non-convolution is controlled by control parameters. Through the predefined General ParaControl section, the output results are quantized and written to DDR. A complete SDK program is used to deploy the FPGA. This SDK is a software package that supports the parameters required for a complete set of artificial intelligence algorithm calculations, including data preprocessing, quantization, and parameter configuration, enabling rapid configuration of the computational logic in the FPGA.

[0110] Data is transmitted via serial and Ethernet ports. Upon receiving a start signal, the FPGA program is initialized, and instructions are sent to the FPGA by accessing its registers, completing parameter read and write functions. The quantization module converts the trained floating-point model into a quantized model via software, directly obtaining the quantized output results using simulation software, and retaining the corresponding output parameters. These parameters are the calculation and control parameters required by the FPGA. The parameter configuration software allows for quick modification of FPGA parameters and, within the product's software architecture, also supports modifying the weights of different artificial intelligence algorithms; only the control parameters need to be modified.

[0111] FPGAs can be developed to meet specific needs, adapting to different algorithm model weights through external input parameters. In this invention, the FPGA starts its pre-trained detection model upon power-up, requiring no configuration and only needing to input detection data to output detection results.

[0112] The algorithm designed in this invention performs real-time processing of pulse radar signals. While traditional methods can only calculate distance and speed information, this invention provides an algorithm for identifying other aircraft types. This algorithm has been successfully deployed on UAVs, meeting the requirements for real-time processing. The accuracy and recall rates are both greater than 90%, and the F1 score (F1-Score, a statistical metric used to measure the accuracy of binary classification models) is greater than 85%. The average power consumption is 30W, meeting the endurance requirements of medium- to long-endurance UAVs.

[0113] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0114] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0115] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An FPGA chip-based radar signal processing device based on artificial intelligence, characterized in that, The processing device includes hardware devices and low-power devices that support real-time information processing on the drone. The hardware device that supports real-time information processing on the drone adopts an FPGA+ARM heterogeneous architecture to execute corresponding instructions without changing the original drone control data transmission and control link. The method for executing corresponding instructions without altering the original UAV control data transmission and control link includes the following steps: S1.

11. Set the parameters of the core computing unit according to the power consumption, weight and volume parameters of the UAV; S1.

21. Process the data according to the internal algorithm of the core computing unit, and use the processed data as the input of the RJ45 interface; S1.

31. Perform data preprocessing and FPGA hyperparameter calculation based on the input data, wherein the data preprocessing and FPGA hyperparameter calculation are performed by ARM. S1.

41. Initialize the instruction set according to the Command driver and input the parameters and input data into the DataBuffer; S1.

51. Transmit decision commands via RS232 serial port to achieve the goal of not changing the original UAV control data transmission and control link; The low-power device is used to optimize the logic and extend the drone's cruise time; The method for optimizing the logic includes the following steps: S1.

12. Obtain input data, read weight data, and directly multiply and accumulate the input data with the weight data. S1.

22. Perform 8-bit quantization on the FPGA calculation results and convert fixed-point numbers to floating-point numbers using the Softmax operator; S1.

32. Quantize highly discrete data within the scope of big data; S1.

42. Merge the operators in the neural network algorithm and output the results.

2. The FPGA chip radar signal processing device based on artificial intelligence according to claim 1, characterized in that, The method for data processing by the internal algorithm of the core computing unit includes the following steps: S2.

1. Obtain input data and cache the data using a FIFO. While caching, call the zero-padding module to process the data. S2.2 Obtain the number of channels in the input feature map and perform zero-padding. S2.3 Obtain the zero-padding data through calculation and output the feature data through FIFO; S2.4 Read weight data through FPGA Conv 1*3; S2.

5. After assembling the feature data into a 1*3 window, perform convolution calculation together with the weight data and output the result.

3. The FPGA chip radar signal processing device based on artificial intelligence according to claim 2, characterized in that, The method for obtaining the number of channels in the input feature map and padding with zeros includes the following steps: S3.1 Analyze the input data and perform zero-padding; S3.

2. Obtain a window size of 1*3, set the convolution stride to 1, and add 0 padding values ​​to the 1*3 window; S3.3, According to the formula The output data dimension values ​​are obtained, where W represents the dimension of the input data, P represents the padding value, and S is the step size. S3.4 Calculate the matrix inner product of the input data and the weight data, and add the calculation result to the corresponding bias value one by one to obtain the corresponding row and column values ​​in the 3*3 output matrix.

4. The FPGA chip radar signal processing device based on artificial intelligence according to claim 1, characterized in that, The method for converting fixed-point numbers to floating-point numbers using the Softmax operator includes the following steps: S5.11, The probability that a sample belongs to category i is: i=1,2,3...,C-1, according to the formula We obtain the first C-1 parameters, i.e. ; S5.21, Add a C-1 dimensional column vector If a sample belongs to the i-th class, then the element in the i-th row is 1, and the rest are 0. ; S5.31, according to Class, that is, when hour, If only one element in the matrix is ​​1 and the rest are 0, then the expected value of y is: ; S5.41, According to the formula i=1,2,3,...,C, we get ; S5.51, according to the Substitute into the formula From ; S5.

61. Replace i with C in the denominator to obtain ,Right now ; S5.71, Through The operator converts the data obtained from FPGA processing from fixed-point to floating-point numbers.

5. The FPGA chip radar signal processing device based on artificial intelligence according to claim 1, characterized in that, The 8-bit quantization method includes the following steps: S5.

12. When acquiring feature maps, the training focus should be on scale parameters and offset parameters. S5.22, According to the formula , s+z handles the skewed activation distribution, where It is a quantified value. These are the inverse quantized values, (x,n,p) represents the scale, z represents the offset parameter, and s represents the scale; S5.32, According to the formula Update the gradient of parameter s; S5.42, According to the formula Update the gradient of parameter z; S5.

52. Weight quantization is achieved by employing a symmetric signed quantization method, according to the formula... Four possible parameters for the relative quantization scheme are obtained, among which... This represents the inverse quantization value of the weight. Indicates the weight quantization value; S5.62: Quantizes large datasets with highly discrete distributions based on an 8-bit quantization scheme.

6. The FPGA chip radar signal processing device based on artificial intelligence according to claim 5, characterized in that, The method for quantizing large-scale, highly discrete data based on an 8-bit quantization scheme includes the following steps: S7.1 Obtain the quantized data value from S5.62; S7.2, Output a 24-bit fixed-point number using a convolution function, and according to... The operator quantizes 24-bit fixed-point quantization to 8 bits; S7.3 Merge the operators in the original neural network algorithm and output the result.

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