Adaptive lockout design method for airborne collision avoidance equipment and air traffic control response equipment
By using an adaptive latching design method, the trailing edge of the latching output signal is adjusted to adapt to changes in high and low temperature environments, thus solving the problem of signal delay instability in bidirectional input-output latching circuits and achieving the stability of latching output and meeting system performance requirements.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SICHUAN JIUZHOU AIR TRAFFIC CONTROL TECHNOLOGY CO LTD
- Filing Date
- 2022-10-27
- Publication Date
- 2026-07-31
AI Technical Summary
The existing bidirectional input/output latching circuit has inconsistent conduction time under high and low temperature environments, which causes the latching output signal to be delayed and changes, and cannot meet the system performance requirements.
An adaptive latching design method is adopted. By detecting the level of the latching input signal, the trailing edge of the latching output signal is adjusted at a predetermined detection point to ensure the stability of the timing relationship between the latching output and the transmit encoding output, and to adapt to changes in high and low temperature environments.
It achieves a fixed delay in the lockout output signal under high and low temperature environments, meeting system performance requirements and ensuring the stability and reliability of the lockout circuit.
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Figure CN115685181B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of aviation technology, and more specifically to an adaptive interlocking design method for airborne collision avoidance equipment and air traffic control response equipment. Background Technology
[0002] In the avionics systems of aircraft equipped with collision avoidance devices and air traffic control transponders, the collision avoidance devices obtain information about the target aircraft through active and passive surveillance, thereby achieving collision avoidance. Active surveillance is accomplished by sending quiet calls and Mode S interrogations, while passive surveillance is accomplished by receiving Automatic Dependent Surveillance-Broadcast (ADS-B OUT) messages from the target aircraft. The transponder receives and responds to Mode A / C and Mode S interrogations from the airborne interrogator or the ground control tower, thus assisting in air traffic control.
[0003] In aircraft avionics systems, collision avoidance devices and transponders operate simultaneously. To prevent the transponder from receiving inquiries from the collision avoidance device to other target aircraft, and to prevent the collision avoidance device from receiving responses from the transponder to other inquiries, or receiving ADS-B OUT information from the transponder, a mutual interlocking signal needs to be added between the collision avoidance device and the transponder.
[0004] Currently, the commonly used interlocking designs are divided into two types: one-way input / output interlocking and two-way input / output interlocking.
[0005] For a one-way input / output interlocking design, the collision avoidance device and the response device each need to employ a one-way input interlock and a one-way output interlock, respectively, to interlock the external device with the device and the device with the external device. This approach is not suitable when the system requires only one interlock between the device and the external device.
[0006] For bidirectional input / output (BIO) interlocking designs, both the collision avoidance and response devices require a BIO circuit design. This approach involves complex hardware design: software outputs an interlocking signal to drive a first-stage diode. When the first-stage diode conducts, the large current generated drives a second-stage diode, which in turn drives the higher-voltage BIO circuit. The advantage of this design is that the interlocking output returns via a hardware loop. However, due to the inconsistent conduction time of the diodes under high and low temperatures, the actual interlocking output signal varies with ambient temperature. In other words, in BIO circuit interlocking schemes, the signal delay of the actual interlocking output is inconsistent depending on the high and low temperature test conditions, preventing the interlocking circuit from achieving complete interlocking and causing the system performance to fail to meet technical specifications. Summary of the Invention
[0007] This invention provides an adaptive interlocking design method for airborne collision avoidance equipment and air traffic control transponder equipment. Unlike the traditional fixed interlocking design method, the adaptive interlocking design can adaptively adjust the delay of the interlocking output according to the inconsistent performance of the interlocking hardware circuit in environmental experiments, thereby ensuring that the timing relationship between the interlocking output and the transmission code output does not change due to changes in the external high and low temperature environment.
[0008] This invention is achieved through the following technical solution:
[0009] An adaptive interlocking design method for airborne collision avoidance equipment and air traffic control transponder equipment includes,
[0010] S1. During a single transmission, the last encoded pulse of the transmission response encoded output signal of the local transponder is used as the detection reference. The level of the latching input signal is detected at a predetermined detection point, and the trailing edge of the latching output signal is adjusted according to the level of the latching input signal.
[0011] S2, repeat S1 until the timing of the actual output signal of the lockout after passing through the bidirectional circuit and the coded pulse signal emitted by the local anti-collision or response device are stabilized at a fixed timing, so that the difference between the trailing edge of the actual output signal of the lockout and the last coded pulse emitted in each transmission process is stabilized at a set threshold, thereby ensuring that the actual output signal of the lockout meets the system performance requirements.
[0012] As an optimization, the specific steps of S1 are as follows:
[0013] S1.1 After the first response code pulse of this transmission from the local transponder device is encoded, the timing starts. The timing ends at a set threshold (usually 1us) from the trailing edge of the last pulse. Based on the timing end point, the bs_delay value is advanced, and the latching output signal bs_out0 is pulled low as the trailing edge position of the latching signal output.
[0014] S1.2 After the pulse code of the last response code output signal of the current transmission of the local transponder device is issued, a last pulse flag last_pluse_trig for a single clock cycle is generated. Taking the last pulse flag last_pluse_trig as the timing start point, after timing to the value of bs_check_delay, a detection point trigger signal check_point_trig is generated. The value of bs_check_delay is the system-required set threshold minus the fixed delay between the trailing edge of the latch input signal bs_in and the trailing edge of the actual latch output signal bs_out1, divided by the system clock cycle. That is, when the set threshold is 1us, the fixed delay is 0.2us, and the system clock cycle is 0.025us, bs_check_delay=(1us-0.2us) / 0.025us=32clock, where clock is the clock cycle.
[0015] S1.3 When the detection point trigger signal check_point_trig is high, the lockout output signal bs_out0 is adjusted by detecting the level of the lockout input signal bs_in and combining it with the bs_delay value.
[0016] As an optimization, the initial default value of the bs_delay value is 1us. When the system clock cycle is 0.025us, the initial default value of the bs_delay value is 40clock (1us). The adjustable range of the bs_delay value is 0clock to 720clock (0us to 18us).
[0017] As an optimization, in S1.3, if the level of the latching input signal bs_in is low and the value of bs_delay is not 0 clock, it means that the trailing edge of the latching output signal bs_out0 needs to be adjusted backward. In this case, the value of bs_delay is reduced by 1 clock, that is, the trailing edge is adjusted backward by 1 clock cycle.
[0018] As an optimization, in S1.3, if the latching input signal bs_in is low and the value of bs_delay is zero, it means that the trailing edge of the latching output signal bs_out0 has been adjusted to the minimum limit. Therefore, the value of bs_delay is maintained to prevent the value of bs_delay from decreasing by 1 clock and becoming negative, which would cause a sudden change in the latching trailing edge.
[0019] As an optimization, in S1.3, if the latching input signal bs_in is high and the value of bs_delay is less than 720 clock, it means that the trailing edge of bs_out0 needs to be adjusted forward. In this case, the value of bs_delay is increased by 1 clock, that is, the trailing edge is adjusted forward by 1 clock cycle.
[0020] As an optimization, in S1.3, if the latching input signal bs_in is high and the value of bs_delay is 720 clock, it means that the trailing edge of the latching output signal bs_out0 has been adjusted to the maximum limit. Therefore, the value of bs_delay is maintained to prevent the value of bs_delay from exceeding the adjustment range.
[0021] As an optimization, in S1.3, if the latching input signal bs_in is a falling edge, it means that the trailing edge of the latching output signal bs_out0 does not need to be adjusted, and the value of bs_delay will be maintained.
[0022] As an optimization, the specific steps of S2 are as follows:
[0023] In the next launch process, the adjusted bs_delay value is used as the trailing edge position of the latch output signal bs_out0, and S1.1 to S1.3 are repeated until the bs_delay value is adjusted to be close to the actual output delay value of the latch output signal bs_out0 and the actual latch output signal bs_out1 at the current temperature, that is, stabilized at the delay value ±1 clock.
[0024] As an optimization, a single clock cycle is 0.025µs.
[0025] Compared with the prior art, the present invention has the following advantages and beneficial effects:
[0026] This invention relates to aircraft avionics systems. To address the issue of varying diode conduction time in bidirectional input / output (BIO) interlocking circuits during high and low temperature environmental experiments, leading to changes in the actual interlocking output due to variations in ambient temperature, this invention proposes an adaptive interlocking output design method based on a BIO interlocking design scheme. This invention is applicable to scenarios where the delay between the loopback interlocking input signal and the actual interlocking output signal is fixed and does not change with ambient temperature. Using the last pulse of the transmitted response coded output signal as a measurement reference, the high and low levels of the interlocking input are detected at predetermined detection points to adjust the trailing edge of the interlocking output. This ensures that the timing of the actual interlocking output signal after passing through the bidirectional circuit and the transmitted coded output signal are stabilized at a fixed timing, thereby guaranteeing that the interlocking output meets system performance requirements. Attached Figure Description
[0027] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:
[0028] Figure 1 This is a timing diagram of the response encoding and latching output in an embodiment of the present invention;
[0029] Figure 2 This is a timing diagram of the locking adjustment process in an embodiment of the present invention. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this invention are only for explaining this invention and are not intended to limit this invention.
[0031] Example 1
[0032] Taking a response device as an example, when the response device needs to encode and send a response pulse, the interlocking signal is required to respond to the first pulse of the response encoding 1µs in advance and lag the trailing edge of the last pulse of the response encoding 1µs later. Its timing diagram is as follows: Figure 1 As shown in the figure, at normal temperature, the actual output signal bs_out1 of the latching output signal bs_out0 after passing through the bidirectional input / output circuit meets the system timing requirements along with the response code output ask_out. However, at high and low temperatures, although the leading edge of the actual output bs_out1 has a small delay compared to bs_out0, which does not affect the leading edge performance, the trailing edge changes significantly with the ambient temperature. The leading edge of the latching input signal bs_in, which loops back through the bidirectional input / output circuit, is also not significantly different from the leading edge of bs_out1. Its trailing edge has a fixed delay compared to the trailing edge of the actual output signal bs_out1, and this delay value does not change with temperature. Furthermore, since this device and the external device are mutually interlocked, the external device does not transmit when this device transmits. The tested latching input signal bs_in can be completely regarded as the loopback signal of the latching output signal bs_out0. Therefore, the trailing edge of the latching output signal bs_out0 can be adjusted according to the position of the trailing edge of the latching input signal bs_in, so that the trailing edge of the actual latching output signal bs_out1 meets the system performance requirements.
[0033] The method of the present invention is as follows:
[0034] like Figure 2As shown, an adaptive interlocking design method for airborne collision avoidance equipment and air traffic control transponder equipment includes,
[0035] S1. During a single transmission, the last encoded pulse of the transmission response encoded output signal of the local transponder is used as the detection reference. The level of the latching input signal is detected at a predetermined detection point, and the trailing edge of the latching output signal is adjusted according to the level of the latching input signal.
[0036] S2, repeat S1 until the timing of the actual output signal of the latch after passing through the bidirectional circuit and the response code output signal transmitted by the response device are stabilized at a fixed timing, so that the difference between the trailing edge of the actual output signal of the latch and the last coded pulse transmitted in each transmission process is stabilized at a set threshold, thereby ensuring that the actual output signal of the latch meets the system performance requirements.
[0037] In this embodiment, the specific steps of S1 are as follows:
[0038] S1.1 After the first response code pulse of this transmission from the local transponder device is encoded, the timing starts. The timing ends at a set threshold (usually 1us) from the trailing edge of the last pulse. Based on the timing end point, the bs_delay value is advanced, and the latching output signal bs_out0 is pulled low as the trailing edge position of the latching signal output.
[0039] S1.2 After the pulse code of the last response code output signal of this transmission from the local transponder device is issued, a last pulse flag last_pluse_trig for a single clock cycle is generated. Using the last pulse flag last_pluse_trig as the timing start point, after timing reaches the bs_check_delay value, a detection point trigger signal check_point_trig is generated. The bs_check_delay value is the system-required set threshold minus the time difference between the trailing edge of the latching input signal bs_in and the actual latching output signal bs_ou. The value of the trailing edge of t1 after a fixed delay is divided by the system clock cycle. That is, when the threshold is set to 1us, the fixed delay is 0.2us, and the system clock cycle is 0.025us, bs_check_delay = (1us - 0.2us) / 0.025us = 32clock, where clock is the clock cycle. When the system clock cycle is 0.025us, the initial default value of the bs_delay value is 40clock (1us), and the adjustable range of the bs_delay value is from 0clock to 720clock (0us to 18us).
[0040] S1.3 When the detection point trigger signal check_point_trig is high, the lockout output signal bs_out0 is adjusted by detecting the level of the lockout input signal bs_in and combining it with the bs_delay value.
[0041] Specifically, if the level of the latching input signal bs_in is low and the value of bs_delay is not 0 clock, it means that the trailing edge of the latching output signal bs_out0 needs to be adjusted backward. In this case, the value of bs_delay is reduced by 1 clock, that is, the trailing edge is adjusted backward by 1 clock cycle.
[0042] If the latching input signal bs_in is low and the value of bs_delay is zero, it means that the trailing edge of the latching output signal bs_out0 has been adjusted to the minimum limit. Therefore, the value of bs_delay is maintained to prevent the value of bs_delay from decreasing by 1 clock and becoming negative, which would cause a sudden change in the latching trailing edge.
[0043] If the latching input signal bs_in is high and the value of bs_delay is less than 720 clock cycles, it means that the trailing edge of bs_out0 needs to be adjusted forward. In this case, the value of bs_delay is increased by 1 clock cycle, that is, the trailing edge is adjusted forward by 1 clock cycle.
[0044] If the latching input signal bs_in is high and the value of bs_delay is 720 clock, it means that the trailing edge of bs_out0 has been adjusted to the maximum limit. Therefore, the value of bs_delay is maintained to prevent the value of bs_delay from exceeding the adjustment range.
[0045] If the latching input signal bs_in is a falling edge (changing from high level to low level), it means that the trailing edge of the latching output signal bs_out0 does not need to be adjusted, and the value of bs_delay will be maintained.
[0046] In this embodiment, the specific steps of S2 are as follows:
[0047] During the next transmission, the adjusted bs_delay value is used as the trailing edge position of the latching output signal bs_out0, and steps S1.1 to S1.3 are repeated until the bs_delay value is adjusted to a stable value. Although the timing of the latching output signal bs_out0 and the response code output signal ask_out differs under high and low temperature environments, since the latching output signal bs_in and the response code output signal ask_out remain within a stable range, and the delay between the latching output signal bs_in and the actual latching output signal bs_out1 is a fixed value, the timing of the actual latching output signal bs_out1 and the response code output signal ask_out also remains within a fixed range, thus meeting the system performance requirements.
[0048] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for adaptive lockout design of airborne collision avoidance equipment with air traffic control response equipment, characterized by, include: S1. During a single transmission, the last encoded pulse of the transmission response encoded output signal of the local transponder is used as the detection reference. The level of the latching input signal is detected at a predetermined detection point, and the trailing edge of the latching output signal is adjusted according to the level of the latching input signal. The specific steps of S1 are as follows: S1.1 After the first coded pulse of this transmission of the local anti-collision or response device is emitted, the timing starts. The timing ends at a set threshold distance from the trailing edge of the last pulse. Based on the timing end point, the bs_delay value is advanced, and the latching output signal bs_out0 is pulled low as the trailing edge position of the latching signal output. S1.2 After the last coded pulse of the current transmission of the local anti-collision or transponder device is emitted, a last pulse flag last_pluse_trig for a single clock cycle is generated. Taking the last pulse flag last_pluse_trig as the timing start point, after timing to the bs_check_delay value, a detection point trigger signal check_point_trig is generated. The bs_check_delay value is the system-required set threshold minus the fixed delay between the trailing edge of the latching input signal bs_in and the trailing edge of the actual latching output signal bs_out1, divided by the system clock cycle. S1.3 When the detection point trigger signal check_point_trig is high, the lockout output signal bs_out0 is adjusted by detecting the level of the lockout input signal bs_in and combining it with the bs_delay value. S2, repeat S1 until the timing of the actual output signal of the lockout after passing through the bidirectional circuit and the coded pulse signal emitted by the local anti-collision or response device are stabilized at a fixed timing, so that the difference between the trailing edge of the actual output signal of the lockout and the last coded pulse emitted in each transmission process is stabilized at a set threshold, thereby ensuring that the actual output signal of the lockout meets the system performance requirements.
2. A method for adaptive lockout design of airborne collision avoidance equipment with ATC response equipment as claimed in claim 1, wherein, When the system clock cycle is 0.025us, the initial default value of the bs_delay value is 40 clocks, and the adjustable range of the bs_delay value is from 0 clocks to 720 clocks.
3. The method for adaptive lockout design of airborne collision avoidance equipment with ATC transponder equipment as claimed in claim 1, wherein, In S1.3, if the level of the latching input signal bs_in is low and the value of bs_delay is not 0 clock, it means that the trailing edge of the latching output signal bs_out0 needs to be adjusted backward. In this case, the value of bs_delay is reduced by 1 clock, that is, the trailing edge is adjusted backward by 1 clock cycle.
4. The method for adaptive lockout design of airborne collision avoidance equipment with ATC transponder equipment as claimed in claim 1, wherein, In S1.3, if the latching input signal bs_in is high and the value of bs_delay is zero, it means that the trailing edge of the latching output signal bs_out0 has been adjusted to the minimum limit. Therefore, the value of bs_delay is maintained to prevent the value of bs_delay from decreasing by 1 clock and becoming negative, which would cause the latching trailing edge to change abruptly.
5. The method for adaptive lockout design of airborne collision avoidance equipment with ATC transponder equipment as claimed in claim 1, wherein, In S1.3, if the latching input signal bs_in is high and the value of bs_delay is less than 720 clock, it means that the trailing edge of bs_out0 needs to be adjusted forward. In this case, the value of bs_delay is increased by 1 clock, that is, the trailing edge is adjusted forward by 1 clock cycle.
6. The method for adaptive lockout design of airborne collision avoidance equipment with ATC transponder equipment as claimed in claim 1, wherein, In S1.3, if the latching input signal bs_in is high and the value of bs_delay is 720 clock, it means that the trailing edge of the latching output signal bs_out0 has been adjusted to the maximum limit. Therefore, the value of bs_delay is maintained to prevent the value of bs_delay from exceeding the adjustment range.
7. The method for adaptive lockout design of airborne collision avoidance equipment with ATC transponder equipment as claimed in claim 1 wherein, In S1.3, if the latching input signal bs_in is a falling edge, it means that the trailing edge of the latching signal output bs_out0 does not need to be adjusted, and the value of bs_delay will be maintained.
8. The method for adaptive lockout design of airborne collision avoidance equipment with ATC transponder equipment as claimed in claim 1 wherein, The specific steps of S2 are as follows: In the next launch process, the adjusted bs_delay value is used as the trailing edge position of the latch signal output bs_out0, and S1.1~S1.3 are repeated until the bs_delay value is adjusted to be close to the actual output delay value of the latch output signal bs_out0 and the actual latch output signal bs_out1 at the current temperature, that is, it is stabilized at the delay value ±1 clock.
9. The method for adaptive lockout design of airborne collision avoidance equipment with ATC transponder equipment as claimed in claim 1, wherein, The single clock cycle is 0.025µs.