Power sourcing equipment, power sourcing system, and non-transitory computer readable medium

Abstract

A power supply device, a power supply system, and a non-transitory computer-readable medium are disclosed. The power supply device includes a temporary storage circuit, an internal control circuit, and a storage circuit. The temporary storage circuit includes a first sub-temporary storage circuit and a second sub-temporary storage circuit, wherein the first and second sub-temporary storage circuits are used to alternately temporarily store data transmitted by an external control circuit. The internal control circuit is coupled to the temporary storage circuit and is used to retrieve the temporarily stored data from the first and second sub-temporary storage circuits. The storage circuit is coupled to the internal control circuit and is used to retrieve data from the internal control circuit and store the data.

Description

Technical Field

[0001] The embodiments described in this disclosure relate to a power supply device, a power supply system, and a non-transitory computer-readable medium, and particularly to a power supply device, a power supply system, and a non-transitory computer-readable medium that enables the power supply device to perform upgrades. Background Technology

[0002] In a power supply system, it is typically necessary to support up to (usually a maximum of 12) power supply devices. After the entire system boots up, the host software system starts first. When it reaches the subsystem for loading power supply devices, it checks the hardware version of the power supply devices. If a new version is available, it initiates a hardware upgrade for the power supply device system. This upgrade runs on the external control circuit. After the upgrade is complete, during the startup process of the external control circuit, the internal firmware of the chips of all power supply devices is loaded.

[0003] As I2C slave devices, taking 12 power supply devices as an example, each device is assigned a different I2C slave address, such as 0x20, 0x22, 0x24...0x34. Hardware upgrades are performed on each of the 12 devices individually, requiring this process to be repeated 12 times, which is time-consuming. Furthermore, the upgrade method uses a request / response mechanism, where the external control circuit transmits the next frame of data after receiving the response from the previous frame. If a request frame includes 32 bits of control data, 32 bits of transmission data, and the response data is also 32 bits, then the hardware data load utilization rate is only 1 / 3, which is low. Summary of the Invention

[0004] Some embodiments of this disclosure relate to a power supply device including a temporary storage circuit, an internal control circuit, and a storage circuit. The temporary storage circuit includes a first sub-temporary storage circuit and a second sub-temporary storage circuit, wherein the first and second sub-temporary storage circuits are used to alternately temporarily store data transmitted by an external control circuit. The internal control circuit is coupled to the temporary storage circuit and is used to retrieve the temporarily stored data from the first and second sub-temporary storage circuits. The storage circuit is coupled to the internal control circuit and is used to retrieve data from the internal control circuit and store the data.

[0005] Some embodiments of this disclosure relate to a power supply system including an external control circuit and a plurality of power supply end devices. The external control circuit is used to transmit data. The plurality of power supply end devices are coupled to the external control circuit, and each power supply end device includes a temporary storage circuit, an internal control circuit, and a storage circuit. The temporary storage circuit includes a first sub-temporary storage circuit and a second sub-temporary storage circuit for alternately temporary storage of the data transmitted by the external control circuit. The internal control circuit is coupled to the temporary storage circuit for retrieving data temporarily stored in the first and second sub-temporary storage circuits. The storage circuit is coupled to the internal control circuit for retrieving and storing data from the control circuit.

[0006] Some embodiments of this disclosure relate to a non-transitory computer-readable medium that stores computer software and is used to execute a data transmission method suitable for a power supply system. The data transmission method includes the following steps: receiving data transmitted from an external control circuit by a temporary storage circuit of a power supply device, wherein a first sub-temporary storage circuit and a second sub-temporary storage circuit of the temporary storage circuit alternately temporary storage of the data; and retrieving the temporary data from the temporary storage register by an internal control circuit of the power supply device and storing the data in a storage circuit. Attached Figure Description

[0007] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0008] Figure 1 This is a schematic diagram of a power supply system shown in accordance with some embodiments of the present disclosure;

[0009] Figure 2 This is a schematic diagram of a power supply device shown according to some embodiments of the present disclosure;

[0010] Figure 3 This is a flowchart illustrating a data transmission method according to some embodiments of the present disclosure;

[0011] Figure 4 These are schematic diagrams of data shown according to some embodiments of this disclosure; and

[0012] Figure 5 This is a flowchart illustrating a data transmission method according to some embodiments of the present disclosure.

[0013] Symbol Explanation

[0014] 100: Power supply system

[0015] 110: Host

[0016] 130: External control circuit

[0017] 150A: Power supply terminal device

[0018] 150B: Power supply terminal device

[0019] 150C: Power supply terminal device

[0020] 152: Temporary storage circuit

[0021] 153A: Sub-temporary storage circuit

[0022] 153B: Sub-temporary storage circuit

[0023] 154: Internal control circuit

[0024] 155: Storage circuit

[0025] 156: Memory

[0026] 158: Memory

[0027] 300: Data transmission method

[0028] S310, S330: Steps

[0029] Data0, Data1, DataN: Data packets

[0030] P: End

[0031] Ack: Acknowledgment signal

[0032] 400: Data

[0033] 500: Data transmission method

[0034] S510, S520, S530, S540: Steps

[0035] S550, S560, S570, S580: Steps Detailed Implementation

[0036] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to two or more components cooperating or interacting with each other.

[0037] refer to Figure 1 . Figure 1 This is a schematic diagram of a power supply system 100 shown according to some embodiments of the present disclosure.

[0038] by Figure 1 For example, the power supply system 100 includes a host 110, an external control circuit 130, and a plurality of power supply devices 150A to 150C. In terms of connection, the host 110 is coupled to the external control circuit 130, and the plurality of power supply devices 150A to 150C are coupled to the external control circuit 130.

[0039] refer to Figure 2 . Figure 2 This is a schematic diagram of a power supply device 150A according to some embodiments of the present disclosure. Only the power supply device 150A is described here as an example; the other power supply devices 150B and 150C are the same as or similar to the power supply device 150A.

[0040] by Figure 2For example, the power supply device 150A includes a temporary storage circuit 152, an internal control circuit 154, and a storage circuit 155. In terms of connectivity, the temporary storage circuit 152 is connected to the internal control circuit 154. The internal control circuit 154 is in turn connected to the storage circuit 155. The temporary storage circuit 152 further includes sub-temporary storage circuits 153A and 153B.

[0041] The configuration of the power supply system 100 and power supply terminal device 150A described above is for illustrative purposes only, and all configurations of the power supply system 100 and power supply terminal device 150A are within the scope of this disclosure. Detailed operating methods of the power supply system 100 and power supply terminal device 150A will be explained below. Figure 3 This will be explained together.

[0042] Figure 3 This is a flowchart illustrating a data transmission method 300 according to some embodiments of the present disclosure. The data transmission method 300 can be applied to, for example... Figure 1 The power supply system 100 and Figure 2 The power supply unit is 150A. Please refer to the following as well. Figures 1 to 3 .

[0043] In step S310, the temporary storage circuit of the power supply device receives data transmitted from the external control circuit, wherein the first sub-temporary storage circuit and the second sub-temporary storage circuit of the temporary storage circuit alternately temporary storage data. In some embodiments, step S310 is performed by, for example... Figure 1 The power supply devices 150A to 150C shown are used.

[0044] In some embodiments, please refer to the following: Figure 1 When the external control circuit 130 transmits data to the power supply devices 150A to 150C, the external control circuit 130 transmits the data to the power supply devices 150A to 150C in a broadcast manner. Furthermore, in some embodiments, the external control circuit 130 and the power supply devices 150A to 150C transmit data via an integrated circuit (I2C). Accordingly, when the external control circuit 130 wants to transmit data to the power supply devices 150A to 150C, all power supply devices 150A to 150C use the same I2C broadcast address. Thus, the external control circuit 130 only needs to send once to enable multiple power supply devices 150A to 150C to receive simultaneously.

[0045] In some embodiments, when the external control circuit 130 transmits data to the power supply device 150A, it only includes a request / reply procedure, which increases the utilization of the integrated bus circuit (I2C) and reduces the delay time between two data packets in the conventional way.

[0046] Please refer to the following: Figure 4 . Figure 4 This is a schematic diagram of data 400 shown according to some embodiments of this disclosure. For example... Figure 4 As shown, the data 400 transmitted by the external control circuit 130 includes a broadcast address, a temporary circuit address, and all data packets Data0 to DataN to be transmitted. Thus, since the data is transmitted once, there will only be one request / response procedure.

[0047] In some embodiments, the alternate data storage mentioned in step S310 refers to the data of the first part being stored by the sub-storage circuit 153A, the data of the second part being stored by the sub-storage circuit 153B, the data of the third part being stored by the sub-storage circuit 153A, the data of the fourth part being stored by the sub-storage circuit 153B, and so on.

[0048] In step S330, the internal control circuit of the power supply device retrieves the temporarily stored data from the register and stores the data in the storage circuit. In some embodiments, step S330 is performed by... Figure 2 The power supply terminal device 150A in the middle is used for execution.

[0049] Please refer to the following: Figure 2 In some embodiments, after the temporary storage circuit 152 of the power supply device 150A receives data, the sub-temporary storage circuits 153A and 153B temporarily store the data. Then, the internal control circuit 154 obtains the temporarily stored data from the sub-temporary storage circuits 153A and 153B, and stores the data temporarily stored by the sub-temporary storage circuits 153A and 153B into the storage circuit 155.

[0050] For example, after the sub-suspension circuit 153A temporarily stores the first part of the data, the internal control circuit 154 retrieves the first part of the data from the sub-suspension circuit 153A and stores it in the storage circuit. Then, after the sub-suspension circuit 135B temporarily stores the second part of the data, the internal control circuit 154 retrieves the second part of the data from the sub-suspension circuit 153B and stores it in the storage circuit. The rest follow the same pattern.

[0051] Please refer to Figure 5 . Figure 5 This is a flowchart illustrating a data transmission method 500 according to some embodiments of the present disclosure. The data transmission method 500 includes steps S510 to S580.

[0052] In step S510, the external control circuit enables the hardware upgrade function. For example, in some embodiments, Figure 1 The external control circuit 130 sets the parameter IMG_UGD_EN to 1 to enable the hardware upgrade function.

[0053] In step S520, the internal control circuit enters an upgrade mode. For example, in some embodiments, Figure 1 The external control circuit 130 sets the parameter IMG_UGD_TRIG to 1, and the power supply device 150 clears the temporarily stored parameters. Figure 2 The internal control circuit 154 sets the parameter IMG_UGD_RDY to enable the power supply device 150 to enter upgrade mode.

[0054] In step S530, the external control circuit initiates I2C propagation. For example, in some embodiments, the external control circuit 130 polls the power supply devices 150A to 150C until all power supply devices 150A to 150C enter upgrade mode, and then initiates I2C transmission. The I2C transmission address is the common broadcast address of the power supply devices 150A to 150C. The I2C data transmission uses sequence write, transmitting data to the I2C line in byte order at a time.

[0055] In step S540, the power supply device writes the received data into the first sub-temporary storage circuit. After writing the data, the first temporary storage parameter of the first sub-temporary storage circuit is set to 1. For example, in some embodiments, such as... Figure 2 The power supply device 150A writes the received data into the sub-scraping circuit 153A. After the sub-scraping circuit 153A stores the first 4 bytes of data, it sets the scrapping parameter EX2IN_MCU_DATA0_RDY to 1.

[0056] In step S550, the internal control circuit reads data from the first temporary storage circuit based on the value of the first temporary storage parameter, and sets the first temporary storage parameter to 0. For example, in some embodiments, such as Figure 2 The internal control circuit 154 cycles through the sub-suspension circuits 153A and 153B. When the internal control circuit 154 detects that the temporary storage parameter EX2IN_MCU_DATA0_RDY of the sub-suspension circuit 153A is 1, the internal control circuit 154 reads data from the sub-suspension circuit 153A and sets the first temporary storage parameter EX2IN_MCU_DATA0_RDY to 0 after reading the data. In some embodiments, the internal control circuit 154 also stores the acquired data in the storage circuit 155.

[0057] In step S560, the power supply device writes the received data into the second sub-temporary storage circuit. After writing the data, the second temporary storage parameter of the second sub-temporary storage circuit is set to 1. For example, in some embodiments, such as... Figure 2The power supply device 150A writes the received data into the sub-scraping circuit 153B. After the sub-scraping circuit 153B stores the second 4 bytes of data, it sets the scrapping parameter EX2IN_MCU_DATA1_RDY to 1.

[0058] In step S570, the internal control circuit reads data from the second temporary storage circuit based on the value of the second temporary storage parameter, and sets the second temporary storage parameter to 0. For example, in some embodiments, such as Figure 2 The internal control circuit 154 cycles through the sub-suspension circuits 153A and 153B. When the internal control circuit 154 detects that the temporary storage parameter EX2IN_MCU_DATA1_RDY of the sub-suspension circuit 153B is 1, the internal control circuit 154 reads data from the sub-suspension circuit 153B and sets the first temporary storage parameter EX2IN_MCU_DATA1_RDY to 0 after reading the data. In some embodiments, the internal control circuit 154 also stores the acquired data in the storage circuit 155.

[0059] In step S580, steps S540 to S570 are repeated until the hardware transmission ends or an abnormal exit occurs. For example, in some embodiments, the third 4-byte data is written to sub-scraping circuit 153A, the fourth 4-byte data is written to sub-scraping circuit 153B, the fifth 4-byte data is written to sub-scraping circuit 153A, and so on.

[0060] In some embodiments, if the power supply device 150A wants to receive data, and both the first temporary parameter and the second temporary parameter are 1, the internal control circuit is also used to transmit a no-acknowledge signal (NOACK) to the external control circuit 130 so that the external control circuit 130 stops transmitting data.

[0061] For example, if the power supply device 150A wants to receive the next 4 bytes of data, and both the temporary storage parameters EX2IN_MCU_WORD0_RDY and EX2IN_MCU_WORD1_RDY are 1, it indicates that the internal control circuit 154 has not yet had time to retrieve the data from the sub-temporary storage circuits 153A or 153B. At this time, the internal control circuit 154 sends a NOACK signal to the external control circuit 130 to stop receiving data transmitted by the external control circuit 130. Simultaneously, the internal control circuit 154 sets the parameter IMG_UGD_TRIG to 0 and the parameter EX2IN_MCU_FAIL to 1 to indicate that the update performed by the external control circuit 130 has failed. Therefore, in the embodiments of this disclosure, it is necessary to ensure that the processing speed of the internal control circuit 154 is faster than the transmission speed over the I2C line.

[0062] In some embodiments, when the power supply device 150A receives a stop signal from the external control circuit 130, the internal control circuit 154 of the power supply device 150A sets the parameter IMG_UGD_TRIG to 0 and the parameter EX2IN_MCU_DONE to 1. After parsing the END flag, the internal control circuit 154 stops accessing data, clears the parameter IMG_UGD_INT, and ends the update.

[0063] In some embodiments, the internal control circuit 154 performs a checksum during data reception. At the end of transmission, the calculated checksum value is compared with the checksum value of the last 4 bytes of data. If there is no error, the parameter IMG_CRC_CHECK_PASS is set to 1; otherwise, it is set to 0. After sending all data, the external control circuit 130 checks whether the power supply device 150A has received the correct data. If the external control circuit 130 reads that the parameter IMG_CRC_CHECK_PASS of the temporary storage circuit 152 is 1, it indicates that the upgrade was successful. Conversely, if the parameter IMG_CRC_CHECK_PASS is not 1, it indicates that the upgrade failed, and the data transmission method 500 is re-executed to perform the upgrade.

[0064] Please refer back to this. Figure 2 In some embodiments, the storage circuit 155 further includes a memory 156 (data memory DMEM) and a memory 158 (instruction memory IMEM). The internal control circuit 154 is also used to transfer data to the memory 156 or the memory 158 for storage based on the received data.

[0065] Based on the foregoing embodiments, some other embodiments of this disclosure provide a non-transitory computer-readable medium. The non-transitory computer-readable medium stores computer software and is used to execute the aforementioned... Figure 3 The data transmission method 300 shown or the aforementioned method as described above Figure 5 The data transmission method 500 is shown. In some embodiments, the non-transitory computer-readable medium is stored in... Figure 1 In the power supply devices 150A, 150B, 150C and / or external control circuit 130.

[0066] In some embodiments, the host 110 is used to control the operation of the external control circuit 130.

[0067] In summary, this disclosure provides a power supply device, a power supply system, and a non-transitory computer-readable medium. Through an external control circuit, data is transmitted in a single pass to all power supply devices sharing a common broadcast address on the I2C bus via sequential I2C writing. A sub-scrambling circuit within the power supply device continuously receives data from the I2C bus and, through the setting of dedicated scraping parameters, marks whether the sub-scrambling circuit has stored data. An error signal can be sent to the external control circuit if the sub-scrambling circuit can no longer store data. Furthermore, the internal control circuit, in coordination with the behavior of the power supply devices, retrieves data from the sub-scrambling circuit and performs data parsing and transfer.

[0068] Accordingly, in the embodiments of this disclosure, the broadcast method can save transmission time. In the sequence write method, except for the initial two bytes used for the I2C address and the temporary register address, all other data is effectively transmitted, achieving nearly 100% I2C utilization. Furthermore, through the design of two sub-temporary circuits and temporary parameters, it is ensured that while the internal control circuit is reading data from one of the sub-temporary circuits, the power supply device can continuously receive data on the I2C line, guaranteeing uninterrupted I2C transmission.

[0069] Various functional components are disclosed herein. For those skilled in the art, these functional components can be implemented by circuits (whether dedicated circuits or general-purpose circuits operating under the control of one or more processors and coded instructions).

[0070] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make various changes and modifications without departing from the concept and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the claims.

Claims

1. A power supply terminal device, comprising: A temporary storage circuit includes a first sub-temporary storage circuit and a second sub-temporary storage circuit, wherein the first sub-temporary storage circuit and the second sub-temporary storage circuit are used to alternately temporarily store data transmitted by an external control circuit, wherein the first sub-temporary storage circuit is used to temporarily store a first portion of the data, and the second sub-temporary storage circuit is used to temporarily store a second portion of the data, wherein the data includes a temporary storage circuit address and multiple data packets; An internal control circuit is coupled to the temporary storage circuit and is used to obtain the temporarily stored data from the first sub-temporary storage circuit and the second sub-temporary storage circuit. as well as A storage circuit is coupled to the internal control circuit and is used to obtain the data from the internal control circuit and store the data.

2. The power supply device as claimed in claim 1, wherein the data transmitted by the external control circuit is broadcast to the temporary storage circuit by the external control circuit, and during the transmission of the plurality of data packets, the plurality of data packets contain only one request / response procedure.

3. The power supply device as claimed in claim 1, wherein the first sub-storage circuit includes a first temporary storage parameter, and the second sub-storage circuit includes a second temporary storage parameter, wherein when the first temporary storage parameter is a first value, the first sub-storage circuit transmits the first portion of the temporarily stored data to the internal control circuit, and when the first temporary storage parameter is a second value, the first sub-storage circuit receives and temporarily stores a third portion of the data transmitted by the external control circuit, wherein when the second temporary storage parameter is the first value, the second sub-storage circuit transmits the second portion of the temporarily stored data to the internal control circuit, and when the second temporary storage parameter is the second value, the second sub-storage circuit receives and temporarily stores a fourth portion of the data transmitted by the external control circuit.

4. The power supply device as claimed in claim 3, wherein after the internal control circuit obtains the first portion of the data temporarily stored in the first sub-storage circuit, the internal control circuit sets the first temporary storage parameter to the first value, and after the internal control circuit obtains the second portion of the data temporarily stored in the second sub-storage circuit, the internal control circuit sets the second temporary storage parameter to the first value.

5. The power supply device as claimed in claim 3, wherein the internal control circuit is further configured to cycle through the first sub-temporary circuit and the second sub-temporary circuit to obtain the first temporary storage parameter and the second temporary storage parameter.

6. The power supply device as claimed in claim 3, wherein when both the first temporary parameter and the second temporary parameter are the second value, the internal control circuit is further configured to transmit a no-response signal to the external control circuit so that the external control circuit stops transmitting the data.

7. A power supply system, comprising: An external control circuit is used to transmit data, wherein the data includes a temporary circuit address and multiple data packets; and Multiple power supply devices are coupled to the external control circuit, each of the multiple power supply devices comprising: A temporary storage circuit includes a first sub-temporary storage circuit and a second sub-temporary storage circuit, wherein the first sub-temporary storage circuit and the second sub-temporary storage circuit are used to alternately temporarily store the data transmitted by the external control circuit, wherein the first sub-temporary storage circuit is used to temporarily store a first part of the data, and the second sub-temporary storage circuit is used to temporarily store a second part of the data. An internal control circuit, coupled to the temporary storage circuit, is used to retrieve the data temporarily stored in the first sub-temporary storage circuit and the second sub-temporary storage circuit; and A storage circuit is coupled to the internal control circuit and is used to retrieve and store the data by the control circuit.

8. A non-transitory computer-readable medium storing computer software for executing a data transmission method, suitable for a power supply system, the data transmission method comprising: A temporary storage circuit of a power supply device receives data transmitted from an external control circuit, wherein a first sub-temporary storage circuit and a second sub-temporary storage circuit of the temporary storage circuit alternately temporary storage of the data, wherein the data includes a temporary storage circuit address and multiple data packets, and wherein the operation of the first sub-temporary storage circuit and the second sub-temporary storage circuit alternately temporary storage of the data transmitted by the external control circuit includes: A first portion of the data is temporarily stored in the first sub-temporary storage circuit; and A second portion of the data is temporarily stored in the second sub-temporary storage circuit; and The data is temporarily stored in a register by an internal control circuit of a power supply device and stored in a storage circuit.

9. The non-transitory computer-readable medium of claim 8, wherein the first sub-suspension circuit includes a first temporary storage parameter, and the second sub-suspension circuit includes a second temporary storage parameter, wherein the data transmission method further includes: When the first temporary storage parameter is a first value, the first part of the temporarily stored data is transmitted by the first sub-temporary storage circuit to the internal control circuit. When the first temporary storage parameter is a second value, the first sub-temporary storage circuit receives and temporarily stores a third part of the data transmitted by the external control circuit. When the second temporary storage parameter is the first value, the second portion of the temporarily stored data is transferred by the second sub-temporary storage circuit to the internal control circuit; and When the second temporary parameter is the second value, the second sub-temporary circuit receives and temporarily stores a fourth part of the data transmitted by the external control circuit.

10. The non-transitory computer-readable medium of claim 8, further comprising: The internal control circuit determines whether the data has been successfully transmitted.

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