A PMC mode state switching method and device under a power management system

Abstract

The application discloses a PMC mode state switching method and device under a power management system, and the method comprises the following steps: when the PMC is in a normal operation state, the state of the PMC is switched from the normal operation state to a PMC waiting state in which the CPU is controlled by the PMC to keep not executing; the power management system judges whether the CPU needs to support CPU memory storage; when the CPU memory storage is performed, read-write CPU memory operation processing is performed, and after the processing is completed, the power management system is triggered by the PMC to enter an isolation enabling state; when the CPU memory storage is not performed, the power management system is triggered by the PMC to enter the isolation enabling state; after the power management system enters the isolation enabling state, the power management system and the PMC enter a standby state. In the embodiment of the application, the power management system and the PMC can orderly enter the standby state, and the state synchronization when the power management system and the PMC are restored to the normal operation state in the standby state is facilitated.

Description

Technical Field

[0001] This invention relates to the field of power management technology, and in particular to a method and apparatus for switching PMC mode states under a power management system. Background Technology

[0002] The PMC (Power Management Controller) in a power management system typically supports three modes: RUN, STOP, and STANDBY. In RUN mode, the chip is entered after power-on reset, and all power supplies, clocks, and functional modules operate normally. In STOP mode, the power management system's power modules maintain power supply but disable the core clock, and the CPU stops reading and writing to flash / SRAM. Other clock sources can be enabled or disabled by the power management system. In STANDBY mode, the power management system consumes the least power, disables most digital circuit power, retains only external wake-up sources, the clock module retains a low-speed 128kHz clock, the flash enters deep power down or power off, and the SRAM enters retention mode.

[0003] In existing technologies, the power management system controls the PMC to enter standby mode by directly shutting down most of the corresponding digital circuits through software. This can lead to problems such as asynchrony between the CPU and PMC when the PMC is woken up later. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a PMC mode state switching method and device under a power management system, which enables the power management system and PMC to enter the standby state in an orderly manner, facilitating state synchronization when restoring to the normal operation state from the standby state.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a PMC mode state switching method under a power management system, the method comprising:

[0006] When the PMC is running in normal operation, the state of the PMC is switched from normal operation to PMC waiting for the CPU to be controlled by the PMC and enter a non-execution state based on the deep sleep instruction.

[0007] While the PMC is waiting for the CPU to be controlled by the PMC to enter a hold-non-execution state, the power management system determines whether the CPU needs to support CPU memory storage.

[0008] When the CPU memory is stored, the power management system enters the CPU memory read / write operation process, and after the CPU memory read / write operation is completed, the PMC triggers the power management system to enter the isolation enable state.

[0009] If the CPU memory storage is not performed, the PMC triggers the power management system to enter the isolation enable state;

[0010] After the power management system enters the isolation enabled state, the power management system and the PMC enter the standby state.

[0011] Optionally, the step of switching the state of the PMC from normal operation to a state where the PMC waits for the CPU to be controlled by the PMC and enters a state of inactivity based on the deep sleep command includes:

[0012] After receiving a deep sleep command from the CPU, the PMC generates a CPU hold sleep signal to control the CPU to remain in a non-executing state, and sends the CPU hold sleep signal to the CPU.

[0013] After the CPU hold sleep signal is sent to the CPU, the state of the PMC changes from normal operation to PMC waiting for the CPU to be controlled by the PMC to enter a hold-not-execute state.

[0014] Optionally, the CPU hold sleep signal is a low active signal; the CPU hold sleep signal is used to control the CPU to enter a state of holding and not executing instructions.

[0015] Optionally, sending the CPU hold sleep signal to the CPU further includes:

[0016] During the process of the CPU hold sleep signal entering standby state, if the PMC receives a wakeup signal sent by the wake-up source, it will set the CPU hold sleep signal to an invalid signal.

[0017] Optionally, the power management system determines whether the CPU needs to perform CPU memory storage, including:

[0018] After the PMC receives the hold sleep ack signal from the CPU, the power management system determines whether the CPU needs to perform CPU memory storage based on whether a CPU save operation is enabled.

[0019] If CPU save operation is enabled, it is determined that the CPU needs to perform CPU memory storage; if CPU save operation is not enabled, it is determined that the CPU does not need to perform CPU memory storage.

[0020] Optionally, the power management system enters the read / write CPU memory operation process, including:

[0021] The PMC in the power management system generates CPU memory storage instructions and sends the CPU memory storage instructions to the CPU memory control unit;

[0022] The CPU memory control unit performs CPU memory operation read and write processing based on the CPU memory storage instructions.

[0023] Optionally, the CPU memory control unit performs CPU memory operation read / write processing based on the CPU memory storage instructions, including:

[0024] The CPU memory control unit reads the corresponding CPU memory operation from the CPU according to the CPU memory storage instruction, and writes the read CPU memory operation into the CPU memory static storage unit for storage.

[0025] Optionally, the PMC triggers the power management system to enter an isolation enabled state, including:

[0026] The PMC enters the open isolation enable state, and the PMC triggers the power management system to enter the isolation enable state based on the open isolation enable state.

[0027] Optionally, the power management system and the PMC enter a standby state, including:

[0028] After the power management system and the PMC enter the isolation enable state, the PMC simultaneously enters the powerdown phase, and after the power down is completed, the power management system and the PMC enter the standby state.

[0029] In addition, embodiments of the present invention also provide a PMC mode state switching device under a power management system, the device comprising:

[0030] State switching module: used to switch the state of PMC from normal operation to PMC waiting for CPU to be controlled by PMC and enter a non-execution state when PMC is running in normal operation state based on deep sleep command;

[0031] Judgment module: Used by the power management system to determine whether the CPU needs to support CPU memory storage when the PMC is waiting for the CPU to be controlled by the PMC to enter a hold-non-execution state;

[0032] Read / write module: When the CPU memory is being stored, the power management system enters the read / write CPU memory operation process, and after the read / write operation of the CPU memory is completed, the PMC triggers the power management system to enter the isolation enable state;

[0033] Trigger module: Used to trigger the power management system to enter the isolation enable state if the CPU memory storage is not performed;

[0034] Standby module: Used to enable the power management system and the PMC to enter standby mode after the power management system enters the isolation enable state.

[0035] In this embodiment of the invention, after the PMC receives a deep sleep command, it controls the CPU to remain in a non-executing state by using the CPU hold sleep signal; then it determines whether the CPU needs to support CPU-based storage, and if so, performs corresponding read and write operations on the CPU memory, and triggers the power management system to enter the isolation enable state after completion; then it controls the power management system and the PMC to enter the standby state, which allows the power management system and the PMC to enter the standby state in an orderly manner, which facilitates the state synchronization when restoring to the normal operating state in the standby state. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the structural composition of the power management system in an embodiment of the present invention;

[0038] Figure 2 This is a flowchart illustrating the PMC mode state switching method under the power management system in the first embodiment of the present invention.

[0039] Figure 3 This is a flowchart illustrating the PMC mode state switching method under the power management system in the second embodiment of the present invention.

[0040] Figure 4 This is a flowchart illustrating the PMC mode state switching method under the power management system in the third embodiment of the present invention.

[0041] Figure 5This is a flowchart illustrating the PMC mode state switching method under the power management system in the fourth embodiment of the present invention.

[0042] Figure 6 This is a schematic diagram of the structural composition of the PMC mode state switching device under the power management system in an embodiment of the present invention. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] Please see Figure 1 , Figure 1 This is a schematic diagram of the structural composition of the power management system in an embodiment of the present invention.

[0045] like Figure 1 As shown, the power management system can be a System-on-a-Chip (SoC) or an independent power management module. The power management system includes: CPU, CPU memory control unit, CPU memory static storage unit, system static storage unit, flash memory unit, analog unit, PMC, etc.

[0046] The system supports CPU memory retention control, which means that before entering standby mode, the system controls the reading of instructions from the CPU and storing them in SRAM (CPU static memory unit). After the system is powered on again in standby mode, the system controls the reload of instructions from SRAM (CPU static memory unit) and writes them back into the CPU.

[0047] In normal operating mode (RUN), the 1.1V power supply to the power management system is provided by the linear regulator LDO11_MR. In low-power mode (STANDBY), LDO11_MR is turned off, and LDO11_LR powers the chip. Specifically, LDO11_LR provides the 1.1V power to the CPU static memory unit, system static memory unit, and flash memory. In standby mode (STANDBY), the CPU and CPU memory control unit have no power supply, belonging to the shutdown domain (shut). The PMC, flash memory units, and analog units are always powered, belonging to the always-on domain (alon). The flash memory unit has an internal power switch, which can be controlled by the SUPPLYON signal. When SUPPLYON = 0, the 1.1V and 3.3V power supplies to the flash memory are turned off. The system supports enable control, which, when preparing to enter standby mode, mainly controls the output of peripherals related to the shutdown domain and maintains the enable signal in the state before power loss. When the system is not powered off, the CPU can perform an abort standby operation by handshaking with the PMC, thereby preventing the CPU from hanging or crashing.

[0048] Example 1

[0049] Please see Figure 2 , Figure 2 This is a flowchart illustrating the PMC mode state switching method under the power management system in an embodiment of the present invention.

[0050] like Figure 2 As shown, a PMC mode state switching method under a power management system includes:

[0051] S11: When the PMC is running in normal operation, the state of the PMC is switched from normal operation to PMC waiting for the CPU to be controlled by the PMC and enter a non-execution state based on the deep sleep instruction;

[0052] In a specific implementation of this invention, the step of switching the state of the PMC from normal operation to PMC waiting for the CPU to be controlled by the PMC to enter a hold-not-execute state based on a deep sleep instruction includes: after receiving a deep sleep instruction issued by the CPU, the PMC generates a CPU hold-sleep signal for controlling the CPU to remain in a hold-not-execute state and sends the CPU hold-sleep signal to the CPU; after sending the CPU hold-sleep signal to the CPU, the state of the PMC switches from normal operation to PMC waiting for the CPU to be controlled by the PMC to enter a hold-not-execute state.

[0053] Furthermore, the CPU hold sleep signal is a low active signal; the CPU hold sleep signal is used to control the CPU to enter a state of holding and not executing instructions.

[0054] Furthermore, sending the CPU hold sleep signal to the CPU also includes:

[0055] During the process of the CPU hold sleep signal entering standby state, if the PMC receives a wakeup signal sent by the wake-up source, it will set the CPU hold sleep signal to an invalid signal.

[0056] Specifically, when the PMC is operating normally, it receives a deep sleep instruction (deep sleep signal) from the CPU and requests the power management system to enter standby mode. After receiving the deep sleep instruction from the CPU, and with standby enable active in application operation, the PMC first generates a CPU hold sleep signal to control the CPU to remain in a non-executing state, and then sends the CPU hold sleep signal to the CPU. After sending the CPU hold sleep signal to the CPU, the state of the PMC will switch from normal operation to PMC waiting for the CPU to enter a hold-to-non-executing state under the control of the PMC.

[0057] The CPU hold sleep signal is a low-active signal. It is a signal that holds the CPU in place and prevents it from executing instructions. This signal is generated by the PMC and sent to the CPU. After the CPU receives the CPU hold sleep signal, it holds the CPU in place. When the PMC receives a wakeup signal from the wakeup source during the process of entering the standby state, it will set the CPU hold sleep signal to an invalid signal on the second clock cycle.

[0058] S12: When the PMC is waiting for the CPU to be controlled by the PMC to enter a hold-non-execution state, the power management system determines whether the CPU needs to support CPU memory storage.

[0059] In a specific implementation of the present invention, the power management system determines whether the CPU needs to perform CPU memory storage, including: after the PMC receives the hold sleep ack signal fed back by the CPU, the power management system determines whether the CPU needs to perform CPU memory storage based on whether a CPU save operation is enabled; wherein, if a CPU save operation is enabled, it is determined that the CPU needs to perform CPU memory storage; if a CPU save operation is not enabled, it is determined that the CPU does not need to perform CPU memory storage.

[0060] Specifically, when the PMC is waiting for the CPU to enter a hold-sleep state under PMC control, the power management system needs to determine whether the CPU needs to support CPU memory storage. Specifically, after the CPU holds, a hold sleepack signal is generated and fed back to the PMC. After the PMC receives the hold sleepack signal from the CPU, the power management system determines whether the CPU needs to perform CPU memory storage by checking if CPU save operation is enabled. That is, if CPU save operation is enabled, it is determined that the CPU needs to perform CPU memory storage; if CPU save operation is not enabled, it is determined that the CPU does not need to perform CPU memory storage.

[0061] The hold sleep ack signal is a low-active signal. It is an acknowledgment signal generated by the CPU and sent to the PMC after the CPU hold sleep signal is received. The hold sleep ack signal becomes invalid after the second clock cycle after the CPU hold sleep signal becomes invalid.

[0062] S13: When performing the CPU memory storage, the power management system enters the CPU memory read / write operation processing, and after completing the CPU memory read / write operation, the PMC triggers the power management system to enter the isolation enable state.

[0063] In a specific implementation of the present invention, the power management system enters the CPU memory read / write operation process, including: the PMC in the power management system generates a CPU memory storage instruction and sends the CPU memory storage instruction to the CPU memory control unit; the CPU memory control unit performs CPU memory read / write operation based on the CPU memory storage instruction.

[0064] Furthermore, the CPU memory control unit performs CPU memory operation read and write processing based on the CPU memory storage instructions, including: the CPU memory control unit reads the corresponding CPU memory operation in the CPU according to the CPU memory storage instructions, and writes the read CPU memory operation into the CPU memory static storage unit for storage.

[0065] Furthermore, the PMC triggering the power management system to enter the isolation enabled state includes: the PMC entering the open isolation enabled state, and the PMC triggering the power management system to enter the isolation enabled state based on the open isolation enabled state.

[0066] Specifically, when performing CPU memory storage, the PMC in the power management system generates a CPU memory storage instruction and then sends the CPU memory storage instruction to the CPU memory control unit. By controlling the CPU memory storage instruction to be sent to the CPU memory control unit to perform read and write processing on the CPU memory operation, the storage of the CPU memory operation can be realized.

[0067] That is, the CPU memory control unit reads the corresponding CPU memory operation in the CPU according to the CPU memory storage instruction, and writes the read CPU memory operation into the CPU memory static storage unit for storage; it should be noted that during this process, the PMC will control the flash to enter a low power mode, which requires controlling the flash control signal in different power modes to prepare it to enter the standby state.

[0068] Then the PMC enters the isolation enabled state, and the PMC triggers the power management system to enter the isolation enabled state based on the isolation enabled state.

[0069] S14: If the CPU memory storage is not performed, the PMC triggers the power management system to enter the isolation enable state;

[0070] In a specific implementation of the present invention, the PMC triggers the power management system to enter the isolation enabled state, including: the PMC entering the open isolation enabled state, and the PMC triggering the power management system to enter the isolation enabled state based on the open isolation enabled state.

[0071] When CPU memory storage is not required, the PMC enters the open isolation enable state, and the PMC triggers the power management system to enter the isolation enable state based on the open isolation enable state.

[0072] S15: After the power management system enters the isolation enable state, the power management system and the PMC enter the standby state.

[0073] In a specific implementation of the present invention, the power management system and the PMC enter a standby state, including: after the power management system and the PMC enter an isolation enable state, the PMC simultaneously enters a power down phase, and after the power down is completed, the power management system and the PMC enter a standby state.

[0074] Specifically, after the power management system and PMC enter the isolation enable state, the PMC simultaneously enters the power down phase, and after the power down is completed, both the power management system and PMC enter the standby state.

[0075] In this embodiment of the invention, after the PMC receives a deep sleep command, it controls the CPU to remain in a non-executing state by using the CPU hold sleep signal; then it determines whether the CPU needs to support CPU-based storage, and if so, performs corresponding read and write operations on the CPU memory, and triggers the power management system to enter the isolation enable state after completion; then it controls the power management system and the PMC to enter the standby state, which allows the power management system and the PMC to enter the standby state in an orderly manner, which facilitates the state synchronization when restoring to the normal operating state in the standby state.

[0076] Example 2

[0077] Please see Figure 3 , Figure 3 This is a flowchart illustrating the PMC mode state switching method under the power management system in the second embodiment of the present invention.

[0078] like Figure 3 As shown, a PMC mode state switching method under a power management system includes:

[0079] S21: When the PMC is running in normal operation, after the PMC receives a deep sleep instruction from the CPU, the PMC generates a CPU hold sleep signal to control the CPU to remain in a non-executing state and sends the CPU hold sleep signal to the CPU.

[0080] In the specific implementation of this invention, when the PMC is running in a normal state, the PMC may receive a deep sleep instruction at any time. The deep sleep instruction is generated by the CPU and sent to the PMC. Then, the PMC generates a CPU hold sleep signal to control the CPU to remain in a non-executing state according to the deep sleep instruction, and sends the CPU hold sleep signal to the CPU.

[0081] In this application, the CPU hold sleep signal is a low active signal; at the same time, the CPU hold sleep signal is used to control the CPU to enter a state of holding and not executing instructions.

[0082] During the process of generating a CPU hold sleep signal and entering standby mode, the PMC also continues to receive wake-up signals from the wake-up source. When the PMC receives the wake-up signal from the wake-up source, it sets the CPU hold sleep signal to an invalid signal. As a result, the CPU will re-enter the working state, and the PMC will also enter the normal working state. In this embodiment of the invention, the CPU hold sleep signal can be used to control the CPU to enter a state of holding no instructions, which allows the power management system to enter the standby state in an orderly manner. Furthermore, since the CPU hold sleep signal is a low-active signal, when the PMC receives the wake-up signal from the wake-up source, it sets the CPU hold sleep signal to an invalid signal, allowing the CPU to quickly enter the normal working state.

[0083] S22: After sending the CPU hold sleep signal to the CPU, the state of the PMC changes from normal operation to PMC waiting for the CPU to be controlled by the PMC to enter a hold-not-execute state;

[0084] In the specific implementation of this invention, after the CPU hold sleep signal is sent to the CPU, the state of the PMC is switched from normal operation to PMC waiting for the CPU to be controlled by the PMC to enter a hold-not-execute state.

[0085] S23: When the PMC is waiting for the CPU to be controlled by the PMC to enter a hold-non-execution state, the power management system determines whether the CPU needs to support CPU memory storage.

[0086] In a specific implementation of the present invention, the power management system determines whether the CPU needs to perform CPU memory storage, including: after the PMC receives the hold sleep ack signal fed back by the CPU, the power management system determines whether the CPU needs to perform CPU memory storage based on whether a CPU save operation is enabled; wherein, if a CPU save operation is enabled, it is determined that the CPU needs to perform CPU memory storage; if a CPU save operation is not enabled, it is determined that the CPU does not need to perform CPU memory storage.

[0087] Specifically, when the PMC is waiting for the CPU to enter a hold-sleep state under PMC control, the power management system needs to determine whether the CPU needs to support CPU memory storage. Specifically, after the CPU holds, a hold sleepack signal is generated and fed back to the PMC. After the PMC receives the hold sleepack signal from the CPU, the power management system determines whether the CPU needs to perform CPU memory storage by checking if CPU save operation is enabled. That is, if CPU save operation is enabled, it is determined that the CPU needs to perform CPU memory storage; if CPU save operation is not enabled, it is determined that the CPU does not need to perform CPU memory storage.

[0088] The hold sleep ack signal is a low-active signal. It is an acknowledgment signal generated by the CPU and sent to the PMC after the CPU hold sleep signal is received. The hold sleep ack signal becomes invalid after the second clock cycle after the CPU hold sleep signal becomes invalid.

[0089] S24: When performing the CPU memory storage, the power management system enters the CPU memory read / write operation processing, and after completing the CPU memory read / write operation, the PMC triggers the power management system to enter the isolation enable state.

[0090] In a specific implementation of the present invention, the power management system enters the CPU memory read / write operation process, including: the PMC in the power management system generates a CPU memory storage instruction and sends the CPU memory storage instruction to the CPU memory control unit; the CPU memory control unit performs CPU memory read / write operation based on the CPU memory storage instruction.

[0091] Furthermore, the CPU memory control unit performs CPU memory operation read and write processing based on the CPU memory storage instructions, including: the CPU memory control unit reads the corresponding CPU memory operation in the CPU according to the CPU memory storage instructions, and writes the read CPU memory operation into the CPU memory static storage unit for storage.

[0092] Furthermore, the PMC triggering the power management system to enter the isolation enabled state includes: the PMC entering the open isolation enabled state, and the PMC triggering the power management system to enter the isolation enabled state based on the open isolation enabled state.

[0093] Specifically, when performing CPU memory storage, the PMC in the power management system generates a CPU memory storage instruction and then sends the CPU memory storage instruction to the CPU memory control unit. By controlling the CPU memory storage instruction to be sent to the CPU memory control unit to perform read and write processing on the CPU memory operation, the storage of the CPU memory operation can be realized.

[0094] That is, the CPU memory control unit reads the corresponding CPU memory operation in the CPU according to the CPU memory storage instruction, and writes the read CPU memory operation into the CPU memory static storage unit for storage; it should be noted that during this process, the PMC will control the flash to enter a low power mode, which requires controlling the flash control signal in different power modes to prepare it to enter the standby state.

[0095] Then the PMC enters the isolation enabled state, and the PMC triggers the power management system to enter the isolation enabled state based on the isolation enabled state.

[0096] S25: If the CPU memory storage is not performed, the PMC triggers the power management system to enter the isolation enable state;

[0097] In a specific implementation of the present invention, the PMC triggers the power management system to enter the isolation enabled state, including: the PMC entering the open isolation enabled state, and the PMC triggering the power management system to enter the isolation enabled state based on the open isolation enabled state.

[0098] When CPU memory storage is not required, the PMC enters the open isolation enable state, and the PMC triggers the power management system to enter the isolation enable state based on the open isolation enable state.

[0099] S26: After the power management system enters the isolation enable state, the power management system and the PMC enter the standby state.

[0100] In a specific implementation of the present invention, the power management system and the PMC enter a standby state, including: after the power management system and the PMC enter an isolation enable state, the PMC simultaneously enters a power down phase, and after the power down is completed, the power management system and the PMC enter a standby state.

[0101] Specifically, after the power management system and PMC enter the isolation enable state, the PMC simultaneously enters the power down phase, and after the power down is completed, both the power management system and PMC enter the standby state.

[0102] In this embodiment of the invention, after the PMC receives a deep sleep command, it controls the CPU to remain in a non-executing state by using the CPU hold sleep signal; then it determines whether the CPU needs to support CPU-based storage, and if so, performs corresponding read and write operations on the CPU memory, and triggers the power management system to enter the isolation enable state after completion; then it controls the power management system and the PMC to enter the standby state, which allows the power management system and the PMC to enter the standby state in an orderly manner, which facilitates the state synchronization when restoring to the normal operating state in the standby state.

[0103] Example 3

[0104] Please see Figure 4 , Figure 4 This is a flowchart illustrating the PMC mode state switching method under the power management system in the third embodiment of the present invention.

[0105] like Figure 4 As shown, a PMC mode state switching method under a power management system includes:

[0106] S31: When the PMC is running in normal operation, the state of the PMC is switched from normal operation to PMC waiting for the CPU to be controlled by the PMC and enter a non-execution state based on the deep sleep instruction;

[0107] In a specific implementation of this invention, the step of switching the state of the PMC from normal operation to PMC waiting for the CPU to be controlled by the PMC to enter a hold-not-execute state based on a deep sleep instruction includes: after receiving a deep sleep instruction issued by the CPU, the PMC generates a CPU hold-sleep signal for controlling the CPU to remain in a hold-not-execute state and sends the CPU hold-sleep signal to the CPU; after sending the CPU hold-sleep signal to the CPU, the state of the PMC switches from normal operation to PMC waiting for the CPU to be controlled by the PMC to enter a hold-not-execute state.

[0108] Furthermore, the CPU hold sleep signal is a low active signal; the CPU hold sleep signal is used to control the CPU to enter a state of holding and not executing instructions.

[0109] Furthermore, sending the CPU hold sleep signal to the CPU also includes:

[0110] During the process of the CPU hold sleep signal entering standby state, if the PMC receives a wakeup signal sent by the wake-up source, it will set the CPU hold sleep signal to an invalid signal.

[0111] Specifically, when the PMC is operating normally, it receives a deep sleep instruction (deep sleep signal) from the CPU and requests the power management system to enter standby mode. After receiving the deep sleep instruction from the CPU, and with standby enable active in application operation, the PMC first generates a CPU hold sleep signal to control the CPU to remain in a non-executing state, and then sends the CPU hold sleep signal to the CPU. After sending the CPU hold sleep signal to the CPU, the state of the PMC will switch from normal operation to PMC waiting for the CPU to enter a hold-to-non-executing state under the control of the PMC.

[0112] The CPU hold sleep signal is a low-active signal. It is a signal that holds the CPU in place and prevents it from executing instructions. This signal is generated by the PMC and sent to the CPU. After the CPU receives the CPU hold sleep signal, it holds the CPU in place. When the PMC receives a wakeup signal from the wakeup source during the process of entering the standby state, it will set the CPU hold sleep signal to an invalid signal on the second clock cycle.

[0113] S32: When the PMC is waiting for the CPU to be controlled by the PMC to enter a hold-non-execution state, the power management system determines whether the CPU needs to support CPU memory storage.

[0114] In a specific implementation of the present invention, the power management system determines whether the CPU needs to perform CPU memory storage, including: after the PMC receives the hold sleep ack signal fed back by the CPU, the power management system determines whether the CPU needs to perform CPU memory storage based on whether a CPU save operation is enabled; wherein, if a CPU save operation is enabled, it is determined that the CPU needs to perform CPU memory storage; if a CPU save operation is not enabled, it is determined that the CPU does not need to perform CPU memory storage.

[0115] Specifically, when the PMC is waiting for the CPU to enter a hold-sleep state under PMC control, the power management system needs to determine whether the CPU needs to support CPU memory storage. Specifically, after the CPU holds, a hold sleepack signal is generated and fed back to the PMC. After the PMC receives the hold sleepack signal from the CPU, the power management system determines whether the CPU needs to perform CPU memory storage by checking if CPU save operation is enabled. That is, if CPU save operation is enabled, it is determined that the CPU needs to perform CPU memory storage; if CPU save operation is not enabled, it is determined that the CPU does not need to perform CPU memory storage.

[0116] The hold sleep ack signal is a low-active signal. It is an acknowledgment signal generated by the CPU and sent to the PMC after the CPU hold sleep signal is received. The hold sleep ack signal becomes invalid after the second clock cycle after the CPU hold sleep signal becomes invalid.

[0117] S33: When performing the CPU memory storage, the PMC in the power management system generates a CPU memory storage instruction and sends the CPU memory storage instruction to the CPU memory control unit;

[0118] In the specific implementation of this invention, when CPU memory storage is required, the PMC in the power management system will generate a CPU memory storage instruction and send the CPU memory storage instruction to the CPU memory control unit.

[0119] S34: The CPU memory control unit performs CPU memory operation read and write processing based on the CPU memory storage instructions, and after completing the CPU memory operation read and write, the PMC triggers the power management system to enter the isolation enable state;

[0120] In the specific implementation of this invention, after receiving the CPU memory storage instruction, the CPU memory control unit reads the corresponding CPU memory operation from the CPU according to the instruction and writes the read CPU memory operation into the CPU memory static storage unit for storage. It should be noted that during this process, the PMC controls the flash to enter a low-power mode, which requires controlling the flash control signal in different power modes to prepare it to enter the standby state. In this embodiment, by storing the CPU memory operation, when the power management system wakes up the CPU, it can read the CPU memory operation stored in the CPU memory static storage unit, enabling the CPU to quickly return to its original operating state.

[0121] Then the PMC enters the isolation enabled state, and the PMC triggers the power management system to enter the isolation enabled state based on the isolation enabled state.

[0122] S35: If the CPU memory storage is not performed, the PMC triggers the power management system to enter the isolation enable state;

[0123] In a specific implementation of the present invention, the PMC triggers the power management system to enter the isolation enabled state, including: the PMC entering the open isolation enabled state, and the PMC triggering the power management system to enter the isolation enabled state based on the open isolation enabled state.

[0124] When CPU memory storage is not required, the PMC enters the open isolation enable state, and the PMC triggers the power management system to enter the isolation enable state based on the open isolation enable state.

[0125] S36 After the power management system enters the isolation enable state, the power management system and the PMC enter the standby state.

[0126] In a specific implementation of the present invention, the power management system and the PMC enter a standby state, including: after the power management system and the PMC enter an isolation enable state, the PMC simultaneously enters a power down phase, and after the power down is completed, the power management system and the PMC enter a standby state.

[0127] Specifically, after the power management system and PMC enter the isolation enable state, the PMC simultaneously enters the power down phase, and after the power down is completed, both the power management system and PMC enter the standby state.

[0128] In this embodiment of the invention, after the PMC receives a deep sleep command, it controls the CPU to remain in a non-executing state by using the CPU hold sleep signal; then it determines whether the CPU needs to support CPU-based storage, and if so, performs corresponding read and write operations on the CPU memory, and triggers the power management system to enter the isolation enable state after completion; then it controls the power management system and the PMC to enter the standby state, which allows the power management system and the PMC to enter the standby state in an orderly manner, which facilitates the state synchronization when restoring to the normal operating state in the standby state.

[0129] Example 4

[0130] Please see Figure 5 , Figure 5 This is a flowchart illustrating the PMC mode state switching method under the power management system in the fourth embodiment of the present invention.

[0131] like Figure 5 As shown, a PMC mode state switching method under a power management system includes:

[0132] S41: When the PMC is running in normal operation, after the PMC receives a deep sleep instruction from the CPU, the PMC generates a CPU hold sleep signal to control the CPU to remain in a non-executing state and sends the CPU hold sleep signal to the CPU.

[0133] S42: After sending the CPU hold sleep signal to the CPU, the state of the PMC changes from normal operation to PMC waiting for the CPU to be controlled by the PMC to enter a hold-not-execute state;

[0134] S43: When the PMC is waiting for the CPU to be controlled by the PMC to enter a hold-non-execution state, the power management system determines whether the CPU needs to support CPU memory storage.

[0135] S44: When performing the CPU memory storage, the PMC in the power management system generates a CPU memory storage instruction and sends the CPU memory storage instruction to the CPU memory control unit;

[0136] S45: The CPU memory control unit performs CPU memory operation read and write processing based on the CPU memory storage instructions; and after completing the CPU memory operation read and write, the PMC triggers the power management system to enter the isolation enable state;

[0137] S46: If the CPU memory storage is not performed, the PMC triggers the power management system to enter the isolation enable state;

[0138] S47 After the power management system enters the isolation enable state, the power management system and the PMC enter the standby state.

[0139] In the embodiments of the present invention, the specific implementation methods can be referred to the above embodiments, and will not be repeated here.

[0140] In this embodiment of the invention, after the PMC receives a deep sleep command, it controls the CPU to remain in a non-executing state by using the CPU hold sleep signal; then it determines whether the CPU needs to support CPU-based storage, and if so, performs corresponding read and write operations on the CPU memory, and triggers the power management system to enter the isolation enable state after completion; then it controls the power management system and the PMC to enter the standby state, which allows the power management system and the PMC to enter the standby state in an orderly manner, which facilitates the state synchronization when restoring to the normal operating state in the standby state.

[0141] Example 5

[0142] Please see Figure 6 , Figure 6 This is a schematic diagram of the structural composition of the PMC mode state switching device under the power management system in an embodiment of the present invention.

[0143] like Figure 6 As shown, a PMC mode state switching device under a power management system includes:

[0144] State switching module 51: When the PMC is running in normal operation, it switches the state of the PMC from normal operation to PMC waiting for the CPU to be controlled by the PMC to enter a non-execution state based on a deep sleep instruction;

[0145] In a specific implementation of this invention, the step of switching the state of the PMC from normal operation to PMC waiting for the CPU to be controlled by the PMC to enter a hold-not-execute state based on a deep sleep instruction includes: after receiving a deep sleep instruction issued by the CPU, the PMC generates a CPU hold-sleep signal for controlling the CPU to remain in a hold-not-execute state and sends the CPU hold-sleep signal to the CPU; after sending the CPU hold-sleep signal to the CPU, the state of the PMC switches from normal operation to PMC waiting for the CPU to be controlled by the PMC to enter a hold-not-execute state.

[0146] Furthermore, the CPU hold sleep signal is a low active signal; the CPU hold sleep signal is used to control the CPU to enter a state of holding and not executing instructions.

[0147] Furthermore, sending the CPU hold sleep signal to the CPU also includes:

[0148] During the process of the CPU hold sleep signal entering standby state, if the PMC receives a wakeup signal sent by the wake-up source, it will set the CPU hold sleep signal to an invalid signal.

[0149] Specifically, when the PMC is operating normally, it receives a deep sleep instruction (deep sleep signal) from the CPU and requests the power management system to enter standby mode. After receiving the deep sleep instruction from the CPU, and with standby enable active in application operation, the PMC first generates a CPU hold sleep signal to control the CPU to remain in a non-executing state, and then sends the CPU hold sleep signal to the CPU. After sending the CPU hold sleep signal to the CPU, the state of the PMC will switch from normal operation to PMC waiting for the CPU to enter a hold-to-non-executing state under the control of the PMC.

[0150] The CPU hold sleep signal is a low-active signal. It is a signal that holds the CPU in place and prevents it from executing instructions. This signal is generated by the PMC and sent to the CPU. After the CPU receives the CPU hold sleep signal, it holds the CPU in place. When the PMC receives a wakeup signal from the wakeup source during the process of entering the standby state, it will set the CPU hold sleep signal to an invalid signal on the second clock cycle.

[0151] Judgment module 52: Used to determine whether the CPU needs to support CPU memory storage when the PMC is waiting for the CPU to be controlled by the PMC to enter the hold-non-execution state;

[0152] In a specific implementation of the present invention, the power management system determines whether the CPU needs to perform CPU memory storage, including: after the PMC receives the hold sleep ack signal fed back by the CPU, the power management system determines whether the CPU needs to perform CPU memory storage based on whether a CPU save operation is enabled; wherein, if a CPU save operation is enabled, it is determined that the CPU needs to perform CPU memory storage; if a CPU save operation is not enabled, it is determined that the CPU does not need to perform CPU memory storage.

[0153] Specifically, when the PMC is waiting for the CPU to enter a hold-sleep state under PMC control, the power management system needs to determine whether the CPU needs to support CPU memory storage. Specifically, after the CPU holds, a hold sleepack signal is generated and fed back to the PMC. After the PMC receives the hold sleepack signal from the CPU, the power management system determines whether the CPU needs to perform CPU memory storage by checking if CPU save operation is enabled. That is, if CPU save operation is enabled, it is determined that the CPU needs to perform CPU memory storage; if CPU save operation is not enabled, it is determined that the CPU does not need to perform CPU memory storage.

[0154] The hold sleep ack signal is a low-active signal. It is an acknowledgment signal generated by the CPU and sent to the PMC after the CPU hold sleep signal is received. The hold sleep ack signal becomes invalid after the second clock cycle after the CPU hold sleep signal becomes invalid.

[0155] Read / write module 53: When the CPU memory is stored, the power management system enters the CPU memory read / write operation processing, and after the CPU memory read / write operation is completed, the PMC triggers the power management system to enter the isolation enable state.

[0156] In a specific implementation of the present invention, the power management system enters the CPU memory read / write operation process, including: the PMC in the power management system generates a CPU memory storage instruction and sends the CPU memory storage instruction to the CPU memory control unit; the CPU memory control unit performs CPU memory read / write operation based on the CPU memory storage instruction.

[0157] Furthermore, the CPU memory control unit performs CPU memory operation read and write processing based on the CPU memory storage instructions, including: the CPU memory control unit reads the corresponding CPU memory operation in the CPU according to the CPU memory storage instructions, and writes the read CPU memory operation into the CPU memory static storage unit for storage.

[0158] Furthermore, the PMC triggering the power management system to enter the isolation enabled state includes: the PMC entering the open isolation enabled state, and the PMC triggering the power management system to enter the isolation enabled state based on the open isolation enabled state.

[0159] Specifically, when performing CPU memory storage, the PMC in the power management system generates a CPU memory storage instruction and then sends the CPU memory storage instruction to the CPU memory control unit. By controlling the CPU memory storage instruction to be sent to the CPU memory control unit to perform read and write processing on the CPU memory operation, the storage of the CPU memory operation can be realized.

[0160] That is, the CPU memory control unit reads the corresponding CPU memory operation in the CPU according to the CPU memory storage instruction, and writes the read CPU memory operation into the CPU memory static storage unit for storage; it should be noted that during this process, the PMC will control the flash to enter a low power mode, which requires controlling the flash control signal in different power modes to prepare it to enter the standby state.

[0161] Then the PMC enters the isolation enabled state, and the PMC triggers the power management system to enter the isolation enabled state based on the isolation enabled state.

[0162] Trigger module 54: If the CPU memory storage is not performed, the PMC triggers the power management system to enter the isolation enable state;

[0163] In a specific implementation of the present invention, the PMC triggers the power management system to enter the isolation enabled state, including: the PMC entering the open isolation enabled state, and the PMC triggering the power management system to enter the isolation enabled state based on the open isolation enabled state.

[0164] When CPU memory storage is not required, the PMC enters the open isolation enable state, and the PMC triggers the power management system to enter the isolation enable state based on the open isolation enable state.

[0165] Standby module 55: Used to enable the power management system and the PMC to enter standby mode after the power management system enters the isolation enable state.

[0166] In a specific implementation of the present invention, the power management system and the PMC enter a standby state, including: after the power management system and the PMC enter an isolation enable state, the PMC simultaneously enters a power down phase, and after the power down is completed, the power management system and the PMC enter a standby state.

[0167] In this embodiment of the invention, after the PMC receives a deep sleep command, it controls the CPU to remain in a non-executing state by using the CPU hold sleep signal; then it determines whether the CPU needs to support CPU-based storage, and if so, performs corresponding read and write operations on the CPU memory, and triggers the power management system to enter the isolation enable state after completion; then it controls the power management system and the PMC to enter the standby state, which allows the power management system and the PMC to enter the standby state in an orderly manner, which facilitates the state synchronization when restoring to the normal operating state in the standby state.

[0168] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0169] Furthermore, the above provides a detailed description of the PMC mode state switching method and apparatus under a power management system provided by the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for switching states in PMC mode under a power management system, characterized in that, The method includes: When the PMC is running in normal operation, the state of the PMC is switched from normal operation to PMC waiting for the CPU to be controlled by the PMC and enter a non-execution state based on the deep sleep instruction. While the PMC is waiting for the CPU to be controlled by the PMC to enter a hold-non-execution state, the power management system determines whether the CPU needs to support CPU memory storage. When the CPU memory is stored, the power management system enters the CPU memory read / write operation process, and after the CPU memory read / write operation is completed, the PMC triggers the power management system to enter the isolation enable state. If the CPU memory storage is not performed, the PMC triggers the power management system to enter the isolation enable state; After the power management system enters the isolation enabled state, the power management system and the PMC enter the standby state.

2. The PMC mode state switching method according to claim 1, characterized in that, The step of switching the PMC's state from normal operation to a state where the PMC waits for the CPU to be controlled by the PMC and remains inactive, based on the deep sleep command, includes: After receiving a deep sleep command from the CPU, the PMC generates a CPU hold sleep signal to control the CPU to remain in a non-executing state, and sends the CPU hold sleep signal to the CPU. After the CPU hold sleep signal is sent to the CPU, the state of the PMC changes from normal operation to PMC waiting for the CPU to be controlled by the PMC to enter a hold-not-execute state.

3. The PMC mode state switching method according to claim 2, characterized in that, The CPU hold sleep signal is a low active signal; the CPU hold sleep signal is used to control the CPU to enter a state of holding and not executing instructions.

4. The PMC mode state switching method according to claim 2, characterized in that, Sending the CPU holdsleep signal to the CPU further includes: During the process of the CPU hold sleep signal entering standby state, if the PMC receives a wakeup signal sent by the wake-up source, it will set the CPU hold sleep signal to an invalid signal.

5. The PMC mode state switching method according to claim 1, characterized in that, The power management system determines whether the CPU needs to perform CPU memory storage, including: After the PMC receives the hold sleep ack signal from the CPU, the power management system determines whether the CPU needs to perform CPU memory storage based on whether a CPU save operation is enabled. If CPU save operation is enabled, it is determined that the CPU needs to perform CPU memory storage; if CPU save operation is not enabled, it is determined that the CPU does not need to perform CPU memory storage.

6. The PMC mode state switching method according to claim 1, characterized in that, The power management system enters the CPU memory read / write operation processing, including: The PMC in the power management system generates CPU memory storage instructions and sends the CPU memory storage instructions to the CPU memory control unit; The CPU memory control unit performs CPU memory operation read and write processing based on the CPU memory storage instructions.

7. The PMC mode state switching method according to claim 6, characterized in that, The CPU memory control unit performs CPU memory operation read and write processing based on the CPU memory storage instructions, including: The CPU memory control unit reads the corresponding CPU memory operation from the CPU according to the CPU memory storage instruction, and writes the read CPU memory operation into the CPU memory static storage unit for storage.

8. The PMC mode state switching method according to claim 1, characterized in that, The PMC triggers the power management system to enter the isolation enable state, including: The PMC enters the open isolation enable state, and the PMC triggers the power management system to enter the isolation enable state based on the open isolation enable state.

9. The PMC mode state switching method according to claim 1, characterized in that, The power management system and the PMC enter standby mode, including: After the power management system and the PMC enter the isolation enable state, the PMC simultaneously enters the power down phase, and after the power down is completed, the power management system and the PMC enter the standby state.

10. A PMC mode state switching device under a power management system, characterized in that, The device includes: State switching module: used to switch the state of PMC from normal operation to PMC waiting for CPU to be controlled by PMC and enter a non-execution state when PMC is running in normal operation state based on deep sleep command; Judgment module: Used by the power management system to determine whether the CPU needs to support CPU memory storage when the PMC is waiting for the CPU to be controlled by the PMC to enter a hold-non-execution state; Read / write module: When the CPU memory is being stored, the power management system enters the read / write CPU memory operation process, and after the read / write operation of the CPU memory is completed, the PMC triggers the power management system to enter the isolation enable state; Trigger module: Used to trigger the power management system to enter the isolation enable state if the CPU memory storage is not performed; Standby module: Used to enable the power management system and the PMC to enter standby mode after the power management system enters the isolation enable state.

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