A configuration method of independent graphics card display memory interface based on configuration data packet
By converting the video memory interface configuration into a register operation stream and encapsulating it into a configuration block package, the problem of too many versions of the graphics card VBIOS program and driver inconsistency is solved. This achieves unified management and flexible interface switching of the graphics card VBIOS and driver, and simplifies firmware data maintenance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN LINGJIU MICROELECTRONICS CO LTD
- Filing Date
- 2022-11-08
- Publication Date
- 2026-07-21
AI Technical Summary
There are too many versions of the existing graphics card VBIOS program. The graphics card VBIOS program and the graphics card driver have inconsistencies in the memory interface driver. In addition, the graphics card VBIOS program is large and easily exceeds the storage capacity limit, making it difficult to manage and maintain.
The process of configuring the video memory interface is transformed into a register operation stream, which is then segmented and encapsulated into configuration block packets and stored in the graphics card memory. The graphics card VBIOS program and driver complete the configuration and driver by reading the configuration data packet and parsing the register operation stream.
It simplifies the video memory interface driver method, realizes unified management of graphics card VBIOS program and driver, reduces the complexity of firmware data maintenance, and supports flexible switching of multiple video memory interface types and bandwidth modes.
Smart Images
Figure CN115686653B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of graphics card technology, and in particular relates to a method for configuring the independent graphics card memory interface based on a configuration data package. Background Technology
[0002] With the rapid development of graphics card technology, graphics card processing performance is increasing, and the bandwidth requirements of graphics card chips for memory interfaces are also rising. Simultaneously, the types of memory interfaces have become more diverse. Some GPU chips support multiple SDRAM types, such as DDR3, DDR4, LPDDR3, and LPDDR4, and each SDRAM type supports multiple bandwidth modes. For example, the DDR4 interface supports bandwidth modes such as 3200Mbps, 2666Mbps, 2400Mbps, and 1600Mbps. Even for graphics cards using the same GPU chip, due to differences in memory chips and circuitry, the bandwidth modes of the memory interfaces often differ.
[0003] To address the diversity of GPU memory interface types and operating bandwidth modes, a custom VBIOS program is typically created for each interface type and bandwidth mode. The graphics card driver then selects different driver branches based on the card's configuration information to drive the memory interface. However, because memory interface drivers are inherently complex, and the firmware for the memory interface processing core is also large, directly using program code to drive the memory interface in both the VBIOS and driver versions would result in an excessively large VBIOS program. Furthermore, this would be highly incompatible with the diversity of memory interface types and bandwidth modes, inevitably leading to numerous VBIOS and driver versions, which is detrimental to software version management and maintenance.
[0004] Therefore, based on practical experience, the existing methods of driving the video memory interface through different VBIOS programs have at least the following technical problems:
[0005] 1. Due to differences in video memory interface hardware, there are too many versions of the graphics card VBIOS program, which is not conducive to the management and maintenance of the graphics card VBIOS program;
[0006] 2. The graphics card VBIOS program and the graphics card driver configure the video memory interface separately, which can easily lead to inconsistencies in their working states when driving the video memory interface.
[0007] 3. Because the driver for the video memory interface is complex, the graphics card VBIOS program is also large. However, the storage capacity of the graphics card VBIOS is limited. The size of the graphics card VBIOS program may exceed the design capacity limit of the VBIOS, causing the VBIOS program to fail to run properly. It is also not conducive to the coexistence of VBIOS programs of various architectures. Summary of the Invention
[0008] In view of the above problems, the purpose of this invention is to provide a method for configuring the independent graphics card memory interface based on configuration data packages, which aims to solve the technical problems of existing methods being difficult to maintain, difficult to manage, and potentially insufficient capacity resources.
[0009] The present invention adopts the following technical solution:
[0010] The method for configuring the discrete graphics card memory interface based on the configuration data package includes the following steps:
[0011] Step S1: Convert the dedicated graphics card's memory interface configuration process into a sequential register operation stream;
[0012] Step S2: Segment the register operation stream according to address change characteristics and encapsulate it into configuration block packets;
[0013] Step S3: According to the original execution order of the configuration block packets, combine the configuration block packets into a video memory interface configuration data packet and store it in the graphics card memory;
[0014] Step S4: When initializing the video memory interface, the graphics card VBIOS program or driver first reads the video memory interface configuration data packet and parses out the video memory interface register operation stream. The configuration and driver of the video memory interface are completed by executing the register operation stream.
[0015] Furthermore, in step S1, the register operations include register write operations, register read operations, and register value verification operations; the register operation flow is a sequence of register operations executed sequentially; and the operation type of the register is identified by several redundant address bits of the highest bit of the register.
[0016] The register value verification operation is as follows: read the register value and determine whether the register value is consistent with the expected value. If they are inconsistent, wait for a period of time and then read the register value again and compare it with the expected value until the read register value is consistent with the expected value and return success. If the timeout number is reached and it is still unsuccessful, return failure.
[0017] Furthermore, in step S2, the register operation flow is divided into two types based on address change characteristics: sequential register operations and random register operations. The specific process of step S2 is as follows:
[0018] S21. When the number of consecutive sequential register operations of the same type reaches a set threshold, these consecutive sequential register operations are divided into a sequential register operation segment, and each random register operation between sequential register operation segments is divided into a random register operation segment.
[0019] S22. Encapsulate the sequential register operation segment and the random register operation segment into corresponding sequential configuration block packets and random configuration block packets, wherein the sequential configuration block packets record the starting address, address step size, and register value information of the sequential register operation segment; and the random configuration block packets record the address and register value information of each random register operation.
[0020] Furthermore, the first byte of the configuration block packet is an identifier character used to indicate whether the configuration block packet exists; in step S3, the configuration block packets are stored sequentially according to the original execution order of the configuration block packets to form a video memory interface configuration data packet, which is then stored in the graphics card memory.
[0021] Furthermore, in step S3, the graphics card memory stores various graphics memory interface configuration data packets. Step S3 also includes setting the graphics card onboard configuration information, which stores the offset address of each graphics memory interface configuration data packet.
[0022] The beneficial effects of this invention are as follows: This invention transforms the configuration process of the discrete graphics card's memory interface into a register operation stream, encapsulates it into a configuration block packet, and then combines it into a configuration data packet, which is stored in the graphics card's memory. The graphics card VBIOS program and graphics card driver read the memory interface configuration data packet from the graphics card memory, parse it into a memory interface configuration stream, and complete the configuration of the memory interface by executing the register operation stream. This invention transforms the discrete graphics card's memory interface configuration method into a configuration data packet. The graphics card VBIOS program and driver can implement complex memory interface drivers by loading the configuration data packet, which is beneficial for the maintenance and management of the VBIOS program and graphics card driver, and also helps to ensure a unified memory interface driver process. Through the combination of onboard configuration information and various configuration data packets, the switching of the memory interface working bandwidth mode can also be flexibly realized on the same graphics card. Attached Figure Description
[0023] Figure 1 This is a flowchart of a method for configuring a dedicated graphics card memory interface based on a configuration data package, provided in an embodiment of the present invention.
[0024] Figure 2 This is a schematic diagram of the storage space allocation of the graphics card memory provided in an embodiment of the present invention;
[0025] Figure 3 This is a schematic diagram of the region division of the graphics card memory provided in an embodiment of the present invention;
[0026] Figure 4 This is a flowchart illustrating a specific step S4 in an embodiment of the present invention. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0028] This invention first transforms the configuration process of a discrete graphics card's memory interface into a register operation stream. Then, based on the characteristics of the register operation stream, it is segmented, such as into sequential register operation segments with increasing register addresses and random register operation segments with randomly changing register addresses. Next, the segmented register operation streams are encapsulated into configuration block packets with added header information. Finally, these configuration block packets are combined into a complete memory interface configuration data packet and stored in the graphics card's internal memory. Thus, the graphics card's VBIOS program or driver can read the complete configuration data packet, parse it into a register operation stream, and load the register operation stream to drive the memory interface. This invention simplifies the driving method for discrete graphics card memory interfaces, and when it is necessary to change the discrete graphics card's memory interface type or operating bandwidth mode, only the content of the configuration data packet needs to be updated, without modifying the graphics card's VBIOS program or driver.
[0029] To illustrate the technical solution described in this invention, specific embodiments are described below.
[0030] Figure 1 The flowchart of the discrete graphics card memory interface configuration method based on configuration data package provided by the embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown.
[0031] like Figure 1 As shown, the discrete graphics card memory interface configuration method based on configuration data packets provided in this embodiment includes the following process:
[0032] Step S1: Convert the configuration process of the discrete graphics card's memory interface into a sequential register operation stream.
[0033] Since the configuration process of the video memory interface is a combination of register write, register read, and register verification processes, this step converts the video memory interface configuration process into a sequentially executed register operation flow. Register operations include register write operations, register read operations, and register value verification operations; the register operation flow is a sequence of register operations executed in sequence.
[0034] The register value verification operation is as follows: read the register value and determine whether the register value is consistent with the expected value. If they are inconsistent, wait for a short period of time and then read the register value again and compare it with the expected value. This process can be repeated multiple times until the read register value is consistent with the expected value and a success is returned. If the timeout number is reached and the operation is still unsuccessful, a failure is returned.
[0035] Typically, several redundant address bits in the highest-order bits of a register are used to identify the register operation type. For example, in a system with fewer than 30 register offset address bits, address bits 31 and 30 can be defined as binary 00 to indicate a register write operation, 01 to indicate a register read operation, and 10 to indicate a register check operation. Therefore, this step can encode the operation type codes of the write, read, and check operations of the video memory interface controller's registers into the redundant high bits of the register offset address to save storage space for the register operation stream.
[0036] Step S2: Segment the register operation stream according to the address change characteristics and encapsulate it into a configuration block packet.
[0037] Register operation flow based on address change characteristics mainly refers to two characteristics: sequential register operations and random register operations.
[0038] The specific process of step S2 is as follows:
[0039] S21. When the number of consecutive sequential register operations of the same type reaches a set threshold, these consecutive sequential register operations are divided into a sequential register operation segment, and each random register operation between sequential register operation segments is divided into a random register operation segment.
[0040] S22. Encapsulate the sequential register operation segment and the random register operation segment into corresponding sequential configuration block packets and random configuration block packets, wherein the sequential configuration block packets record the starting address, address step size, and register value information of the sequential register operation segment; and the random configuration block packets record the address and register value information of each random register operation.
[0041] The header information of a configuration block packet typically includes packet type, register data bit width, number of registers configured, starting register address of the sequential register operation segment, CRC checksum, etc.
[0042] For the encapsulation of sequential register operation segments, since the register addresses are contiguous, only the starting register address of the operation segment needs to be recorded, and the body of the configuration block packet is used to store the register values. However, for some special sequential register operation segments, when their contents may be contained in multiple configuration block packets, in order to save data storage space, the register values of the operation segment will be stored sequentially in fixed locations. The configuration block packet type is a special reference type packet, and the packet body only includes the starting position information of the register segment data and the number of registers.
[0043] In this embodiment, the configuration block packet is stored in the graphics card's SPIFlash. For all DDR4 type graphics memory interfaces, the data for the one-dimensional and two-dimensional training programs is the same, and therefore is stored separately in 32KB areas starting at 0x10000 and 0x18000 respectively, for reference by the register configuration block packet.
[0044] Step S3: Following the original execution order of the configuration block packets, assemble the configuration block packets into a video memory interface configuration data packet and store it in the graphics card memory. Graphics card memory typically refers to non-volatile memory such as SPI Flash, NOR Flash, NAND Flash, and EEPROM.
[0045] In this embodiment, as Figure 2 As shown, a configuration data packet consisting of N configuration block packets is stored in the graphics card memory. Configuration block packets typically use a 2-byte alignment mode; 2 bytes can represent the value of a 16-bit register, and two 2-byte blocks can represent the value or address of a 32-bit register. The first byte of the configuration block packet is an identifier character, such as hexadecimal 0xA5, used to indicate whether the configuration block packet exists. If the graphics memory interface configuration data packet has no subsequent configuration block packets, it indicates that the graphics memory interface configuration data packet has ended.
[0046] In one implementation, the configuration data packet with a bandwidth of 3200Mbps is stored in the region starting at the SPIFlash offset address 0x28000, the configuration data packet with a bandwidth of 2666Mbps is stored in the region starting at the SPIFlash offset address 0x30000, and the configuration data packet with a bandwidth of 2400Mbps is stored in the region starting at the SPIFlash offset address 0x38000.
[0047] Taking the DDR4 memory interface type with a 3200Mbps memory bandwidth mode as an example, Figure 3 As shown. Assume that random register configuration block packet 1, sequential register configuration block packet 1, random register configuration block packet 2, sequential register configuration block packet 2, and random register configuration block packet 3 are generated.
[0048] For Random Register Configuration Block Packet 1, the first byte of the configuration block packet is hexadecimal 0xA5, the second byte is hexadecimal packet type code 0x01, indicating a random register configuration block packet. The combination of the third and fourth bytes indicates that the total number of bytes in the configuration block packet is 3336 bytes. The combination of the fifth and sixth bytes is 32, indicating that the register bit width is 32 bits. The combination of the seventh and eighth bytes is hexadecimal 0xD5B9, which is the CRC checksum of the data area of this configuration block packet. The data area of this configuration block packet is from the ninth byte to the end of the packet. Each register operation contains a data item consisting of a 32-bit register address and a 32-bit register value. For registers that require verification operations, the 31st bit of the register address is set to 1.
[0049] For Sequential Register Configuration Block Packet 1: The first byte of this configuration block packet is hexadecimal 0xA5, the second byte is hexadecimal packet type code 0x02, indicating a reference-type sequential register configuration block packet, the combination of the third and fourth bytes indicates that the total number of bytes in this configuration block packet is 16 bytes, the combination of the fifth and sixth bytes is 16, indicating that the register bit width is 16 bits, the combination of the seventh and eighth bytes is hexadecimal 0xFFEA, which is the CRC checksum of the data area of this configuration block packet, the ninth, tenth, eleventh, and twelfth bytes represent the starting address of the sequential register 0x00140000, and the combination of the thirteenth, fourteenth, fifteenth, and sixteenth bytes is 0x10000, indicating that the starting offset address of the reference register value data in the SPIFlash is 0x10000;
[0050] For Random Register Configuration Block Packet 2: The first byte of this configuration block packet is hexadecimal 0xA5, the second byte is hexadecimal packet type code 0x01, indicating a random register configuration block packet, the combination of the third and fourth bytes indicates that the total number of bytes in this configuration block packet is 7472 bytes, the combination of the fifth and sixth bytes is 32, indicating that the register bit width is 32 bits, the combination of the seventh and eighth bytes is hexadecimal 0x1670, which is the CRC checksum of the data area of this configuration block packet, and the data area of this configuration block packet is from the ninth byte to the end of the packet. Each register operation contains a data item consisting of a 32-bit register address and a 32-bit register value. For registers that require verification operations, the 31st bit of the register address is set to 1.
[0051] For Sequential Register Configuration Block Packet 2: The first byte of this configuration block packet is hexadecimal 0xA5, the second byte is hexadecimal packet type code 0x02, indicating a reference-type sequential register configuration block packet, the combination of the third and fourth bytes indicates that the total number of bytes in this configuration block packet is 16 bytes, the combination of the fifth and sixth bytes is 16, indicating that the register bit width is 16 bits, the combination of the seventh and eighth bytes is hexadecimal 0x7FEA, which is the CRC checksum of the data area of this configuration block packet, the ninth, tenth, eleventh, and twelfth bytes represent the starting address of the sequential register 0x00140000, and the combination of the thirteenth, fourteenth, fifteenth, and sixteenth bytes is 0x18000, indicating that the starting offset address of the reference register value data in SPIFlash is 0x18000;
[0052] For Random Register Configuration Block Packet 3: The first byte of this configuration block packet is hexadecimal 0xA5, the second byte is hexadecimal packet type code 0x01, indicating a random register configuration block packet. The combination of the third and fourth bytes indicates that the total number of bytes in this configuration block packet is 7936 bytes. The combination of the fifth and sixth bytes is 32, indicating that the register bit width is 32 bits. The combination of the seventh and eighth bytes is hexadecimal 0xF539, which is the CRC checksum of the data area of this configuration block packet. The data area of this configuration block packet is from the ninth byte to the end of the packet. Each register operation contains a data item consisting of a 32-bit register address and a 32-bit register value. For registers that require verification operations, the 31st bit of the register address is set to 1.
[0053] Step S4: When initializing the video memory interface, the graphics card VBIOS program or driver first reads the video memory interface configuration data packet and parses out the video memory interface register operation stream. The configuration and driver of the video memory interface are completed by executing the register operation stream.
[0054] In this embodiment, the graphics card memory stores a variety of video memory interface configuration data packets. Step S3 also includes setting the graphics card onboard configuration information, which stores the offset addresses of each video memory interface configuration data packet. Figure 3 The graphics card memory stores configuration data packages for three DDR4 operating modes with different bandwidths. Switching between these modes can be achieved by configuring the onboard configuration information. During operation, simply adjusting the offset address of the memory interface configuration package in the graphics card's onboard configuration information is sufficient to switch the memory interface configuration, enabling support for different memory chips. This eliminates the need to update the data in the configuration data package area, further reducing the complexity of firmware data maintenance.
[0055] Figure 4 The specific process for this step is shown in the figure below:
[0056] First, the onboard configuration information of the graphics card is read. Based on the type of configuration data packet, the offset address of the corresponding memory interface configuration data packet is obtained from the onboard configuration information. The corresponding memory interface configuration data packet is then read from the graphics card memory using this offset address. Next, the configuration block packets within the memory interface configuration data packets are read sequentially. The configuration block packets are parsed, and the validity of the identifier characters is checked. If valid, it is further checked whether the configuration packet is a reference type packet. If it is, the register operation stream pointed to by the data offset address is read; otherwise, the register operation stream within the configuration block packet is read. Finally, the read register operation stream is executed, and a register check is performed to check for timeout. If no timeout occurs, the next configuration block packet is read, and this process continues until all configuration data packets have been processed.
[0057] In practice, the graphics card VBIOS program or graphics card driver first reads the onboard configuration information of the graphics card starting from offset address 0x20000 in the SPIFlash, and parses out the offset address of the video memory interface configuration data packet in the SPIFlash. Then, the graphics card VBIOS program or graphics card driver starts reading the configuration data packet of the video memory interface according to the offset address of the video memory interface configuration data packet in the SPIFlash, parses it into configuration block packets, and then executes the configuration block packets in sequence. For each configuration block packet, a register operation stream is executed. When the 31st bit of the operation address of the register is 1, a status register verification operation is performed. That is, the register value is read first and compared with the expected value. If it matches the expected value, it means that the verification is successful and returns. Otherwise, it delays for 1 microsecond and then reads the register value again and compares it with the expected value until the verification is successful or the verification times out and returns an error. The first byte 0xA5 of the block configuration packet is used to determine whether the configuration data packet has ended. If the first byte of the next block configuration packet is not 0xA5, it means that the current configuration data packet has been read and the video memory interface has been configured.
[0058] In summary, firstly, this invention converts the memory interface configuration driver process into a simple parameter data packet, which is stored in the graphics card memory. Thus, with the same graphics card VBIOS program or driver, only the content of the configuration data packet needs to be updated to switch between different interface types or bandwidth modes, without changing the graphics card VBIOS program or graphics card driver, solving the problem of diverse memory interface types and operating bandwidth modes. Secondly, the memory interface configuration method proposed in this invention is fully described by the configuration data packet stored in the graphics card memory. Both the graphics card VBIOS program and the graphics card driver configure the memory interface using the same configuration data packet, resolving the potential inconsistency in memory interface configuration methods between the graphics card VBIOS and the graphics card driver. Furthermore, by setting the graphics card onboard configuration information, multiple memory interface configuration data packets can be stored in the graphics card memory. Switching between memory interface configurations can be achieved simply by adjusting the offset address of the memory interface configuration packet in the graphics card onboard configuration information module, enabling support for different memory chips without updating the data in the configuration data packet area, further reducing the complexity of firmware data maintenance.
[0059] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for configuring a dedicated graphics card memory interface based on a configuration data package, characterized in that, The method includes the following steps: Step S1: Convert the dedicated graphics card's memory interface configuration process into a sequential register operation stream; Step S2: Segment the register operation stream according to address change characteristics and encapsulate it into configuration block packets; Step S3: According to the original execution order of the configuration block packets, combine the configuration block packets into a video memory interface configuration data packet and store it in the graphics card memory; Step S4: When initializing the video memory interface, the graphics card VBIOS program or driver first reads the video memory interface configuration data packet and parses out the video memory interface register operation stream. It then completes the configuration and driving of the video memory interface by executing the register operation stream. The specific process of step S4 is as follows: First, read the onboard configuration information of the graphics card. Based on the type of configuration data packet, obtain the offset address of the corresponding video memory interface configuration data packet from the onboard configuration information of the graphics card. Based on the offset address, the corresponding video memory interface configuration data packet can be read from the graphics card memory. Then, the configuration block packets in the video memory interface configuration data packet are read sequentially; the configuration block packets are parsed, and it is determined whether the identifier characters of the configuration block packets are valid; if valid, it is further determined whether the configuration packet is a reference type packet; if it is a reference type packet, the register operation stream pointed to by the data offset address is read; if it is not a reference type packet, the register operation stream inside the configuration block packet is read; finally, the read register operation stream is executed, and the register check is performed to see if it times out; if it does not time out, the next configuration block packet is read, until the entire configuration data packet is processed. In step S1, register operations include register write operations, register read operations, and register value verification operations; the register operation flow is a sequence of register operations executed in sequence; the operation type of the register is identified by several redundant address bits of the highest bit of the register. The register value verification operation is as follows: read the register value and determine whether the register value is consistent with the expected value. If they are inconsistent, wait for a period of time and then read the register value again and compare it with the expected value until the read register value is consistent with the expected value and return success. If the timeout number is reached and it is still unsuccessful, return failure. In step S2, the register operation flow is divided into two types based on address change characteristics: sequential register operations and random register operations. The specific process of step S2 is as follows: S21. When the number of consecutive sequential register operations of the same type reaches a set threshold, these consecutive sequential register operations are divided into a sequential register operation segment, and each random register operation between sequential register operation segments is divided into a random register operation segment. S22. Encapsulate the sequential register operation segment and the random register operation segment into corresponding sequential configuration block packets and random configuration block packets, wherein the sequential configuration block packets record the starting address, address step size, and register value information of the sequential register operation segment; and the random configuration block packets record the address and register value information of each random register operation.
2. The method for configuring the dedicated graphics card memory interface of the configuration data packet as described in claim 1, characterized in that, The first byte of the configuration block packet is an identifier character, used to indicate whether the configuration block packet exists.
3. The method for configuring the dedicated graphics card memory interface for configuring the data package as described in claim 2, characterized in that, In step S3, the configuration block packets are stored sequentially according to the original execution order of the configuration block packets to form a video memory interface configuration data packet, which is then stored in the graphics card memory.
4. The method for configuring the dedicated graphics card memory interface for configuring data packets as described in claim 3, characterized in that, In step S3, the graphics card memory stores various graphics memory interface configuration data packets.
5. The method for configuring the dedicated graphics card memory interface for configuring the data package as described in claim 4, characterized in that, Step S3 further includes setting the graphics card onboard configuration information, which stores the offset address of the configuration data packet for each video memory interface.