电子系统、集成电路晶粒及其操作方法
By introducing splitting and merging circuits into the integrated circuit die, the problem of inconsistent delays between interface circuit chips is solved, achieving more efficient data transmission timing alignment and performance improvement.
CN115687209BActive Publication Date: 2026-07-17GLOBAL UNICHIP CORPORATION +1
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GLOBAL UNICHIP CORPORATION
- Filing Date
- 2021-09-06
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
The existence of different delays among multiple interface circuit chips affects the timing alignment of data transmission and overall performance.
Method used
By introducing splitting and merging circuits into the integrated circuit die, the transmitted data stream is split into multiple sub-data streams, these sub-data streams are aligned in timing, and the data is merged back into the original data to reduce the different delays of the interface circuit chips.
Benefits of technology
It effectively reduces the different delays of the interface circuit chips, and improves the timing alignment and overall performance of data transmission.
✦ Generated by Eureka AI based on patent content.
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Figure CN115687209B_ABST
Abstract
本发明提供一种电子系统、集成电路晶粒及其操作方法。集成电路晶粒包括多个接口电路片以及合并电路。从传送器晶粒所传送的传输数据串流被拆分多个子数据串流。这些接口电路片的每一个提供物理层以接收这些子数据串流中的对应者。合并电路耦接至这些接口电路片，以接收这些子数据串流。合并电路将来自这些接口电路片的这些子数据串流合并回传输数据串流所对应的原始数据以提供给应用层。合并电路在时序上对齐来自这些接口电路片的这些子数据串流，以减轻这些接口电路片的不同延迟。
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