Scanning key circuit testing method and device

Abstract

The embodiment of the present application provides a kind of scanning key circuit test method and device, the method includes: generating key data class based on VMM verification methodology, key data class includes random variable and the constraint condition of random variable value, random variable includes the random variable corresponding to the number of triggered key, the random variable corresponding to the key label triggered;Object is obtained by instantiating key data class, object includes the number of triggered key and the key label triggered;Using object as random test sample excitation simulated scanning key circuit module, simulate the key corresponding to each key label in object is triggered in the process of scanning of scanning key circuit module simulation;Whether scanning key circuit module is correct is verified according to the register value related to key trigger of scanning key circuit module, and the register related to key trigger includes the state register corresponding to each key trigger state and / or the interrupt register for realizing key interrupt function.

Description

Technical Field

[0001] This invention relates to the field of electronic information technology, and more particularly to a method and apparatus for testing scanning key circuits. Background Technology

[0002] In the integrated circuit chip (IC) design flow, after the designer completes the register transfer level (RTL) code according to the design specification, the verification personnel need to verify the correctness of the conversion from the design specification to the RTL, including but not limited to the following: (1) whether the behavior of the device under test (DUT) is consistent with the requirements in the design specification; (2) whether the DUT has implemented all the functions in the design specification; (3) whether the DUT's response to abnormal conditions is consistent with the design specification; (4) whether the DUT is robust enough to recover from abnormal conditions to normal working mode.

[0003] As chip size increases, verification work accounts for a growing proportion of the entire chip design process. Currently, verification workload accounts for 70% to 80% of the entire IC R&D cycle. However, a significant portion of ICs still rely on manual verification, resulting in low efficiency and impacting R&D progress. Therefore, improving chip verification efficiency has become crucial. Summary of the Invention

[0004] This invention provides a method and apparatus for testing scanning button circuits, which solves the problem of low efficiency in manually verifying scanning button circuit designs in the prior art.

[0005] This invention provides a method for testing scanning key circuits, including:

[0006] Based on the VMM verification method in the verification method manual, a key data class is generated. The key data class includes random variables and constraints on the values ​​of the random variables. The random variables include random variables corresponding to the number of triggered keys and random variables corresponding to the number of triggered keys.

[0007] An object is obtained by instantiating the key data class, and the object includes the number of triggered keys and the key number of the triggered keys;

[0008] The object is used as a random test sample to stimulate the simulation of the scanning key circuit module. During the simulation scanning process of the scanning key circuit module, the keys corresponding to each key label in the object are simulated to be triggered.

[0009] Verify the correctness of the scanning button circuit module based on the register values ​​related to button triggering in the scanning button circuit module;

[0010] The registers related to key triggering include status registers corresponding to each key triggering state and / or interrupt registers that implement key interruption functions.

[0011] Optionally, the constraints on the values ​​of the random variable include:

[0012] The number of triggered buttons is a natural number and is not greater than the total number of buttons in the simulated scanning button circuit;

[0013] The triggered button number belongs to the button number in the simulated scanning button circuit, and when there are multiple triggered button numbers, each button number is different from the others.

[0014] Optionally, the random variable may also include a random variable corresponding to the bounce state of the triggered key;

[0015] The constraints on the values ​​of the random variable also include:

[0016] The number of random variables corresponding to the jitter state is the same as the number of triggered buttons;

[0017] The jitter state includes a no-jitter state and a jitter state, wherein the jitter state is triggered and the duration of the trigger is less than the preset trigger duration.

[0018] Optionally, the scanning button circuit module performs two rounds of cyclic scanning in each simulation;

[0019] The jittering state includes a first jittering state and a second jittering state. The first jittering state is used to excite the corresponding button to be triggered during the first round of cyclic scanning, but not during the second round of cyclic scanning. The second jittering state is used to excite the corresponding button to not be triggered during the first round of cyclic scanning, but to be triggered during the second round of cyclic scanning.

[0020] Optionally, instantiating the button data class to obtain an object includes:

[0021] Based on the constraints of the random variable values ​​of the key data class, the number of triggered keys, the key number of triggered keys, and the bounce state of the triggered keys are determined in a random manner.

[0022] Optionally, the object is used as a random test sample to stimulate the scanning key circuit module in the simulation. During the simulation scanning process of the scanning key circuit module, the keys corresponding to each key label in the object are simulated to be triggered, including:

[0023] At the start of each scan, the value of the corresponding element in the key register array is set to a valid value according to the key number triggered in the object;

[0024] If, during the scanning process of the scanning button circuit module, the scanning signal line connected to the button is in the output state and the value of the element corresponding to the button is valid, the value of the output variable of the button is assigned to the value of the input variable of the button.

[0025] Upon completion of this scan, all elements in the key register array are reset to invalid values.

[0026] In the process of simulating scanning, the scanning signal line of the scanning button circuit module is set to the output state in sequence, the signal variable corresponding to the scanning signal line is assigned the value of the scanning signal, and the value of the input variable of the button connected to the scanning signal line is assigned the value of the signal variable to simulate the scanning signal line being scanned.

[0027] During simulation scanning, the input variable of the button corresponds to the signal connection terminal connected to the scan signal line being scanned, the output variable corresponds to the other signal connection terminal of the button, and each element in the button register array corresponds one-to-one with each button in the simulated scanning button circuit.

[0028] Optionally, the object is used as a random test sample to stimulate the scanning key circuit module in the simulation. During the simulation scanning process of the scanning key circuit module, the keys corresponding to each key label in the object are simulated to be triggered, including:

[0029] At the start of the first round of scanning, based on the key labels triggered in the object whose jitter state is not the second jitter state, the value of the corresponding element in the key register array is set to a valid value;

[0030] If, during the scanning process of the scanning button circuit module, the scanning signal line connected to the button is in the output state and the value of the element corresponding to the button is valid, the value of the output variable of the button is assigned to the value of the input variable of the button.

[0031] Upon completion of the first round of scanning, all elements in the key register array are reset to invalid values.

[0032] When the second round of scanning begins, based on the key labels triggered in the object whose jitter state is not the first jitter state, the value of the corresponding element in the key register array is set to a valid value.

[0033] If, during the scanning process of the scanning button circuit module, the scanning signal line connected to the button is in the output state and the value of the element corresponding to the button is valid, the value of the output variable of the button is assigned to the value of the input variable of the button.

[0034] Upon completion of the second round of scanning, all elements in the key register array are reset to invalid values.

[0035] In the process of simulating scanning, the scanning signal line of the scanning button circuit module is set to the output state in sequence, the signal variable corresponding to the scanning signal line is assigned the value of the scanning signal, and the value of the input variable of the button connected to the scanning signal line is assigned the value of the signal variable to simulate the scanning signal line being scanned.

[0036] During simulation scanning, the input variable of the button corresponds to the signal connection terminal connected to the scan signal line being scanned, the output variable corresponds to the other signal connection terminal of the button, and each element in the button register array corresponds one-to-one with each button in the simulated scanning button circuit.

[0037] Based on the same inventive concept, embodiments of the present invention also provide a scanning key circuit testing device, comprising:

[0038] An abstract unit is used to generate a key data class based on the VMM verification method in the verification method manual. The key data class includes random variables and constraints on the values ​​of the random variables. The random variables include random variables corresponding to the number of triggered keys and random variables corresponding to the number of triggered keys.

[0039] A random instance generation unit is used to instantiate the key data class to obtain an object, the object including the number of triggered keys and the key number of the triggered keys;

[0040] The test unit is used to stimulate the scanning key circuit module of the simulation using the object as a random test sample, and to simulate the triggering of the keys corresponding to each key label in the object during the simulation scanning process of the scanning key circuit module.

[0041] The verification unit is used to verify whether the scanning button circuit is correct based on the register values ​​related to button triggering in the scanning button circuit module.

[0042] The registers related to key triggering include status registers corresponding to each key triggering state and / or interrupt registers that implement key interruption functions.

[0043] Based on the same inventive concept, embodiments of the present invention also provide an electronic device, including: a processor and a memory for storing processor-executable instructions;

[0044] The processor is configured to execute the instructions to implement the scanning button circuit testing method.

[0045] Based on the same inventive concept, embodiments of the present invention also provide a computer storage medium storing a computer program, the computer program being used to implement any of the scanning key circuit testing methods described in the present invention.

[0046] The beneficial effects of this invention are as follows:

[0047] The scanning button circuit testing method and apparatus provided in this invention significantly improves the efficiency of circuit verification compared to manual testing by automatically generating test samples using simulation software. Attached Figure Description

[0048] Figure 1 This is a circuit diagram of a scanning key circuit;

[0049] Figure 2 This is a circuit diagram for another type of scanning button circuit;

[0050] Figure 3 A flowchart of a scanning button circuit testing method provided in an embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram of the verification environment provided in an embodiment of the present invention;

[0052] Figure 5 This is a schematic diagram of the structure of the scanning key circuit testing device provided in an embodiment of the present invention;

[0053] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0054] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction in the present invention are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of the present invention. The accompanying drawings of the present invention are for illustrative purposes only and do not represent actual proportions.

[0055] It should be noted that specific details are set forth in the following description to provide a full understanding of the invention. However, the invention can be practiced in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below. The following description is a preferred embodiment for carrying out the present application; however, the description is for the purpose of illustrating the general principles of the application and is not intended to limit the scope of the application. The scope of protection of this application shall be determined by the appended claims.

[0056] Before introducing the specific embodiments of the present invention, the terminology involved in the embodiments of the present invention will be introduced first:

[0057] Verification Methodology Manual (VMM): Verification methodologies

[0058] The VMM verification methodology is an advanced verification methodology in the field of IC design verification, used to develop advanced verification environments. Its underlying language is SystemVerilog. The VMM verification methodology primarily describes how to use SystemVerilog to create a comprehensive verification environment that employs coverage-driven, random constraint generation, and assertion-based verification techniques, while also specifying library data blocks for interoperable verification components.

[0059] The embodiments of the present invention do not limit the scanning key circuit involved, for example, it can be as follows: Figure 1 The scanning key circuit shown, or as... Figure 2 The scanning button circuit shown below. The following will combine... Figure 1 The scanning button circuit shown is explained below.

[0060] Figure 1 The button scanning circuit shown includes two circuit connection terminals and one normally open contact. All buttons in the button scanning circuit are connected to the circuit connection terminals in a matrix, with signal line PA corresponding to the first row, signal line PB corresponding to the second row, and so on. The first circuit connection terminal of the button in the nth row ( Figure 1 The circuit connection terminal on the left side of the button (as shown in the diagram) is connected to the signal line in row (n+1), and the second circuit connection terminal of the button in column m ( Figure 1The circuit connection terminal on the right side of the illustrated button is connected to the m-th row of signal lines, where m and n are both positive integers. When the button scanning circuit is working, it sequentially sets each row of scan signal lines to the output state, inputting a scan signal to the circuit connection terminal of the connected button, and sets unscanned scan signal lines to the input state, receiving the signal output by the triggered button. For example, when button 1, whose circuit connection terminal is connected to the 1st row of signal lines (scan signal line PA) and the 3rd row of signal lines (scan signal line PC), is triggered, when scanning to the 1st row of signal lines, the 3rd row of signal lines receives the signal from the 1st row of signal lines; or when scanning to the 3rd row of signal lines, the 1st row of signal lines receives the signal from the 3rd row of signal lines. This confirms that the button has been triggered.

[0061] Figure 2 The button scanning circuit shown includes two circuit connection terminals and one normally open contact for each button. All buttons in the circuit scanning circuit are connected in a matrix, with signal line A corresponding to row 1, signal line B corresponding to row 2, and so on. Therefore, the first circuit connection terminal of the button in row n (the circuit connection terminal on the left side of the button shown in the diagram) is connected to the signal line in row n, and the second circuit connection terminal of the button in column m (the circuit connection terminal on the right side of the button shown in the diagram) is connected to the signal line in row N+m. Here, m, n, and N are all positive integers, and N is the total number of rows of buttons in the circuit scanning circuit. Figure 2 (Illustration: N=4). The first N rows of signal lines are scanning signal lines, and the remaining signal lines are not scanned. When the button scanning circuit is working, it sequentially sets the first N rows of signal lines to the output state, inputting scanning signals to the circuit connection terminals of the connected buttons. The remaining signal lines are always in the input state, receiving the signals output by the triggered buttons. For example, when buttons whose circuit connection terminals are connected to the 1st row of signal lines (signal line A) and the 7th row of signal lines (signal line G) are triggered, when scanning reaches the 1st row of signal lines, the 7th row of signal lines receives the signal from the 1st row of signal lines, thus confirming that the button has been triggered.

[0062] The scanning button circuit testing method and apparatus provided in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0063] This invention provides a method for testing scanning button circuits, such as... Figure 3 As shown, it includes:

[0064] S101. Generate a key data class based on the VMM verification method. The key data class includes random variables and constraints on the values ​​of the random variables. The random variables include random variables corresponding to the number of triggered keys and random variables corresponding to the key labels of the triggered keys.

[0065] For example, the key data class `keyscan_transaction` can be declared using the VMM-based authentication method:

[0066] class keyscan_transaction extends vmm_data;

[0067] The following statement sets the random variable key_num in the keyscan_transaction key data class to include the number of triggered keys:

[0068] rand int key_num;

[0069] The following statement sets the random array variable key_index[] in the key data class keyscan_transaction to include the random variable corresponding to the triggered key number:

[0070] rand int key_index[];

[0071] S102. Instantiate the key data class to obtain an object, the object including the number of triggered keys and the key number of the triggered keys.

[0072] S103. Using the object as a random test sample to stimulate the simulation of the scanning key circuit module, during the simulation scanning process of the scanning key circuit module, the keys corresponding to each key label in the object are simulated to be triggered.

[0073] S104. Verify whether the scanning button circuit module is correct based on the register values ​​related to button triggering in the scanning button circuit module;

[0074] The registers related to key triggering include status registers corresponding to each key triggering state and / or interrupt registers that implement key interruption functions.

[0075] In practice, the design of the key scanning circuit can be verified by checking whether the register values ​​related to key triggering meet the design goals of the key scanning circuit.

[0076] During the simulation process, by establishing, for example Figure 4The simulation environment shown is used for verification. The simulation environment Testbench.sv includes the simulation platform module Keyscan_test.sv and the simulated key scanning circuit module Keyscan.v. The Keyscan_test.sv module obtains the object stimulus Keyscan.v module through instantiation. Each time the above steps are performed, the key scanning circuit module Keyscan.v performs a line-by-line simulation scan.

[0077] The scanning button circuit testing method provided in this invention improves the efficiency of circuit verification by automatically generating test samples using simulation software, compared with manual testing.

[0078] Optionally, the constraints on the values ​​of the random variable include:

[0079] The number of triggered buttons is a natural number and is not greater than the total number of buttons in the simulated scanning button circuit.

[0080] For example, for Figure 1 The schematic scanning button circuit has the following constraints set in the button data class keyscan_transaction:

[0081] key_num>=0&&key_num<=28;

[0082] / / The number of key presses triggered in this loop scan test ranges from 0 to 28.

[0083] key_index.size()==key_num;

[0084] / / The number of key labels that are triggered is equal to the number of keys that are triggered.

[0085] The triggered button number belongs to the button number in the simulated scanning button circuit, and when there are multiple triggered button numbers, each button number is different from the others.

[0086] For example, the following constraints are set in the key data class keyscan_transaction:

[0087] foreach(key_index[i])

[0088] foreach(key_index[j])

[0089] if(j>i)key_index[i]! =key_index[j];

[0090] In this way, by setting constraints on the values ​​of random variables, it can be ensured that the instantiated object of the button data class is a test sample that conforms to the actual circuit function.

[0091] Optionally, the random variable may also include a random variable corresponding to the bounce state of the triggered key;

[0092] For example, the key_break[], a random array variable corresponding to the bounce state of the triggered key, is set in the keyscan_transaction key data class using the following statement:

[0093] rand int key_break[];

[0094] The constraints on the values ​​of the random variable also include:

[0095] The number of random variables corresponding to the jitter state is the same as the number of triggered buttons.

[0096] For example, the following constraints are set in the key data class keyscan_transaction:

[0097] key_break.size==key_num;

[0098] / / The number of variables in the bounce state of the triggered key is equal to the number of keys that were triggered.

[0099] Alternatively, the following constraints can be set to simultaneously constrain the random variable corresponding to the jitter state and the random variable corresponding to the triggered button number:

[0100] key_index.size()==key_num&&key_break.size==key_num;

[0101] The jitter state includes a no-jitter state and a jitter state, wherein the jitter state is triggered and the duration of the trigger is less than the preset trigger duration.

[0102] In the specific implementation process, in order to eliminate jitter, the same key is scanned multiple times during each scan. Only when all multiple scans of the key confirm that it is triggered can it be determined that the key is triggered without jitter. Otherwise, if at least one scan of the key is not triggered, the duration of the trigger is less than the preset trigger duration, and the key is determined to be triggered by jitter.

[0103] Optionally, the scanning button circuit module performs at least two rounds of cyclic scanning in each simulation.

[0104] As an optional implementation, the scanning button circuit module performs two rounds of cyclic scanning in each simulation.

[0105] For the simulated scanning key circuit, two rounds of cyclic scanning are performed on each key. The bouncing state includes a first bouncing state and a second bouncing state. The first bouncing state is used to activate the corresponding key during the first round of cyclic scanning, but not during the second round of cyclic scanning. The second bouncing state is used to activate the corresponding key during the second round of cyclic scanning, but not during the first round of cyclic scanning. That is, the key timing is shown in the table below:

[0106] Table 1. Timing Table for Jitter Status

[0107] No shaking state 1 1 First shaking state 1 0 Second shaking state 0 1

[0108] Therefore, the random variable corresponding to the bounce state of the triggered button also has the following constraints:

[0109] foreach(key_break[i])key_break[i]>=0&&key_break[i]<=2;

[0110] / / Constrain the range of values ​​for all random variables corresponding to jitter states to {0,1,2}.

[0111] / / Among them, the jitter state with a value of 0 is the no-jitter state, the jitter state with a value of 1 is the first jitter state, and the jitter state with a value of 2 is the second jitter state.

[0112] Optionally, step S102, instantiating the button data class to obtain an object, specifically includes:

[0113] Based on the constraints of the random variable values ​​of the key data class, the number of triggered keys, the key number of triggered keys, and the bounce state of the triggered keys are determined in a random manner.

[0114] As an optional implementation, when the random variables in the key data class include random variables corresponding to the number of triggered keys and random variables corresponding to the key labels of the triggered keys, step S103, using the object as a random test sample to stimulate the scanning key circuit module for simulation, simulates the triggering of keys corresponding to each key label in the object during the simulation scanning process of the scanning key circuit module, including:

[0115] At the start of each scan, the value of the corresponding element in the key register array is set to a valid value according to the key number triggered in the object;

[0116] If, during the scanning process of the scanning button circuit module, the scanning signal line connected to the button is in the output state and the value of the element corresponding to the button is valid, the value of the output variable of the button is assigned to the value of the input variable of the button.

[0117] Upon completion of this scan, all elements in the key register array are reset to invalid values.

[0118] In the process of simulating scanning, the scanning signal line of the scanning button circuit module is set to the output state in sequence, the signal variable corresponding to the scanning signal line is assigned the value of the scanning signal, and the value of the input variable of the button connected to the scanning signal line is assigned the value of the signal variable to simulate the scanning signal line being scanned.

[0119] During simulation scanning, the input variable of the button corresponds to the signal connection terminal connected to the scan signal line being scanned, the output variable corresponds to another signal connection terminal of the button, and each element in the button register array corresponds one-to-one with each button in the simulated scanning button circuit. As another optional implementation, when the random variables in the button data class include random variables corresponding to the number of triggered buttons, random variables corresponding to the button labels of the triggered buttons, and random variables corresponding to the bounce state of the triggered buttons, step S103, using the object as a random test sample to excite the simulated scanning button circuit module, and simulating the triggering of buttons corresponding to each button label in the object during the simulation scanning process of the scanning button circuit module, includes:

[0120] At the start of the first round of scanning, based on the key labels triggered in the object whose jitter state is not the second jitter state, the value of the corresponding element in the key register array is set to a valid value;

[0121] If, during the scanning process of the scanning button circuit module, the scanning signal line connected to the button is in the output state and the value of the element corresponding to the button is valid, the value of the output variable of the button is assigned to the value of the input variable of the button.

[0122] Upon completion of the first round of scanning, all elements in the key register array are reset to invalid values.

[0123] When the second round of scanning begins, based on the key labels triggered in the object whose jitter state is not the first jitter state, the value of the corresponding element in the key register array is set to a valid value.

[0124] If, during the scanning process of the scanning button circuit module, the scanning signal line connected to the button is in the output state and the value of the element corresponding to the button is valid, the value of the output variable of the button is assigned to the value of the input variable of the button.

[0125] Upon completion of the second round of scanning, all elements in the key register array are reset to invalid values.

[0126] In the process of simulating scanning, the scanning signal line of the scanning button circuit module is set to the output state in sequence, the signal variable corresponding to the scanning signal line is assigned the value of the scanning signal, and the value of the input variable of the button connected to the scanning signal line is assigned the value of the signal variable to simulate the scanning signal line being scanned.

[0127] During simulation scanning, the input variable of the button corresponds to the signal connection terminal connected to the scan signal line being scanned, the output variable corresponds to the other signal connection terminal of the button, and each element in the button register array corresponds one-to-one with each button in the simulated scanning button circuit.

[0128] by Figure 1 Taking the scan button circuit shown as an example, the states of each row of scan signal lines can be abstracted into state variables sequentially (for example, the states of each row of scan signal lines can be abstracted into output state variables PA.OE, PB.OE...PH.OE, where a value of 1 indicates that the corresponding scan signal line is in an output state). The signals of each row of signal lines can be abstracted into signal variables PA, PB...PH of the Keyscan.v module. When the first row of scan signal lines is scanned, it is in an output state, so the output state variable PA.OE of the first row is set to 1. The second to eighth rows of scan signal lines are in an input state, and PB.OE...PH.OE = 0. Assigning the scan signal signal (e.g., 0) to the signal variable PA is equivalent to inputting the scan signal (0 corresponds to a low-level signal) to the first row of signal lines in a real button scanning circuit. Similarly, for... Figure 2The scanning button circuit shown can abstract the states of each row of signal lines into state variables sequentially (for example, the states of each row of scan signal lines can be abstracted into output state variables A.OE, B.OE, ..., where an output state variable of 1 indicates that the corresponding scan signal line is in an output state). The signals of each row of signal lines can be abstracted into signal variables A, B, ... H of the Keyscan.v module. When the first row of signal lines is scanned, it is in an output state, so the output state variable A.OE = 1. The fifth to eighth rows of signal lines are in an input state, and E.OE = ... = H.OE = 0. The button contacts in the scanning button circuit can be abstracted into variables sequentially, where a value of 1 or 0 indicates whether the contact is triggered. Continuing... Figure 1 Taking the scanning button circuit shown as an example, the abstract variables of all contacts in the scanning button circuit can be combined into a register array key_mask[27:0], that is, the variable corresponding to the contact is the corresponding element in the register array.

[0129] by Figure 4 Taking the simulation environment shown as an example, the Keyscan_test.sv module of the simulation platform first declares and creates a key register array. Each element in the key register array represents the contact point of the key with the corresponding key number.

[0130] bit key_mask[27:0]

[0131] At the start of the first round of scanning, for key labels whose bounce state is not the second bounce state triggered in the key data class, the corresponding element in the key register array is set to the valid value 1.

[0132] for(int j = 0; j <tr.key_num;j++)

[0133] Key_mask[tr.key_index[j]]=tr.key_break[j]==2?1'b0:1'b1;

[0134] Specifically, the simulation platform Keyscan_test.sv module drives the scanning button circuit module Keyscan.v module through the following program:

[0135] alway@(*)begin

[0136] if(key_mask[0]&&PB.OE) / / Key 0 is pressed

[0137] force PA = PB;

[0138] else if(key_mask[1]&&PC.OE) / / Key 1 is pressed

[0139] force PA = PC;

[0140] else if(key_mask[2]&&PD.OE) / / Key 2 is pressed

[0141] force PA = PD;

[0142] else if(key_mask[3]&&PE.OE) / / Key 3 is pressed

[0143] force PA = PE;

[0144] else if(key_mask[4]&&PF.OE) / / Key 4 is pressed

[0145] force PA = PF;

[0146] else if(key_mask[5]&PG.OE) / / Key 5 is pressed

[0147] force PA = PG;

[0148] else if(key_mask[6]&&PH.OE) / / Key 6 is pressed

[0149] force PA = PH;

[0150] else

[0151] Release PA;

[0152] end

[0153] alway@(*)begin

[0154] if(key_mask[0]&&PA.OE) / / Key 0 is pressed

[0155] force PB = PA;

[0156] else if(key_mask[7]&&PC.OE) / / Key 7 is pressed

[0157] force PB = PC;

[0158] else if(key_mask[8]&&PD.OE) / / Key 8 is pressed

[0159] force PB = PD;

[0160] else if(key_mask[9]&&PE.OE) / / Key 9 is pressed

[0161] force PB = PE;

[0162] else if(key_mask

[10] &&PF.OE) / / Key 10 is pressed

[0163] force PB = PF;

[0164] else if(key_mask

[11] &&PG.OE) / / Key 11 is pressed

[0165] force PB = PG;

[0166] else if(key_mask

[12] &&PH.OE) / / Key 12 is pressed

[0167] force PB = PH;

[0168] else

[0169] Release PB;

[0170] end

[0171] alway@(*)begin

[0172] if(key_mask[1]&&PA.OE) / / Key 1 is pressed

[0173] force PC = PA;

[0174] else if(key_mask[7]&&PB.OE) / / Key 7 is pressed

[0175] force PC = PB;

[0176] else if(key_mask

[13] &&PD.OE) / / Key 13 is pressed

[0177] force PC = PD;

[0178] else if(key_mask

[14] &&PE.OE) / / Key 14 is pressed

[0179] force PC = PE;

[0180] else if(key_mask

[15] &&PF.OE) / / Key 15 is pressed

[0181] force PC = PF;

[0182] else if(key_mask

[16] &&PG.OE) / / Key 16 is pressed

[0183] force PC = PG;

[0184] else if(key_mask

[17] &&PH.OE) / / Key 17 is pressed

[0185] force PC = PH;

[0186] else

[0187] Release PC;

[0188] end

[0189] alway@(*)begin

[0190] if(key_mask[2]&&PA.OE) / / Key 2 is pressed

[0191] force PD = PA;

[0192] else if(key_mask[8]&&PB.OE) / / Key 8 is pressed

[0193] force PD = PB;

[0194] else if(key_mask

[13] &&PC.OE) / / Key 13 is pressed

[0195] force PD = PC;

[0196] else if(key_mask

[18] &&PE.OE) / / Key 18 is pressed

[0197] force PD = PE;

[0198] else if(key_mask

[19] &&PF.OE) / / Key 19 is pressed

[0199] force PD = PF;

[0200] else if(key_mask

[20] &&PG.OE) / / Key 20 is pressed

[0201] force PD = PG;

[0202] else if(key_mask

[21] &&PH.OE) / / Key 21 is pressed

[0203] force PD = PH;

[0204] else

[0205] Release PD;

[0206] end

[0207] alway@(*)begin

[0208] if(key_mask[3]&&PA.OE) / / Key 3 is pressed

[0209] force PE = PA;

[0210] else if(key_mask[9]&&PB.OE) / / Key 9 is pressed

[0211] force PE = PB;

[0212] else if(key_mask

[14] &&PC.OE) / / Key 14 is pressed

[0213] force PE = PC;

[0214] else if(key_mask

[18] &&PD.OE) / / Key 18 is pressed

[0215] force PE = PD;

[0216] else if(key_mask

[22] &&PF.OE) / / Key 22 is pressed

[0217] force PE = PF;

[0218] else if(key_mask

[23] &&PG.OE) / / Key 23 is pressed

[0219] force PE = PG;

[0220] else if(key_mask

[24] &&PH.OE) / / Key 24 is pressed

[0221] force PE = PH;

[0222] else

[0223] Release PE;

[0224] end

[0225] alway@(*)begin

[0226] if(key_mask[4]&&PA.OE) / / Key 4 is pressed

[0227] force PF = PA;

[0228] else if(key_mask

[10] &&PB.OE) / / Key 10 is pressed

[0229] force PF = PB;

[0230] else if(key_mask

[15] &&PC.OE) / / Key 15 is pressed

[0231] force PF = PC;

[0232] else if(key_mask

[19] &&PD.OE) / / Key 19 is pressed

[0233] force PF = PD;

[0234] else if(key_mask

[22] &&PE.OE) / / Key 22 is pressed

[0235] force PF = PE;

[0236] else if(key_mask

[25] &&PG.OE) / / Key 25 is pressed

[0237] force PF = PG;

[0238] else if(key_mask

[26] &&PH.OE) / / Key 26 is pressed

[0239] force PF = PH;

[0240] else

[0241] Release PF;

[0242] end

[0243] alway@(*)begin

[0244] if(key_mask[5]&&PA.OE) / / Key 5 is pressed

[0245] force PG = PA;

[0246] else if(key_mask

[11] &&PB.OE) / / Key 11 is pressed

[0247] force PG = PB;

[0248] else if(key_mask

[16] &&PC.OE) / / Key 16 is pressed

[0249] force PG = PC;

[0250] else if(key_mask

[20] &&PD.OE) / / Key 20 is pressed

[0251] force PG = PD;

[0252] else if(key_mask

[23] &&PE.OE) / / Key 23 is pressed

[0253] force PG = PE;

[0254] else if(key_mask

[25] &&PG.OE) / / Key 25 is pressed

[0255] force PG = PF;

[0256] else if(key_mask

[27] &&PH.OE) / / Key 27 is pressed

[0257] force PG = PH;

[0258] else

[0259] Release PG;

[0260] end

[0261] alway@(*)begin

[0262] if(key_mask[6]&&PA.OE) / / Key 6 is pressed

[0263] force PH = PA;

[0264] else if(key_mask

[12] &&PB.OE) / / Key 12 is pressed

[0265] force PH = PB;

[0266] else if(key_mask

[17] &&PC.OE) / / Key 17 is pressed

[0267] force PH = PC;

[0268] else if(key_mask

[21] &&PD.OE) / / Key 21 is pressed

[0269] force PH = PD;

[0270] else if(key_mask

[24] &&PE.OE) / / Key 24 is pressed

[0271] force PH = PE;

[0272] else if(key_mask

[26] &&PG.OE) / / Key 26 is pressed

[0273] force PH = PF;

[0274] else if(key_mask

[27] &&PH.OE) / / Key 27 is pressed

[0275] force PH=PG;

[0276] else

[0277] Release pH;

[0278] end

[0279] Assume that only key number 27 is triggered in the first bounce state during this simulation test. Then, key_mask

[27] will be set to a valid value of 1 in the first round of scanning. When the Keyscan.v module scans to line 7 (line PG), PG.OE is a valid value of 1, and the value of PH will be forcibly assigned to the value of PG; when the Keyscan.v module scans to line 8 (line PH), PH.OE is a valid value of 1, and the value of PG will be forcibly assigned to the value of PH. If the Keyscan.v module meets the design goals, the values ​​of the interrupt register of the Keyscan.v module and the status register corresponding to key number 27 will also meet the expectations (for example, the value of the interrupt register is the interrupt status value, and the value of the status register corresponding to key number 27 is the value indicating that it has been triggered).

[0280] Upon completion of the first round of scanning, all elements in the key register array key_mask[27:0] are reset to the invalid value 0.

[0281] Similarly, at the start of the second round of scanning, the corresponding element in the key register array is set to the valid value 1 based on the bounce state of the triggered key:

[0282] for(int j = 0; j <tr.key_num;j++)

[0283] Key_mask[tr.key_index[j]]=tr.key_break[j]==1?1'b0:1'b1;

[0284] Then, the second scan key_mask

[27] will be set to an invalid value of 0. When the Keyscan.v module scans to the 7th line (PG line), PG.OE is a valid value of 1, and the value of PH will not be forcibly assigned to the value of PG; when the Keyscan.v module scans to the 8th line (PH line), PH.OE is a valid value of 1, and the value of PG will not be forcibly assigned to the value of PH. If the Keyscan.v module meets the design goal, the values ​​of the interrupt register of the Keyscan.v module and the status register corresponding to the 27th key will also meet the expectations (for example, the value of the interrupt register is a non-interrupt state value, and the value of the status register corresponding to the 27th key is a value indicating that it has not been triggered). Conversely, if the values ​​of the interrupt register and status register of the Keyscan.v module are different from the values ​​of the scan button circuit module corresponding to the design goal, it can be determined that the design of the scan button circuit does not meet the design goal.

[0285] Based on the same inventive concept, embodiments of the present invention also provide a scanning key circuit testing device, such as... Figure 5 As shown, it includes:

[0286] Abstract unit U101 is used to generate key data class based on the VMM verification method in the verification method manual. The key data class includes random variables and constraints on the values ​​of the random variables. The random variables include random variables corresponding to the number of triggered keys and random variables corresponding to the number of triggered keys.

[0287] The random instance generation unit U102 is used to instantiate the key data class to obtain an object, the object including the number of triggered keys and the key number of the triggered keys;

[0288] Test unit U103 is used to use the object as a random test sample to stimulate the simulation of the scanning key circuit module, and to simulate the triggering of the keys corresponding to each key label in the object during the scanning process of the scanning key circuit.

[0289] Verification unit U104 is used to verify whether the scanning button circuit module is correct based on the register value related to button triggering of the scanning button circuit module;

[0290] The registers related to key triggering include status registers corresponding to each key triggering state and / or interrupt registers that implement key interruption functions.

[0291] Optionally, the constraints on the values ​​of the random variable include:

[0292] The number of triggered buttons is a natural number and is not greater than the total number of buttons in the simulated scanning button circuit;

[0293] The triggered button number belongs to the button number in the simulated scanning button circuit, and when there are multiple triggered button numbers, each button number is different from the others.

[0294] Optionally, the random variable may also include a random variable corresponding to the bounce state of the triggered key;

[0295] The constraints on the values ​​of the random variable also include:

[0296] The number of random variables corresponding to the jitter state is the same as the number of triggered buttons;

[0297] The jitter state includes a no-jitter state and a jitter state, wherein the jitter state is triggered and the duration of the trigger is less than the preset trigger duration.

[0298] Optionally, the scanning button circuit module performs two rounds of cyclic scanning in each simulation;

[0299] The jittering state includes a first jittering state and a second jittering state. The first jittering state is used to activate the corresponding button during the first round of cyclic scanning, but not during the second round of cyclic scanning. The second jittering state is used to activate the corresponding button during the second round of cyclic scanning, but not during the first round of cyclic scanning.

[0300] Optionally, instantiating the button data class to obtain an object includes:

[0301] Based on the constraints of the random variable values ​​of the key data class, the number of triggered keys, the key number of triggered keys, and the bounce state of the triggered keys are determined in a random manner.

[0302] Optionally, the object is used as a random test sample to stimulate the simulation of the scanning key circuit module. During the simulation scanning process of the scanning key circuit module, the key corresponding to each key label in the object is triggered, including:

[0303] At the start of each scan, the value of the corresponding element in the key register array is set to a valid value according to the key number triggered in the object;

[0304] If, during the scanning process of the scanning button circuit module, the scanning signal line connected to the button is in the output state and the value of the element corresponding to the button is valid, the value of the output variable of the button is assigned to the value of the input variable of the button.

[0305] Upon completion of this scan, all elements in the key register array are reset to invalid values.

[0306] In the process of simulating scanning, the scanning signal line of the scanning button circuit module is set to the output state in sequence, the signal variable corresponding to the scanning signal line is assigned the value of the scanning signal, and the value of the input variable of the button connected to the scanning signal line is assigned the value of the signal variable to simulate the scanning signal line being scanned.

[0307] During simulation scanning, the input variable of the button corresponds to the signal connection terminal connected to the scan signal line being scanned, the output variable corresponds to the other signal connection terminal of the button, and each element in the button register array corresponds one-to-one with each button in the simulated scanning button circuit.

[0308] Optionally, the object is used as a random test sample to stimulate the simulation of the scanning key circuit module. During the simulation scanning process of the scanning key circuit module, the key corresponding to each key label in the object is triggered, including:

[0309] At the start of the first round of scanning, based on the key labels triggered in the object whose jitter state is not the second jitter state, the value of the corresponding element in the key register array is set to a valid value;

[0310] If, during the scanning process of the scanning button circuit module, the scanning signal line connected to the button is in the output state and the value of the element corresponding to the button is valid, the value of the output variable of the button is assigned to the value of the input variable of the button.

[0311] Upon completion of the first round of scanning, all elements in the key register array are reset to invalid values.

[0312] When the second round of scanning begins, based on the key labels triggered in the object whose jitter state is not the first jitter state, the value of the corresponding element in the key register array is set to a valid value.

[0313] If, during the scanning process of the scanning button circuit module, the scanning signal line connected to the button is in the output state and the value of the element corresponding to the button is valid, the value of the output variable of the button is assigned to the value of the input variable of the button.

[0314] Upon completion of the second round of scanning, all elements in the key register array are reset to invalid values.

[0315] In the process of simulating scanning, the scanning signal line of the scanning button circuit module is set to the output state in sequence, the signal variable corresponding to the scanning signal line is assigned the value of the scanning signal, and the value of the input variable of the button connected to the scanning signal line is assigned the value of the signal variable to simulate the scanning signal line being scanned.

[0316] During simulation scanning, the input variable of the button corresponds to the signal connection terminal connected to the scan signal line being scanned, the output variable corresponds to the other signal connection terminal of the button, and each element in the button register array corresponds one-to-one with each button in the simulated scanning button circuit.

[0317] Since the specific implementation of the scanning button circuit testing device is similar to the scanning button circuit testing method, the implementation of the method can be referred to, and will not be repeated here.

[0318] Based on the same inventive concept, embodiments of the present invention also provide an electronic device, such as... Figure 6 As shown, it includes: a processor 110 and a memory 120 for storing executable instructions of the processor 110; wherein, the processor 110 is configured to execute the instructions to implement the scanning key circuit testing method.

[0319] In specific implementations, the device may vary significantly due to differences in configuration or performance, and may include one or more processors 110 and a memory 120 for storing application programs 131 or data 132, and one or more storage media 130. The memory 120 and storage media 130 may be temporary or persistent storage. The application program 131 stored in the memory 120 may include one or more of the aforementioned units (…). Figure 6(Not shown in the image), each module may include a series of instruction operations on the device. Furthermore, the processor 110 may be configured to communicate with the storage medium 130 and execute a series of instruction operations on the storage medium 130 on the device. The device may also include one or more power supplies (…). Figure 6 (not shown in the image); one or more network interfaces 140, including a wired network interface 141 or a wireless network interface 142; one or more input / output interfaces 143; and / or one or more operating systems 133, such as Windows, Mac OS, Linux, IOS, Android, Unix, FreeBSD, etc.

[0320] Based on the same inventive concept, embodiments of the present invention also provide a computer storage medium storing a computer program, which is used to implement the scanning key circuit test.

[0321] The scanning button circuit testing method and apparatus provided in this invention significantly improves the efficiency of circuit verification compared to manual testing by automatically generating test samples using simulation software.

[0322] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0323] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0324] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0325] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0326] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for testing a scanning key circuit, characterized in that, include: Based on the VMM verification method from the verification method manual, a key data class is generated. The key data class includes random variables and constraints on the values ​​of the random variables. The random variables include random variables corresponding to the number of triggered keys, random variables corresponding to the number of triggered keys, and random variables corresponding to the bounce state of the triggered keys. The constraints on the values ​​of the random variables include that the number of random variables corresponding to the bounce state is consistent with the number of triggered keys. The bounce state includes a no-bounce state and a bounced state. The bounced state is a triggered state in which the duration of the trigger is less than a preset trigger duration. An object is obtained by instantiating the key data class, and the object includes the number of triggered keys and the key number of the triggered keys; The object is used as a random test sample to stimulate the simulation of the scanning key circuit module. During the simulation scanning process of the scanning key circuit module, the keys corresponding to each key label in the object are simulated to be triggered. Verify the correctness of the scanning button circuit module based on the register values ​​related to button triggering in the scanning button circuit module; The registers related to key triggering include status registers corresponding to each key triggering state and / or interrupt registers that implement key interruption functions.

2. The method as described in claim 1, characterized in that, The constraints on the values ​​of the random variable also include: The number of triggered buttons is a natural number and is not greater than the total number of buttons in the simulated scanning button circuit; The triggered button number belongs to the button number in the simulated scanning button circuit, and when there are multiple triggered button numbers, each button number is different from the others.

3. The method as described in claim 1, characterized in that, The scanning button circuit module performs two rounds of cyclic scanning in each simulation. The jittering state includes a first jittering state and a second jittering state. The first jittering state is used to activate the corresponding button during the first round of cyclic scanning, but not during the second round of cyclic scanning. The second jittering state is used to activate the corresponding button during the second round of cyclic scanning, but not during the first round of cyclic scanning.

4. The method according to any one of claims 1-3, characterized in that, Instantiating the button data class to obtain an object includes: Based on the constraints of the random variable values ​​of the key data class, the number of triggered keys, the key number of triggered keys, and the bounce state of the triggered keys are determined in a random manner.

5. The method as described in claim 1 or 2, characterized in that, The object is used as a random test sample to stimulate the simulation of a scanning key circuit module. During the simulation scanning process of the scanning key circuit module, the keys corresponding to each key label in the object are simulated to be triggered, including: At the start of each scan, the value of the corresponding element in the key register array is set to a valid value according to the key number triggered in the object; If, during the scanning process of the scanning button circuit module, the scanning signal line connected to the button is in the output state and the value of the element corresponding to the button is valid, the value of the output variable of the button is assigned to the value of the input variable of the button. Upon completion of this scan, all elements in the key register array are reset to invalid values. In the process of simulating scanning, the scanning signal line of the scanning button circuit module is set to the output state in sequence, the signal variable corresponding to the scanning signal line is assigned the value of the scanning signal, and the value of the input variable of the button connected to the scanning signal line is assigned the value of the signal variable to simulate the scanning signal line being scanned. During simulation scanning, the input variable of the button corresponds to the signal connection terminal connected to the scan signal line being scanned, the output variable corresponds to the other signal connection terminal of the button, and each element in the button register array corresponds one-to-one with each button in the simulated scanning button circuit.

6. The method as described in claim 3, characterized in that, The object is used as a random test sample to stimulate the simulation of a scanning key circuit module. During the simulation scanning process of the scanning key circuit module, the keys corresponding to each key label in the object are simulated to be triggered, including: At the start of the first round of scanning, based on the key labels triggered in the object whose jitter state is not the second jitter state, the value of the corresponding element in the key register array is set to a valid value; If, during the scanning process of the scanning button circuit module, the scanning signal line connected to the button is in the output state and the value of the element corresponding to the button is valid, the value of the output variable of the button is assigned to the value of the input variable of the button. Upon completion of the first round of scanning, all elements in the key register array are reset to invalid values. When the second round of scanning begins, based on the key labels triggered in the object whose jitter state is not the first jitter state, the value of the corresponding element in the key register array is set to a valid value. If, during the scanning process of the scanning button circuit module, the scanning signal line connected to the button is in the output state and the value of the element corresponding to the button is valid, the value of the output variable of the button is assigned to the value of the input variable of the button. Upon completion of the second round of scanning, all elements in the key register array are reset to invalid values. In the process of simulating scanning, the scanning signal line of the scanning button circuit module is set to the output state in sequence, the signal variable corresponding to the scanning signal line is assigned the value of the scanning signal, and the value of the input variable of the button connected to the scanning signal line is assigned the value of the signal variable to simulate the scanning signal line being scanned. During simulation scanning, the input variable of the button corresponds to the signal connection terminal connected to the scan signal line being scanned, the output variable corresponds to the other signal connection terminal of the button, and each element in the button register array corresponds one-to-one with each button in the simulated scanning button circuit.

7. A testing device for scanning key circuits, characterized in that, include: An abstract unit is used to generate key data classes based on the VMM verification method from the verification method manual. The key data classes include random variables and constraints on the values ​​of the random variables. The random variables include random variables corresponding to the number of triggered keys, random variables corresponding to the number of triggered keys, and random variables corresponding to the bounce state of the triggered keys. The constraints on the values ​​of the random variables include that the number of random variables corresponding to the bounce state is consistent with the number of triggered keys. The bounce state includes a no-bounce state and a bounced state. The bounced state is a triggered state in which the duration of the trigger is less than a preset trigger duration. A random instance generation unit is used to instantiate the key data class to obtain an object, the object including the number of triggered keys and the key number of the triggered keys; The test unit is used to stimulate the scanning key circuit module of the simulation using the object as a random test sample, and to simulate the triggering of the keys corresponding to each key label in the object during the simulation scanning process of the scanning key circuit module. The verification unit is used to verify whether the scanning button circuit is correct based on the register values ​​related to button triggering in the scanning button circuit module. The registers related to key triggering include status registers corresponding to each key triggering state and / or interrupt registers that implement key interruption functions.

8. An electronic device, characterized in that, include: A processor and a memory for storing processor-executable instructions; The processor is configured to execute the instructions to implement the scanning key circuit testing method as described in any one of claims 1-6.

9. A computer storage medium, characterized in that, The computer storage medium stores a computer program, which is used to implement the scanning key circuit testing method as described in any one of claims 1-6.

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