Shift register unit and driving method thereof, gate driving circuit and driving method thereof

Abstract

A shift register unit comprises: a pull-up circuit connected to an input signal terminal, a total pull-up node and a pull-down node, configured to provide the input signal terminal signal to the total pull-up node, and to pull down the total pull-up node potential; a control circuit connected to the total pull-up node and the pull-down node, configured to control the pull-down node potential; a cascade circuit connected to the total pull-up node, the pull-down node, a cascade output terminal and a control clock signal terminal, configured to provide the control clock signal terminal signal to the cascade output terminal, and to pull down the cascade output terminal potential; and an nth output circuit in N output circuits connected to the input signal terminal, the pull-down node, an nth output signal terminal and an nth partial pull-up node, configured to input the input signal terminal signal to the nth partial pull-up node, to provide the nth output clock signal terminal signal to the nth output signal terminal under the control of the potential thereof, and to pull down the nth output signal terminal potential under the control of the pull-down node potential.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register unit and its driving method, as well as a gate driving circuit and its driving method. Background Technology

[0002] In existing display devices, at least one gate driving circuit is typically included. When the display device displays an image, the gate driving circuit can scan each sub-pixel row of the display device, thereby charging each sub-pixel in the sub-pixel row according to the image data corresponding to the image to be displayed, so as to realize image display. Summary of the Invention

[0003] On one hand, a shift register unit is provided, including a pull-up circuit, a control circuit, a cascaded circuit, and N output circuits. The pull-up circuit is connected to the input signal terminal, a main pull-up node, and a pull-down node of the shift register unit. The pull-up circuit is configured to provide the signal from the input signal terminal to the main pull-up node and pull down the potential of the main pull-up node under the control of the potential of the pull-down node. The control circuit is connected to the main pull-up node and the pull-down node and is configured to control the potential of the pull-down node according to the potential of the main pull-up node. The cascaded circuit is connected to the main pull-up node, the pull-down node, the cascaded output terminal of the shift register unit, and a control clock signal terminal. The cascaded circuit is configured to provide the signal from the control clock signal terminal to the cascaded output terminal under the control of the potential of the main pull-up node and pull down the potential of the cascaded output terminal under the control of the potential of the pull-down node. N output circuits are respectively connected to the input signal terminal, the pull-down node, and the N output clock signal terminals, N sub-pull-up nodes, and N output signal terminals of the shift register unit. The nth output circuit is connected to the input signal terminal, the pull-down node, the nth output signal terminal, and the nth sub-pull-up node, and is configured to input the signal from the input signal terminal to the nth sub-pull-up node, provide the signal from the nth output clock signal terminal to the nth output signal terminal under the control of the potential of the nth sub-pull-up node, and pull down the potential of the nth output signal terminal under the control of the potential of the pull-down node. N is an integer greater than 1, and n is an integer where 1 ≤ n ≤ N.

[0004] In some embodiments, the nth output circuit includes: an input sub-circuit, an output sub-circuit, and a pull-down sub-circuit. The input sub-circuit is connected to the input signal terminal and the nth pull-up node, and is configured to provide the signal from the input signal terminal to the nth pull-up node. The output sub-circuit is connected to the nth pull-up node, the nth output clock signal terminal, and the nth output signal terminal, and is configured to provide the signal from the nth output clock signal terminal to the nth output signal terminal under the control of the potential of the nth pull-up node. The pull-down sub-circuit is connected to the pull-down node and is configured to pull down the potential of the nth pull-up node and the nth output signal terminal under the control of the potential of the pull-down node.

[0005] In some embodiments, the pull-down node includes a first pull-down node and a second pull-down node, and the pull-down sub-circuit includes a first pull-down sub-circuit and a second pull-down sub-circuit. The first pull-down sub-circuit is connected to the first pull-down node and is configured to pull down the potential of at least one of the nth pull-up node and the nth output signal terminal under the control of the potential of the first pull-down node. The second pull-down sub-circuit is connected to the second pull-down node and is configured to pull down the potential of at least one of the nth pull-up node and the nth output signal terminal under the control of the potential of the second pull-down node.

[0006] In some embodiments, the control circuit includes: a first control sub-circuit and a second control sub-circuit. The first control sub-circuit is connected to the main pull-up node and the first pull-down node, and is configured to control the potential of the first pull-down node based on the potential of the main pull-up node. The second control sub-circuit is connected to the main pull-up node and the second pull-down node, and is configured to control the potential of the second pull-down node based on the potential of the main pull-up node.

[0007] In some embodiments, the nth output circuit further includes a reset sub-circuit, connected to the nth pull-up node and the reset signal terminal and reference signal terminal of the shift register unit, and configured to reset the nth pull-up node using the potential of the reference signal terminal under the control of the signal at the reset signal terminal.

[0008] In some embodiments, the input sub-circuit is also connected to a power signal terminal and is configured to provide the potential of the power signal terminal to the nth pull-up node under the control of a signal at the input signal terminal.

[0009] In some embodiments, the first output clock signal terminal among the N output clock signal terminals is connected to the control clock signal terminal.

[0010] In some embodiments, the input sub-circuit includes: a first transistor, the gate and a first terminal of the first transistor being connected to the input signal terminal, and the second terminal of the first transistor being connected to the nth pull-up node.

[0011] In some embodiments, the input sub-circuit includes: a first transistor, the gate of the first transistor being connected to the input signal terminal, a first terminal of the first transistor being connected to the power signal terminal, and a second terminal of the first transistor being connected to the nth pull-up node.

[0012] In some embodiments, the output sub-circuit includes a second transistor and a first capacitor. The gate of the second transistor is connected to the nth pull-up node, the first terminal of the second transistor is connected to the nth output clock signal terminal, and the second terminal of the second transistor is connected to the nth output signal terminal. The first capacitor has its first terminal connected to the nth pull-up node and its second terminal connected to the nth output signal terminal.

[0013] In some embodiments, the pull-down sub-circuit includes a third transistor and a fourth transistor. The gate of the third transistor is connected to the pull-down node, the first terminal of the third transistor is connected to the first reference signal terminal of the shift register unit, and the second terminal of the third transistor is connected to the nth pull-up node. The gate of the fourth transistor is connected to the pull-down node, the first terminal of the fourth transistor is connected to the second reference signal terminal of the shift register unit, and the second terminal of the fourth transistor is connected to the nth output signal terminal.

[0014] In some embodiments, the first pull-down sub-circuit includes a third transistor and a fourth transistor. The gate of the third transistor is connected to the first pull-down node, the first terminal of the third transistor is connected to the first reference signal terminal of the shift register unit, and the second terminal of the third transistor is connected to the nth pull-up node. The gate of the fourth transistor is connected to the first pull-down node, the first terminal of the fourth transistor is connected to the second reference signal terminal of the shift register unit, and the second terminal of the fourth transistor is connected to the nth output signal terminal. The second pull-down sub-circuit includes a fifth transistor and a sixth transistor. The gate of the fifth transistor is connected to the second pull-down node, the first terminal of the fifth transistor is connected to the first reference signal terminal, and the second terminal of the fifth transistor is connected to the nth pull-up node. The gate of the sixth transistor is connected to the second pull-down node, the first terminal of the sixth transistor is connected to the second reference signal terminal, and the second terminal of the sixth transistor is connected to the nth output signal terminal.

[0015] In some embodiments, the reset sub-circuit includes a seventh transistor, the gate of which is connected to the reset signal terminal, the first terminal of which is connected to the reference signal terminal, and the second terminal of which is connected to the nth pull-up node.

[0016] In some embodiments, the control circuit includes an eighth transistor and a ninth transistor. The eighth transistor has its gate and a first terminal connected to the power supply signal terminal of the shift register unit, and its second terminal connected to the pull-down node. The ninth transistor has its gate connected to the overall pull-up node, its first terminal connected to the reference signal terminal of the shift register unit, and its second terminal connected to the pull-down node.

[0017] In some embodiments, the first control sub-circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The gate and first terminal of the tenth transistor are connected to the power supply signal terminal of the shift register unit. The second terminal of the tenth transistor is connected to the gate of the eleventh transistor. The first terminal of the eleventh transistor is connected to the power supply signal terminal and the second terminal of the eleventh transistor is connected to the first pull-down node. The gate of the twelfth transistor is connected to the total pull-up node. The first terminal of the twelfth transistor is connected to the reference signal terminal of the shift register unit and the second terminal of the twelfth transistor is connected to the gate of the eleventh transistor. The gate of the thirteenth transistor is connected to the total pull-up node. The first terminal of the thirteenth transistor is connected to the reference signal terminal and the second terminal of the thirteenth transistor is connected to the first pull-down node. The second control sub-circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor. The gate and first terminal of the fourteenth transistor are connected to the power supply signal terminal. The second terminal of the fourteenth transistor is connected to the gate of the fifteenth transistor. The first terminal of the fifteenth transistor is connected to the power supply signal terminal and the second terminal of the fifteenth transistor is connected to the second pull-down node. The gate of the sixteenth transistor is connected to the total pull-up node. The first terminal of the sixteenth transistor is connected to the reference signal terminal and the second terminal of the sixteenth transistor is connected to the gate of the fifteenth transistor. The gate of the seventeenth transistor is connected to the total pull-up node. The first terminal of the seventeenth transistor is connected to the reference signal terminal and the second terminal of the seventeenth transistor is connected to the second pull-down node.

[0018] In some embodiments, the pull-up circuit includes: an eighteenth transistor, a nineteenth transistor, and a twentieth transistor. The gate and first terminal of the eighteenth transistor are connected to the input signal terminal, and the second terminal of the eighteenth transistor is connected to the overall pull-up node. The nineteenth transistor has its gate connected to the pull-down node, its first terminal connected to the reference signal terminal of the shift register unit, and its second terminal connected to the overall pull-up node. The twentieth transistor has its gate connected to the reset signal terminal of the shift register unit, its first terminal connected to the reference signal terminal, and its second terminal connected to the overall pull-up node.

[0019] In some embodiments, the pull-down node includes a first pull-down node and a second pull-down node, and the pull-up circuit further includes a twenty-first transistor. The gate of the nineteenth transistor is connected to the first pull-down node, the gate of the twenty-first transistor is connected to the second pull-down node, the first terminal of the twenty-first transistor is connected to the reference signal terminal, and the second terminal of the twenty-first transistor is connected to the overall pull-up node.

[0020] In some embodiments, the cascaded circuit includes: a twenty-second transistor, a twenty-third transistor, and a second capacitor. The gate of the twenty-second transistor is connected to the overall pull-up node, the first terminal of the twenty-second transistor is connected to the control clock signal terminal, and the second terminal of the twenty-second transistor is connected to the cascaded output terminal. The twenty-third transistor has its gate connected to the pull-down node, its first terminal connected to the reference signal terminal of the shift register unit, and its second terminal connected to the cascaded output terminal. The second capacitor has its first terminal connected to the gate of the twenty-second transistor, and its second terminal connected to the cascaded output terminal.

[0021] In some embodiments, the pull-down node includes a first pull-down node and a second pull-down node, and the cascaded circuit further includes a twenty-fourth transistor. The gate of the twenty-fourth transistor is connected to the first pull-down node, the gate of the twenty-fourth transistor is connected to the second pull-down node, the first terminal of the twenty-fourth transistor is connected to the reference signal terminal, and the second terminal of the twenty-fourth transistor is connected to the cascaded output terminal.

[0022] In some embodiments, the shift register unit further includes a total reset circuit. The total reset circuit includes a twenty-fifth transistor, the gate of which is connected to the total reset terminal of the shift register unit, the first terminal of which is connected to the reference signal terminal of the shift register unit, and the second terminal of which is connected to the total pull-up node.

[0023] In some embodiments, N = 4 or 2.

[0024] On the other hand, a gate driving circuit is provided, comprising M cascaded shift register units, which are shift register units as described above. The input signal terminal of the m-th stage shift register unit is connected to the cascaded output terminal of the (m-1)-th stage shift register unit, and the reset signal terminal of the m-th stage shift register unit is connected to the cascaded output terminal of the (m+2)-th stage shift register unit, where M is an integer greater than 1, m is an integer and 1 < m < M-1. The M cascaded shift register units are connected to K clock signal lines, where K is an even number greater than or equal to 2N.

[0025] In some embodiments, N=4, K=12, and the M-stage cascaded shift register units are divided into multiple groups. Each group includes a first shift register unit, a second shift register unit, and a third shift register unit cascaded in three stages. The N output clock signal terminals of the first shift register unit are connected one-to-one with the first to fourth clock signal lines, the N output clock signal terminals of the second shift register unit are connected one-to-one with the fifth to eighth clock signal lines, and the N output clock signal terminals of the third shift register unit are connected one-to-one with the ninth to twelfth clock signal lines.

[0026] In some embodiments, N=4, K=8, the M-stage cascaded shift register units are divided into multiple groups, each group including a first shift register unit and a second shift register unit cascaded in two stages, wherein the N output clock signal terminals of the first shift register unit are connected one-to-one with the first clock signal line to the fourth clock signal line, and the N output clock signal terminals of the second shift register unit are connected one-to-one with the fifth clock signal line to the eighth clock signal line.

[0027] In some embodiments, the first output clock signal of the N output clock signal terminals of each shift register unit is connected to the control clock signal terminal of the shift register unit.

[0028] In some embodiments, N=2, K=6, and the K clock signal lines include a first control clock signal line, a second control clock signal line, a first output clock signal line, a second output clock signal line, a third output clock signal line, and a fourth output clock signal line. The M-stage cascaded shift register units are divided into multiple groups, each group including two-stage cascaded first shift register units and second shift register units. The N output clock signal terminals of the first shift register unit are connected one-to-one with the first and second output clock signal lines, and the control clock signal terminal of the first shift register unit is connected to the first control clock signal line. The N output clock signal terminals of the second shift register unit are connected one-to-one with the third and fourth clock signal lines, and the control clock signal terminal of the second shift register unit is connected to the second control clock signal line.

[0029] Furthermore, a driving method for the aforementioned shift register unit is provided. The method includes: in a first time period, a pull-up circuit provides a first level of the input signal terminal to the main pull-up node, and the nth output circuit among the N output circuits inputs the first level of the input signal terminal to the nth sub-pull-up node; in a second time period, a cascaded circuit, under the control of the potential of the main pull-up node, provides a signal of the control clock signal terminal to the cascaded output terminal, and the nth output circuit among the N output circuits, under the control of the potential of the nth sub-pull-up node, provides a signal of the nth output clock signal terminal to the nth output signal terminal; and in a third time period, the pull-up circuit provides a second level of the input signal terminal to the main pull-up node, the potential of the pull-up node causes the control circuit to control the pull-down node to a first level, the potential of the pull-down node causes the cascaded circuit to pull down the cascaded output terminal to a second level, and causes the nth output circuit among the N output circuits to pull down the nth output signal terminal to the second level.

[0030] On another front, another driving method for the aforementioned shift register unit is provided. This method includes: in a first mode, applying K first clock signals, each shifted row-by-row, to the K clock signal lines, causing the M-stage shift register unit of the gate driving circuit to generate a plurality of first output signals, each shifted row-by-row; and in a second mode, applying K second clock signals, each shifted k rows-by-row, to the K clock signal lines, causing the M-stage shift register unit of the gate driving circuit to generate a plurality of second output signals, each shifted k rows-by-row, wherein the frequency of the K second clock signals is k times the frequency of the K first clock signals, where k is an integer less than or equal to K.

[0031] In some embodiments, N = 4, K = 12 or 8, and k = 2 or 4.

[0032] In another aspect, a driving method for the aforementioned gate driving circuit is provided. The K clock signal lines include multiple output clock signal lines. The method includes: in a first mode, applying multiple first output clock signals that are sequentially shifted row-by-row to the multiple output clock signal lines, causing the M-stage shift register unit of the gate driving circuit to generate multiple first output signals that are sequentially shifted row-by-row, wherein each of the N output circuits of the shift register unit generates an output signal; in a second mode, applying multiple second output clock signals to a portion of the multiple output clock signal lines, causing the M-stage shift register unit of the gate driving circuit to generate multiple second output signals that are sequentially shifted, wherein at least one of the N output circuits of each shift register does not generate an output signal.

[0033] In some embodiments, N=2, K=6, and the K clock signal lines include a first control clock signal line, a second control clock signal line, a first output clock signal line, a second output clock signal line, a third output clock signal line, and a fourth output clock signal line. In a first mode, a first control clock signal is applied to the first control clock signal line, a second control clock signal is applied to the second control clock signal line, and four sequentially shifted first output clock signals are applied to the first, second, third, and fourth output clock signal lines respectively, causing both output circuits of each shift register unit to generate an output signal. In a second mode, the first control clock signal is applied to the first control clock signal line, the second control clock signal is applied to the second control clock signal line, and two sequentially shifted second output clock signals are applied to either the odd or even number of clock signal lines among the first, second, third, and fourth output clock signal lines respectively, causing one of the two output circuits of each shift register unit to generate an output signal.

[0034] In some embodiments, the period of the second output clock signal is equal to the period of the first output clock signal, and the duty cycle of the second output clock signal is greater than the duty cycle of the first output clock signal. Attached Figure Description

[0035] Figure 1 This is a schematic block diagram of a shift register unit according to some embodiments;

[0036] Figure 2 This is a circuit diagram of a shift register unit according to some embodiments;

[0037] Figure 3 This is a circuit diagram of another shift register unit according to some embodiments;

[0038] Figure 4 This is a circuit diagram of yet another shift register unit according to some embodiments;

[0039] Figure 5 This is a circuit diagram of yet another shift register unit according to some embodiments;

[0040] Figure 6 This is a schematic diagram of a gate drive circuit according to some embodiments;

[0041] Figure 7 This is a schematic diagram of another gate drive circuit according to some embodiments;

[0042] Figure 8 This is a schematic diagram of another gate drive circuit according to some embodiments;

[0043] Figure 9 This is a signal timing diagram of a shift register unit driving method according to some embodiments;

[0044] Figure 10 This is a signal timing diagram of a gate drive circuit driving method in a first mode according to some embodiments;

[0045] Figure 11 This is a signal timing diagram of a gate drive circuit driving method in a second mode according to some embodiments;

[0046] Figure 12 This is a signal timing diagram of a driving method for another gate driving circuit according to some embodiments in a first mode;

[0047] Figure 13 This is a signal timing diagram of a second mode for another gate drive circuit driving method according to some embodiments; and

[0048] Figure 14 This is a signal timing diagram of a gate drive circuit driving method according to some embodiments in the first and second modes. Detailed Implementation

[0049] While this disclosure will be fully described with reference to the accompanying drawings containing preferred embodiments, it should be understood before this description that those skilled in the art can modify the disclosure described herein to obtain the technical effects of this disclosure. Therefore, it should be understood that the above description is a broad disclosure to those skilled in the art and is not intended to limit the exemplary embodiments described herein.

[0050] Furthermore, in the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments disclosed herein. However, it will be apparent that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and apparatuses are illustrated to simplify the figures.

[0051] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0052] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0053] In the description of embodiments of this disclosure, the terms “connected to,” “connected,” or “electrically connected” can refer to two components being directly connected, or to two components being connected via one or more other components.

[0054] In related technologies, display devices typically include a display panel and at least one gate driving circuit electrically connected to the display panel. Exemplarily, the gate driving circuit can be fabricated independently of the display panel, and the two can be connected together via, for example, a flexible printed circuit board. As another example, during the manufacturing process of the display panel, the aforementioned gate driving circuit can be directly fabricated on the substrate of the display panel, for example, in the peripheral area surrounding the display area of ​​the display panel; this technology is also known as GOA (Gate On Array) technology. When a display device employs GOA technology, each sub-pixel in a sub-pixel row of the display panel can be driven by a corresponding shift register unit in the gate driving circuit.

[0055] However, when the display device has a high resolution and a high refresh rate (e.g., 8K resolution), the number of shift register units required by the display device is large, which will result in a larger bezel size and affect the aesthetics of the product.

[0056] See Figure 1Some embodiments of this disclosure provide a shift register unit 100. The shift register unit 100 includes a pull-up circuit 10, a control circuit 20, a cascaded circuit 30, and N output circuits 40.

[0057] Pull-up circuit 10 is connected to the input signal terminal INPUT, the main pull-up node PU, and the pull-down node PD of the shift register unit 100. Pull-up circuit 10 is configured to provide the signal of the input signal terminal INPUT to the main pull-up node PU, and pull down the potential of the main pull-up node PU under the control of the potential of the pull-down node PD.

[0058] The control circuit 20 is connected to the main pull-up node PU and the pull-down node PD. The control circuit 20 is configured to control the potential of the pull-down node PD according to the potential of the main pull-up node PU.

[0059] The cascade circuit 30 is connected to the cascade output terminal OUT_C ​​and the control clock signal terminal CLK_C of the main pull-up node PU, the pull-down node PD, and the shift register unit 100. The cascade circuit 30 is configured to provide the signal of the control clock signal terminal CLK_C to the cascade output terminal OUT_C ​​under the control of the potential of the main pull-up node PU, and to pull down the potential of the cascade output terminal OUT_C ​​under the control of the potential of the pull-down node PD.

[0060] N output circuits 40 are respectively connected to the input signal terminal INPUT, the pull-down node PD, and the N output clock signal terminals of the shift register unit 100 (e.g., Figure 1 CLK_1 to CLK_N), and N sub-pull-up nodes (e.g., Figure 1 PU_1 to PU_N) and N output signal terminals (e.g., Figure 1 The nth output circuit 40 is connected to the input signal terminal INPUT, the pull-down node PD, the nth output signal terminal OUT_n, and the nth pull-up node PU_n. It is configured to input the signal from the input signal terminal INPUT to the nth pull-up node PU_n, provide the signal from the nth output clock signal terminal CLK_n to the nth output signal terminal OUT_n under the control of the potential of the nth pull-up node PU_n, and pull down the potential of the nth output signal terminal OUT_n under the control of the potential of the pull-down node PD. Here, N is an integer greater than 1, and n is an integer where 1 ≤ n ≤ N. In some embodiments, 2 ≤ N ≤ 8; for example, N can be 2, 3, 4, 5, or 6.

[0061] The embodiments of this disclosure employ a structure where N output circuits share a single control circuit within a shift register unit. This allows the shift register unit to independently generate multiple output signals, replacing the traditional combination of multiple shift register units, resulting in a simpler circuit structure. For example, in the aforementioned shift register unit, N output circuits share a single control circuit, controlled by the potential of the same pull-down node PD. Each output circuit includes its own pull-up node, enabling it to generate outputs independently. Compared to related technologies, when driving the same number of sub-pixel rows, the shift register unit of the embodiments of this disclosure can reduce the number of required control circuits, resulting in a simpler circuit structure and facilitating a reduction in the bezel size of the display device.

[0062] Figure 2 This is a circuit diagram of a shift register unit 200 according to some embodiments.

[0063] like Figure 2 As shown, the shift register unit 200 includes a pull-up circuit 10, a control circuit 20, a cascaded circuit 30, and N output circuits. N can be 2, that is, the N output circuits include a first output circuit 40_1 and a second output circuit 40_2 (hereinafter collectively referred to as output circuit 40). The first output circuit 40_1 and the second output circuit 40_2 share a control circuit 20. In this case, the shift register unit 200 may include a first output clock signal terminal CLK_1 and a second output clock signal terminal CLK_2, a first output signal terminal OUT_1 and a second output signal terminal OUT_2, a first pull-up node PU_1, and a second pull-up node PU_2.

[0064] See Figure 2 Each output circuit 40 includes an input sub-circuit 401, an output sub-circuit 402, and a pull-down sub-circuit 403. The structure of the output sub-circuit will be explained below using any one of the output sub-circuits 40 (i.e., the nth output sub-circuit 40, n = 1 or 2) as an example.

[0065] The input sub-circuit 401 is connected to the input signal terminal INPUT and the nth pull-up node PU_n, and is configured to provide the signal of the input signal terminal INPUT to the nth pull-up node PU_n.

[0066] The output sub-circuit 402 is connected to the nth pull-up node PU_n, the nth output clock signal terminal CLK_n, and the nth output signal terminal OUT_n, and is configured to provide the signal of the nth output clock signal terminal CLK_n to the nth output signal terminal OUT_n under the control of the potential of the nth pull-up node PU_n.

[0067] The pull-down sub-circuit 403 is connected to the pull-down node PD and is configured to pull down the potential of the nth sub-pull-up node PU_n and the nth output signal terminal OUT_n under the control of the potential of the pull-down node PD.

[0068] like Figure 2 As shown, in the first output circuit 40_1, the input sub-circuit 401 may include a first transistor M1. The gate and the first terminal of the first transistor M1 are connected to the input signal terminal INPUT, and the second terminal of the first transistor M1 is connected to the first pull-up node PU_1.

[0069] In the first output circuit 40_1, the output sub-circuit 402 may include a second transistor M2 and a first capacitor C1. The gate of the second transistor M2 is connected to the first pull-up node PU_1, the first terminal of the second transistor M2 is connected to the first output clock signal terminal CLK_1, and the second terminal of the second transistor M2 is connected to the first output signal terminal OUT_1. The first terminal of the first capacitor C1 is connected to the first pull-up node PU_1, and the second terminal of the first capacitor C1 is connected to the first output signal terminal OUT_1.

[0070] In the first output circuit 40_1, the pull-down sub-circuit 403 may include a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 is connected to the pull-down node PD, the first terminal of the third transistor M3 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit 200, and the second terminal of the third transistor M3 is connected to the first pull-up node PU_1. The gate of the fourth transistor M4 is connected to the pull-down node PD, the first terminal of the fourth transistor M4 is connected to the reference signal terminal (e.g., the second reference signal terminal VGL) of the shift register unit 200, and the second terminal of the fourth transistor M4 is connected to the first output signal terminal OUT_1.

[0071] The second output circuit 40_2 has a similar structure to the second output circuit 40_1, the difference being that it connects the second pull-up node PU_2, the second output clock signal terminal CLK_2, and the second output signal terminal OUT_2. For example... Figure 2As shown, in the second output circuit 40_2, the gate and first terminal of the first transistor M1 are connected to the input signal terminal INPUT, and the second terminal of the first transistor M1 is connected to the second pull-up node PU_2. The gate of the second transistor M2 is connected to the second pull-up node PU_2, the first terminal of the second transistor M2 is connected to the second output clock signal terminal CLK_2, and the second terminal of the second transistor M2 is connected to the second output signal terminal OUT_2. The first terminal of the first capacitor C1 is connected to the second pull-up node PU_2, and the second terminal of the first capacitor C1 is connected to the second output signal terminal OUT_2. The gate of the third transistor M3 is connected to the pull-down node PD, the first terminal of the third transistor M3 is connected to the first reference signal terminal LVGL, and the second terminal of the third transistor M3 is connected to the second pull-up node PU_2. The gate of the fourth transistor M4 is connected to the pull-down node PD, the first terminal of the fourth transistor M4 is connected to the second reference signal terminal VGL, and the second terminal of the fourth transistor M4 is connected to the second output signal terminal OUT_2.

[0072] The control circuit 20 may include an eighth transistor M8 and a ninth transistor M9. The gate and first terminal of the eighth transistor M8 are connected to the power supply signal terminal VDD of the shift register unit 200, and the second terminal of the eighth transistor M8 is connected to the pull-down node PD. The gate of the ninth transistor M9 is connected to the total pull-up node PU, the first terminal of the ninth transistor M9 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit 200, and the second terminal of the ninth transistor M9 is connected to the pull-down node PD.

[0073] The pull-up circuit 10 includes an eighteenth transistor M18, a nineteenth transistor M19, and a twentieth transistor M20. The gate and first terminal of the eighteenth transistor M18 are connected to the input signal terminal INPUT, and the second terminal of the eighteenth transistor M18 is connected to the total pull-up node PU. The gate of the nineteenth transistor M19 is connected to the pull-down node, and the first terminal of the nineteenth transistor M19 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit 200. The second terminal of the nineteenth transistor M19 is connected to the total pull-up node PU. The gate of the twentieth transistor M20 is connected to the reset signal terminal RST_PU of the shift register unit, and the first terminal of the twentieth transistor M20 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL). The second terminal of the twentieth transistor M20 is connected to the total pull-up node PU.

[0074] The cascaded circuit 30 may include a twenty-second transistor M22, a twenty-third transistor M23, and a second capacitor C2. The gate of the twenty-second transistor M22 is connected to the overall pull-up node PU, its first terminal is connected to the control clock signal terminal CLK_C, and its second terminal is connected to the cascaded output terminal OUT_C. The gate of the twenty-third transistor M23 is connected to the pull-down node PD, its first terminal is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit 100, and its second terminal is connected to the cascaded output terminal OUT_C. The first terminal of the second capacitor C2 is connected to the gate of the twenty-second transistor M22, and its second terminal is connected to the cascaded output terminal OUT_C.

[0075] Figure 3 This is a circuit diagram of another shift register unit 300 according to some embodiments. Figure 3 circuit and Figure 2 Similarly, the difference lies at least in that the pull-down nodes of the shift register unit include a first pull-down node PD_1 and a second pull-down node PD_2. To simplify the description, the differences will be explained in detail below.

[0076] See Figure 3 Each output circuit 40_1 and 40_2 may include a first pull-down circuit and a second pull-down circuit. Figure 3 In this circuit, the first pull-down circuit includes the third transistor M3 and the fourth transistor M4. The second pull-down circuit includes the fifth transistor M5 and the sixth transistor M6. The structure of the output circuit will be explained below using the first output circuit 40_1 as an example.

[0077] In the output circuit 40_1, a first pull-down sub-circuit is connected to the first pull-down node PD_1 and is configured to pull down the potentials of the first pull-up node PU_1 and the first output signal terminal OUT_1 under the control of the potential of the first pull-down node PD_1. For example, the first pull-down sub-circuit includes a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 is connected to the first pull-down node PD_1, the first terminal of the third transistor M3 is connected to the first reference signal terminal LVGL, and the second terminal of the third transistor M3 is connected to the first pull-up node PU_1. The gate of the fourth transistor M4 is connected to the first pull-down node PD_1, the first terminal of the fourth transistor M4 is connected to the second reference signal terminal VGL, and the second terminal of the fourth transistor M4 is connected to the first output signal terminal OUT_1.

[0078] In output circuit 40_1, a second pull-down sub-circuit is connected to a second pull-down node PD_2 and is configured to pull down the potentials of the second pull-up node PU_2 and the second output signal terminal OUT_2 under the control of the potential of the second pull-down node PD_2. For example, the second pull-down sub-circuit includes a fifth transistor M5 and a sixth transistor M6. The gate of the fifth transistor M5 is connected to the second pull-down node PD_2, the first terminal of the fifth transistor M5 is connected to the first reference signal terminal LVGL, and the second terminal of the fifth transistor M5 is connected to the first pull-up node PU_1. The gate of the sixth transistor M6 is connected to the second pull-down node PD_2, the first terminal of the sixth transistor M6 is connected to the second reference signal terminal VGL, and the second terminal of the sixth transistor M6 is connected to the first output signal terminal OUT_1.

[0079] The pull-down circuit of the second output circuit 40_2 has a similar structure to that of the first output circuit 40_1, and will not be described in detail here.

[0080] In some embodiments, see Figure 3 Each output circuit 40_1 and 40_2 may further include a reset sub-circuit. The reset sub-circuit may include a seventh transistor M7. Taking the first output circuit 40_1 as an example, the gate of the seventh transistor M7 is connected to the reset signal terminal RST_PU, the first terminal of the seventh transistor M7 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL), and the second terminal of the seventh transistor M7 is connected to the first pull-up node PU_1. The reset sub-circuit of the second output circuit 40_2 has a similar structure, which will not be described further here.

[0081] exist Figure 3 In this circuit, the control circuit 20 may include a first control sub-circuit 201 and a second control sub-circuit 202. The first control sub-circuit 201 is connected to the total pull-up node PU and the first pull-down node PD_1, and is configured to control the potential of the first pull-down node PD_1 based on the potential of the total pull-up node PU. The second control sub-circuit 202 is connected to the total pull-up node PU and the second pull-down node PD_2, and is configured to control the potential of the second pull-down node PD_2 based on the potential of the total pull-up node PU.

[0082] The first control sub-circuit 201 may include a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13. The gate and first terminal of the tenth transistor M10 are connected to the power supply signal terminal (e.g., power supply signal terminal VDDO) of the shift register unit 300. The second terminal of the tenth transistor M10 is connected to the gate of the eleventh transistor M11, and the first terminal of the eleventh transistor M11 is connected to the power supply signal terminal (e.g., power supply signal terminal VDDO). The second terminal of the eleventh transistor M11 is connected to the first pull-down node PD_1. The gate of the twelfth transistor M12 is connected to the total pull-up node PU, and the first terminal of the twelfth transistor M12 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit 300. The second terminal of the twelfth transistor M12 is connected to the gate of the eleventh transistor M11. The gate of the thirteenth transistor M13 is connected to the total pull-up node PU, the first terminal of the thirteenth transistor M13 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL), and the second terminal of the thirteenth transistor M13 is connected to the first pull-down node PD_1.

[0083] The second control sub-circuit 202 may include a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17. The gate and first terminal of the fourteenth transistor M14 are connected to a power supply signal terminal (e.g., power supply signal terminal VDDE), and the second terminal of the fourteenth transistor M14 is connected to the gate of the fifteenth transistor M15. The first terminal of the fifteenth transistor M15 is connected to a power supply signal terminal (e.g., power supply signal terminal VDDE), and the second terminal of the fifteenth transistor M15 is connected to the second pull-down node PD_2. The gate of the sixteenth transistor M16 is connected to the total pull-up node PU, the first terminal of the sixteenth transistor M16 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL), and the second terminal of the sixteenth transistor M16 is connected to the gate of the fifteenth transistor M15. The gate of the seventeenth transistor M17 is connected to the total pull-up node, the first terminal of the seventeenth transistor M17 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL), and the second terminal of the seventeenth transistor M17 is connected to the second pull-down node PD_2.

[0084] By setting up a first control sub-circuit 201 and a second control sub-circuit 202 to control the signal output of N output circuits 40, the N output circuits 40 can be divided into two independent parts. One part is controlled by the first control sub-circuit 201 to output signals, and the other part is controlled by the first control sub-circuit 201 to output signals. Therefore, it is possible to realize the alternating opening and closing of the gates of sub-pixels in corresponding two sub-pixel rows.

[0085] exist Figure 3 In addition to the twenty-second transistor M22, the twenty-third transistor M23, and the second capacitor C2, the cascaded circuit 30 may also include a twenty-fourth transistor M24. The descriptions of the twenty-second transistor M22 and the twenty-third transistor M23 above also apply to... Figure 3 .exist Figure 3 In this configuration, the gate of the twenty-fourth transistor M24 is connected to the first pull-down node PD_1, the gate of the twenty-fourth transistor M24 is connected to the second pull-down node PD_2, the first terminal of the twenty-fourth transistor M24 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL), and the second terminal of the twenty-fourth transistor M24 is connected to the cascaded output terminal OUT_C.

[0086] exist Figure 3 In the circuit, pull-up circuit 10 includes not only the eighteenth transistor M18, the nineteenth transistor M19, and the twentieth transistor M20, but also the twenty-first transistor M21. (The last sentence appears to be incomplete and possibly refers to a different circuit.) Figure 2 The difference is that the gate of the nineteenth transistor M19 is connected to the first pull-down node PD_1, the gate of the twentieth transistor M20 is connected to the reset signal terminal RST_PU of the shift register unit 300, the first terminal of the twentieth transistor M20 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL), and the second terminal of the twentieth transistor M20 is connected to the total pull-up node PU.

[0087] In some embodiments, see Figure 3 The shift register unit 300 also includes a total reset circuit 50. The total reset circuit 50 may include a twenty-fifth transistor M25. The gate of the twenty-fifth transistor M25 is connected to the total reset terminal RST_T of the shift register unit 300, the first terminal of the twenty-fifth transistor M25 is connected to a reference signal terminal (e.g., the first reference signal terminal LVGL), and the second terminal of the twenty-fifth transistor M25 is connected to the total pull-up node PU.

[0088] Figure 4 This is a circuit diagram of another shift register unit 400 according to some embodiments. Figure 4 shift register 400 and Figure 2Similar to the shift register 200, the difference lies at least in the connection method of the input sub-circuits of each output circuit. For the sake of simplicity, the differences will be explained in detail below.

[0089] See Figure 4 The first input sub-circuit 40_1, in addition to being connected to the input signal terminal INPUT, is also connected to the power signal terminal VGH. The input sub-circuit 401 can provide the signal from the power signal terminal VGH to the first pull-up node PU_1 based on the potential of the signal at the input signal terminal INPUT. For example, in the input sub-circuit 401, the gate of the first transistor M1 is connected to the input signal terminal INPUT, the first terminal is connected to the power signal terminal VGH, and the second terminal is connected to the first pull-up node PU_1. The input sub-circuit 40_2 of the second input sub-circuit 40_2 is similar to the first input sub-circuit 40_1, and will not be described further here.

[0090] In some embodiments, the eighteenth transistor M18 in the input circuit 10 can also be connected in a similar manner. For example... Figure 14 As shown, the gate of the eighteenth transistor M18 is connected to the input signal terminal INPUT, the first terminal of the eighteenth transistor M18 is connected to the power supply signal terminal VGH, and the second terminal of the eighteenth transistor M18 is connected to the total pull-up node PU.

[0091] Since the power signal at the VGH terminal is relatively stable and not subject to crosstalk, the operational stability of the shift register unit can be improved.

[0092] Figure 5 This is a circuit diagram of yet another shift register unit according to some embodiments. Figure 5 shift register unit 500 and Figure 2 The shift register unit 200 is similar, with the difference being at least in the number of output circuits and the connection method of the clock signal terminal. For ease of description, the differences will be explained in detail below.

[0093] In shift register unit 500, N=4, meaning it includes 4 output circuits, 4 output clock signal terminals, 4 output signal terminals, and 4 pull-up nodes. For example... Figure 5As shown, the shift register unit 500 includes a first output circuit 40_1, a second output circuit 40_2, a third output circuit 40_3, and a fourth output circuit 40_4. The shift register unit 500 also includes first output clock signal terminals CLK_1 to fourth output clock signal terminals CLK_4, first output signal terminals OUT_1 to fourth output signal terminals OUT_4, and first output pull-up nodes PU_1 to fourth output pull-up nodes PU_2. Each output circuit is connected to a corresponding output clock signal terminal, a corresponding output signal terminal, and a corresponding pull-up node. For example, the first output circuit 40_1 is connected to the first output clock signal terminal CLK_1, the first output signal terminal OUT_1, and the first output pull-up node PU_1; the second output circuit 40_2 is connected to the second output clock signal terminal CLK_2, the second output signal terminal OUT_2, and the first output pull-up node PU_3, and so on. Figure 5 As shown, the structures and connection methods of the first output circuit 40_1, the second output circuit 40_2, the third output circuit 40_3, and the fourth output circuit 40_4 are the same as those in the above reference. Figure 2 The output circuit is described similarly, so it will not be repeated here.

[0094] exist Figure 5 In this circuit, the first output clock signal terminal CLK_1 is connected to the control clock signal terminal CLK_C as a single signal terminal. This reduces wiring and further simplifies the circuit structure.

[0095] Although Figure 5 The example illustrates that the first output clock signal terminal CLK_1 and the control clock signal terminal CLK_C can be connected to each other; however, the embodiments of this disclosure are not limited to this. In the shift register unit of any of the above embodiments, one of the N output clock signal terminals can be connected to the control clock signal terminal CLK_C.

[0096] Although Figure 5 The embodiments in Figure 2 The number of output circuits has been increased based on the shift register unit, however, the embodiments of this disclosure are not limited thereto. The number of output circuits of the shift register unit in any of the above embodiments can be set as needed. For example, the number of output circuits of the shift register units 300 and 400 described above can be set to 3, 4 or more.

[0097] Some embodiments of this disclosure provide a gate drive circuit, which will be referenced below. Figure 6 and Figure 7 This needs to be explained.

[0098] Figure 6 This is a schematic diagram of a gate drive circuit according to some embodiments.

[0099] See Figure 6 The gate drive circuit includes M cascaded shift register units GOA1, GOA2, ..., GOAM, and each shift register unit can be implemented by any of the shift register units in the above embodiments. Figure 6 For ease of description, the diagram uses M=3, representing GOA1, GOA2, and GOA3. (See diagram below.) Figure 6 As shown, the input signal terminal INPUT of the m-th stage shift register unit GOAm is connected to the cascaded output terminal OUT_C ​​of the (m-1)-th stage shift register unit GOA(m-1), and the reset signal terminal RST_PU of the m-th stage shift register unit GOAm is connected to the cascaded output terminal OUT_C ​​of the (m+2)-th stage shift register unit GOA(m+2), where M is an integer greater than 1, m is an integer and 1 < m < M-1. Figure 6 As shown, the M-stage cascaded shift register units GOA1, GOA2, ..., GOAM are connected to K clock signal lines, where K is an even number greater than or equal to 2N.

[0100] See Figure 6 N=4, K=12, meaning the gate drive circuit is connected to 12 clock signal lines. Each shift register unit in the gate drive circuit has 4 output circuits, as can be seen from the above reference. Figure 5 The shift register units described are used for implementation. The M-stage cascaded shift register units GOA1, GOA2, ..., GOAM are divided into multiple groups, each group including a 3-stage cascaded first shift register unit, second shift register unit, and third shift register unit. For example, in... Figure 6 In the first group, the first to third level shift register units GOA1, GOA2 and GOA3 are respectively the first to third shift register units in the first group. The second group, the fourth to sixth level shift register units GOA4, GOA5 and GOA6 are respectively the first to third shift register units in the second group, and so on.

[0101] Taking the first group as an example, the four output clock signal terminals CLK_1 to CLK_4 of the first shift register unit GOA1 in this group are connected one-to-one with the first clock signal line CLK1 to the fourth clock signal line CLK4. The four output clock signal terminals CLK_1 to CLK_4 of the second shift register unit GOA2 are connected one-to-one with the fifth clock signal line CLK5 to the eighth clock signal line CLK8. The four output clock signal terminals CLK_1 to CLK_4 of the third shift register unit GOA3 are connected one-to-one with the ninth clock signal line CLK9 to the twelfth clock signal line CLK12.

[0102] Similarly, in the second group, the four output clock signal terminals CLK_1 to CLK_4 of the first shift register unit GOA4 are connected one-to-one with the first clock signal line CLK1 to the fourth clock signal line CLK4. The four output clock signal terminals CLK_1 to CLK_4 of the second shift register unit GOA5 are connected one-to-one with the fifth clock signal line CLK5 to the eighth clock signal line CLK8. The four output clock signal terminals CLK_1 to CLK_4 of the third shift register unit GOA6 are connected one-to-one with the ninth clock signal line CLK9 to the twelfth clock signal line CLK12, and so on.

[0103] exist Figure 6 In the first-stage shift register unit GOA1, the input signal terminal INPUT is connected to the start signal line STV to receive the start signal.

[0104] In operation, the first-stage shift register unit GOA1, controlled by the clock signals on clock lines CLK1 to CLK4, outputs four output signals G1 to G4 at its four output terminals OUT_1 to OUT_4 based on the signal on the start signal line STV. It also outputs a cascaded signal at the cascaded output terminal OUT_C ​​to the input terminal INPUT of the second-stage shift register unit GOA2. The second-stage shift register unit GOA2, controlled by clock lines CLK5 to CLK8, outputs four output signals G5 to G8 at its four output terminals OUT_1 to OUT_4 based on the cascaded signal at the input terminal INPUT, and so on.

[0105] Figure 7 This is a schematic diagram of another gate drive circuit according to some embodiments. Figure 7 The gate drive circuit and Figure 6 Similarly, the difference lies at least in K=8, that is, the gate drive circuit is connected to 8 clock signal lines.

[0106] like Figure 7 As shown, the gate drive circuit includes M cascaded shift register units GOA1, GOA2, ..., GOAM. Figure 7 For ease of description, the diagram uses M=3, namely GOA1, GOA2, and GOA3. Each shift register unit can be implemented by a shift register unit with 4 output circuits (i.e., N=4) as described in the above embodiment, for example, it can be implemented by the above reference. Figure 5 The shift register unit described is used to implement this.

[0107] Similar to Figure 6The input signal terminal INPUT of the m-th stage shift register unit GOAm is connected to the cascaded output terminal OUT_C ​​of the (m-1)-th stage shift register unit GOA(m-1), and the reset signal terminal RST_PU of the m-th stage shift register unit GOAm is connected to the cascaded output terminal OUT_C ​​of the (m+2)-th stage shift register unit GOA(m+2), where M is an integer greater than 1, m is an integer and 1 < m < M-1.

[0108] like Figure 7 As shown, the M-stage cascaded shift register units GOA1, GOA2, ..., GOAM are connected to eight clock signal lines CLK1 to CLK8. The M-stage cascaded shift register units GOA1, GOA2, ..., GOAM are divided into multiple groups, each group consisting of two cascaded first and second shift register units. For example, in... Figure 7 In this diagram, the first group includes first-stage and second-stage shift register units GOA1 and GOA2, which serve as the first and second shift register units in the first group, respectively. The second group includes third-stage and sixth-stage shift register units GOA3 and GOA4, which serve as the first and second shift register units in the second group, respectively, and so on. Taking the first group as an example, the four output clock signal terminals CLK_1 to CLK_4 of the first shift register unit GOA1 are connected one-to-one with the first clock signal lines CLK1 to CLK4. Similarly, the four output clock signal terminals CLK_1 to CLK_4 of the second shift register unit GOA2 are connected one-to-one with the fifth clock signal lines CLK5 to CLK8. The shift register units GOA3 and GOA4 in the second group are connected to the clock signal lines CLK1 to CLK8 in a similar manner, which will not be elaborated further here.

[0109] exist Figure 6 and Figure 7 In the gate drive circuit, the first output clock signal terminal CLK_1 of the N output clock signal terminals CLK_1 to CLK_N of each shift register unit is connected to the control clock signal terminal CLK_C of the shift register unit, so that the first output circuit and the cascaded circuit generate output based on the same clock signal, thereby outputting signals with the same waveform at the first output signal terminal OUT_1 and the cascaded output terminal OUT_C.

[0110] Figure 8 This is a schematic diagram of another gate drive circuit according to some embodiments. Figure 8 The gate drive circuit and Figure 7 Similarly, the difference lies at least in N=2 and K=6, that is, the gate drive circuit is connected to 6 clock signal lines, and each shift register unit of the gate drive circuit can be implemented by the shift register unit with 2 output circuits in the above embodiment.

[0111] See Figure 8 The gate drive circuit includes M cascaded shift register units GOA1, GOA2, ..., GOAM. Figure 8 For ease of description, M=3 is used for illustration, namely GOA1, GOA2, and GOA3. Each shift register unit can be implemented by a shift register unit with two output circuits as described in the above embodiments, for example, it can be implemented by the above reference. Figures 2 to 4 It can be implemented using any shift register unit as described.

[0112] Similar to Figure 7 The input signal terminal INPUT of the m-th stage shift register unit GOAm is connected to the cascaded output terminal OUT_C ​​of the (m-1)-th stage shift register unit GOA(m-1), and the reset signal terminal RST_PU of the m-th stage shift register unit GOAm is connected to the cascaded output terminal OUT_C ​​of the (m+2)-th stage shift register unit GOA(m+2), where M is an integer greater than 1, m is an integer and 1 < m < M-1.

[0113] See Figure 8 The six clock signal lines include the first control clock signal line CLKC1, the second control clock signal line CLKC2, the first output clock signal line CLK1, the second output clock signal line CLK2, the third output clock signal line CLK3, and the fourth output clock signal line CLK4.

[0114] The M-stage cascaded shift register units GOA1, GOA2, ..., GOAM are divided into multiple groups, each group including two cascaded first and second shift register units. For example, in... Figure 8In this diagram, the first group includes first-stage and second-stage shift register units GOA1 and GOA2, which serve as the first and second shift register units in the first group, respectively. The second group includes third-stage and sixth-stage shift register units GOA3 and GOA4, which serve as the first and second shift register units in the second group, respectively, and so on. Taking the first group as an example, the two output clock signal terminals CLK_1 and CLK_2 of the first shift register unit GOA1 are connected one-to-one with the first output clock signal line CLK1 and the second output clock signal line CLK2. The control clock signal terminal CLK_C of the first shift register unit GOA1 is connected to the first control clock signal line CLKC1. The two output clock signal terminals CLK_1 and CLK_2 of the second shift register unit GOA2 are connected one-to-one with the third clock signal line CLK3 and the fourth clock signal line CLK4. The control clock signal terminal CLK_C of the second shift register unit GOA2 is connected to the second control clock signal line CLKC2. The shift register units GOA3 and GOA4 in the second group are connected to the clock signal lines CLKC1, CLKC2, and CLK1-CLK8 in a similar manner, which will not be elaborated here.

[0115] exist Figure 8 In the gate drive circuit, the N output clock signal terminals CLK_1 to CLK_N of each shift register unit are separated from the control clock signal terminal CLK_C of the shift register unit, so that the cascaded circuit can be independently clocked relative to the N output circuits, improving control flexibility.

[0116] Figure 9 This is a signal timing diagram of a driving method for a shift register unit according to some embodiments. This method is applicable to the shift register unit of any of the above embodiments. The following uses... Figure 2 Taking the shift register unit shown as an example, this driving method will be described exemplarily.

[0117] In the first time period T1, pull-up circuit 10 provides the first level of the input signal terminal INPUT to the main pull-up node PU, and the nth output circuit 40 of the N output circuits 40 inputs the first level of the input signal terminal INPUT to the nth sub-pull-up node PU_n. Combined with... Figure 2During this period, a high level at the input signal terminal INPUT turns on transistor M11, thereby providing the high level of the input signal terminal INPUT to the main pull-up node PU. A high level at pull-up node PU turns on transistor M22. The high level at the input signal terminal INPUT also turns on transistor M1 of each of the first output circuit 40_1 and the second output circuit 40_2, thereby providing the high level of the input signal terminal INPUT to the first sub-pull-up node PU_1 and the second sub-pull-up node PU_2, respectively. A high level at the first sub-pull-up node PU_1 turns on transistor M2 in the first output circuit 40_1, and a high level at the second sub-pull-up node PU_2 turns on transistor M2 in the second output circuit 40_2.

[0118] During the second time period T2, under the control of the potential of the total pull-up node PU, the cascaded circuit 30 provides the control clock signal CLK_C to the cascaded output terminal OUT_C, and the nth output circuit 40 of the N output circuits 40 provides the nth output clock signal CLK_n to the nth output signal terminal OUT_n under the control of the potential of the nth pull-up node PU_n. Combined with... Figure 2 During this period, the high levels of the first output clock signal terminal CLK_1 and the second output clock signal terminal CLK_2 arrive sequentially. Since the transistor M2 of each of the first output circuit 40_1 and the second output circuit 40_2 is in the on state, the signals of the first output clock signal terminal CLK_1 and the second output clock signal terminal CLK_2 are respectively provided to the first output signal terminal OUT_1 and the second output signal terminal OUT_2. During this period, due to the bootstrap effect of capacitor C1, the high levels of the first output signal terminal OUT_1 and the second output signal terminal OUT_2 further increase the potential of the first pull-up node PU_1 and the second pull-up node PU_2, respectively.

[0119] The signal at the control clock signal terminal CLK_C is the same as the signal at the first output clock signal terminal CLK_1. Similarly, since transistor M22 is in the on state, the signal at the control clock signal terminal CLK_C is provided to the cascaded output terminal OUT_C.

[0120] In the third time period T3, the pull-up circuit 10 provides the second level of the reset signal terminal RST_PU to the total pull-up node PU. The potential of the pull-up node PU causes the control circuit 20 to control the pull-down node PD to the first level. The potential of the pull-down node PD causes the cascade circuit 30 to pull down the cascade output terminal OUT_C ​​to the second level, and causes the nth output circuit 40 of the N output circuits 40 to pull down the nth output signal terminal OUT_n to the second level. Figure 2During this period, the reset signal terminal RST_PU is high, transistor M20 is turned on, thereby pulling down the main pull-up node PU to the low level of the first reference signal terminal LVGL. The low level of the main pull-up node PU turns off transistor M9, thereby making the pull-down node PD high. The high level of the pull-down node PD turns on transistor M23, as well as transistors M3 and M4 of the first output circuit 40_1 and the second output circuit 40_2. The turn-on of transistor M23 pulls down the cascaded output terminal OUT_C ​​to the low level of the first reference signal terminal LVGL. The turn-on of the two transistors M3 pulls down the first sub-pull-up node PU_1 and the second sub-pull-up node PU_12 to the low level of the first reference signal terminal LVGL. The turn-on of the two transistors M4 pulls down the first output signal terminal OUT_1 and the second output signal terminal OUT_2 to the low level of the second reference signal terminal VGL.

[0121] Some embodiments of this disclosure also provide a driving method for a gate driving circuit, the method comprising: in a first mode, applying K first clock signals, each shifted row-by-row, to the K clock signal lines, causing the M-stage shift register unit of the gate driving circuit to generate a plurality of first output signals, each shifted row-by-row; and in a second mode, applying K second clock signals, each shifted k rows-by-row, to the K clock signal lines, causing the M-stage shift register unit of the gate driving circuit to generate a plurality of second output signals, each shifted k rows-by-row, wherein the frequency of the K second clock signals is k times the frequency of the K first clock signals, where k is an integer less than or equal to K. Reference will be made below. Figure 10 and Figure 11 Let's illustrate this method with an example.

[0122] Figure 10 This is a signal timing diagram of a gate drive circuit driving method in a first mode according to some embodiments; Figure 11 This is a signal timing diagram in a second mode of a gate drive circuit driving method according to some embodiments. This method is applicable to the gate drive circuits of any of the above embodiments. The following will use... Figure 6 The driving method will be exemplified by taking the gate driving circuit as an example.

[0123] See Figure 10 and Figure 6In the first mode, 12 first clock signals, each shifted sequentially row-by-row, are applied to the 12 clock signal lines CLK1 to CLK12 of the gate drive circuit. This causes the M-stage shift register units GOA1, GOA2, ..., GOAM of the gate drive circuit to generate multiple first output signals G1, G2, ..., GM, each shifted sequentially row-by-row. The 12 first clock signals can be periodic signals. The term "row-by-row shift" refers to the shift of the first clock signal on the second clock signal line CLK2 relative to the first clock signal on the first clock signal line, the shift of the first clock signal on the third clock signal line CLK3 relative to the first clock signal on the second clock signal line CLK2, and so on. The shift values ​​can be equal, for example, all of them H or integer multiples of H, where H represents the time required to scan one row of sub-pixels, also known as the unit scan time.

[0124] Combination Figure 6 At the start of the scan, the signal on the start signal line STV is high. Under the control of the clock signals on clock lines CLK1 to CLK4, the first-stage shift register unit GOA1 outputs four sequentially shifted output signals G1 to G4 at its four output terminals OUT_1 to OUT_4, based on the signal on the start signal line STV. It also outputs a cascaded signal identical to output signal G1 at the cascaded output terminal OUT_C ​​to the input terminal INPUT of the second-stage shift register unit GOA2. The second-stage shift register unit GOA2, based on the cascaded signal received at the input terminal INPUT, outputs four sequentially shifted output signals G5 to G8 at its four output terminals OUT_1 to OUT_4, controlled by clock lines CLK5 to CLK8. Figure 10 At the moment indicated by the dashed line, the fourth-stage shift register unit GOA4 generates a high-level output signal G9 and a cascaded signal identical to G9. This cascaded signal is received by the reset signal RST_PU of the first-stage shift register GOA1, causing the main pull-up node PU and the four sub-pull-up nodes PU_1 to PU_4 of the first-stage shift register GOA1 to be pulled low, thereby achieving a reset. Similarly, in this way, the gate drive circuit outputs sequentially shifted output signals G1, G2, ... GM.

[0125] See Figure 11 and Figure 6 In the second mode, k-row-by-k strokes (e.g., ) are applied to the 12 clock signal lines CLK1 to CLK12 of the gate drive circuit. Figure 11 The 12 second clock signals, shifted sequentially (k=2), cause the M-stage shift register unit of the gate drive circuit to generate multiple second output signals G1 to G4, shifted sequentially k rows by k, wherein the frequency of the 12 second clock signals is k times the frequency of the 12 first clock signals CLK1 to CLK12. For example, in Figure 11 In this configuration, the first clock signal on the first clock signal line CLK1 and the second clock signal line CLK2 is the same, and the first clock signal on the third clock signal line CLK3 and the fourth clock signal line CLK4 is the same, but shifted relative to the first clock signals on the first and second clock signal lines CLK1 and CLK2. Similarly, the clock signals on the fifth and sixth clock signal lines CLK5 and CLK6 are the same, but shifted relative to the first clock signals on the third and fourth clock signal lines CLK3 and CLK4, and so on.

[0126] Combination Figure 6 At the start of scanning, the start signal STV is high. Based on the start signal STV, the first-stage shift register unit GOA1 of the gate drive circuit generates four output signals G1 to G4 under the control of the first clock signal on the first to fourth clock signal lines CLK1-CLK4. Output signals G1 and G2 are identical, while output signals G3 and G4 are identical but shifted relative to output signals G1 and G2. This process continues, enabling simultaneous scanning of every two lines. Figure 11 In the second mode, the frequencies of the 12 second clock signals on clock signal lines CLK1 to CLK12 are Figure 10 The 12 first clock signals CLK1 to CLK12 are doubled, thereby improving the scanning speed. The pixel data line charging time can be the same as in the first mode (still 1 hour, because two rows of pixels are charged simultaneously), so there is no reduction in image quality, thus achieving a 2x refresh rate to drive the display.

[0127] Although Figure 11 The example given uses K=12 and k=2; however, the embodiments disclosed herein are not limited to this. k and K can be set to other integers less than or equal to K as needed. For example, K=12 and k=4, meaning that with 12 clock signals, scanning can be performed row by row in the second mode. The driving principle is similar to the above, except that the frequency of the second clock signal used in the second mode is 1 / 4 of the frequency of the first clock signal used in the first mode. Similarly, with K=8, scanning can be performed row by row (k=2) or row by row (k=4).

[0128] Although the above text is Figure 6 Taking the gate drive circuit as an example Figure 10 and Figure 11 The driving method described herein is not limited to this; however, the embodiments disclosed herein are not limited thereto. The above driving method is also applicable to other gate driving circuits, such as gate driving circuits with K=8 and N=4, for example... Figure 7 The gate drive circuit. This driving method is applied to... Figure 7When driving the gate circuit, eight clock signals are applied to the eight clock signal lines CLK1 to CLK8 respectively. In the first mode, the pulse width of the first clock signal on the clock signal lines CLK1 to CLK8 is 4H and the duty cycle is 50%; in the second mode, the pulse width of the second clock signal on the clock signal lines CLK1 to CLK8 is 2H, the duty cycle is still 50%, and the frequency is twice that of the first clock signal.

[0129] Embodiments of this disclosure also provide another driving method for a gate driving circuit, wherein the gate circuit is connected to K clock signal lines including multiple output clock signal lines. The method includes: in a first mode, applying a plurality of first output clock signals that are sequentially shifted row by row to the plurality of output clock signal lines, causing the M-stage shift register unit of the gate driving circuit to generate a plurality of first output signals that are sequentially shifted row by row, wherein each of the N output circuits of the shift register unit generates an output signal; in a second mode, applying a plurality of second output clock signals to a portion of the plurality of output clock signal lines, causing the M-stage shift register unit of the gate driving circuit to generate a plurality of second output signals that are sequentially shifted, wherein at least one of the N output circuits of each shift register does not generate an output signal. Reference will be made below. Figure 12 and Figure 13 Let's illustrate this method with an example.

[0130] Figure 12 This is a signal timing diagram of a driving method for another gate driving circuit according to some embodiments in a first mode; Figure 13 This is a signal timing diagram in the second mode of another gate drive circuit driving method according to some embodiments. This method is applicable to gate drive circuits where the control clock signal terminal CLK_C of the shift register unit is separated from the output signal terminals CLK_1 to CLK_N, such as those referenced above. Figure 8 The described gate drive circuit.

[0131] The following will refer to Figure 12 and 13 ,by Figure 8 Taking the gate drive circuit shown as an example, the driving method will be described in practice.

[0132] See Figure 12 and Figure 8In the first mode, four first output clock signals, each shifted sequentially row-by-row, are applied to the four output clock signal lines CLK1 to CLK4 of the gate drive circuit. This causes the M-stage shift register units GOA1, GOA2, ..., GOAM of the gate drive circuit to generate multiple first output signals G1, G2, ..., GM, each shift register unit, where both output circuits generate output signals. In some embodiments, the pulse width of the first output clock signal is 4H, and the duty cycle is 50%.

[0133] For example, combining Figure 8 A first control clock signal can be applied to the first control clock signal line CLKC1, a second control clock signal can be applied to the second control clock signal line CLKC2, and four sequentially shifted first output clock signals can be applied to the first output clock signal line CLK1, the second output clock signal line CLK2, the third output clock signal line CLK3, and the fourth output clock signal line CLK4, respectively, so that the two output circuits of each shift register unit GOA1, GOA2, ..., GOAM generate output signals.

[0134] like Figure 12 As shown, at the start of the scan, the signal on the start signal line STV is high. Under the control of the clock signals on the output clock lines CLK1 and CLK2, the first-stage shift register unit GOA1 outputs two sequentially shifted output signals G1 and G2 at the two output signal terminals OUT_1 and OUT_2, respectively, based on the signal on the start signal line STV. Under the control of the control clock signal on the control clock line CLKC1, it outputs a cascaded signal at the cascaded output terminal OUT_C. This cascaded signal is provided to the input signal terminal INPUT of the second-stage shift register unit GOA2. Based on the cascaded signal received at the input signal terminal INPUT, the second-stage shift register unit GOA2 outputs two sequentially shifted output signals G3 and G4 at the two output signal terminals OUT_1 and OUT_2, respectively, under the control of the output clock signals CLK3 and CLK4. Under the control of the control clock signal on the control clock line CLKC2, it outputs a cascaded signal at the cascaded output terminal OUT_C. In this way, the gate drive circuit outputs sequentially shifted output signals G1, G2, ... GM.

[0135] See Figure 13 and Figure 8 In the second mode, a portion of the output clock signal lines CLK1 to CLK4 are output clock signal lines (in... Figure 13The even-numbered output clock signal lines CLK2 and CLK4 apply a second output clock signal, causing the M-stage shift register units GOA1, GOA2, ..., GOAM of the gate drive circuit to generate a plurality of sequentially shifted second output signals G2, G4, G6, ..., wherein at least one of the two output circuits of each stage shift register unit does not generate an output signal.

[0136] For example, combining Figure 8 The first control clock signal CLKC1 can be applied to the first control clock signal line CLKC1, the second control clock signal CLKC2 can be applied to the second control clock signal line CLKC2, and two sequentially shifted second output clock signals can be applied to the odd or even output clock signal lines of the first output clock signal line CLK1, the second output clock signal line CLK2, the third output clock signal line CLK3, and the fourth output clock signal line CLK4, respectively, so that one of the two output circuits of each stage shift register unit generates an output signal. Figure 13 In the example, the first output circuit of each shift register unit does not generate an output because it does not receive a clock signal, while the second output circuit generates an output based on the received clock signal. This causes the first-stage shift register unit GOA1 to generate an output signal G2, the second-stage shift register unit GOA2 to generate an output signal G4, and so on. This achieves the goal of turning off odd-numbered rows of pixels and scanning even-numbered rows, and vice versa. For example, output clock signals can be applied to output clock signal lines CLK1 and CLK3, but not to output clock signal lines CLK2 and CLK4. This causes the second output circuit of each shift register unit to generate a signal, while the first output circuit does not generate an output signal, thereby achieving the goal of turning off even-numbered rows of pixels and scanning odd-numbered rows.

[0137] By disabling one or more output signals, the gates of one or more sub-pixel rows are kept closed, preventing the writing of data signals. This avoids delays caused by high data signal load and short switching times, thus preventing the erroneous writing of data signals to adjacent sub-pixel rows and preventing serialization problems, thereby improving the display quality of the display device. For example, the gates of subpixels located in odd-numbered sub-pixel rows can be turned off, while the gates of subpixels located in even-numbered sub-pixel rows are normally turned on to write the corresponding data signals. In this way, even if the transmission of data signals in an even-numbered sub-pixel row is delayed, since the gates of the subpixels in the next odd-numbered sub-pixel row are closed, the data signals of that even-numbered sub-pixel row will not be written to the subsequent odd-numbered sub-pixel rows, thus avoiding display serialization during image display.

[0138] In some embodiments, the gate drive signal can be generated by scanning an even number of lines in one frame and by scanning an odd number of lines in the next frame. By alternating between odd and even line off modes between different frames, the persistence of vision of the human eye can be used to achieve the effect of overlaying the complete image between frames.

[0139] Figure 14 This is a signal timing diagram of a gate drive circuit driving method according to some embodiments in the first and second modes. Figure 14 The driving method shown is the same as the one mentioned above. Figure 12 and Figure 13 The described driving methods are similar, the difference being at least in Figure 14 In the second mode, output clock signals are applied to output clock signal lines CLK1 and CLK3, but not to output clock signal lines CLK2 and CLK4. This causes the second output circuit of each shift register unit to generate a signal, while the first output circuit does not generate an output signal, thereby achieving the goal of turning off even rows of pixels and scanning odd rows.

[0140] See Figure 14 In the second mode, the period of the second output clock signal applied to the output clock signal lines CLK1 to CLK4 is equal to the period of the first output clock signal applied to the clock signal lines CLK1 to CLK4 in the first mode, but its duty cycle is greater than that of the first output clock signal. For example, the effective level duration of the former is longer than that of the latter by T, where T ≤ H. In this case, the pulse width of the data signal Data can also be increased by T compared to the first mode, thereby increasing the charging time of each odd-numbered line by T, thus improving the charging rate. When the next frame is displayed, the odd-numbered lines are turned off, and the charging time is increased using the same principle.

[0141] It should be noted that although the above embodiments illustrate the parity switching method in the second mode, the embodiments of this disclosure are not limited thereto. Multiple output circuits of the shift register unit of the gate drive circuit can be switched as needed to generate different gate drive signals. For example, in the case where each shift register unit of the gate drive circuit has four output circuits, a clock signal can be used to control each shift register unit to turn off the first output circuit and generate outputs from the second to fourth output circuits in one frame; while in the next frame, the first output circuit generates outputs, and the second and fourth output circuits turn off, thereby achieving a 1:3 switching. Other switching methods are also permitted, and this disclosure does not limit them.

[0142] Those skilled in the art will understand that the embodiments described above are exemplary and can be improved upon. The structures described in the various embodiments can be freely combined without causing any conflict in structure or principle.

[0143] After a detailed description of the preferred embodiments of this disclosure, those skilled in the art will clearly understand that various changes and modifications can be made without departing from the scope and spirit of the appended claims, and that this disclosure is not limited to the implementation of the exemplary embodiments described in the specification.

Claims

1. A shift register unit, comprising: A pull-up circuit is connected to the input signal terminal, the main pull-up node, and the pull-down node of the shift register unit. The pull-up circuit is configured to provide the signal from the input signal terminal to the main pull-up node and pull down the potential of the main pull-up node under the control of the potential of the pull-down node. A control circuit, connected to the main pull-up node and the pull-down node, is configured to control the potential of the pull-down node based on the potential of the main pull-up node; A cascaded circuit is connected to the cascaded output terminal and control clock signal terminal of the main pull-up node, the pull-down node, and the shift register unit. The cascaded circuit is configured to provide the signal of the control clock signal terminal to the cascaded output terminal under the control of the potential of the main pull-up node, and to pull down the potential of the cascaded output terminal under the control of the potential of the pull-down node. N output circuits are respectively connected to the input signal terminal, the pull-down node, and the N output clock signal terminals, N sub-pull-up nodes, and N output signal terminals of the shift register unit. The nth output circuit is connected to the input signal terminal, the pull-down node, the nth output signal terminal, and the nth sub-pull-up node, and is configured to input the signal from the input signal terminal to the nth sub-pull-up node, provide the signal from the nth output clock signal terminal to the nth output signal terminal under the control of the potential of the nth sub-pull-up node, and pull down the potential of the nth output signal terminal under the control of the potential of the pull-down node, where N is an integer greater than 1, n is an integer and 1≤n≤N; The nth output circuit includes: A pull-down sub-circuit, connected to the pull-down node, is configured to pull down the potential of the nth pull-up node and the nth output signal terminal under the control of the potential of the pull-down node; The N output clock signal terminals are connected to N clock signal lines respectively. In the first mode, multiple first output clock signals that are shifted row by row are applied to the N clock signal lines. In the second mode, multiple second output clock signals are applied to a portion of the N clock signal lines. The period of the second output clock signal is equal to the period of the first output clock signal, and the duty cycle of the second output clock signal is greater than the duty cycle of the first output clock signal.

2. The shift register unit according to claim 1, wherein, The nth output circuit includes: An input sub-circuit is connected to the input signal terminal and the nth pull-up node, and is configured to provide the signal from the input signal terminal to the nth pull-up node; An output sub-circuit is connected to the nth pull-up node, the nth output clock signal terminal, and the nth output signal terminal, and is configured to provide the signal from the nth output clock signal terminal to the nth output signal terminal under the control of the potential of the nth pull-up node.

3. The shift register unit according to claim 2, wherein, The pull-down node includes a first pull-down node and a second pull-down node, and the pull-down sub-circuit includes a first pull-down circuit and a second pull-down circuit, wherein... The first pull-down sub-circuit is connected to the first pull-down node and is configured to pull down the potential of at least one of the nth pull-up node and the nth output signal terminal under the control of the potential of the first pull-down node; The second pull-down sub-circuit is connected to the second pull-down node and is configured to pull down the potential of at least one of the nth pull-up node and the nth output signal terminal under the control of the potential of the second pull-down node.

4. The shift register unit according to claim 3, wherein, The control circuit includes: A first control sub-circuit is connected to the main pull-up node and the first pull-down node, and is configured to control the potential of the first pull-down node according to the potential of the main pull-up node; A second control sub-circuit is connected to the main pull-up node and the second pull-down node, and is configured to control the potential of the second pull-down node based on the potential of the main pull-up node.

5. The shift register unit according to claim 2, wherein, The nth output circuit also includes: A reset sub-circuit is connected to the nth pull-up node and the reset signal terminal and reference signal terminal of the shift register unit, and is configured to reset the nth pull-up node using the potential of the reference signal terminal under the control of the signal at the reset signal terminal.

6. The shift register unit according to claim 2, wherein, The input sub-circuit is also connected to the power signal terminal and is configured to provide the potential of the power signal terminal to the nth pull-up node under the control of the signal at the input signal terminal.

7. The shift register unit according to claim 1, wherein, The first output clock signal terminal among the N output clock signal terminals is connected to the control clock signal terminal.

8. The shift register unit according to claim 2, wherein, The input sub-circuit includes: a first transistor, the gate and a first terminal of the first transistor being connected to the input signal terminal, and the second terminal of the first transistor being connected to the nth pull-up node.

9. The shift register unit according to claim 6, wherein, The input sub-circuit includes: a first transistor, the gate of the first transistor being connected to the input signal terminal, the first terminal of the first transistor being connected to the power signal terminal, and the second terminal of the first transistor being connected to the nth pull-up node.

10. The shift register unit according to claim 2, wherein, The output sub-circuit includes: The second transistor, whose gate is connected to the nth pull-up node, whose first terminal is connected to the nth output clock signal terminal, and whose second terminal is connected to the nth output signal terminal; and A first capacitor, the first end of which is connected to the nth pull-up node, and the second end of which is connected to the nth output signal terminal.

11. The shift register unit according to claim 2, wherein, The pull-down sub-circuit includes: The third transistor has its gate connected to the pull-down node, its first terminal connected to the first reference signal terminal of the shift register unit, and its second terminal connected to the nth pull-up node. The fourth transistor has its gate connected to the pull-down node, its first terminal connected to the second reference signal terminal of the shift register unit, and its second terminal connected to the nth output signal terminal.

12. The shift register unit according to claim 3, wherein, The first pull-down sub-circuit includes a third transistor and a fourth transistor. The gate of the third transistor is connected to the first pull-down node, the first terminal of the third transistor is connected to the first reference signal terminal of the shift register unit, the second terminal of the third transistor is connected to the nth pull-up node, the gate of the fourth transistor is connected to the first pull-down node, the first terminal of the fourth transistor is connected to the second reference signal terminal of the shift register unit, and the second terminal of the fourth transistor is connected to the nth output signal terminal. The second pull-down sub-circuit includes a fifth transistor and a sixth transistor. The gate of the fifth transistor is connected to the second pull-down node, the first terminal of the fifth transistor is connected to the first reference signal terminal, and the second terminal of the fifth transistor is connected to the nth pull-up node. The gate of the sixth transistor is connected to the second pull-down node, the first terminal of the sixth transistor is connected to the second reference signal terminal, and the second terminal of the sixth transistor is connected to the nth output signal terminal.

13. The shift register unit according to claim 5, wherein, The reset sub-circuit includes a seventh transistor, the gate of which is connected to the reset signal terminal, the first terminal of which is connected to the reference signal terminal, and the second terminal of which is connected to the nth pull-up node.

14. The shift register unit according to claim 1, wherein, The control circuit includes: The eighth transistor has its gate and first terminal connected to the power supply signal terminal of the shift register unit, and its second terminal connected to the pull-down node. The ninth transistor has its gate connected to the total pull-up node, its first terminal connected to the reference signal terminal of the shift register unit, and its second terminal connected to the pull-down node.

15. The shift register unit according to claim 4, wherein, The first control sub-circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The gate and first terminal of the tenth transistor are connected to the power supply signal terminal of the shift register unit. The second terminal of the tenth transistor is connected to the gate of the eleventh transistor. The first terminal of the eleventh transistor is connected to the power supply signal terminal and the second terminal of the eleventh transistor is connected to the first pull-down node. The gate of the twelfth transistor is connected to the total pull-up node. The first terminal of the twelfth transistor is connected to the reference signal terminal of the shift register unit and the second terminal of the twelfth transistor is connected to the gate of the eleventh transistor. The gate of the thirteenth transistor is connected to the total pull-up node. The first terminal of the thirteenth transistor is connected to the reference signal terminal and the second terminal of the thirteenth transistor is connected to the first pull-down node. The second control sub-circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor. The gate and first terminal of the fourteenth transistor are connected to the power supply signal terminal. The second terminal of the fourteenth transistor is connected to the gate of the fifteenth transistor. The first terminal of the fifteenth transistor is connected to the power supply signal terminal and the second terminal of the fifteenth transistor is connected to the second pull-down node. The gate of the sixteenth transistor is connected to the total pull-up node. The first terminal of the sixteenth transistor is connected to the reference signal terminal and the second terminal of the sixteenth transistor is connected to the gate of the fifteenth transistor. The gate of the seventeenth transistor is connected to the total pull-up node. The first terminal of the seventeenth transistor is connected to the reference signal terminal and the second terminal of the seventeenth transistor is connected to the second pull-down node.

16. The shift register unit according to claim 1, wherein, The pull-up circuit includes: The eighteenth transistor has its gate and first terminal connected to the input signal terminal, and its second terminal connected to the total pull-up node. The nineteenth transistor has its gate connected to the pull-down node, its first terminal connected to the reference signal terminal of the shift register unit, and its second terminal connected to the general pull-up node. The twentieth transistor has its gate connected to the reset signal terminal of the shift register unit, its first terminal connected to the reference signal terminal, and its second terminal connected to the total pull-up node.

17. The shift register unit according to claim 16, wherein, The pull-down node includes a first pull-down node and a second pull-down node, and the pull-up circuit further includes a twenty-first transistor, wherein... The gate of the nineteenth transistor is connected to the first pull-down node, the gate of the twenty-first transistor is connected to the second pull-down node, the first terminal of the twenty-first transistor is connected to the reference signal terminal, and the second terminal of the twenty-first transistor is connected to the total pull-up node.

18. The shift register unit according to claim 1, wherein, The cascaded circuit includes: The 22nd transistor has its gate connected to the total pull-up node, its first terminal connected to the control clock signal terminal, and its second terminal connected to the cascaded output terminal. The 23rd transistor has its gate connected to the pull-down node, its first terminal connected to the reference signal terminal of the shift register unit, and its second terminal connected to the cascaded output terminal. The second capacitor has its first terminal connected to the gate of the twentieth transistor and its second terminal connected to the cascaded output terminal.

19. The shift register unit according to claim 18, wherein, The pull-down node includes a first pull-down node and a second pull-down node, and the cascaded circuit further includes a twenty-fourth transistor, wherein... The gate of the 24th transistor is connected to the first pull-down node, the gate of the 24th transistor is connected to the second pull-down node, the first terminal of the 24th transistor is connected to the reference signal terminal, and the second terminal of the 24th transistor is connected to the cascaded output terminal.

20. The shift register unit according to claim 1 further includes a total reset circuit, the total reset circuit including a twenty-fifth transistor, the gate of the twenty-fifth transistor being connected to the total reset terminal of the shift register unit, the first terminal of the twenty-fifth transistor being connected to the reference signal terminal of the shift register unit, and the second terminal of the twenty-fifth transistor being connected to the total pull-up node.

21. The shift register unit according to any one of claims 1 to 20, wherein, 2≤N≤8。 22. A gate driving circuit comprising M cascaded shift register units, wherein the shift register units are the shift register units as described in any one of claims 1 to 21. in, The input signal terminal of the m-th stage shift register unit is connected to the cascaded output terminal of the (m-1)-th stage shift register unit, and the reset signal terminal of the m-th stage shift register unit is connected to the cascaded output terminal of the (m+2)-th stage shift register unit, where M is an integer greater than 1, m is an integer and 1 < m < M-1, and... The M-stage cascaded shift register units are connected to K clock signal lines, where K is an even number greater than or equal to 2N.

23. The gate driving circuit according to claim 22, wherein N=4, K=12, the M-stage cascaded shift register units are divided into multiple groups, each group including a 3-stage cascaded first shift register unit, a second shift register unit, and a third shift register unit, wherein the N output clock signal terminals of the first shift register unit are connected one-to-one with the first to fourth clock signal lines, the N output clock signal terminals of the second shift register unit are connected one-to-one with the fifth to eighth clock signal lines, and the N output clock signal terminals of the third shift register unit are connected one-to-one with the ninth to twelfth clock signal lines.

24. The gate driving circuit according to claim 22, wherein N=4, K=8, the M-stage cascaded shift register units are divided into multiple groups, each group including a first shift register unit and a second shift register unit cascaded in two stages, wherein the N output clock signal terminals of the first shift register unit are connected one-to-one with the first clock signal line to the fourth clock signal line, and the N output clock signal terminals of the second shift register unit are connected one-to-one with the fifth clock signal line to the eighth clock signal line.

25. The gate drive circuit according to claim 23 or 24, wherein, The first output clock signal of the N output clock signals of each shift register unit is connected to the control clock signal of that shift register unit.

26. The gate driving circuit according to claim 22, wherein N=2, K=6, and the K clock signal lines include a first control clock signal line, a second control clock signal line, a first output clock signal line, a second output clock signal line, a third output clock signal line, and a fourth output clock signal line. in, The M-level cascaded shift register units are divided into multiple groups, each group including a first shift register unit and a second shift register unit cascaded in two levels. The N output clock signal terminals of the first shift register unit are connected one-to-one with the first output clock signal line and the second output clock signal line, and the control clock signal terminal of the first shift register unit is connected to the first control clock signal line. The N output clock signal terminals of the second shift register unit are connected one-to-one with the third clock signal line and the fourth clock signal line, and the control clock signal terminal of the second shift register unit is connected to the second control clock signal line.

27. A method for driving a shift register unit as described in any one of claims 1 to 21, comprising: In the first time period, the pull-up circuit provides the first level of the input signal terminal to the main pull-up node, and the nth output circuit in the N output circuits inputs the first level of the input signal terminal to the nth sub-pull-up node; In the second time period, the cascaded circuit provides the signal of the control clock signal terminal to the cascaded output terminal under the control of the potential of the total pull-up node, and the nth output circuit in the N output circuits provides the signal of the nth output clock signal terminal to the nth output signal terminal under the control of the potential of the nth pull-up node. as well as, During the third time period, the pull-up circuit provides the second level of the reset signal terminal to the total pull-up node. The potential of the pull-up node causes the control circuit to control the pull-down node to the first level. The potential of the pull-down node causes the cascaded circuit to pull down the cascaded output terminal to the second level, and causes the nth output circuit in the N output circuits to pull down the nth output signal terminal to the second level.

28. A driving method for a gate driving circuit as described in any one of claims 22 to 26, comprising: In the first mode, K first clock signals, each shifted sequentially row by row, are applied to the K clock signal lines, causing the M-stage shift register unit of the gate drive circuit to generate multiple first output signals, each shifted sequentially row by row. In the second mode, K second clock signals, each shifted k rows sequentially, are applied to the K clock signal lines, causing the M-stage shift register unit of the gate drive circuit to generate a plurality of second output signals, each shifted k rows sequentially. The frequency of the K second clock signals is k times that of the K first clock signals, where k is an integer greater than 1 and less than or equal to K.

29. The method according to claim 28, wherein, N=4, K=12 or 8, k=2 or 4.

30. A driving method for a gate driving circuit as described in any one of claims 22 to 26, wherein the K clock signal lines include a plurality of output clock signal lines, the method comprising: In the first mode, multiple first output clock signals that are sequentially shifted row by row are applied to the multiple output clock signal lines, causing the M-stage shift register unit of the gate drive circuit to generate multiple first output signals that are sequentially shifted row by row, wherein each of the N output circuits of the shift register unit generates an output signal. In the second mode, multiple second output clock signals are applied to a portion of the multiple output clock signal lines, causing the M-stage shift register unit of the gate drive circuit to generate multiple sequentially shifted second output signals, wherein at least one of the N output circuits of each stage shift register unit does not generate an output signal.

31. The method according to claim 30, wherein, N=2, K=6, and the K clock signal lines include a first control clock signal line, a second control clock signal line, a first output clock signal line, a second output clock signal line, a third output clock signal line, and a fourth output clock signal line. In the first mode, a first control clock signal is applied to the first control clock signal line, a second control clock signal is applied to the second control clock signal line, and four sequentially shifted first output clock signals are applied to the first, second, third, and fourth output clock signal lines, respectively, so that both output circuits of each shift register unit generate output signals; and In the second mode, the first control clock signal is applied to the first control clock signal line, the second control clock signal is applied to the second control clock signal line, and two sequentially shifted second output clock signals are applied to the odd or even clock signal lines of the first, second, third, and fourth output clock signal lines, respectively, so that one of the two output circuits of each shift register unit generates an output signal.

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