Semiconductor memory device

Abstract

A semiconductor memory device capable of high-speed operation is provided. The semiconductor memory device includes a first pad capable of transmitting and receiving a first-time-point signal, a second pad capable of transmitting and receiving a data signal based on the first-time-point signal, a third pad capable of receiving a second-time-point signal, a fourth pad capable of receiving control information based on the second-time-point signal, a memory cell array, a sense amplifier connected to the memory cell array, a first register connected to the sense amplifier, a second register capable of storing first control information, a third register capable of storing second control information, and a control circuit capable of performing data output of data stored in the first register from the first pad. The first control information is stored in the second register based on input to the fourth pad corresponding to the second-time-point signal for i periods. The second control information is stored in the third register based on input to the fourth pad corresponding to the second-time-point signal for j periods.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-120333 (filed July 21, 2021) and Japanese Patent Application No. 2021-170466 (filed October 18, 2021). This application incorporates the entire contents of the aforementioned basic applications by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known, comprising: a memory cell array including a plurality of memory cells; and peripheral circuitry connected to the memory cell array, which outputs user data based on an input of a command group including command data and address data. Summary of the Invention

[0005] A high-speed semiconductor memory device is provided.

[0006] One embodiment of a semiconductor memory device includes: a first pad capable of transmitting and receiving a first time-point signal; a second pad capable of transmitting and receiving data signals based on the first time-point signal; a third pad capable of receiving a second time-point signal; a fourth pad capable of receiving control information based on the second time-point signal; a memory cell array comprising a string of characters in series with multiple memory cell transistors connected in series; a sense amplifier connected to the memory cell array; a first register connected to the sense amplifier capable of storing data read from the memory cell array; a second register capable of storing first control information; a third register capable of storing second control information; and a control circuit capable of performing data output from the first pad to the data stored in the first register. The first control information is stored in the second register based on an input to the fourth pad corresponding to an i-th time-point signal (i being an integer greater than or equal to 2). The second control information is stored in the third register based on an input to the fourth pad corresponding to a j-th time-point signal (j being an integer different from i). Attached Figure Description

[0007] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0008] Figure 2 This is a schematic side view showing an example of the configuration of the memory system 10.

[0009] Figure 3 This is a schematic top view showing an example of the configuration of the memory system 10.

[0010] Figure 4 This is a schematic block diagram representing the structure of a memory die (MD).

[0011] Figure 5 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0012] Figure 6 This is a schematic 3D diagram representing a portion of a memory die (MD).

[0013] Figure 7 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0014] Figure 8 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0015] Figure 9 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0016] Figure 10 It is a schematic diagram used to explain the action mode MODEa.

[0017] Figure 11 It is a schematic diagram used to explain the action mode MODEb.

[0018] Figure 12 It is a truth table used to describe the action mode MODEa.

[0019] Figure 13 It is a truth table used to describe the action mode MODEb.

[0020] Figure 14 It is a truth table used to describe the action mode MODEb.

[0021] Figure 15 It is a truth table used to describe the action mode MODEb.

[0022] Figure 16 It is a schematic waveform diagram used to illustrate the action mode MODEa.

[0023] Figure 17 It is a schematic waveform diagram used to illustrate the action mode MODEb.

[0024] Figure 18 It is a schematic waveform diagram used to illustrate the action mode MODEa.

[0025] Figure 19 It is a schematic waveform diagram used to illustrate the action mode MODEa.

[0026] Figure 20 It is a schematic waveform diagram used to illustrate the action mode MODEb.

[0027] Figure 21 It is a schematic waveform diagram used to illustrate the action mode MODEb.

[0028] Figure 22 It is a schematic waveform diagram used to illustrate the action mode MODEb.

[0029] Figure 23 It is a schematic waveform diagram used to illustrate the action mode MODEa.

[0030] Figure 24 It is a schematic waveform diagram used to illustrate the action mode MODEb.

[0031] Figure 25 It is a schematic waveform diagram used to illustrate the action mode MODEa.

[0032] Figure 26 It is a schematic waveform diagram used to illustrate the action mode MODEb.

[0033] Figure 27 It is a schematic waveform diagram used to illustrate the action mode MODEa.

[0034] Figure 28 It is a schematic waveform diagram used to illustrate the action mode MODEb.

[0035] Figure 29 It is a schematic waveform diagram used to illustrate the action mode MODEa.

[0036] Figure 30 It is a schematic waveform diagram used to illustrate the action mode MODEb.

[0037] Figure 31 It is a schematic waveform diagram used to illustrate the action mode MODEb.

[0038] Figure 32 This is a schematic flowchart used to illustrate a partial configuration example of a memory die (MD).

[0039] Figure 33 This is a schematic circuit diagram representing a partial configuration example of a memory die (MD).

[0040] Figure 34 It is used to Figure 33 The circuit shown is illustrated with a schematic waveform diagram to explain its operation.

[0041] Figure 35This is a schematic circuit diagram representing a partial configuration example of a memory die (MD).

[0042] Figure 36 This is a schematic circuit diagram representing a partial configuration example of a memory die (MD).

[0043] Figure 37 This is a schematic circuit diagram representing a partial configuration example of a memory die (MD).

[0044] Figure 38 This is a schematic block diagram showing the configuration of the memory die MD2 in the second embodiment.

[0045] Figure 39 This is a schematic circuit diagram representing a portion of the memory die MD2.

[0046] Figure 40 It is a schematic diagram used to explain the action mode MODEb.

[0047] Figure 41 This is a schematic block diagram showing the configuration of the memory die MD3 in the third embodiment.

[0048] Figure 42 It is a truth table used to describe the action mode MODEb.

[0049] Figure 43 It is a truth table used to describe the action mode MODEb.

[0050] Figure 44 (a) to (b) are schematic diagrams used to illustrate the threshold voltage of the storage unit MC that records 3 bits of data.

[0051] Figure 45 It is a timing diagram used to explain the reading action.

[0052] Figure 46 (a) to (c) are timing diagrams used to illustrate the displacement readings.

[0053] Figure 47 This is a schematic waveform diagram showing the state of displacement reading when performing an action mode MODEb.

[0054] Figure 48 This is a schematic block diagram showing the configuration of the memory die MD4 in the fourth embodiment.

[0055] Figure 49 It is a schematic waveform diagram representing the state when the read action is performed in the action mode MODEb.

[0056] Figure 50This is a schematic waveform diagram showing the state of displacement reading when performing an action mode MODEb.

[0057] Figure 51 This is a schematic waveform diagram used to illustrate other embodiments of a semiconductor memory device. Detailed Implementation

[0058] Next, with reference to the accompanying drawings, a semiconductor memory device according to an embodiment will be described in detail. Furthermore, the following embodiments are merely examples and are not intended to limit the invention.

[0059] Furthermore, in this specification, the term "semiconductor memory device" sometimes refers to a memory die (memory chip), and sometimes refers to a memory system that includes a controller die, such as a memory card or an SSD (Solid State Disk). Moreover, it sometimes refers to a configuration including a mainframe computer such as a smartphone, tablet, or personal computer.

[0060] Furthermore, this specification mentions that when the first component is "electrically connected" to the second component, the first component can be directly connected to the second component, or the first component can be connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected" to the third transistor.

[0061] Furthermore, in this specification, the mention that the first component is "connected between" the second and third components sometimes means that the first, second, and third components are connected in series, and that the second component is connected to the third component via the first component.

[0062] Furthermore, in this specification, when it is mentioned that a circuit or the like "conducts" two wirings, for example, it sometimes means that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings, and the transistor or the like is in an ON state.

[0063] [First Implementation]

[0064] [Memory System 10]

[0065] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0066] The memory system 10 performs read operations, write operations, erase operations and the like in accordance with signals transmitted from a host computer 20. The memory system 10 is, for example, a memory card, an SSD, or another system capable of storing user data. The memory system 10 includes: a plurality of memory dice MD that store user data; and a controller die CD connected between the plurality of memory dice MD and the host computer 20. The controller die CD includes, for example, a processor, a RAM (Random Access Memory), and the like, and performs processes such as conversion between logical addresses and physical addresses, bit error detection / correction, garbage collection (compression), and wear leveling.

[0067] Figure 2 is a schematic side view showing an example configuration of the memory system 10 according to the present embodiment. Figure 3 is a schematic top view showing the same example configuration. For convenience of explanation, in Figure 2 and Figure 3 a part of the configuration is omitted.

[0068] As shown in Figure 2 , the memory system 10 according to the present embodiment includes a mounting substrate MSB, a plurality of memory dice MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory dice MD. A pad electrode P is provided in an end region in the Y-direction on the upper surface of the mounting substrate MSB, and another partial region is connected to the lower surface of the memory die MD via an adhesive or the like. A pad electrode P is provided in an end region in the Y-direction on the upper surface of the memory die MD, and the other region is connected to the lower surface of another memory die MD or the controller die CD via an adhesive or the like. A pad electrode P is provided in an end region in the Y-direction on the upper surface of the controller die CD.

[0069] As shown in Figure 3 , each of the mounting substrate MSB, the plurality of memory dice MD, and the controller die CD has a plurality of pad electrodes P arranged in the X-direction. The plurality of pad electrodes P provided on the mounting substrate MSB, the plurality of memory dice MD, and the controller die CD are connected to each other via bonding wires B, respectively.

[0070] In addition, Figure 2 and Figure 3 the configuration shown is merely an example, and the specific configuration can be appropriately adjusted. For example, Figure 2 and Figure 3In the example shown, a controller die CD is stacked on a plurality of memory dies MD, and these components are connected by bonding wires B. In this configuration, the plurality of memory dies MD and the controller die CD are contained in one package. However, the controller die CD may also be contained in a package different from that of the memory dies MD. In addition, the plurality of memory dies MD and the controller die CD may also be connected to each other through through electrodes or the like instead of bonding wires B.

[0071] [Configuration of Memory Die MD]

[0072] Figure 4 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figure 5 is a schematic circuit diagram showing a partial configuration of the memory die MD. Figure 6 is a schematic perspective view showing a partial configuration of the memory die MD. Figures 7-9 is a circuit diagram showing a partial configuration of the memory die MD. For convenience of explanation, Figures 4-9 a part of the configuration is omitted.

[0073] In addition, Figure 4 a plurality of control terminals and the like are illustrated. The plurality of control terminals may be represented as control terminals corresponding to active-high signals (positive logic signals), represented as control terminals corresponding to active-low signals (negative logic signals), or represented as control terminals corresponding to both active-high signals and active-low signals. Figure 4 the symbol of a control terminal corresponding to an active-low signal includes an overline (upper line). In this specification, the symbol of a control terminal corresponding to an active-low signal includes a slash (" / "). In addition, Figure 4 the description herein is illustrative, and specific aspects can be adjusted as appropriate. For example, part or all of active-high signals may be set as active-low signals, or part or all of active-low signals may be set as active-high signals.

[0074] Furthermore, Figure 4 arrows indicating input / output directions are illustrated beside the plurality of shown control terminals. Figure 4 a control terminal marked with an arrow pointing from left to right can be used for inputting data or other signals from the controller die CD to the memory die MD. Figure 4 a control terminal marked with an arrow pointing from right to left can be used for outputting data or other signals from the memory die MD to the controller die CD. Figure 4 a control terminal marked with arrows in both left and right directions can be used for both inputting data or other signals from the controller die CD to the memory die MD, and outputting data or other signals from the memory die MD to the controller die CD.

[0075] As shown in Figure 4As shown, the memory die MD includes memory cell arrays MCA0 and MCA1 for storing user data, and peripheral circuitry PC connected to the memory cell arrays MCA0 and MCA1. In the following description, memory cell arrays MCA0 and MCA1 are sometimes referred to as memory cell array MCA. Furthermore, memory cell arrays MCA0 and MCA1 are sometimes referred to as planar arrays PLN0 and PLN1.

[0076] [Composition of a Memory Cell Array (MCA)]

[0077] Storage cell array MCA such as Figure 5 As shown, the system comprises multiple memory blocks BLK. Each memory block BLK comprises multiple word string units SU. Each word string unit SU comprises multiple memory word strings MS. One end of each memory word string MS is connected to the peripheral circuit PC via a bit line BL. Furthermore, the other end of each memory word string MS is connected to the peripheral circuit PC via a common source line SL.

[0078] The memory word string MS has a drain-side selection transistor STD connected in series between the bit line BL and the source line SL, multiple memory cells MC (memory cell transistors), a source-side selection transistor STS, and a source-side selection transistor STSb. Hereinafter, the drain-side selection transistor STD, the source-side selection transistor STS, and the source-side selection transistor STSb are sometimes referred to simply as selection transistors (STD, STS, STSb).

[0079] A memory cell (MC) is a field-effect transistor (FET) comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge accumulation film. The threshold voltage of the memory cell (MC) varies depending on the amount of charge in the charge accumulation film. The memory cell (MC) stores one or more bits of user data. Furthermore, the gate electrodes of multiple memory cells (MCs) corresponding to a memory word string (MS) are connected to word lines (WL). These word lines (WL) are collectively connected to all memory word strings (MS) within a memory block (BLK).

[0080] Select transistors (STD, STS, STSb) are field-effect transistors with a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Select gate lines (SGD, SGS, SGSb) are connected to the gate electrodes of the select transistors (STD, STS, STSb), respectively. The drain-side select gate line SGD corresponds to the word string unit SU and is connected to all memory word strings MS within one word string unit SU. The source-side select gate line SGS is connected to all memory word strings MS within the memory block BLK. The source-side select gate line SGSb is connected to all memory word strings MS within the memory block BLK.

[0081] Storage cell array (MCA) such as Figure 6 As shown, it is disposed above the semiconductor substrate 100. Additionally, Figure 6 In the example, multiple transistors Tr that constitute the peripheral circuit PC are disposed between the semiconductor substrate 100 and the memory cell array MCA.

[0082] The memory cell array (MCA) has multiple memory blocks (BLKs) arranged in the Y direction. In addition, an inter-block insulating layer (ST) such as silicon oxide (SiO2) is provided between two adjacent memory blocks (BLKs) in the Y direction.

[0083] For example, memory block BLK Figure 6 As shown, it includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor pillars 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0084] The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction. The conductive layer 110 may also comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Furthermore, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged in the Z direction.

[0085] Furthermore, two or more of the bottommost conductive layers 110 among the multiple conductive layers 110 serve as source-side selected gate lines SGS, SGSb ( Figure 5 The gate electrodes of the multiple source-side selection transistors STS and STSb connected to it function. The multiple conductive layers 110 are electrically independent for each memory block BLK.

[0086] In addition, multiple conductive layers 110 located above it serve as word lines WL ( Figure 5 ) and multiple storage units MC connected to it Figure 5 The gate electrode of the memory block BLK functions. The plurality of conductive layers 110 are electrically independent for each memory block BLK.

[0087] Furthermore, one or more conductive layers 110 located above it serve as drain-side selected gate lines SGD and multiple drain-side selected transistors STD connected thereto. Figure 5 The gate electrode of the plurality of conductive layers 110 functions. The width of the plurality of conductive layers 110 in the Y direction is smaller than that of the other conductive layers 110.

[0088] Below the conductive layer 110, a semiconductor layer 112 is disposed. The semiconductor layer 112 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Furthermore, an insulating layer 101, such as silicon oxide (SiO2), is disposed between the semiconductor layer 112 and the conductive layer 110.

[0089] Semiconductor layer 112 serves as the source line SL ( Figure 5 It functions as follows: The source line SL, for example, is a common setting for all memory blocks BLK contained in the memory cell array MCA.

[0090] Semiconductor pillar 120, for example Figure 6 As shown, they are arranged in a specific pattern in the X and Y directions. The semiconductor pillars 120 serve as a memory word MS ( Figure 5 The multiple memory cells MC and the channel regions of the selection transistors (STD, STS, STSb) contained in the semiconductor pillar 120 function as such. The semiconductor pillar 120 is, for example, a semiconductor layer such as polysilicon (Si). Figure 6 As shown, it has a generally cylindrical shape, with an insulating layer 125 such as silicon oxide disposed in the central part. In addition, the outer peripheral surfaces of the semiconductor pillar 120 are surrounded by conductive layers 110, which face each other.

[0091] At the upper end of the semiconductor pillar 120, an impurity region 121 containing N-type impurities such as phosphorus (P) is provided. The impurity region 121 is connected to the bit line BL via contact Ch and contact Cb.

[0092] The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 may include, for example, a channel insulating film, a charge accumulating film, and a bulk insulating film deposited between the semiconductor pillar 120 and the conductive layer 110. The channel insulating film and the bulk insulating film may be, for example, insulating films such as silicon oxide (SiO2). The charge accumulating film may be, for example, a film capable of accumulating charge in the form of silicon nitride (Si3N4). The channel insulating film, the charge accumulating film, and the bulk insulating film have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120, excluding the contact portion between the semiconductor pillar 120 and the semiconductor layer 112.

[0093] Alternatively, the gate insulating film 130 may also have a floating gate, such as polysilicon containing N-type or P-type impurities.

[0094] Multiple contacts CC are provided at the ends of the multiple conductive layers 110 in the X direction. The multiple conductive layers 110 are connected to the peripheral circuit PC via the multiple contacts CC. Figure 6 As shown, the plurality of contacts CC extend in the Z direction and are connected at their lower ends to the conductive layer 110. The contacts CC may also comprise, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0095] [Construction of the peripheral circuit PC]

[0096] Peripheral circuit PC, for example Figure 4 As shown, the system includes line decoders RD0 and RD1, respectively connected to memory cell arrays MCA0 and MCA1, and sense amplifiers SA0 and SA1. Furthermore, the peripheral circuit PC includes a voltage generation circuit VG and a sequence generator SQC. The peripheral circuit PC also includes input / output control circuits (I / O), logic circuits (CTR), address register (ADR), command register (CMR), status register (STR), and data output timing adjustment unit (TCT). In the following description, line decoders RD0 and RD1 will sometimes be referred to as line decoders RD, and sense amplifiers SA0 and SA1 will sometimes be referred to as sense amplifiers SA.

[0097] [The structure of the line decoder RD]

[0098] Line decoder RD( Figure 4 For example, Figure 5 As shown, it includes: an address decoder 22, which adds address data (Add( Figure 4 Decoding; Block selection circuit 23 and voltage selection circuit 24 transmit the operating voltage to the memory cell array MCA according to the output signal of address decoder 22.

[0099] Address decoder 22 has multiple block select lines BLKSEL and multiple voltage select lines 33. Address decoder 22, for example, references the address register ADR sequentially according to control signals from sequence generator SQC. Figure 4 The row address RA is decoded, and the specific block select transistor 35 and voltage select transistor 37 corresponding to the row address RA are turned on, while the other block select transistors 35 and voltage select transistors 37 are turned off. For example, the voltage of a specific block select line BLKSEL and voltage select line 33 is set to "H" (high), and the other voltages are set to "L" (low). Alternatively, if P-channel transistors are used instead of N-channel transistors, the opposite voltage is applied to these traces.

[0100] In the illustrated example, the address decoder 22 provides one block select line (BLKSEL) for each memory block (BLK). However, this configuration can be modified. For example, it is also possible to provide one block select line (BLKSEL) for each of two or more memory blocks (BLK).

[0101] The block select circuit 23 includes multiple block select sections 34 corresponding to memory blocks BLK. Each of the multiple block select sections 34 includes multiple block select transistors 35 corresponding to word lines WL and select gate lines (SGD, SGS, SGSb). The block select transistors 35 are, for example, field-effect transistors. The drain electrodes of the block select transistors 35 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS, SGSb). The source electrodes are electrically connected to the voltage supply line 31 via wiring CG and voltage selection circuit 24. The gate electrodes are all connected to the corresponding block select line BLKSEL.

[0102] Additionally, the block selection circuit 23 also includes a plurality of transistors (not shown). These transistors are connected to the select gate lines (SGD, SGS, SGSb) and are supplied with a ground voltage V. SS The voltage supply lines are connected by field-effect transistors. These transistors supply ground voltage V to the select gate lines (SGD, SGS, SGSb) contained in the non-select memory block BLK. SS Additionally, the multiple word lines (WL) contained in the non-selected memory block (BLK) become floating.

[0103] The voltage selection circuit 24 includes multiple voltage selection sections 36 corresponding to word lines WL and select gate lines (SGD, SGS, SGSb). Each of the multiple voltage selection sections 36 includes multiple voltage selection transistors 37. The voltage selection transistors 37 are, for example, field-effect transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS, SGSb) via wiring CG and block select circuit 23. The source terminals are electrically connected to the corresponding voltage supply lines 31. The gate electrodes are connected to the corresponding voltage selection lines 33.

[0104] [Composition of the Sensing Amplifier SA]

[0105] Sensing amplifiers SA0, SA1 ( Figure 4 Each of them has a sense amplifier module SAM0, SAM1, and a high-speed cache memory CM0, CM1 (data register). The high-speed cache memory CM0, CM1 each has a latch circuit XDL0, XDL1.

[0106] Additionally, in the following description, the sense amplifier modules SAM0 and SAM1 are referred to as sense amplifier modules SAM, the cache memories CM0 and CM1 are referred to as cache memories CM, and the latch circuits XDL0 and XDL1 are referred to as latch circuits XDL.

[0107] The sense amplifier module (SAM) includes, for example, sense circuits corresponding to multiple bit lines (BL) and multiple latch circuits connected to the sense circuits.

[0108] The cache memory CM has multiple latch circuits XDL. These multiple latch circuits XDL are connected to latch circuits within the sense amplifier module SAM. The latch circuits XDL, for example, store user data Dat written to or read from the memory unit MC.

[0109] In the cache memory CM, for example, Figure 7 As shown, connect the column decoder COLD. The column decoder COLD will be stored in the address register ADR ( Figure 4 The column address CA () Figure 4 Decode and select the latch circuit XDL corresponding to the column address CA.

[0110] Furthermore, the user data Dat stored in the plurality of latch circuits XDL is sequentially transmitted to the latch circuits within the sense amplifier module SAM during a write operation. Additionally, the user data Dat contained in the latch circuits within the sense amplifier module SAM is sequentially transmitted to the latch circuits XDL during a read operation. Moreover, the user data Dat contained in the latch circuits XDL is sequentially transmitted to the input / output control circuit I / O via the column decoder COLD and the multiplexer MPX during data output, as described later.

[0111] [Construction of the voltage generation circuit VG]

[0112] Voltage generation circuit VG ( Figure 4 For example, Figure 5 As shown, it is connected to multiple voltage supply lines 31. The voltage generation circuit VG includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. The step-down circuit and the step-up circuit are respectively connected to the supplied power supply voltage V. CC and grounding voltage V SS ( Figure 4 The voltage supply line is, for example, connected to the reference. Figure 2 , Figure 3 The pad electrode P is described. The voltage generation circuit VG, for example, generates multiple operating voltages applied to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS, SGSb) when performing read, write, and erase operations on the memory cell array MCA according to the control signal from the sequence generator SQC, and simultaneously outputs them to multiple voltage supply lines 31. The operating voltages output from the voltage supply lines 31 are appropriately adjusted according to the control signal from the sequence generator SQC.

[0113] [Structure of Sequence Generator (SQC)]

[0114] Sequence generator SQC ( Figure 4 According to the command data Cmd stored in the command register CMR, the internal control numbers are output to the line decoders RD0 and RD1, the sense amplifier modules SAM0 and SAM1, and the voltage generation circuit VG. In addition, the sequence generator SQC outputs the status data Stt, which represents the status of the memory die MD, to the status register STR as appropriate.

[0115] Furthermore, the sequence generator SQC generates a ready / busy signal and outputs it to the terminal RY / / BY. The terminal RY / / BY is in the "L" state during operations such as read, write, and erase that supply voltage to the memory cell array MCA. It is in the "H" state during feature acquisition and feature setting (described later). However, it is in the "L" state even when performing data output and status read operations (described later). When the terminal RY / / BY is in the "L" state (busy period), access to the memory die MD is essentially prohibited. When the terminal RY / / BY is in the "H" state (ready period), access to the memory die MD is permitted. Additionally, the terminal RY / / BY is, for example, controlled by a reference... Figure 2 , Figure 3 The pad electrode P is implemented as described.

[0116] Furthermore, the sequence generator SQC has a feature register FR. The feature register FR is a register that stores feature data Fd. Feature data Fd includes, for example, control parameters of the memory die MD. Feature data Fd also includes, for example, a value indicating which of the following operating modes, MODEa and MODEb, the memory die MD should operate. Additionally, feature data Fd includes, for example, values ​​indicating the state of the input / output control circuit (I / O), as described later.

[0117] [Structure of the Address Register (ADR)]

[0118] Address Register (ADR) Figure 4 As shown, the address register (ADR) is connected to the input / output control circuit (I / O) and stores the address data (Add) input from the I / O. The ADR may have multiple 8-bit register columns. These register columns, for example, store multiple address data (Add) containing the address data (Add) corresponding to the currently executing action and the address data (Add) corresponding to the next action to be executed, during internal operations such as read, write, or erase.

[0119] Address data Add, for example, includes column address CA ( Figure 4 ) and row address RA ( Figure 4 The row address RA, for example, contains a specific memory block BLK. Figure 5 The block address of a specific string cell (SU) and word line (WL), the page address of a specific memory cell array (MCA) (plane), and the chip address of a specific memory die (MD).

[0120] Furthermore, if an action corresponding to another address data "Add" is instructed during the execution of an action corresponding to one address data "Add", there is a possibility that the expected action will not be executed properly. For example, in a memory die MD, if an instruction is given to output data to another plane (address data "Add" corresponding to a different plane) during the execution of outputting data from one plane, the timing of the action should be adjusted so that the next data output begins only after the initial data output has finished.

[0121] In contrast, for example, Figure 2 and Figure 3 As shown, in a configuration that connects multiple memory dies (MDs), when executing the output of data from a certain memory die MD, and instructing the output of data to other memory die MDs (address data corresponding to different memory dies), there is a situation where the user data Dat corresponding to the expected address cannot be output appropriately.

[0122] The output of user data Dat is indicated by toggling the input signals of the external control terminals / RE and RE. For example... Figure 2 and Figure 3 As shown, in a configuration with multiple memory die MDs connected, when outputting data from one memory die MD, and instructing to output data to other memory die MDs (address data corresponding to different memory MDs), there is a concern that two memory die MDs may perform data output in response to the toggle of the input signals of the external control terminal / RE.

[0123] Therefore, the semiconductor memory device of the first embodiment is configured to perform a switch on address data Add, which is the target of the operation, by means of an input trigger signal. For example, Figure 2 and Figure 3As shown, in a configuration connecting multiple memory dies (MDs), if, during the execution of data output from one memory die MD, data is instructed to be output to other memory die MDs (address data corresponding to different memory dies), the memory die MD subsequently instructing data output will not begin data output even if the input signals of the external control terminals / RE, RE are toggled, until a trigger signal is input. Furthermore, after detecting the completion of data output from the memory die MD that first performed data output, the controller die CD inputs a trigger signal to toggle the address data Add to all commonly connected memory die MDs, and then toggles the input signals of the external control terminals / RE, RE. The memory die MD that first performed data output will not respond even if it receives a trigger signal from the controller die CD. In contrast, the memory die MD subsequently instructing data output can respond to the toggle of the input signals of the external control terminals / RE, RE by receiving a trigger signal from the controller die CD, and thus perform data output. Therefore, conflicts can be avoided between memory die MDs that perform data output first and those that perform data output later. In other words, the trigger signal functions as a signal indicating when data output to the memory die MD can begin. Thus, as... Figure 2 and Figure 3 As shown, in a configuration that connects multiple memory dies (MDs), data can be continuously output from multiple memory dies (MDs).

[0124] [Composition of the Command Register (CMR)]

[0125] The command register (CMR) is connected to the input / output control circuit (I / O) and stores the command data (Cmd) input from the I / O. The command register CMR typically has at least one 8-bit register column. When the command data Cmd is stored in the command register CMR, a control signal is input to the sequence generator (SQC).

[0126] [The structure of the status register STR]

[0127] The status register STR is connected to the input / output control circuit (I / O) and stores the status data Stt of the I / O output. The status register STR may have multiple 8-bit register columns. These register columns store the status data Stt related to internal operations such as read, write, or erase during execution. Furthermore, the register columns may store the ready / busy information of memory cell arrays MCA0 and MCA1.

[0128] [Structure of the Data Output Timing Adjustment Unit (TCT)]

[0129] The data output timing adjustment unit (TCT) is connected to the bus wiring DB between the cache memories CM0 and CM1 and the input / output control circuit (I / O). For example, in the case where data output to cache memories CM0 and CM1 is performed continuously (as described later), after the data output from cache memory CM0 is completed, the TCT adjusts the start timing of the data output to cache memory CM1 to start the data output to cache memory CM1 without leaving any time gaps.

[0130] [Composition of Input / Output Control Circuit (I / O)]

[0131] Input / output control circuit I / O ( Figure 4 It features data signal input / output terminals DQ0~DQ7, data strobe signal input terminals DQS, / DQS, a shift register, and buffer circuitry. Input / output control circuit (I / O) Figure 4 The circuits in the circuit are connected to the power supply voltage V. CCQ and voltage V SS ( Figure 4 The terminals of the circuit. Additionally, the power supply voltage V is... CCQ and grounding voltage V SS For example, the terminals are from the reference. Figure 2 , Figure 3 The pad electrode P is implemented as described.

[0132] Data signal input / output terminals DQ0~DQ7 and data strobe signal input / output terminals DQS, / DQS are each available for reference. Figure 2 , Figure 3 The pad electrode P is implemented as described. Data input via data signal input / output terminals DQ0 to DQ7 is input from the buffer circuit to the cache memory CM, address register ADR, or command register CMR according to the internal control signal from the logic circuit CTR. Furthermore, data output via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit according to the internal control signal from the logic circuit CTR.

[0133] Signals input via data strobe signal input / output terminals DQS and / DQS (e.g., data strobe signals and their compensation signals) are used when data is input via data signal input / output terminals DQ0 to DQ7. The data input via data signal input / output terminals DQ0 to DQ7 is extracted into a shift register within the input / output control circuit I / O at the points when the voltage rises (switching input signal) of data strobe signal input / output terminal DQS and the voltage falls (switching input signal) of data strobe signal input / output terminal / DQS, and at the points when the voltage falls (switching input signal) of data strobe signal input / output terminal DQS and the voltage rises (switching input signal) of data strobe signal input / output terminal / DQS.

[0134] Input / output control circuit I / O ( Figure 4 For example, Figure 8 As shown, the circuit includes data signal input / output terminals DQ0 to DQ7, and an input circuit 201 and an output circuit 202 connected to each data strobe signal input / output terminal DQS, / DQS. The input circuit 201 is, for example, a receiver such as a comparator. The output circuit 202 is, for example, a driver such as an OCD (Off-Chip Driver) circuit.

[0135] In addition, input / output control circuit I / O ( Figure 4 The system includes multiple latching circuits 203 corresponding to each data signal input / output terminal DQ0 to DQ7. These latching circuits 203 are connected to the output terminals of the input circuits 201 connected to the corresponding data signal input / output terminals DQ0 to DQ7. Furthermore, at the switching point of the input signals of the data strobe signal input / output terminals DQS and / DQS as described above, the multiple latching circuits 203 latch either "H" or "L" based on the voltage value of the output terminal of the input circuit 201.

[0136] In addition, input / output control circuit I / O ( Figure 4 The system includes a signal transmission circuit 204 that corresponds to each data selection signal input / output terminal DQS, / DQS. The signal transmission circuit 204 may include, for example, an even number of CMOS (Complementary Metal Oxide Semiconductor) inverters connected in series. The input terminals of the signal transmission circuit 204 are connected to the output terminals of the input circuit 201. The output terminals of the signal transmission circuit 204 are connected to the latch circuit 203.

[0137] In addition, input / output control circuit I / O ( Figure 4 It has an internal path delay detection circuit 205. The internal path delay detection circuit 205, as shown... Figure 9As shown, it includes a signal transmission circuit 211 and a NAND (Not And) circuit 212. The signal transmission circuit 211 includes a reference circuit. Figure 8 The signal transmission circuit 204 described herein has the same configuration. Signal transmission circuit 211 functions as a copy of signal transmission circuit 204. One input terminal of NAND circuit 212 is connected to the output terminal of signal transmission circuit 211. The start signal for internal path delay detection circuit 205 is input to the other input terminal of NAND circuit 212. The output terminal of NAND circuit 212 is connected to both the input terminal of signal transmission circuit 211 and the input terminal of counter 213.

[0138] Depending on the usage conditions of the semiconductor memory device, this can sometimes lead to reference... Figure 8 The operating state of the signal transmission circuit 204 described herein varies. In such cases, the amount of signal delay may differ between the propagation path of the signal corresponding to the data signal input / output terminals DQ0 to DQ7 and the propagation path of the signal corresponding to the data strobe signal input / output terminals DQS and / DQS. The internal path delay detection circuit 205 is used to detect this difference in signal delay.

[0139] For example, when detecting the delay of a signal, NAND circuit 212 ( Figure 9 The start signal of the NAND circuit 204 is in the "H" state for a certain period of time. Accompanying this, the output signal of the NAND circuit 212 oscillates at a frequency corresponding to the delay of the signal transmission circuit 211. Therefore, during this period, the number of pulses output from the output terminal of the NAND circuit 212 is detected by the counter 213, thereby determining the signal delay in the signal transmission circuits 204 and 211. Furthermore, the number of pulses is stored as one of the feature data Fd in the feature register FR.

[0140] [The structure of the logic circuit CTR]

[0141] Logic circuit CTR ( Figure 4 It has multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP, and logic circuits connected to these external control terminals. The logic circuit CTR receives external control signals from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP, and responds to these signals by outputting internal control signals to the input / output control circuit (I / O).

[0142] Logic circuit CTR, for example Figure 8As shown, the system includes: an input circuit 201 connected to each of the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and / WP; and an output circuit 202 connected to each of the external control terminals CLE and ALE. Additionally, each of the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and / WP is, for example, derived from a reference... Figure 2 , Figure 3 The pad electrode P is implemented as described.

[0143] Signals input via the external control terminal / CE (e.g., a chip start signal) are used when selecting the memory die MD. In the first embodiment, the memory die MD input with "L" to the external control terminal / CE is in a state where it can input and output user data Dat, command data Cmd, and address data Add (hereinafter, sometimes simply referred to as "data"). Furthermore, in the first embodiment, the memory die MD input with "H" to the external control terminal / CE is in a state where it cannot input or output data. Additionally, as... Figure 8 As shown, the external control terminal / CE is connected to the input circuit 201.

[0144] Signals input via the external control terminal CLE (such as the command latch start signal) are used when using the command register CMR, etc. The function of the external control terminal CLE is described below.

[0145] Signals input via the external control terminal ALE (such as the address latch start signal) are used when using the address register ADR, etc. The function of the external control terminal ALE is described below.

[0146] Signals input via the external control terminal / WE (e.g., write start signal) are used when inputting data from the controller die CD to the memory die MD. The function of the external control terminal / WE is described below.

[0147] Signals input via external control terminals / RE and RE (e.g., read start signal and its compensation signal) are used when outputting data via data signal input / output terminals DQ0 to DQ7. The data output from data signal input / output terminals DQ0 to DQ7 is switched at the points when the voltage of external control terminal / RE drops (switching input signal) and the voltage of external control terminal RE rises (switching input signal), and at the points when the voltage of external control terminal / RE rises (switching input signal) and the voltage of external control terminal RE drops (switching input signal).

[0148] Signals input via external control terminals / WP (e.g., write start signal) are used to restrict the input of user data such as Dat from the controller die CD to the memory die MD.

[0149] In addition, logic circuit CTR, for example, Figure 4 As shown, a switching circuit C20 is included. In the memory die MD, when executing data output from one plane and instructing data output to other planes (address data corresponding to different planes), the switching circuit C20 adjusts the timing of its operation so that the next data output begins after the initial data output ends. Furthermore, the switching circuit C20, as shown... Figure 2 and Figure 3 In the configuration shown, which connects multiple memory dies (MDs), control is performed as follows: when outputting data from other memory dies (MDs) and instructing the output of data to the memory die (add corresponding to the address data of the different memory dies), even if the input signals of the external control terminals / RE and RE are toggled, data output will not begin until a trigger signal is received from the controller die CD.

[0150] [Motion Mode MODEa and Action Mode MODEb]

[0151] The semiconductor memory device of this embodiment can operate in operating mode MODEa and operating mode MODEb. Hereinafter, refer to... Figures 10-31 The following explanation is provided for action modes MODEa and MODEb.

[0152] [Function of external terminals in each mode]

[0153] Figure 10 This is a schematic diagram used to explain the function of the signal input / output terminals and external control terminals in the MODEa operating mode. Figure 11 This is a schematic diagram used to explain the function of the signal input / output terminals and external control terminals in the MODEb operating mode. Additionally, in the following explanation, data signal input / output terminals DQ0 to DQ7 are sometimes referred to as data signal input / output terminals DQ<7:0>.

[0154] In the action mode MODEa, for example... Figure 10 As shown, the data signal input / output terminals DQ<7:0> are used not only for the input and output of user data Dat, but also for the input and output of data other than user data Dat, such as command data Cmd, address data Add, status data Stt, and feature data Fd.

[0155] On the other hand, in the action mode MODEb, for example... Figure 11As shown, although the data signal input / output terminals DQ<7:0> are used for input / output of user data Dat, they are generally not used for input / output of data other than user data Dat, such as command data Cmd, address data Add, status data Stt, and feature data Fd. In operation mode MODEb, the external control terminals CLE and ALE are used for input / output of data other than user data Dat.

[0156] [The function of external terminals in MODEa]

[0157] Figure 12 This is a truth table used to explain the function of external terminals in the MODEa action mode. Additionally, Figure 12 In this code, "Z" indicates that either "H" or "L" can be input. "X" indicates that the input signal is fixed as either "H" or "L". "Input" indicates data input. "Output" indicates data output.

[0158] When the command data Cmd is input in the operation mode MODEa, the controller die CD sets the voltage of the data signal input / output terminal DQ<7:0> to "H" or "L" according to each bit of the 8-bit command data Cmd. When "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, the voltage of the external control terminal / WE is increased from "L" to "H".

[0159] When "H" or "L" is input to the external control terminals CLE and ALE, the data input via the data signal input / output terminals DQ<7:0> is used as command data Cmd, stored in the buffer memory within the input / output control circuit I / O, and then transferred to the command register CMR. Figure 4 ).

[0160] Furthermore, when the address data Add is input, the controller die CD sets the voltage of the data signal input / output terminal DQ<7:0> to "H" or "L" according to each bit of the 8-bit data constituting the address data Add. When "L" is input to the external control terminal CLE and "H" is input to the external control terminal ALE, the voltage of the external control terminal / WE is increased from "L" to "H".

[0161] When "L" or "H" is input to the external control terminals CLE and ALE, the data input via the data signal input / output terminals DQ<7:0> is used as address data Add, stored in the buffer memory within the input / output control circuit I / O, and then transferred to the address register ADR. Figure 4 ).

[0162] Furthermore, when inputting user data Dat, the controller die CD sets the voltage of the data signal input / output terminal DQ<7:0> to "H" or "L" according to each bit of the 8-bit data constituting user data Dat. With "L" input to the external control terminal CLE and "L" input to the external control terminal ALE, the input signal of the data strobe signal input / output terminal DQS and / DQS is toggled.

[0163] When the external control terminals CLE and ALE are input with "L", the data input via the data signal input / output terminals DQ<7:0> is used as user data Dat, stored in the buffer memory within the input / output control circuit I / O, and then transferred to the high-speed buffer memory CM via the bus DB. Figure 4 ).

[0164] Furthermore, when outputting user data Dat or status data Stt, the controller die CD toggles the input signals of external control terminals / RE and RE. Simultaneously, 8 bits of the user data Dat or status data Stt are output to the data signal input / output terminals DQ0 to DQ7. Additionally, the output signals of the data strobe signal input / output terminals DQS and / DQS are toggled.

[0165] Furthermore, when the memory die MD is set to standby mode, the controller die CD inputs "H" to the external control terminal / CE, for example.

[0166] Furthermore, when the memory die MD is set to the bus idle state, the controller die CD, for example, inputs "H" to the external control terminal / WE.

[0167] [The function of external terminals in the MODEb mode]

[0168] Figures 13-15 This is a truth table used to explain the function of the external terminals in the MODEb action mode. Additionally, Figures 13-15 In this code, "Z" indicates that either "H" or "L" can be input. "X" indicates that the input signal is fixed as either "H" or "L". "Input" indicates data input. "Output" indicates data output.

[0169] As described above, in operation mode MODEb, the external control terminals CLE and ALE are used for input and output of command data Cmd, address data Add, status data Stt, feature data Fd, etc. Here, please refer to... Figure 17As will be discussed later, in Action Mode MODEb, a signal is input before these data inputs and outputs, specifying the type of input or output data. Hereinafter, this signal will be called the Input / Output Data Selection Signal. In Action Mode MODEb, the Input / Output Data Selection Signal can be called the Header, and the command data (Cmd), address data (Add), status data (Stt), feature data (Fd), etc., input / output following the Input / Output Data Selection Signal can be called the Body. Furthermore, a combination of a Header and a Body can also be called a Frame.

[0170] Figure 13 This represents the period of the input / output data selection signal FSel ( Figure 17 The function of the external control terminal in the first cycle of )

[0171] During the first cycle of FSel, when the input address data Add is input to the input / output data selection signal, the controller die CD, for example, with "L" input to external control terminal CLE and "H" input to external control terminal ALE, will increase the voltage of external control terminal / WE from "L" to "H".

[0172] During the first cycle of FSel, if "L" is input to the external control terminal CLE and "H" is input to the external control terminal ALE, the first cycle of FSel ends. Furthermore, the data input during the subsequent FSel cycle S_In is stored as address data Add in the buffer memory within the input / output control circuit I / O and then transferred to the address register ADR. Figure 4 ).

[0173] During the first cycle of FSel, when the input address data Cmd is input and the input / output data selection signal is received, the controller die CD, for example, when "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, will increase the voltage of the external control terminal / WE from "L" to "H".

[0174] During the first cycle of FSel, if "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, the first cycle of FSel ends. Furthermore, the data input during the period S_In immediately following FSel is stored as command data Cmd in the buffer memory within the input / output control circuit I / O and transferred to the command register CMR. Figure 4 ).

[0175] During the first cycle of FSel, when the input / output data selection signal, which is used to indicate the trigger signal that can start data output, is input, the controller die CD, for example, with "H" input to external control terminal CLE and "H" input to external control terminal ALE, will increase the voltage of external control terminal / WE from "L" to "H".

[0176] During the first cycle of FSel, if "H" is input to both the external control terminal CLE and the external control terminal ALE, the first cycle of FSel ends. Additionally, the address data of the action object is switched.

[0177] During the first cycle of FSel, when the input / output data selection signal for the purpose of performing other actions is input, the controller die CD, for example, when "L" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, will increase the voltage of the external control terminal / WE from "L" to "H".

[0178] If “L” is input to the external control terminal CLE and “L” is input to the external control terminal ALE during the first cycle of FSel, a second cycle is added to FSel.

[0179] Figure 14 This indicates the function of the external control terminal during the second cycle of FSel, which is used to indicate the input / output data selection signal.

[0180] During the second cycle of FSel, when inputting user data Dat, address data Add, and command data Cmd, and other input / output data selection signals, the controller die CD, for example, with "L" input to external control terminal CLE and "H" input to external control terminal ALE, will raise the voltage of external control terminal / WE from "L" to "H".

[0181] In addition to user data (Dat), address data (Add), and command data (Cmd), the following data are listed: address data when specifying an address during execution status reading or feature acquisition. Furthermore, the feature data (Fd) required for execution feature setting is listed.

[0182] During the second cycle of FSel, if "L" is input to the external control terminal CLE and "H" is input to the external control terminal ALE, the data input during the period S_In immediately following FSel will be transferred to the address register ADR according to the command data Cmd input earlier. Figure 4 ), Feature register FR ( Figure 4 )wait.

[0183] During the second cycle of FSel, when the input / output data selection signal is selected for the main data other than the input / output user data Dat, the controller die CD, for example, when inputting "H" to the external control terminal CLE and inputting "H" to the external control terminal ALE, will raise the voltage of the external control terminal / WE from "L" to "H".

[0184] Other data besides user data Dat include, for example, status data Stt and feature data Fd output based on execution characteristics.

[0185] During the second cycle of FSel, if “H” is input to the external control terminal CLE and “H” is input to the external control terminal ALE, the data output by the period S_In immediately following the period of FSel is selected based on the command data Cmd input previously, and output from the input / output control circuit I / O.

[0186] During the second cycle of FSel, when the input / output data selection signal for the purpose of performing other actions is input, the controller die CD, for example, when "L" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, will increase the voltage of the external control terminal / WE from "L" to "H".

[0187] Additionally, during the Fsel period, signals input to external control terminals CLE and ALE are not stored in the command register CMR. Figure 4 Address register ADR ( Figure 4 Furthermore, if "L" is input to the external control terminal CLE and "L" is input to the external control terminal ALE during the second cycle of FSel, a third cycle can be added to FSel.

[0188] Figure 15 The function of the external control terminal is to indicate the period for inputting data other than user data Dat (S_In) or outputting data other than user data Dat (S_Out).

[0189] During the S_In period, when inputting data other than user data Dat, the controller die CD sets the voltage of the external control terminals CLE and ALE to "H" or "L" according to the bits of the 2-bit data that constitutes the user data Dat, and raises the voltage of the external control terminal / WE from "L" to "H".

[0190] Additionally, in operation mode MODEb, when user data Dat is input, the controller die CD sets the voltage of the data signal input / output terminals DQ<7:0> to "H" or "L" according to each bit of the 8-bit data constituting user data Dat. With "H" or "L" input to the external control terminals / RE and RE, the input signals of the data strobe signal input / output terminals DQS and / DQS are switched. This operation can be performed even during periods FSel, S_In, and S_Out.

[0191] In the MODEb operating mode, the data input via the data signal input / output terminals DQ<7:0> is stored as user data Dat in the buffer memory within the input / output control circuit I / O, and then transferred to the high-speed buffer memory CM via the bus DB.

[0192] During the S_Out period, when outputting data other than user data Dat, the controller die CD, for example, lowers the input signal of the external control terminal / WE. Simultaneously, 2 bits of data constituting the user data Dat are output from the external control terminals CLE and ALE.

[0193] During the S_In and S_Out periods, when the memory die MD is set to standby mode, the controller die CD inputs "H" to the external control terminal / CE, for example.

[0194] During the S_In and S_Out periods, when the memory die MD is set to the bus idle state, the controller die CD inputs "H" to the external control terminal / WE, for example.

[0195] [Signal input / output examples for each mode]

[0196] Figure 16 and Figure 17 This is a schematic waveform diagram used to explain the operation of the memory die MD in the first embodiment.

[0197] Figure 16 The waveforms are shown when the input command data Cmd and address data Add are entered in the action mode MODEa. Figure 16In the example shown, at time t101, the controller die CD inputs command data Cmd to the memory die MD. Furthermore, at time t102, the controller die CD inputs address data Add to the memory die MD. In the illustrated example, at times t102 and t103, 8 bits of data constituting the address data Add are input, but the number of cycles can be less than or more than 5. Furthermore, at time t103, the controller die CD inputs command data Cmd to the memory die MD. Furthermore, at time t104, corresponding to the rising edge of the signal input to the external control terminal / WE, the command data Cmd is received. This initiates readout operations, and the voltage at terminal RY / / BY drops from "H" to "L". However, there may be a slight delay from receiving the command data Cmd until the voltage at terminal RY / / BY drops from "H" to "L".

[0198] Figure 17 The waveform is shown when the command data Cmd and address data Add are input in the action mode MODEb. Figure 17 In the example, "L" and "H" are input to the external control terminal / WE at approximately a fixed speed. Furthermore, if the period from the first drop to the second drop of the input signal to the external control terminal / WE is set to one cycle, Figure 17 The example shows a period of 1 cycle FSel and a period of 4 cycles S_In.

[0199] Figure 17 In the example, during the period FSel from time t151 to t152, the controller die CD inputs the input / output data selection signal of the specified input command data Cmd to the memory die MD.

[0200] In addition, during time point t152 to t153, S_In, the controller die CD inputs command data Cmd to the memory die MD.

[0201] Here, Figure 17 In the example, during the S_In period, the controller die CD is divided into 4 cycles, each cycle inputting 8 bits of command data Cmd to the memory die MD in 2-bit units. For example, the 8-bit command data Cmd is set to bits "7" to "0". First, in the data input of the first cycle, according to bits "7" and "6", while the voltage of the external control terminals CLE and ALE is set to "H" or "L", the voltage of the external control terminal / WE is increased from "L" to "H". The data input of the second to fourth cycles is the same, according to bits "5" and "4", bits "3" and "2", and bits "1" and "0", while the voltage of the external control terminals CLE and ALE is set to "H" or "L" respectively, the voltage of the external control terminal / WE is increased from "L" to "H".

[0202] In addition, during time points t153 to t154, FSel, the controller die CD inputs the input / output data selection signal of the specified input address data Add to the memory die MD.

[0203] In addition, during time point t154 to t155, S_In, the controller die CD inputs address data Add to the memory die MD.

[0204] Here, Figure 17 In the example, during the period S_In, the controller die CD is divided into 4 cycles, and the 8-bit data of address data Add is formed by inputting the memory die MD in 2-bit units.

[0205] In addition, although the attached diagram is omitted, the same applies at time points t155 to t156, where the data constituting the address data Add is input in units of 2 bits each.

[0206] Furthermore, during time points t156 to t157, FSel, similar to time points t151 to t152, inputs the input / output data selection signal for the specified input command data Cmd.

[0207] Furthermore, during time points t157 to t158, S_In, the controller die CD inputs command data Cmd to the memory die MD. Additionally, slightly earlier than time point t158, at the rising edge of the signal input to the external control terminal / WE, readout operations begin, and the voltage at terminal RY / / BY drops from "H" to "L".

[0208] [action]

[0209] Next, the operation of the memory die MD will be explained.

[0210] The memory die (MD) is constructed by performing read operations. The read operation is performed by the sense amplifier module (SAM). Figure 4 The user data Dat is read from the memory cell array MCA and then transferred to the latch circuit XDL. Figure 4 The operation of reading out data is as follows: During the readout operation, the user data Dat read from the memory cell array MCA is transmitted to the latch circuit XDL via the bit line BL and the sense amplifier module SAM.

[0211] Furthermore, the memory die (MD) is configured to perform data output. Data output is achieved by using the latch circuit XDL (…). Figure 4 The user data Dat contained in the output is sent to the controller's bare CD. Figure 1 The operation involves... In the data output, the user data Dat contained in the latch circuit XDL is passed through a reference... Figure 7The description includes the column decoder COLD, multiplexer MPX, bus wiring DB, and input / output control circuit I / O, with outputs to the controller bare die CD.

[0212] Furthermore, the memory die MD is configured to perform status reads (status information output actions). Status reads involve accessing the status register STR (...). Figure 4 The status data Stt contained in the ) is output to the controller bare CD ( Figure 1 The operation involves reading the status data Stt contained in the status register STR and outputting it to the controller die CD via the input / output control circuit I / O or the logic circuit CTR.

[0213] Furthermore, the memory die MD is constructed by performing feature acquisition (feature information output action). Feature acquisition is achieved by transferring the feature register FR ( Figure 4 The feature data Fd contained in the ) is output to the controller bare die CD ( Figure 1 The action of ) is as follows. During feature acquisition, the feature data Fd contained in the feature register FR is output to the controller die CD via the input / output control circuit I / O or the logic circuit CTR.

[0214] Furthermore, the memory die MD can be configured by performing feature settings. Feature setting involves inputting feature data Fd into the feature register FR. Figure 4 The action of ) is as follows. In the feature setting, feature data Fd is input to the feature register FR from the controller die CD via the input / output control circuit I / O or the logic circuit CTR.

[0215] [Reading actions and data output in MODEa mode]

[0216] Figure 18 It is a schematic waveform diagram showing the status of reading and data output when performing actions in MODEa. Figure 18 In the example, the memory die MD is set to the operation mode MODEa.

[0217] Figure 18 In the example, firstly, command data "00h", address data "Add", and command data "30h" are sequentially input via the data signal input / output terminals DQ<7:0>. Command data "00h" is the command data Cmd input at the beginning of the command group indicating the read operation. Command data "30h" is the command data Cmd input at the end of the command group indicating the read operation.

[0218] With the input of command data "00h", address data Add, and command data "30h", the read operation begins, and the voltage at terminal RY / / BT drops from "H" to "L". Additionally, user data Dat is transmitted to the latch circuit XDL. Furthermore, at the end of the read operation, the voltage at terminal RY / / BY rises from "L" to "H".

[0219] Next, via the data signal input / output terminals DQ<7:0>, the command data "05h", address data Add, and command data "E0h" are input sequentially. Command data "05h" is the command data Cmd input at the beginning of the command group indicating data output. Command data "E0h" is the command data Cmd input at the end of the command group indicating data output.

[0220] With the input of command data "05h", address data Add, and command data "E0h", after a specific standby time, the controller's bare die CD toggle the input signals of the external control terminals / RE and RE. This initiates data output, sending the user data Dat via the data signal input / output terminal DQ.

[0221] Figure 19 It is a schematic waveform diagram representing other states when performing read actions and data output under the MODEa action mode. Figure 19 In the example, the memory die MD is set to the operation mode MODEa.

[0222] Figure 19 In the example, firstly, command data "00h", address data Add, and command data "30h" are sequentially input via the data signal input / output terminals DQ<7:0>. The address data Add contained in the command group includes the plane PLN0 (which becomes the object of the read operation). Figure 4 The information is used as the plane address.

[0223] With the input of command data "00h", address data Add and command data "30h", the reading operation of plane PLN0 begins, and the user data Dat is transmitted to latch circuit XDL0.

[0224] Next, via the data signal input / output terminals DQ<7:0>, command data "00h", address data Add, and command data "30h" are sequentially input. The address data Add included in the command group contains the plane PLN1 (which becomes the object of the read operation). Figure 4 The information is used as the plane address.

[0225] With the input of command data "00h", address data Add and command data "30h", the reading operation of plane PLN1 begins, and the user data Dat is transmitted to latch circuit XDL1.

[0226] Next, command data "70h" is input via the data signal input / output terminal DQ<7:0>. Command data "70h" is command data Cmd indicating status reading. With the input of command data "70h", status reading is performed, and status data Stt is output via the data signal input / output terminal DQ<7:0>.

[0227] Next, via the data signal input / output terminals DQ<7:0>, command data "05h", address data Add, and command data "E0h" are sequentially input. The address data Add included in the command group contains the plane PLN0 (which becomes the object of data output). Figure 4 The information is used as the plane address.

[0228] With the input of command data "05h", address data Add, and command data "E0h", after a specific standby time, the controller die CD toggle the input signals of the external control terminals / RE and RE. This initiates data output to the plane PLN0, outputting user data "DataOut" via the data signal input / output terminals DQ<7:0>.

[0229] After the data output to plane PLN0 is completed, the command data "70h" is input via the data signal input / output terminal DQ<7:0>. With the input of the command data "70h", the status is read again, and the status data Stt is output via the data signal input / output terminal DQ<7:0>.

[0230] Next, similar to the data output to PLN0, command data "05h", address data Add, and command data "E0h" are sequentially input via data signal input / output terminals DQ<7:0>. The address data Add included in the command group contains the plane PLN1 (which becomes the object of data output). Figure 4 The information is used as the plane address.

[0231] After a specific period of time, the controller toggle the input signals of the external control terminals / RE and RE on the bare die CD. This initiates data output to the plane PLN1, outputting user data "DataOut" via the data signal input / output terminals DQ<7:0>.

[0232] [Reading Actions and Data Output under Action Mode MODEb]

[0233] Figure 20It is a schematic waveform diagram showing the status of reading and data output when performing the action mode MODEb. Figure 20 In the example, the memory die MD is set to the operation mode MODEb.

[0234] Figure 20 In the example, firstly, a command group containing the command data "00h" is input via the external control terminals CLE and ALE. Next, a command group containing the command data "05h" is input via the external control terminals CLE and ALE. Additionally, in operation mode MODEb, data input / output via the data signal input / output terminals DQ<7:0> and data input / output via the external control terminals CLE and ALE can be performed at independent points in time. For example, Figure 20 In the example, these command groups are input during the period of data output execution (during the period when the input signals of the external control terminal / RE, RE are triggered).

[0235] Figure 21 It is a schematic waveform diagram representing other states when performing read actions and data output under the action mode MODEb. Figure 21 In the example, the memory die MD is set to the operation mode MODEb.

[0236] Figure 21 In the example, firstly, command data "00h", address data Add, and command data "30h" are sequentially input via external control terminals CLE and ALE. The address data Add included in the command group contains the plane PLN0 (which is the object of the read operation). Figure 4 The information is used as the plane address.

[0237] Next, via external control terminals CLE and ALE, command data "00h", address data Add, and command data "30h" are input sequentially. The address data Add included in the command group contains the plane PLN1 (which becomes the object of the read operation). Figure 4 The information is used as the plane address.

[0238] Next, input the command data "70h" via the external control terminals CLE and ALE. As the command data "70h" is input, the status is read, and the status data Stt is output via the external control terminals CLE and ALE.

[0239] Next, via external control terminals CLE and ALE, command data "05h", address data Add, and command data "E0h" are input sequentially. The address data Add includes the plane PLN0 (which becomes the object of data output). Figure 4 The information is used as the plane address.

[0240] After a specific standby time, data is output to the plane PLN0, and user data "DataOut" is output via the data signal input / output terminals DQ<7:0>.

[0241] also, Figure 21 In the example, during data output to plane PLN0, command data "70h" is input via external control terminals CLE and ALE. Status is read along with the input of command data "70h". In the illustrated example, during data output to plane PLN0, status data Stt is output via external control terminals CLE and ALE.

[0242] also, Figure 21 In the example, during data output to plane PLN0, command data "05h", address data Add, and command data "E0h" are sequentially input via external control terminals CLE and ALE. The address data Add includes the plane PLN1 that is the object of the data output. Figure 4 The information is used as the plane address.

[0243] Here, in Action Mode MODEb, unlike Action Mode MODEa, the data output timing adjustment unit TCT (…) Figure 4 Adjust the start time of data output to plane PLN1. After the data output to plane PLN0 is completed, according to the internal signal issued by the data output timing adjustment unit TCT, start outputting data to plane PLN1 and output user data "DataOut" through the data signal input / output terminals DQ<7:0>.

[0244] Figure 22 It is a schematic waveform diagram representing other states when performing read actions and data output under the action mode MODEb. Figure 22 In the example, the memory die MD is set to operation mode MODEb. Here, an example is given... Figure 2 and Figure 3 The following example illustrates how multiple memory dies (MDs) perform read operations and data outputs.

[0245] As described above, the memory die MD of the semiconductor memory device in the first embodiment is configured such that, after indicating data output, it receives a trigger signal from the controller die CD, thereby enabling data output to be performed in accordance with the toggle of the input signals of the external control terminals / RE and RE. For example, Figure 22In the example, during the data output to memory die MD0, data output is indicated to memory die MD1. At this point, memory die MD0 performs data output by toggling the input signals of the external control terminals / RE and RE. In contrast, memory die MD1, after indicating data output, does not begin data output until it receives a trigger signal from the controller die CD, even if the input signals of the external control terminals / RE and RE are toggled. Therefore, data output conflicts are avoided between the commonly connected memory dies MD0 and MD1. After detecting the completion of data output from memory die MD0, the controller die CD inputs a trigger signal to the commonly connected memory dies MD0 and MD1. That is, as referenced... Figure 13 As explained, input "H" to the external control terminal CLE and input "H" to the external control terminal ALE. Accompanying this, as... Figure 22 As shown, data is started being output from the memory die MD1.

[0246] [Status reading in MODEa mode]

[0247] Figure 23 This represents the waveform when reading the execution status under the MODEa action mode. Figure 23 In the example, at time t201, the controller die CD inputs command data 70h to the memory die MD. Furthermore, at time t202, it outputs status data Stt.

[0248] [Status reading under MODEb mode]

[0249] Figure 24 This represents the waveform when reading the execution status under the action mode MODEb.

[0250] Figure 24 In the example, during the period FSel from time point t251 to t252, the controller die CD inputs the input / output data selection signal of the specified input command data Cmd to the memory die MD.

[0251] In addition, during the period S_In from time point t252 to t253, the controller die CD inputs command data 70h to the memory die MD.

[0252] in addition, Figure 24 In the example, during the period S_In, the controller die CD is divided into 4 cycles, each in 2-bit units, to input 8-bit command data 70h to the memory die MD.

[0253] Furthermore, during the period FSel from time t253 to t254, the controller die CD inputs the input / output data selection signal to the memory die MD to specify the output data.

[0254] In addition, during the period from time t254 to t255, S_Out, the memory die MD outputs status data Stt to the controller die CD.

[0255] [Reading other states under MODEa]

[0256] Figure 25 This shows the waveform when other state reads are performed under the action mode MODEa. Figure 25 In the example, at time t301, the controller die CD inputs command data 78h to the memory die MD. Command data "78h" is command data Cmd indicating the reading of other states. Furthermore, at time t302, the controller die CD inputs address data Add to the memory die MD. Additionally, in the illustrated example, after time t302, 8 bits of data constituting the address data Add are input for 3 cycles, but the number of cycles can be less than 3 or more than 5. Furthermore, at time t303, status data Stt is output.

[0257] [Reading other states under Action Mode MODEb]

[0258] Figure 26 This shows the waveform when other state reads are performed under the action mode MODEb.

[0259] Figure 26 In the example, during the period FSel from time t351 to t352, the controller die CD inputs the input / output data selection signal of the specified input command data Cmd to the memory die MD.

[0260] In addition, during the period S_In from time point t352 to t353, the controller die CD inputs command data to the memory die MD for 78 hours.

[0261] Here, Figure 26 In the example, during the period S_In, the controller die CD is divided into 4 cycles, each consisting of 2 bits, to input 8 bits of command data 78h to the memory die MD.

[0262] Furthermore, during the period FSel from time t353 to t354, the controller die CD inputs an input / output data selection signal to the memory die MD to specify the input address data.

[0263] In addition, during the period S_In from time point t354 to t355, the controller die CD inputs address data Add to the memory die MD.

[0264] Similarly, during the period FSel from time point t355 to t356, and during the period FSel from time point t357 to t358, the controller die CD inputs the input / output data selection signal to the memory die MD to specify the input address data.

[0265] In addition, during the period S_In from time point t356 to t357, the controller die CD inputs address data Add to the memory die MD.

[0266] [Feature Acquisition in Action Mode MODEa]

[0267] Figure 27 This shows the waveform when feature acquisition is performed in action mode MODEa. Figure 27 In the example, at time t401, the controller die CD inputs command data EEh to the memory die MD. The command data "EEh" is the command data Cmd indicating feature acquisition. Furthermore, at time t402, the controller die CD inputs address data Add to the memory die MD. In the illustrated example, after time t402, 8 bits of data constituting the address data Add are input for 3 cycles, but the number of cycles can be less than 3 or more than 5. Furthermore, at time t403, corresponding to the rising edge of the signal input to the external control terminal / WE, feature acquisition begins, and the voltage at terminal RY / / BY drops from "H" to "L". Furthermore, at time t404, feature acquisition ends, and the voltage at terminal RY / / BY rises from "L" to "H". Furthermore, at time t405, feature data Fd is output.

[0268] [Status reading under MODEb mode]

[0269] Figure 28 This displays the waveform when the execution status is read under action mode MODEb.

[0270] Figure 28 In the example, during the period FSel from time t451 to t452, the controller die CD inputs the input / output data selection signal of the specified input command data Cmd to the memory die MD.

[0271] In addition, during the period S_In from time point t452 to t453, the controller die CD inputs command data EEh to the memory die MD.

[0272] in addition, Figure 28 In the example, during the period S_In, the controller die CD is divided into 4 cycles, each in 2-bit units, to input 8-bit command data EEh to the memory die MD.

[0273] Furthermore, during the period FSel from time t453 to t454, the controller die CD inputs an input / output data selection signal to the memory die MD to specify the input address data.

[0274] In addition, during the period S_In from time point t454 to t455, the controller die CD inputs address data Add to the memory die MD.

[0275] Similarly, during the period FSel from time t455 to t456 and during the period FSel from time t457 to t458, the controller die CD inputs the input / output data selection signal to the memory die MD to specify the input address data.

[0276] In addition, during the period S_In from time point t456 to t457, the controller die CD inputs address data Add to the memory die MD.

[0277] [Feature settings under Action Mode]

[0278] Figure 29 This represents the waveform when performing feature settings in the MODEa action mode. Figure 29 In the example, at time t501, the controller die CD inputs command data EFh to the memory die MD. Command data "EFh" is command data Cmd indicating feature settings. Furthermore, at time t502, the controller die CD inputs address data Add to the memory die MD. Additionally, in the illustrated example, after time t502, 8 bits of data constituting the address data Add are input, but the number of cycles can be less than or more than 3. Furthermore, at time t503, the controller die CD inputs feature data Fd to the memory die MD. Furthermore, at time t504, feature settings begin, and the voltage at terminals RY / / BY drops from "H" to "L".

[0279] [Feature settings under Action Mode MODEb]

[0280] Figure 30 This displays the waveform when the feature settings are executed under the action mode MODEb.

[0281] Figure 30 In the example, during the period FSel from time t551 to t552, the controller die CD inputs the input / output data selection signal of the specified input command data Cmd to the memory die MD.

[0282] In addition, during the period S_In from time point t552 to t553, the controller die CD inputs command data EFh to the memory die MD.

[0283] Here, Figure 30In the example, during the period S_In, the controller die CD is divided into 4 cycles, each in 2-bit units, to input 8-bit command data EFh to the memory die MD.

[0284] In addition, during time points t553 to t554, FSel is the input / output data selection signal for the controller die CD to input data at a specified address to the memory die MD.

[0285] In addition, during the period S_In from time point t554 to t555, the controller die CD inputs address data Add to the memory die MD.

[0286] Similarly, during the period FSel from time t555 to t556, the controller die CD inputs the input / output data selection signal to the memory die MD to specify the input address data.

[0287] In addition, during the period S_In after time point t556 and during the period S_In up to time point t557, the controller die CD inputs address data Add to the memory die MD.

[0288] Furthermore, during the period FSel from time t557 to t558, the controller die CD inputs the input / output data selection signal to the memory die MD to specify the input data.

[0289] In addition, during the period S_In from time point t558 to t559, the controller die CD inputs characteristic data Fd to the memory die MD.

[0290] Similarly, during the period FSel from time t559 to t560, the controller die CD inputs the input / output data selection signal to the memory die MD to specify the input data.

[0291] In addition, during the period S_In after time point t560 and during the period S_In up to time point t561, the controller die CD inputs characteristic data Fd to the memory die MD.

[0292] [Effect]

[0293] For reference Figure 10 As explained above, in operating mode MODEa, the data signal input / output terminals DQ<7:0> are used not only for the input / output of user data Dat, but also for the input / output of command data Cmd, address data Add, and other data other than user data Dat. Therefore, for example, as referenced... Figure 19 As explained, if readout actions and data outputs are continuously performed on planes PLN0 and PLN1, and if the data output to plane PLN0 is not completed, then there is a situation where the command group for performing data output to plane PLN1 cannot be input.

[0294] Here, the semiconductor memory device of this embodiment can operate in Operation Mode MODEb. In Operation Mode MODEb, as described above, during data output via the data signal input / output terminals DQ<7:0>, command data Cmd and address data Add can also be input via the external control terminals CLE and ALE. Therefore, for example, as referenced... Figure 21 As explained, when continuously performing read operations and data outputs on planes PLN0 and PLN1, if a data output to plane PLN0 is being performed, a command group for performing data output to plane PLN1 can be input. This reduces the time required to input command groups to the memory die MD, thereby achieving high-speed operation of the semiconductor memory device.

[0295] In addition, as referenced Figure 13 , Figure 14 As explained, in the semiconductor memory device of this embodiment, if any one of "L, H", "H, L", or "H, H" is input to the external control terminals CLE and ALE during the first cycle of FSel, the first cycle of FSel ends. Furthermore, if "L, L" is input to the external control terminals CLE and ALE during the first cycle of FSel, a second cycle can be added to FSel to further specify other operations. Therefore, for some functions, high-speed operation can be achieved, and operations can be appropriately specified.

[0296] For example, the semiconductor memory device according to this embodiment, such as Figure 31 As illustrated, during the data output process, actions such as feature setting and feature acquisition can also be performed.

[0297] [A deserializer applicable to the memory die MD of the first embodiment]

[0298] In the memory die MD of the first embodiment, the functions of the data signal input / output terminals DQ<7:0> and external control terminals CLE, ALE, etc., change depending on which operation mode MODEa or MODEb is selected. Hereinafter, refer to... Figures 32-36 Here is an example of a circuit that has this function. Figure 32 This is a schematic flowchart used to illustrate one example of this type of circuit. Figure 33 , Figure 35 and Figure 36 This is a schematic circuit diagram used to illustrate other examples of this type of circuit. Figure 34 It is used to Figure 33 The circuit shown is illustrated with a schematic waveform diagram to explain its operation.

[0299] and Figure 32 The corresponding circuit can also be implemented by a state machine, for example. The circuit, for example, stores the signals input to the external control terminals CLE and ALE as part of the input / output selection signals (step S101). Next, it determines whether the external control terminals CLE and ALE are "L, L" (step S102). If the external control terminals CLE and ALE are "L, L", it returns to step S101. If the external control terminals CLE and ALE are not "L, L", the variable cnt is set to 0, and the process proceeds to step S103. Next, the signals input to the external control terminals CLE and ALE are stored as part of data other than user data Dat (step S103). Next, it determines whether the variable cnt is less than 4 (step S104). If the variable cnt is less than 4, 1 is added to the variable cnt, and the process returns to step S103. If the variable cnt is not less than 4, the process returns to step S101.

[0300] Figure 33 Examples include the data signal input / output terminal DQ<7:0>, the external control terminals CLE, ALE, / WE, and the circuit section 200 connected to the terminals.

[0301] The circuit section 200 includes, for example, a latch circuit 210, multiplexers 220 and 230, and a deserializer 300.

[0302] Latch circuit 210 is a latch circuit included in the command register CMR, address register ADR, or feature register FR. For example, multiple latch circuits 210 are configured corresponding to the command register CMR. The number of latch circuits 210 can also be the same as the number of usable command data Cmd. In addition, multiple latch circuits 210 are configured corresponding to the address register ADR. The number of address data Add that can be stored can also be the product of the number of bits of the address data Add. In addition, multiple latch circuits 210 can also be configured corresponding to the feature register FR. In the illustrated example, latch circuit 210 corresponds to the input command data Cmd and stores 1 bit of data. Latch circuit 210 connects the data input terminal to the output terminals DINh<7:0>, CLEh, and ALEh of multiplexer 220 via logic circuits, and connects the clock input terminal to the output terminal / WEh' of multiplexer 230.

[0303] Input the selection signal SerialCA to the respective selection control terminals of multiplexers 220 and 230. When the operation mode MODEa is selected, the selection signal SerialCA becomes "0" and when the operation mode MODEb is selected, it becomes "1".

[0304] The multiplexer 220 has 10 output terminals: DINh<7:0>, CLEh, and ALEh. Eight of these output terminals, DINh<7:0>, correspond to data other than the user data Dat. The remaining two output terminals, CLEh and ALEh, correspond to the input signals of the external control terminals CLE and ALE.

[0305] Furthermore, the multiplexer 220 includes 10 input terminals selected when the selection signal SerialCA is "0" and 10 input terminals selected when the selection signal SerialCA is "1". Eight of the ten input terminals corresponding to the "0" state are connected to the data signal input / output terminals DQ<7:0>. The remaining two are connected to the external control terminals CLE and ALE. The ten input terminals corresponding to the "1" state are connected to the output terminals of the deserializer 300.

[0306] The multiplexer 230 has one output terminal / WEh'. Furthermore, the multiplexer 230 has one input terminal / WEh that is selected when the selection signal SerialCA is "1"; and one input terminal that is selected when the selection signal SerialCA is "0". The input terminal / WEh corresponding to the "1" state is connected to the output terminal of the deserializer 300. The input terminal corresponding to the "0" state is connected to the external control terminal / WE.

[0307] The deserializer 300 has 10 output terminals connected to the multiplexer 220. The deserializer 300 converts data input from external control terminals CLE and ALE in 2-bit units each over 4 cycles into 8-bit data, adding 2 bits to indicate whether the 8-bit data is command data (Cmd) or address data (Add), resulting in 10-bit data. Furthermore, the deserializer 300 outputs the 10-bit data to the multiplexer 220 via the 10 output terminals. The 10-bit data can also be switched at the start of the FSel period, for example.

[0308] Furthermore, the deserializer 300 has one output terminal connected to the multiplexer 230. During the period from the input of the first cycle of data from multiple cycles input from the external control terminal / WE to the input of the second cycle of data (the first cycle of period FSel), the deserializer 300 outputs "L" to the input terminal / WEh of the multiplexer 230. Additionally, during this further period, it outputs "H" to the input terminal / WEh of the multiplexer 230.

[0309] In operation mode MODEa, the 8-bit data input via the data signal input / output terminals DQ<7:0> is input to the logic circuit via the output terminals DINh<7:0> of the multiplexer 220. Furthermore, the start signal input via the external control terminals CLE and ALE is input to the logic circuit via the output terminals CLEh and ALEh of the multiplexer 220. For example, if the 8-bit data input via the data signal input / output terminals DQ<7:0> is command data "05h", and the input signals of the external control terminals CLE and ALE are "H" and "L", the output signal of the logic circuit corresponding to the command data "05h" becomes "H". Otherwise, the output signal of the logic circuit corresponding to the command data "05h" becomes "L".

[0310] In addition, in operating mode MODEa, the signal input from the external control terminal / WE is output from the output terminal / WEh' of the multiplexer 230 and input to the clock input terminal of the latch circuit 210.

[0311] In operation mode MODEb, 2-bit × multiple-cycle (e.g., 5 or 6 cycles) data input via external control terminals CLE and ALE is converted into multi-bit (e.g., 10 or 12 bits) data by deserializer 300. Furthermore, 10 bits of this multi-bit data are input to the input terminals of multiplexer 220. The data and signals are input to the logic circuit via the output terminals DINh<7:0>, CLEh, and ALEh of multiplexer 220. For example, if during period FSel, "H" or "L" is input from external control terminals CLE and ALE, and during period S_In, command data "05h" is input from external control terminals CLE and ALE, the output signal of the logic circuit corresponding to command data "05h" becomes "H". Otherwise, the output signal of the logic circuit corresponding to command data "05h" becomes "L". Furthermore, for example... Figure 34 As illustrated, in action mode MODEb, the deserializer 300 sets / WEh to the "H" state in any one of the multiple cycles contained in the period FSel or the periods S_In and S_Out, and sets / WEh to the "L" state in other cycles.

[0312] In addition, in operation mode MODEb, the signal input to the input terminal / WEh of the multiplexer 230 is output from the output terminal / WEh' of the multiplexer 230 and input to the clock input terminal of the latch circuit 210.

[0313] Figure 35 and Figure 36 This is a schematic circuit diagram showing a portion of the deserializer 300. The deserializer 300 includes, for example: Figure 35 The circuit section 310 shown, and as shown Figure 36 The circuit section 320 shown.

[0314] like Figure 35 As shown, the circuit section 310 includes seven D flip-flops 311 and one D latch circuit 312.

[0315] The output terminal of the first D flip-flop 311 is connected to the data input terminals of the second and fourth D flip-flops 311 via a switching circuit 315. When the external control terminals CLE and ALE are "L, L", the switching circuit 315 transmits the output signal of the first D flip-flop 311 to the data input terminal of the second D flip-flop 311. Furthermore, in other cases, the output signal of the first D flip-flop 311 is transmitted to the data input terminal of the fourth D flip-flop 311.

[0316] The output terminal of the second D flip-flop 311 is connected to the data input terminals of the third and fourth D flip-flops 311 via a switching circuit 315. When the external control terminals CLE and ALE are "L, L", the switching circuit 315 transmits the output signal of the second D flip-flop 311 to the data input terminal of the third D flip-flop 311. Furthermore, in other cases, the output signal of the second D flip-flop 311 is transmitted to the data input terminal of the fourth D flip-flop 311.

[0317] The output terminal of the third D flip-flop 311 is connected to the data input terminal of the fourth D flip-flop 311. Similarly, the output terminals of the fourth to sixth D flip-flops 311 are connected to the data input terminals of the fifth to seventh D flip-flops 311, respectively. The output terminal of the seventh D flip-flop 311 is connected to the data input terminal of the D flip-flop 312. The output terminal of the D latch circuit 312 is connected to the data input terminal of the first D flip-flop 311. Furthermore, the clock input terminals of the seven D flip-flops 311 and the one D latch circuit 312 are connected to the external control terminal / WE.

[0318] Furthermore, the circuit section 310 includes seven D latch circuits 313 and seven AND circuits 314. The data input terminals of the seven D latch circuits 313 are respectively connected to the output terminals of the seven D flip-flops 311. Additionally, the inverted signal of the external control terminal / WE is input to the clock input terminals of the seven D latch circuits 313. One input terminal of each of the seven AND circuits 314 is connected to the output terminal of each of the seven D latch circuits 313. The other input terminal of each of the seven AND circuits 314 is connected to the external control terminal / WE. Furthermore, Figure 35In the example, the first to third output terminals of the seven AND circuits 314 are designated as output terminals WE1_1 to WE1_3. Furthermore, the fourth to sixth output terminals are designated as output terminals WE2 to WE4. The remaining output terminal is connected to the multiplexer 230. Figure 33 ) input terminal / WEh.

[0319] Here, the initial value of the data stored in the 7 D flip-flops 311 is set to 0, and the initial value of the data stored in the D latch circuit 312 is set to 1.

[0320] If the output signal of the D latch circuit 312 is “H” and “H” is input to the external control terminal / WE, then the output terminal WE1_1 will change to the “H” state, and the signals of the output terminals WE1_2, WE1_3, WE2, WE3, and WE4, as well as the output signal of the D latch circuit 312, will change to the “L” state.

[0321] If the signal at output terminal WE1_1 is “H” and the signals at external control terminals CLE and ALE are “L”, and “H” is input to external control terminal / WE, then the signal at output terminal WE1_2 will change to “H”, and the signals at output terminals WE1_1, WE1_3, WE2, WE3, and WE4, as well as the output signal of D latch circuit 312, will change to “L”.

[0322] If the signal at output terminal WE1_1 is “H” and the signals at external control terminals CLE and ALE are “L, H”, “H, L”, or “H, H”, and “H” is input to external control terminal / WE, then the signal at output terminal WE2 will change to “H”, and the signals at output terminals WE1_1, WE1_2, WE1_3, WE3, and WE4, as well as the output signal of D latch circuit 312, will change to “L”.

[0323] If the signal at output terminal WE1_2 is “H” and the signals at external control terminals CLE and ALE are “L”, and “H” is input to external control terminal / WE, then the signal at output terminal WE1_3 will change to “H”, and the signals at output terminals WE1_1, WE1_2, WE2, WE3, and WE4, as well as the output signal of D latch circuit 312, will change to “L”.

[0324] If the signal at output terminal WE1_2 is “H” and the signals at external control terminals CLE and ALE are “L, H”, “H, L”, or “H, H”, and then “H” is input to external control terminal / WE, then the signal at output terminal WE2 will change to “H”, and the signals at output terminals WE1_1, WE1_2, WE1_3, WE3, and WE4, as well as the output signal of D latch circuit 312, will change to “L”.

[0325] If the signal at the output terminal WE1_3 is “H”, and “H” is input to the external control terminal / WE, then the signal at the output terminal WE2 will become “H”, and the signals at the output terminals WE1_1, WE1_2, WE1_3, WE3, and WE4, as well as the output signal of the D latch circuit 312, will become “L”.

[0326] If the signal at output terminal WE2 is “H” and “H” is input to external control terminal / WE, then the signal at output terminal WE3 will become “H”, and the signals at output terminals WE1_1, WE1_2, WE1_3, WE2, and WE4, as well as the output signal of D latch circuit 312, will become “L”.

[0327] If the signal at the output terminal WE3 is "H", and an "H" is input to the external control terminal / WE, then the signal at the output terminal WE4 will become "H", and the signals at the output terminals WE1_1, WE1_2, WE1_3, WE2, and WE3, as well as the output signal of the D latch circuit 312, will become "L".

[0328] If the signal at output terminal WE4 is in the "H" state, and "H" is input to the external control terminal / WE, then the output signal of the D latch circuit 312 will change to the "H" state, and the signals at output terminals WE1_1, WE1_2, WE_3, WE2, WE3, and WE4 will change to the "L" state.

[0329] like Figure 36 As shown, the circuit section 320 includes two D latch circuits 321 to two D latch circuits 326. The data input terminals of one D latch circuit 321 to one D latch circuit 326 are connected to the external control terminal CLE. The data input terminals of the other D latch circuit 321 to one D latch circuit 326 are connected to the external control terminal ALE. Furthermore, the clock input terminals of the two D latch circuits 321 are connected to the AND circuit 314. Figure 35 The output terminal WE1_1 of the AND circuit is connected to the clock input terminals of the D latch circuits 322, 323, 324, 325, and 326. Similarly, the clock input terminals of the AND circuits 314, 322, 323, 324, 325, and 326 are connected to the clock input terminals of the AND circuit 314. Figure 35 The output terminals are WE1_2, WE1_3, WE2, WE3, and WE4.

[0330] Two D latch circuits 321 store the data from the external control terminals CLE and ALE during the first cycle of FSel. Two D latch circuits 322 store the data from the external control terminals CLE and ALE during the second cycle of FSel. Two D latch circuits 324 store the data from the external control terminals CLE and ALE during the first cycle of S_In. Two D latch circuits 325 store the data from the external control terminals CLE and ALE during the second cycle of S_In. Two D latch circuits 326 store the data from the external control terminals CLE and ALE during the third cycle of S_In.

[0331] The output terminals of D latch circuits 321 to 323 are connected to the decoding circuit 327. The decoding circuit, for example, has multiple output terminals corresponding to multiple input / output data selection signals. These input / output data selection signals, for example, include reference... Figure 13 The described input / output data selection signals are for the input address data Add, the input command data Cmd, and the trigger signal used to switch the address data Add. Furthermore, these input / output data selection signals may include, for example, references... Figure 14 The input / output data selection signal for the main body of the input data and the input / output data selection signal for the main body of the output data are described.

[0332] For example, during the first cycle of FSel, if "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, the signal of the output terminal corresponding to the output terminal CLEh will change to the "H" state, and the signals of other output terminals will change to the "L" state. Furthermore, for example, during the first cycle of FSel, if "L" is input to the external control terminal CLE and "H" is input to the external control terminal ALE, the signal of the output terminal corresponding to the output terminal ALEh will change to the "H" state, and the signals of other output terminals will change to the "L" state.

[0333] The output terminals of D latch circuits 324 to 325 are connected to multiplexer 220 ( Figure 33 ), connected to the output terminal DINh<7:2>. Additionally, the external control terminals CLE and ALE are connected via multiplexer 220 ( Figure 33 ), connected to the output terminal DINh<1:0>.

[0334] [A serializer applicable to the memory die MD of the first embodiment]

[0335] In the memory die MD of the first embodiment, when the operation mode MODEb is selected, 8-bit data is converted into 2-bit×4-cycle data for output. For example, this function can also be implemented as Figure 37 shows the circuit implementation. Figure 37 is a schematic circuit diagram showing a partial configuration of the memory die MD.

[0336] Figure 37 The circuit shown includes a serializer 331 and two switching circuits 332.

[0337] The serializer 331 includes 8 first input terminals and 1 second input terminal. One bit of 8-bit data FDATA<7:0> constituting output data is input to each of the first input terminals, respectively. An external control terminal / WE is input to the second input terminal. According to the input from the external control terminal / WE, the serializer 331 converts the 8-bit data FDATA<7:0> into 2-bit data FDATA2<1:0>, and outputs the converted data sequentially in 4 cycles.

[0338] The two switching circuits 332 are provided corresponding to the external control terminals CLE and ALE, respectively. The output terminal of the switching circuit 332 is connected to the external control terminal CLE or the external control terminal ALE. The input terminal of the switching circuit 332 is connected to the output terminal of the serializer 331. The switching circuit 332 outputs an input signal according to the input of gate signal S 332 the input of gate signal S. In gate signal S 332 , for example, when the external control terminal / WE is in "L" state, in the first cycle of period S_Out and the first cycle of period FSel, "L, L" is input to the external control terminals CLE and ALE; in the second cycle of period FSel, "H, L" is input to the external control terminals CLE and ALE, and when operation mode MODEb is selected and the memory die MD is selected, the gate signal S can also be in "H" state.

[0339] [Second Embodiment]

[0340] Next, with reference to Figure 38 and Figure 39 , the configuration of the semiconductor memory device according to the second embodiment will be described. Figure 38 is a schematic block diagram showing the configuration of the memory die MD2 according to the second embodiment. Figure 39 is a schematic circuit diagram showing a partial configuration of the memory die MD2. For convenience of explanation, in Figure 38 and Figure 39 , partial configurations are omitted.

[0341] As shown in Figure 38 and Figure 39As shown, the semiconductor memory device of this embodiment is basically constructed in the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the second embodiment, in addition to the external control terminals CLE and ALE, can also perform signal input and output via the external control terminal / CE. Figure 39 As shown, in the second embodiment, the external control terminal / CE is connected to the input circuit 201 and the output circuit 202. Furthermore, as... Figure 39 As shown, the external control terminal / CE of the second embodiment includes a latching circuit 206.

[0342] In the semiconductor memory device of the first embodiment, two bits of data are input or output in parallel within one cycle via external control terminals CLE and ALE. For example, during the operation mode MODEb, FSel inputs two or four bits of data within one or two cycles. Furthermore, during the S_In period, eight bits of data other than the user data Dat are input within four cycles. Therefore, 10 to 12 bits of data are input within five to six cycles.

[0343] In the semiconductor memory device of the second embodiment, in addition to the external control terminals CLE and ALE, signal input and output can also be performed via the external control terminal / CE. Therefore, three bits of data can be input or output in parallel within one cycle. This reduces the number of cycles required for data input, thereby achieving higher operating speeds.

[0344] Furthermore, in the semiconductor memory device of the first embodiment, when the external control terminal / CE is in the "L" state, the memory die MD is selected, and when the external control terminal / CE is in the "H" state, the memory die MD is deselected. The same applies when the semiconductor memory device of the second embodiment is operated in operating mode MODEa. On the other hand, when the semiconductor memory device of the second embodiment is operated in operating mode MODEb, when the latch circuit 206 is held in the "L" state, the memory die MD is selected, and when the latch circuit 206 is held in the "H" state, the memory die MD is deselected.

[0345] Next, refer to Figure 40 The operation of the semiconductor memory device according to the second embodiment will be explained. Figure 40 This is a schematic waveform diagram used to explain the operation of the semiconductor memory device according to the second embodiment.

[0346] Figure 40 In the example, at time t600, the controller die CD inputs "L" to the external control terminal / CE of the memory die MD2. Accompanying this, the latch circuit 206 ( Figure 39Enter "L" to select the memory die MD2.

[0347] Furthermore, during the period FSel from time t601 to t602, the controller die CD inputs "X, H, L" to the external control terminals / CE, CLE, ALE of the memory die MD2. Simultaneously, the input / output data selection signal for the input command data Cmd is also input.

[0348] Furthermore, during the period S_In from time point t602 to t603, the controller die CD inputs command data Cmd to the memory die MD2 within 3 cycles. Additionally, in the illustrated example, during the first cycle of S_In, "0" is input to the external control terminal / CE.

[0349] Additionally, in the illustrated example, the 1-bit data input to the external control terminal / CE during the first cycle of period S_In is used as flag data. For example, if "0" is input to the external control terminal / CE during the first cycle of period S_In, the cycle immediately following S_In is designated as period FSel. On the other hand, if "1" is input to the external control terminal / CE during the first cycle of period S_In, period FSel is omitted, and the cycle immediately following S_In is designated as period S_In. In the omitted period FSel, the data input to the external control terminals / CE, CLE, and ALE is input again to the external control terminals / CE, CLE, and ALE in the preceding period FSel.

[0350] Furthermore, during the period FSel from time t603 to t604, the controller die CD inputs "X, L, H" to the external control terminals / CE, CLE, ALE of the memory die MD2. Accompanying this is the input / output data selection signal for the input address data Add.

[0351] Furthermore, during the period S_In from time point t604 to t605, the controller die CD inputs address data Add to the memory die MD2 within 3 cycles. Additionally, in the illustrated example, during the first cycle of period S_In, a "1" is input to the external control terminal / CE. The subsequent period FSel is omitted.

[0352] Furthermore, during the periods S_In from time points t605 to t606, t606 to t607, and t607 to t608, the controller die CD inputs address data Add to the memory die MD2 within three cycles. Additionally, in the illustrated example, during the first cycle of the aforementioned period S_In, a "1" is input to the external control terminal / CE. The periods FSel immediately following these periods are omitted.

[0353] Furthermore, during the period S_In from time point t608 to t609, the controller die CD inputs address data Add to the memory die MD2 within 3 cycles. Additionally, in the illustrated example, during the first cycle of period S_In, "0" is input to the external control terminal / CE. The subsequent period FSel is omitted.

[0354] Furthermore, during the period FSel from time t609 to t610, the controller die CD inputs "X, H, L" to the external control terminals / CE, CLE, ALE of the memory die MD2. Accompanying this, the input / output data selection signal for the input command data Cmd is also input.

[0355] In addition, during the period S_In from time point t610 to t611, the controller die CD inputs command data Cmd to the memory die MD2 within 3 cycles.

[0356] [Third Implementation]

[0357] [constitute]

[0358] Next, refer to Figure 41 The configuration of the semiconductor memory device according to the third embodiment will be described. Figure 41 This is a schematic block diagram showing the configuration of the memory die MD3 in the third embodiment.

[0359] like Figure 41 As shown, the semiconductor memory device of this embodiment is configured in essentially the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the third embodiment replaces the command register CMR with a command register CMR'. The command register CMR' is configured in essentially the same way as the command register CMR.

[0360] However, the command register CMR is configured to output a maximum of 2 based on the 8-bit command data Cmd. 8 (=256) control signals.

[0361] On the other hand, the command register CMR' is configured to output more than 257 control signals. For example, the command register CMR' can also be configured to output a maximum of 512 control signals. For example, the command register CMR' includes a command processing unit cmr1 and a command processing unit cmr2.

[0362] The command processing unit CMR1 is configured to output a maximum of 256 control signals based on 8-bit command data Cmd. The command processing unit CMR1 corresponds, for example, to the command data Cmd that can be used in the semiconductor memory device of the first embodiment. Figure 41In this context, such command data Cmd is exemplified as "Basic Command" or below, and is sometimes referred to as "basic command data Cmd".

[0363] The command processing unit CMR2 is configured to output up to 256 control signals based on 8-bit command data Cmd. The command processing unit CMR2 corresponds, for example, to command data Cmd other than "Basic Command". Figure 41 In this context, this type of command data Cmd is exemplified as "Extended Command". Hereinafter, this type of command data Cmd will sometimes be referred to as "Extended Command Data Cmd".

[0364] Furthermore, the command register CMR' may also have the same configuration as the command processing units cmr1 and cmr2. In this case, the command register CMR' is configured to output more than 513 control signals.

[0365] [Function of external terminals under MODEb action mode]

[0366] Figure 42 and 43 This is a truth table used to explain the function of the external terminals in the MODEb action mode. Figure 42 This refers to the function of the external control terminal during the second cycle of the input / output data selection signal FSel. Figure 43 This refers to the function of the external control terminal during the third cycle of the input / output data selection signal FSel.

[0367] The semiconductor memory device of this embodiment operates in essentially the same way as the semiconductor memory device of the first embodiment.

[0368] However, in this embodiment, during the first cycle of FSel, when the input / output data selection signal of the main body of the command data Cmd corresponding to the "Basic Command" is input, the controller die CD, for example, when "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, raises the voltage of the external control terminal / WE from "L" to "H" (see reference). Figure 13 ).

[0369] During the first cycle of FSel, if "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, the FSel cycle ends after one cycle. Furthermore, the data input during the period S_In immediately following the FSel cycle is stored as command data Cmd corresponding to the "Basic Command" in the buffer memory within the input / output control circuit I / O, and then transferred to the command register CMR'. Figure 41 ), by the command processing unit cmr1 ( Figure 41 ) to process.

[0370] Furthermore, in this embodiment, when the input / output data selection signal for the main content of the extended command data Cmd is input during the second cycle of FSel, such as Figure 42 As illustrated, the controller die CD, for example, with "H" input to external control terminal CLE and "L" input to external control terminal ALE, raises the voltage of external control terminal / WE from "L" to "H".

[0371] During the second cycle of FSel, if "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, the FSel period ends after two cycles. Furthermore, the data input during the period S_In immediately following the FSel period is stored as the extended command data Cmd in the buffer memory within the input / output control circuit I / O and transferred to the command register CMR'. Figure 41 ), by the command processing unit cmr2 ( Figure 41 ) to process.

[0372] In addition, as mentioned above, the command register CMR' is configured to output more than 513 control signals.

[0373] In this case, during the third cycle of FSel, when the input command data Cmd is input, the input / output data selection signal is used, such as... Figure 43 As illustrated, the controller die CD can, for example, raise the voltage of the external control terminal / WE from "L" to "H" when "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE.

[0374] Furthermore, if "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE during the third cycle of FSel, the FSel period can also end after three cycles. Additionally, the data input during the period S_In immediately following the FSel period can be stored as command data Cmd in the buffer memory within the input / output control circuit I / O, and then transferred to the command register CMR'. Figure 41), by command processing units CMR1 and CMR2 ( Figure 41 Processing components other than those listed above.

[0375] [Extended Command Data Cmd Use Cases]

[0376] The extended command data Cmd can be used for various purposes. Below, two examples of uses for the extended command data Cmd are given.

[0377] [Shift read using extended command data Cmd]

[0378] First, let's take a shift read as an example, using the extended command data Cmd.

[0379] Figure 44 (a) is a schematic bar chart used to illustrate the threshold voltage of the memory cell MC that records 3 bits of data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC. Figure 44 (b) is a table showing an example of the relationship between the threshold voltage of the storage unit MC that records 3 bits of data and the recorded data.

[0380] Figure 44 In example (a), the threshold voltage of the memory cell MC is controlled to eight states. The threshold voltage of the memory cell MC controlled to the Er state is less than the erase verification voltage V. VFYEr Furthermore, for example, the threshold voltage of the memory cell MC controlled in state A is greater than the verification voltage V. VFYA Less than the verification voltage V VFYB Furthermore, for example, the threshold voltage of the memory cell MC controlled in state B is greater than the verification voltage V. VFYB Less than the verification voltage V VFYC Similarly, the threshold voltages of memory cells MC controlled in states C through F are respectively greater than the verification voltage V. VFYC ~Verification voltage V VFYF Less than the verification voltage V VFYD ~Verification voltage V VFYG Furthermore, for example, the threshold voltage of the memory cell MC controlled in state G is greater than the verification voltage V. VFYG Less than the readout path voltage V READ .

[0381] also, Figure 44 In example (a), a readout voltage V is set between the threshold distribution corresponding to state Er and the threshold distribution corresponding to state A. CGAR Furthermore, a readout voltage V is set between the threshold distribution corresponding to state A and the threshold distribution corresponding to state B. CGBRSimilarly, in the following cases, readout voltages V are set between the threshold distribution corresponding to state B and the threshold distribution corresponding to state C, and between the threshold distribution corresponding to state F and the threshold distribution corresponding to state G. CGCR ~Read the voltage V CGGR .

[0382] For example, the Er state corresponds to the lowest threshold voltage. The memory cell MC in the Er state is, for example, the memory cell MC in the erase state. The memory cell MC in the Er state is, for example, assigned the data "111".

[0383] Furthermore, state A corresponds to a threshold voltage higher than the threshold voltage corresponding to state Er. For example, the storage cell MC for state A is assigned the data "011".

[0384] Furthermore, state B corresponds to a threshold voltage higher than the threshold voltage corresponding to state A. For example, the storage cell MC for state B is allocated the data "001".

[0385] Similarly, states C through G in the diagram correspond to threshold voltages higher than those corresponding to states B through F. The memory cells MC for these states are, for example, assigned "101", "100", "000", "010", and "110".

[0386] In addition, such as Figure 44 (b) In the illustrated allocation case, the next-order data can be read from a single readout voltage V. CGDR The intermediate-order data can be determined by two readout voltages V. CGBR V CGFR The upper-order data can be determined by four readout voltages V. CGAR V CGCR V CGER V CGGR Discrimination. This type of data allocation is sometimes referred to as 1-2-4 encoding.

[0387] In addition, the number of bits, the number of states, and the data allocation for each state recorded in the storage unit MC can be changed appropriately.

[0388] Figure 45 It is a timing diagram used to explain the reading action.

[0389] Additionally, in the following explanation, the word line WL that will sometimes become the object of the action is referred to as the selection word line WL. S The additional word lines WL are referred to as non-selective word lines WL. U Furthermore, in the following description, the string unit SU (which becomes the object of the action) is referred to. Figure 5 The multiple memory cells (MCs) contained in the selection word line (WL) are connected to the select word line. SAn example of a read operation performed by a memory cell MC (hereinafter sometimes referred to as "select memory cell MC") is given.

[0390] In addition, the following explanations, if referenced Figure 44 (a) illustrates storing 3 bits of data in multiple memory cells MC, and performing operations on the multiple memory cells MC as described in the reference. Figure 44 (b) Examples of data allocation are explained. Furthermore, the following explanation illustrates examples of determining the intermediate data for the selection of the memory cell MC.

[0391] exist Figure 45 At time t701, the readout operation begins, and the voltage at terminal RY / / BY drops from "H" to "L".

[0392] At time t702, select word line WL S and non-selective word line WL U Supply Reference Figure 44 (a) The readout path voltage V described READ In addition, a voltage V is supplied to the select gate lines (SGD, SGS, SGSb). SG Voltage V SG It has a magnitude that enables the select gate lines (SGD, SGS, SGSb) to be in the ON state.

[0393] At time t703, select word line WL S Supply readout voltage V CGBR Furthermore, during the period from time t703 to time t704, the current of the bit line BL is detected by the sensing amplifier SA, thereby obtaining data indicating the on / off state of the memory cell MC.

[0394] At time t704, select word line WL S Supply readout voltage V CGFR Furthermore, during the period from time t704 to time t705, the current of the bit line BL is detected by the sensing amplifier SA, thereby obtaining data indicating the on / off state of the memory cell MC.

[0395] At time t705, select word line WL S and non-selective word line WL U Supply readout path voltage V READ .

[0396] At time t706, select word line WL S Non-selective word line WL U and select the gate line (SGD, SGS, SGSb) to supply ground voltage V SS .

[0397] Figure 46 It is a timing diagram used to illustrate shift reads. Figure 46 (a) indicates the select line WL in the readout action. S The voltage. Figure 46 (b) Indicates the select word line WL during a shift read in one aspect. S The voltage. Figure 46 (c) indicates the select word line WL in another shift read operation. S The voltage.

[0398] Shift reads are performed essentially the same as reads. However, during a shift read, the select word line WL is fed in... S The voltage supplied to the select word line WL during the read operation S The voltages are different.

[0399] Here, when a write operation is performed on multiple memory cells MC, the threshold voltage of the multiple memory cells MC is, for example, as follows: Figure 44 (a) is the distribution shown in the example. However, there are cases where the threshold voltages of multiple memory cells MC vary after a write operation and before an erase operation. In such cases, for example, some memory cells MC controlled in state A may have threshold voltages greater than the read voltage V. CGBR This data was then classified as "0". Furthermore, a portion of the threshold voltage of the memory cell MC, which is controlled in state B, is lower than the read voltage V. CGBR This bit is then interpreted as a data "1". The bit read from this memory cell MC becomes an error bit. In this case, there is a way to correct this by adjusting the select word line WL. S Supply is greater than readout voltage V CGAR ~V CGGR The voltage, or less than the read voltage V CGAR ~V CGGR The voltage is adjusted to minimize or near-minimum the number of memory cells (MC) that will become error bits. Therefore, during shift reads, the select word line WL... S Supply is greater than readout voltage V CGAR ~V CGGR The voltage, or less than the read voltage V CGAR ~V CGGR The voltage.

[0400] For example, Figure 46 In example (b), at time t703, the selected word line WL S Supply readout voltage V CGBR 'Instead of reading voltage V' CGBR Read the voltage V CGBR Less than the readout voltage V CGBR .

[0401] In addition, for example Figure 46 In example (b), at time t704, the selected word line WL S Supply readout voltage VCGFR' instead of readout voltage V CGFR Read the voltage V CGFR Less than the readout voltage V CGFR .

[0402] Additionally, when performing a read operation, for example, as shown in the reference... Figure 20 As explained above, the controller bare CD ( Figure 1 The controller die CD supplies the memory die MD with the command data "00h" as the command data Cmd. Then, the controller die CD supplies the memory die MD with the address data Add and the command data "30h".

[0403] On the other hand, execution Figure 46 (b) In the case of the illustrated shift read, the controller on the bare CD ( Figure 1 Alternatively, command data such as "11h", "12h", "13h", etc., can be supplied to the memory die MD as extended command data Cmd, instead of supplying command data "00h" as command data Cmd (basic command data Cmd). Furthermore, the read voltage V when inputting command data "12h"... CGBR With readout voltage V CGBR The difference between ' and the read voltage V CGFR With readout voltage V CGFR The difference (hereinafter referred to as "voltage shift amount") can also be greater than the voltage shift amount when inputting command data "11h". Similarly, the voltage shift amount when inputting command data "13h" can also be greater than the voltage shift amount when inputting command data "12h". Furthermore, after inputting command data "11h", "12h", "13h", etc., the controller die CD can supply address data Add and command data "30h" to the memory die MD. Command data "30h" can be basic command data Cmd or extended command data Cmd.

[0404] In addition, for example Figure 46 In example (c), at time t703, the selected word line WL S Supply readout voltage V CGBR "Instead of reading voltage V" CGBR Read the voltage V CGBR "Greater than the readout voltage V" CGBR .

[0405] In addition, for example Figure 46 In example (c), at time t704, the selected word line WL S Supply readout voltage V CGFR "Instead of reading voltage V" CGFRRead the voltage V CGFR "Greater than the readout voltage V" CGFR .

[0406] In addition, execution Figure 46 (c) In the case of the illustrated shift read, the controller bare CD ( Figure 1 Alternatively, command data "21h", "22h", "23h", etc., can be supplied to the memory die MD as extended command data Cmd, instead of supplying command data "00h" as command data Cmd (basic command data Cmd). Similarly, the voltage shift amount when inputting command data "22h" can be greater than the voltage shift amount when inputting command data "21h". Likewise, the voltage shift amount when inputting command data "23h" can be greater than the voltage shift amount when inputting command data "22h". Furthermore, after inputting command data "21h", "22h", "23h", etc., the controller die CD can supply address data Add and command data "30h" to the memory die MD. Command data "30h" can be either basic command data Cmd or extended command data Cmd.

[0407] Figure 47 This is a schematic waveform diagram representing the state of the shift read operation in the MODEb action mode. Figure 47 In the example, the memory die MD is set to the operation mode MODEb.

[0408] Figure 47 In this example, firstly, a command group containing the command data "11h" is input via the external control terminals CLE and ALE. Additionally, the command data "11h" is input as extended command data Cmd.

[0409] Here, for example in the first embodiment, when performing a shift read, for example as referenced Figure 30 The described method performs feature setting, thereby inputting the voltage shift amount as feature data Fd into the memory die MD. Then, as referenced... Figure 20 The method described is used to perform the read operation.

[0410] On the other hand, in the third embodiment, when performing a shift read, feature setting is not performed, and the process is as described in the reference... Figure 47 The method described performs a shift read.

[0411] According to this method, the speed of the action can be increased by omitting the execution feature settings.

[0412] [Using the internal path delay detection circuit 205 of extended command data Cmd ( Figure 9 [Control]

[0413] Next, as an example of the use of extended command data Cmd, the internal path delay detection circuit 205 is shown. Figure 9 ) control.

[0414] For reference Figure 9 As explained, in the semiconductor memory device of the first embodiment, the number of pulses output from the internal path delay detection circuit 205 can be obtained as feature data Fd. Furthermore, based on the feature data Fd, the signal transmission circuit 204 ( Figure 8 The signal delay in ).

[0415] Here, in the semiconductor memory device of the first embodiment, the internal path delay detection circuit 205 is driven according to the execution of feature acquisition. That is, according to the execution of feature acquisition, the NAND circuit 212 in the internal path delay detection circuit 205 ( Figure 9 The start signal of the device becomes "H". Therefore, in the semiconductor memory device of the first embodiment, after feature acquisition is performed, feature data Fd cannot be obtained until the delay amount of the internal path delay detection circuit 205 is measured.

[0416] On the other hand, in the semiconductor memory device of the third embodiment, the internal path delay detection circuit 205 can be driven according to the input of the extended command data Cmd. That is, the NAND circuit 212 in the internal path delay detection circuit 205 can be driven according to the input of the extended command data Cmd. Figure 9 The start signal is set to "H".

[0417] Based on this configuration, there is a case where feature acquisition can be performed at high speed by pre-driving the internal path delay detection circuit 205 before feature acquisition is performed.

[0418] [Fourth Implementation]

[0419] Next, refer to Figure 48 The configuration of the semiconductor memory device according to the fourth embodiment will be described. Figure 48 This is a schematic block diagram showing the configuration of the memory die MD4 in the fourth embodiment.

[0420] like Figure 48 As shown, the semiconductor memory device of this embodiment is configured in essentially the same way as the semiconductor memory device of the second embodiment. However, the semiconductor memory device of the fourth embodiment has a command register CMR' instead of the command register CMR.

[0421] Next, refer to Figure 49 and Figure 50The operation of the semiconductor memory device according to the fourth embodiment will be described. The semiconductor memory device of the fourth embodiment operates in basically the same way as the semiconductor memory device of the second embodiment.

[0422] However, in the semiconductor memory device of the second embodiment, one bit of data input to the external control terminal / CE during the first cycle of S_In is used as flag data. Furthermore, in the semiconductor memory device of the second embodiment, the period S_In is omitted based on the flag data.

[0423] On the other hand, in the semiconductor memory device of the fourth embodiment, it is determined whether the input command data Cmd is extended command data Cmd based on the flag data.

[0424] For example, if the flag data is "0", the command data Cmd input during the S_In period will be identified as non-extended command data Cmd. In this case, the command data Cmd is processed by the command processing unit cmr1 in the command register CMR'. Figure 48 )deal with.

[0425] On the other hand, when the flag data is "1", the command data Cmd input during the S_In period is identified as extended command data Cmd. In this case, the command data Cmd is processed by the command processing unit cmr2 in the command register CMR'. Figure 48 )deal with.

[0426] Figure 49 This is a schematic waveform diagram representing the state when a read action is performed under the action mode MODEb. Figure 49 In the example, the memory die MD is set to the operation mode MODEb.

[0427] Figure 49 In the example, at time t800, the controller die CD inputs "L" to the external control terminal / CE of the memory die MD4. Accompanying this, the latch circuit 206 ( Figure 39 Enter "L" to select the MD4 memory die.

[0428] Furthermore, during the period FSel from time t801 to t802, the controller die CD inputs "X, H, L" to the external control terminals / CE, CLE, ALE of the memory die MD4. Simultaneously, the input / output data selection signal for the input command data Cmd is also input.

[0429] Furthermore, during the S_In period from time t802 to t803, the controller die CD inputs command data "00h" to the memory die MD4 within 3 cycles. Additionally, in the illustrated example, during the first cycle of S_In, "0" is input to the external control terminal / CE. Therefore, the command data "00h" is identified as non-extended command data Cmd.

[0430] Furthermore, during the period FSel from time t803 to t804, the controller die CD inputs "X, L, H" to the external control terminals / CE, CLE, ALE of the memory die MD4. Accompanying this is the input / output data selection signal for the input address data Add.

[0431] Furthermore, during the period S_In from time point t804 to t805, the controller die CD inputs address data Add to the memory die MD4 within 3 cycles. Additionally, in the illustrated example, during the first cycle of S_In, either "0" or "1" can be input to the external control terminal / CE.

[0432] In addition, during the period t805~t806, F_Sel during the period t807~t808, F_Sel during the period t809~t810, and FSel during the period t803~t804, the controller die CD inputs “X, L, H” to the external control terminals / CE, CLE, ALE of the memory die MD4.

[0433] Furthermore, during the periods S_In from time point t806 to t807, after time point t808, before time point t809, and from time point t810 to t811, the controller die CD inputs address data Add to the memory die MD4 within three cycles, similar to the period S_In from time point t804 to t805.

[0434] Furthermore, during the period FSel from time t811 to t812, the controller die CD inputs "X, H, L" to the external control terminals / CE, CLE, ALE of the memory die MD4. Simultaneously, the input / output data selection signal for the input command data Cmd is also input.

[0435] Furthermore, during the period S_In from time point t812 to t813, the controller die CD inputs command data "30h" to the memory die MD4 within 3 cycles. Additionally, in the illustrated example, during the first cycle of S_In, "0" is input to the external control terminal / CE.

[0436] Figure 50This is a schematic waveform diagram illustrating the state of shift reading when performing operation mode MODEb. Figure 50 In the example, the memory die MD is set to the operation mode MODEb.

[0437] Figure 50 The actions shown are basically the same as Figure 49 The actions shown are performed in the same way.

[0438] but, Figure 50 In the example shown, during the period S_In from time point t802 to t803, the controller die CD inputs the command data "11h" to the memory die MD4 within 3 cycles. Furthermore, in the illustrated example, during the first cycle of S_In, "1" is input to the external control terminal / CE. Therefore, the command data "11h" is determined to be the extended command data Cmd.

[0439] [Other Implementation Methods]

[0440] The semiconductor memory devices of the first to fourth embodiments have been described above. However, the above description is merely illustrative and the specific configuration and operation can be adjusted as appropriate.

[0441] For example, in the semiconductor memory devices of the first and third embodiments, 2-bit data input / output using external control terminals CLE and ALE is performed in operation mode MODEb. Furthermore, in the semiconductor memory devices of the second and fourth embodiments, 3-bit data input / output using external control terminals / CE, CLE, and ALE is performed in operation mode MODEb. However, this method is merely an example, and the specific method can be appropriately adjusted. For example, in operation mode MODEb, other terminals may be used to perform 3-bit or 4-bit or more data input / output. More specifically, for example, in operation mode MODEb, external control terminals / WP may be used instead of or in addition to external control terminals / CE to perform 3-bit or 4-bit data input / output. Furthermore, at least one terminal may be selected from those including external control terminals / CE, CLE, and ALE to perform 1-bit or 2-bit data input / output.

[0442] Furthermore, in embodiments 1 to 4, the functional allocation of external control terminals / CE, CLE, ALE, etc., has been illustrated. However, this allocation is ultimately illustrative, and the actual allocation can be adjusted appropriately.

[0443] For example, in the semiconductor memory device of the first embodiment, it is also possible to replace Figure 13 and Figure 14 This is part of the illustrated functionality. Additionally, for example, additional features may be added. Figure 13 and Figure 14Functions other than those shown in the examples can also be omitted. Figure 13 and Figure 14 This is part of the illustrated function. Additionally, a third cycle of the FSel period can be added. Furthermore, the function of allocating data input in the second cycle of the FSel period based on the data input in the first cycle of the FSel period can be changed.

[0444] The command group includes command data Cmd and address data Add. In operation mode MODEb, the semiconductor memory device of the first embodiment uses an input / output data selection signal (header) and command data Cmd or address data Add (body) to send and receive command data Cmd and address data Add within several cycles. Here, there is a case where the input of the command group is stopped midway. In this case, there is a case where no command data Cmd and address data Add are input until the final cycle. In this case, each memory die MD can also be configured to be reset according to a reset instruction signal from the controller die CD.

[0445] For example, controller bare CD such as Figure 51 As shown, in the case of an interrupted input command group, a reset indication signal is sent, causing the voltage at the external control terminal / CE to change from "L" to "H" for a certain period, and then return to "L". Afterwards, the controller die CD inputs a new command group to the memory die MD. The new command group may be the same as or different from the interrupted command group. Upon receiving the new input command group, the memory die MD executes the action corresponding to the command group.

[0446] A semiconductor memory device that can operate stably even when the input command group needs to be interrupted, by configuring the controller die CD to send a reset indication signal and configuring the memory die MD to be reset according to the reset signal.

[0447] Furthermore, in the semiconductor memory devices of embodiments 2 and 4, for example, the 1-bit data input to the external control terminal / CE during the first cycle of S_In is used as flag data. In the semiconductor memory device of embodiment 2, the S_In period is omitted based on the flag data. Furthermore, in the semiconductor memory device of embodiment 2, it is determined whether the input command data Cmd is extended command data Cmd based on the flag data. However, this method is merely an example, and the specific method can be appropriately adjusted. For example, the data input to the external control terminal / CE during the first cycle of S_In may also be used as a parity bit. In this case, the parity bit may be a parity bit corresponding to the 3-bit data input during FSel, or it may be a parity bit corresponding to the 8-bit data input during S_In.

[0448] Furthermore, in the semiconductor memory devices of embodiments 2 and 4, for example, one bit of data input to the external control terminal / CE during the first cycle of S_In is used as flag data. However, data input to a terminal other than the external control terminal / CE, or data input after the second cycle of S_In, may also be used as the flag data, parity bit, or other data.

[0449] Furthermore, in the semiconductor memory device of the third embodiment, for example, examples are shown where the extended command data Cmd used to perform shift reads is “11h”, “12h”, “13h”, ... and “21h”, “22h”, “23h”, ... However, the extended command data Cmd assigned to the shift read is not limited to the data described above. Any command data can be assigned within the range that can be assigned as extended command data Cmd.

[0450] Furthermore, in the semiconductor memory devices of embodiments 3 and 4, examples are shown where the extended command data Cmd is the same as the general command data Cmd, and is 8 bits. However, the extended command data Cmd may be shorter than 8 bits or longer than 8 bits.

[0451] For example, when the extended command data Cmd is less than 8 bits, the command processing unit cmr2 can be reduced in size. Figure 41 The area of ​​the memory chip is [not specified]. Furthermore, for example, in the third embodiment, when the extended command data Cmd is 8 bits, the extended command data Cmd is input to the memory die MD3 within 4 cycles. On the other hand, in the third embodiment, when the extended command data Cmd is 5 or 6 bits, the extended command data Cmd is input to the memory die MD3 within 3 cycles. In other words, when the extended command data Cmd is shorter than 8 bits, higher speeds of operation can be achieved.

[0452] Furthermore, for example, when the extended command data Cmd is longer than 8 bits, it can handle more command data Cmd.

[0453] [other]

[0454] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the technical solution and its equivalents.

[0455] [Symbol Explanation]

[0456] MC storage unit

[0457] MCA storage cell array

[0458] PC peripheral circuits

[0459] ADR Address Register

[0460] CMR command register.

Claims

1. A semiconductor memory device, comprising: The first solder pad can transmit and receive signals at the first time point; The second solder pad can transmit and receive data according to the signal at the first time point; The third pad can receive the signal at the second time point; The fourth solder pad can receive control information according to the second time point signal; A memory cell array, comprising a string of words in which multiple memory cell transistors are connected in series; A sensing amplifier is connected to the memory cell array; The first register, connected to the sensing amplifier, is capable of storing data read from the memory cell array; The second register can store the first control information; The third register can store the second control information; and The control circuit is capable of performing a data output operation, outputting the data stored in the first register from the second solder pad; and Based on the input to the fourth pad corresponding to the second time point signal corresponding to i cycles, the first control information is stored in the second register, wherein, i is an integer greater than or equal to 2. Based on the input to the fourth pad corresponding to the second time point signal with j cycles, the second control information is stored in the third register, where j is an integer different from i.

2. The semiconductor memory device according to claim 1, wherein The fourth bonding pad includes: Command latch start signal receiving pad; and Address latch start signal receiving pad; and j is an integer greater than i.

3. The semiconductor memory device according to claim 2, wherein... The first control information includes command signals or address signals. The second control information includes characteristic data information. The second register includes either a command register or an address register. The third register includes a feature register.

4. The semiconductor memory device according to claim 3, further comprising: The first receiver and the first driver are connected to the second pad; and The second receiver and the second driver are connected to the fourth pad; and In the data output operation, the first driver outputs the data stored in the first register to the second pad. During the characteristic information output action, the second driver outputs the characteristic data information stored in the characteristic register to the fourth pad.

5. The semiconductor memory device according to claim 4, further comprising: The fourth register stores the status information. During the status information output action, the second driver outputs the status information stored in the fourth register to the fourth pad.

6. The semiconductor memory device according to claim 5, further comprising: The 5th solder pad receives the signal at time point 3; and The receiving unit receives the trigger signal and outputs a start signal; and Based on the input to the fourth pad corresponding to the second time point signal with k cycle quantities, the trigger signal is transmitted to the receiving unit. After accepting the command group that indicates the data stored in the first register, and After the receiving unit outputs the output start signal Based on the third timing signal input to the fifth pad, the first driver outputs the data to the second pad. After accepting the instruction to output the command group containing the data stored in the first register, and Before the receiving unit outputs the output start signal. Even if the third time point signal is input to the fifth pad, the first driver does not output the data to the second pad.

7. A semiconductor memory device, comprising: The first solder pad can transmit and receive signals at the first time point; The second solder pad can transmit and receive data according to the signal at the first time point; The third pad can receive the signal at the second time point; The fourth solder pad can receive control information according to the second time point signal; A memory cell array, comprising a string of words in which multiple memory cell transistors are connected in series; A sensing amplifier is connected to the memory cell array; The first register, connected to the sensing amplifier, is capable of storing data read from the memory cell array; The second register can store the first control information; The third register can store the second control information; and The control circuit is capable of performing a data output operation, outputting the data stored in the first register from the second solder pad; and Based on the input to the fourth pad corresponding to the second time point signal corresponding to i cycles, the received control information is stored in one of the second register or the third register, wherein... i is an integer greater than or equal to 2. Based on the input to the fourth pad corresponding to the second time point signal corresponding to the j-cycle quantity following the i-cycle, the received control information is stored in either the second register or the third register, where j is an integer less than i.

8. The semiconductor memory device according to any one of claims 1 to 7, wherein The first control information includes command signals and also has: The first command processing unit that processes the first command signal; and The second command processing unit processes the second command signal.

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