Tcam and bit cell thereof, write operation method

Abstract

The application provides a TCAM, a bit unit of the TCAM, and a write operation method, wherein the TCAM bit unit comprises: an information storage unit configured to store information, comprising a first storage unit and a second storage unit; and a multi-bit write unit connected with the first storage unit and the second storage unit, and configured to simultaneously perform write operation on the first storage unit and the second storage unit. The TCAM, the bit unit of the TCAM, and the write operation method can greatly shorten the write time.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuits, and in particular to a TCAM and its bit cells and write operation method. Background Technology

[0002] Ternary Content Addressable Memory (TCAM) is an associative memory implemented based on traditional storage technology. It has three storage states: "0", "1" and "don't care", which enables it to perform both exact matching and fuzzy matching searches.

[0003] TCAM has three basic operations: write, read, and search. The write and read operations are performed in the same way as random access memory (RAM). The search operation is the main purpose of TCAM, which can quickly search from a huge database and return the best matching address. The fastest search speed can reach more than 100 million times per second.

[0004] A TCAM bit cell typically contains two basic storage units, so it takes two write cycles to complete the input of information into one storage unit, which is time-consuming. Summary of the Invention

[0005] The technical problem to be solved by this application is to provide a TCAM and its bit unit, and a write operation method that can significantly shorten the write time.

[0006] To address the aforementioned technical problems, this application provides a TCAM bit unit, comprising: an information storage unit for storing information, including a first storage unit and a second storage unit; and a multi-bit write unit connected to the first storage unit and the second storage unit, wherein the multi-bit write unit is configured to simultaneously perform write operations on the first storage unit and the second storage unit.

[0007] In this embodiment of the application, the first storage unit is connected to the first word line, the second storage unit is connected to the second word line, and the multi-bit write unit is connected to the third word line.

[0008] In this embodiment of the application, when writing different data to the first storage unit and the second storage unit at the same time, the first word line or the second word line is opened, and the third word line is opened; when writing the same data to the first storage unit and the second storage unit at the same time, the first word line and the second word line are opened, and the third word line is closed.

[0009] In this embodiment of the application, the multi-bit write unit includes: a fifth MOS transistor, the source of which is connected to the first memory cell and the drain of which is connected to the second memory cell; and a sixth MOS transistor, which is connected to the fifth MOS transistor through its gate, the source of which is connected to the second memory cell and the drain of which is connected to the first memory cell.

[0010] In this embodiment, the gate terminals of the fifth MOS transistor and the sixth MOS transistor are connected to the third word line.

[0011] In this embodiment of the application, the first memory unit and the second memory unit are respectively connected to the first bit line and the second bit line, wherein the first memory unit includes a first MOS transistor, a first inverting unit and a second MOS transistor connected in sequence, and the second memory unit includes a third MOS transistor, a second inverting unit and a fourth MOS transistor connected in sequence.

[0012] In this embodiment of the application, the drain of the first MOS transistor is connected to the first bit line, the source of the first MOS transistor is connected to the first inverting unit, and the gate of the first MOS transistor is connected to the first word line; the drain of the second MOS transistor is connected to the first inverting unit, the source of the second MOS transistor is connected to the second bit line, and the gate of the second MOS transistor is connected to the first word line.

[0013] In this embodiment of the application, the drain of the third MOS transistor is connected to the first bit line, the source of the third MOS transistor is connected to the second inverting unit, and the gate of the third MOS transistor is connected to the second word line; the drain of the fourth MOS transistor is connected to the second inverting unit, the source of the fourth MOS transistor is connected to the second bit line, and the gate of the fourth MOS transistor is connected to the second word line.

[0014] In this embodiment, the source terminal of the fifth MOS transistor is connected to the output terminal of the first inverting unit, and the drain terminal of the fifth MOS transistor is connected to the input terminal of the second inverting unit; the source terminal of the sixth MOS transistor is connected to the output terminal of the second inverting unit, and the drain terminal of the sixth MOS transistor is connected to the input terminal of the first inverting unit.

[0015] In this embodiment of the application, the first inverter unit includes a first inverter and a second inverter connected end to end; the second inverter unit includes a third inverter and a fourth inverter connected end to end.

[0016] In this embodiment of the application, the first storage unit is a data storage unit, and the second storage unit is a mask storage unit.

[0017] In this embodiment of the application, the TCAM bit unit further includes: a matching comparison unit connected to the information storage unit, used to compare input information with stored information and output the comparison result.

[0018] In this embodiment, the matching comparison unit includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, and a tenth MOS transistor connected in sequence, wherein: the gate terminal of the seventh MOS transistor is connected to the first inverting unit, and the source terminal of the seventh MOS transistor is connected to the comparison result output line; the source terminal of the eighth MOS transistor is connected to the drain terminal of the seventh MOS transistor, and the gate terminal of the eighth MOS transistor is used to receive the input information; the drain terminal of the ninth MOS transistor is connected to the drain terminal of the eighth MOS transistor, and the gate terminal of the ninth MOS transistor is used to receive the input information; the drain terminal of the tenth MOS transistor is connected to the source terminal of the ninth MOS transistor, the source terminal of the tenth MOS transistor is connected to the comparison result output line, and the gate terminal of the tenth MOS transistor is connected to the second inverting unit.

[0019] This application also provides a write operation method using the above-mentioned TCAM bit unit. The write operation method includes: simultaneously writing data into a first storage unit and a second storage unit using a multi-bit write unit.

[0020] In this embodiment, when the write state is 0, 0 is written in the first storage unit and 1 is written in the second storage unit; when the write state is 1, 1 is written in the first storage unit and 0 is written in the second storage unit; when the write state is X, 0 is written in the first storage unit and 0 is written in the second storage unit; when the write state is invalid, 1 is written in the first storage unit and 1 is written in the second storage unit.

[0021] This application also provides a TCAM, including: the TCAM bit unit described above.

[0022] The technical solution of this application designs a multi-bit write unit in the logic circuit structure of the TCAM bitcell. The multi-bit write unit is connected to each memory unit and can perform write operations on each memory unit simultaneously through the logic control of the peripheral circuit, thereby realizing one-time writing of the TCAM bitcell and greatly improving the write speed. Attached Figure Description

[0023] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0024] Figure 1 This is a schematic diagram of the logic circuit for a TCAM bitcell;

[0025] Figure 2 This is a schematic diagram of the logic circuit of the TCAM bitcell in an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of the current direction of the TCAM bitcell in write state 0 according to an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of the current direction of the TCAM bitcell in write state 1 according to an embodiment of this application;

[0028] Figure 5 This is a schematic diagram of the current direction of the TCAM bitcell in write state X according to an embodiment of this application;

[0029] Figure 6 This is a schematic diagram of the matching comparison unit in the TCAM bitcell of this application embodiment. Detailed Implementation

[0030] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0031] refer to Figure 1A TCAM bitcell includes a first storage unit 10, a second storage unit 11, and a match comparison unit 13. During a write operation, data D is written to the first storage unit 10, and data M is written to the second storage unit 11.<D,M> To form a set of data, when<D,M> When <0, 1>, it represents a storage state of "0"; when<D,M> When <1, 0>, it represents a storage state of "1"; when<D,M> When <0, 0>, it represents a storage state of "X"; when<D,M> When the value is <1, 1>, it means that the storage state is meaningless.

[0032] Write data<D,M> At this time, a write operation needs to be performed on the first storage unit 10 and the second storage unit 11 respectively, so two write cycles are needed to complete the information input of one TCAMbitcell.

[0033] To shorten the write time, the technical solution of this application improves the circuit structure of the TCAM bitcell by adding a multi-bit write unit. The multi-bit write unit is configured to perform write operations on each storage unit in the information storage unit simultaneously, thus significantly improving the write speed.

[0034] The TCAM bitcell of this application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] refer to Figure 2 The TCAM bitcell 100 of this application embodiment includes: an information storage unit, a multi-bit write unit 120, and a matching comparison unit 130. The information storage unit is used to store information and includes a first storage unit 111 and a second storage unit 112. The first storage unit 111 can be a data storage unit, such as a static random access memory (SRAM) cell, and data D is written to the first storage unit 111 during a write operation. The second storage unit 112 can be a mask storage unit, such as an SRAM cell, and data M is written to the second storage unit 112 during a write operation. The data stored in the first storage unit 111 and the second storage unit 112 constitute a two-bit state.<D,M> <0, 1> represents state 0, <1, 0> represents state 1, <0, 0> represents state X, and <1, 1> represents an invalid state.

[0036] The first memory cell 111 is connected to a first word line WL1, a first bit line BL1, and a second bit line BL2. Specifically, the first memory cell 111 includes a first MOS transistor M1, a first inverting unit, and a second MOS transistor M2 connected in sequence. The drain of the first MOS transistor M1 is connected to the first bit line BL1, the source of the first MOS transistor M1 is connected to the first inverting unit, and the gate of the first MOS transistor M1 is connected to the first word line WL1. The drain of the second MOS transistor M2 is connected to the first inverting unit, the source of the second MOS transistor M2 is connected to the second bit line BL2, and the gate of the second MOS transistor M2 is connected to the first word line WL1.

[0037] The first inverting unit includes a first inverter X1 and a second inverter X2 connected end to end. The first inverter X1 and the second inverter X2 can be inverters of any structure, as long as they can achieve the inversion effect.

[0038] The second memory cell 112 is connected to the first word line WL1, the first bit line BL1, and the second bit line BL2. Specifically, the second memory cell 112 includes a third MOS transistor M3, a second inverting unit, and a fourth MOS transistor M4 connected in sequence. The drain of the third MOS transistor M3 is connected to the first bit line BL1, the source of the third MOS transistor M3 is connected to the second inverting unit, and the gate of the third MOS transistor M3 is connected to the second word line WL2. The drain of the fourth MOS transistor M4 is connected to the second inverting unit, the source of the fourth MOS transistor M4 is connected to the second bit line BL2, and the gate of the fourth MOS transistor M4 is connected to the second word line WL2.

[0039] The second inverting unit includes a third inverter X3 and a fourth inverter X4 connected end to end. The structure of the third inverter X3 and the fourth inverter X4 is not particularly limited, as long as it achieves the inverting effect.

[0040] The multi-bit write unit 120 includes a fifth MOS transistor M5 and a sixth MOS transistor M6. The source terminal of the fifth MOS transistor M5 is connected to the first memory cell 111, and the drain terminal of the fifth MOS transistor M5 is connected to the second memory cell 112. In this embodiment, the source terminal of the fifth MOS transistor M5 is connected to the first inverter unit of the first memory cell 111. Specifically, the source terminal of the fifth MOS transistor M5 can be connected to the output terminal of the first inverter X1 and the input terminal of the second inverter X2. The drain terminal of the fifth MOS transistor M5 is connected to the second inverter unit of the second memory cell 112. For example, the drain terminal of the fifth MOS transistor M5 is connected to the input terminal of the third inverter X3 and the output terminal of the fourth inverter X4. The source terminal of the sixth MOS transistor M6 is connected to the second inverter unit of the second memory cell 112. For example, the source terminal of the sixth MOS transistor M6 is connected to the output terminal of the third inverter X3 and the input terminal of the fourth inverter X4. The drain of the sixth MOS transistor M6 is connected to the first inverter unit of the first memory cell 111. For example, the drain of the sixth MOS transistor M6 is connected to the input terminal of the first inverter X1 and the output terminal of the second inverter X2. The gate terminals of the fifth and sixth MOS transistors are interconnected and connected to the third word line WL3.

[0041] By controlling the on / off states of the first word line WL1, the second word line WL2, and the third word line WL3, and inputting correct data from the first or second bit line, write operations can be performed on all memory cells within one write cycle, thereby enabling writes in different states. Specifically, when writing different data to the first memory cell 111 and the second memory cell 112 simultaneously, the first word line WL1 or the second word line WL2 is turned on, and the third word line WL3 is turned on; when writing the same data to the first memory cell 111 and the second memory cell 112 simultaneously, the first word line WL1 and the second word line WL2 are turned on, and the third word line WL3 is turned off.

[0042] In this embodiment of the application, writing operations to both the first storage unit 111 and the second storage unit 112 can be performed simultaneously within one write cycle, which can be achieved by the following method: when writing state 0, that is...<D,M> For <0, 1>, simultaneously turn on the first word line WL1 and the third word line WL3, turn off the second word line WL2, set the first bit line BL1 low, and set the second bit line BL2 high (current direction as follows). Figure 3 When the arrow direction in the text is written to state 1, that is...<D,M> When the value is <1, 0>, the first word line WL1 and the third word line WL3 are simultaneously turned on, the second word line WL2 is turned off, the first bit line BL1 is set high, and the second bit line BL2 is set low (current direction is as follows). Figure 4(The direction of the arrow in the text); when writing state X, that is...<D,M> When the value is <0,0>, the first word line WL1 and the second word line WL2 are simultaneously turned on, the third word line WL3 is turned off, the first bit line BL1 is set low, and the second bit line BL2 is set high (current direction as follows). Figure 5 (The arrow direction in the text); When the write is invalid, the first word line WL1 and the second word line WL2 are turned on simultaneously, the third word line WL3 is turned off, the first bit line BL1 is set high, and the second bit line BL2 is set low.

[0043] In other embodiments, write operations on the first memory cell 111 and the second memory cell 112 can also be performed simultaneously within a single write cycle using the following method: In write state 0, the second word line WL2 and the third word line WL3 are simultaneously enabled, the first word line WL1 is disabled, the first bit line BL1 is high, and the second bit line BL2 is low; in write state 1, the second word line WL2 and the third word line WL3 are simultaneously enabled, the first word line WL1 is disabled, the first bit line BL1 is low, and the second bit line BL2 is high; in write state X, the first word line WL1 and the second word line WL2 are simultaneously enabled, the third word line WL3 is disabled, the first bit line BL1 is low, and the second bit line BL2 is high; in write invalid state, the first word line WL1 and the second word line WL2 are simultaneously enabled, the third word line WL3 is disabled, the first bit line BL1 is high, and the second bit line BL2 is low.

[0044] Therefore, it can be seen that by adding multiple write units to the TCAM bitcell and cooperating with the logic control of the peripheral circuit, the TCAM bitcell can be written in one go, reducing the write time by half.

[0045] refer to Figure 6The matching comparison unit 130 is used to compare input information with stored information and output a comparison result. It may include a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, and a tenth MOS transistor M10 connected in sequence. Specifically, the gate of the seventh MOS transistor M7 is connected to the first inverter unit; more specifically, the gate of the seventh MOS transistor M7 is connected to the output of the first inverter X1 and the input of the second inverter. The source of the seventh MOS transistor M7 is connected to the comparison result output line HL. The source of the eighth MOS transistor M8 is connected to the drain of the seventh MOS transistor M7, and the gate of the eighth MOS transistor M8 is used to receive the input information. The drain of the ninth MOS transistor M9 is connected to the tenth MOS transistor M10. The drain terminal of the eighth MOS transistor M8 and the gate terminal of the ninth MOS transistor M9 are used to receive the input information, wherein the input information includes opposite first input information KEY and second input information KEYB, and the first input information KEY and the second input information KEYB are received by the gate terminals of the eighth MOS transistor M8 and the ninth MOS transistor M9, respectively; the drain terminal of the tenth MOS transistor M10 is connected to the source terminal of the ninth MOS transistor M9, the source terminal of the tenth MOS transistor M10 is connected to the comparison result output line HL, and the gate terminal of the tenth MOS transistor M10 is connected to the second inverting unit. Specifically, the gate terminal of the tenth MOS transistor M10 is connected to the output terminal of the third inverter X3 and the input terminal of the fourth inverter X4.

[0046] This application embodiment also provides a write operation method using the aforementioned TCAM bit unit. The write operation method includes: simultaneously writing data into a first storage unit and a second storage unit using a multi-bit write unit. In some embodiments, when the write state is 0, 0 is written into the first storage unit and 1 is written into the second storage unit; when the write state is 1, 1 is written into the first storage unit and 0 is written into the second storage unit; when the write state is X, 0 is written into the first storage unit and 0 is written into the second storage unit; when the write state is invalid, 1 is written into the first storage unit and 1 is written into the second storage unit.

[0047] This application also provides a TCAM, including the TCAM bit unit described above.

[0048] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0049] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0050] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0051] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0052] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A TCAM bit unit, characterized in that, include: An information storage unit is used to store information, including a first storage unit and a second storage unit; A multi-bit write unit is connected to the first storage unit and the second storage unit. The multi-bit write unit is configured to simultaneously perform write operations on the first storage unit and the second storage unit. The first storage unit is connected to a first word line, the second storage unit is connected to a second word line, and the multi-bit write unit is connected to a third word line. When writing different data to the first storage unit and the second storage unit at the same time, the first word line or the second word line is opened, and the third word line is also opened. When writing the same data to the first storage unit and the second storage unit simultaneously, the first word line and the second word line are opened, and the third word line is closed.

2. The TCAM bit unit according to claim 1, characterized in that, The multi-bit write unit includes: The fifth MOS transistor has its source terminal connected to the first memory cell and its drain terminal connected to the second memory cell. The sixth MOS transistor is connected to the fifth MOS transistor via its gate terminal, and the source terminal of the sixth MOS transistor is connected to the second memory cell, while the drain terminal of the sixth MOS transistor is connected to the first memory cell.

3. The TCAM bit unit according to claim 2, characterized in that, The gate terminals of the fifth and sixth MOS transistors are connected to the third word line.

4. The TCAM bit unit according to claim 2, characterized in that, The first memory cell and the second memory cell are respectively connected to the first bit line and the second bit line. The first memory cell includes a first MOS transistor, a first inverting unit and a second MOS transistor connected in sequence. The second memory cell includes a third MOS transistor, a second inverting unit and a fourth MOS transistor connected in sequence.

5. The TCAM bit unit according to claim 4, characterized in that, The drain of the first MOS transistor is connected to the first bit line, the source of the first MOS transistor is connected to the first inverting unit, and the gate of the first MOS transistor is connected to the first word line; the drain of the second MOS transistor is connected to the first inverting unit, the source of the second MOS transistor is connected to the second bit line, and the gate of the second MOS transistor is connected to the first word line.

6. The TCAM bit unit according to claim 4, characterized in that, The drain of the third MOS transistor is connected to the first bit line, the source of the third MOS transistor is connected to the second inverting unit, and the gate of the third MOS transistor is connected to the second word line; the drain of the fourth MOS transistor is connected to the second inverting unit, the source of the fourth MOS transistor is connected to the second bit line, and the gate of the fourth MOS transistor is connected to the second word line.

7. The TCAM bit unit according to claim 4, characterized in that, The source terminal of the fifth MOS transistor is connected to the output terminal of the first inverting unit, and the drain terminal of the fifth MOS transistor is connected to the input terminal of the second inverting unit; the source terminal of the sixth MOS transistor is connected to the output terminal of the second inverting unit, and the drain terminal of the sixth MOS transistor is connected to the input terminal of the first inverting unit.

8. The TCAM bit unit according to claim 4, characterized in that, The first inverter unit includes a first inverter and a second inverter connected end to end; the second inverter unit includes a third inverter and a fourth inverter connected end to end.

9. The TCAM bit unit according to claim 1, characterized in that, The first storage unit is a data storage unit, and the second storage unit is a mask storage unit.

10. The TCAM bit unit according to claim 4, characterized in that, Also includes: The matching and comparison unit is connected to the information storage unit and is used to compare the input information with the stored information and output the comparison result.

11. The TCAM bit unit according to claim 10, characterized in that, The matching comparison unit includes a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, and a tenth MOSFET connected in sequence, wherein: The gate terminal of the seventh MOS transistor is connected to the first inverting unit, and the source terminal of the seventh MOS transistor is connected to the comparison result output line; The source terminal of the eighth MOS transistor is connected to the drain terminal of the seventh MOS transistor, and the gate terminal of the eighth MOS transistor is used to receive the input information; The drain terminal of the ninth MOS transistor is connected to the drain terminal of the eighth MOS transistor, and the gate terminal of the ninth MOS transistor is used to receive the input information. The drain terminal of the tenth MOS transistor is connected to the source terminal of the ninth MOS transistor, the source terminal of the tenth MOS transistor is connected to the comparison result output line, and the gate terminal of the tenth MOS transistor is connected to the second inverting unit.

12. A write operation method, characterized in that, Using the TCAM bit cell according to any one of claims 1 to 11, the write operation method includes: simultaneously writing data into the first storage cell and the second storage cell using a multi-bit write cell.

13. The write operation method according to claim 12, characterized in that, When the write state is 0, 0 is written to the first storage unit and 1 is written to the second storage unit; when the write state is 1, 1 is written to the first storage unit and 0 is written to the second storage unit; when the write state is X, 0 is written to the first storage unit and 0 is written to the second storage unit; when the write state is invalid, 1 is written to the first storage unit and 1 is written to the second storage unit.

14. A TCAM, characterized in that, include: The TCAM bit unit according to any one of claims 1 to 11.

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