Block allocation and erase techniques for sequential write memory devices

Abstract

This application relates to a block allocation and erasure technique for sequential write-to-memory devices. Multiple region reset counters and a global reset counter are maintained. The region reset counters represent the number of times a corresponding region of the memory device has been reset. The global reset counter represents a measure of the central tendency of the multiple region reset counters. A write command is received pointing to a target region of the memory device, and in response to determining that a target portion of the target region is not open, the value of the region reset counter for the target region is compared with the value of the global reset counter. If the value of the target region reset counter is equal to or greater than the value of the global reset counter, then a portion from a free block list is allocated to the target region. The allocated portion has the highest programmable erase count among one or more portions of the free block list.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to block allocation and erasure techniques for sequential write memory devices. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this application provides a system comprising: a memory device; and a processing means operably coupled to the memory device to perform operations including: maintaining a plurality of region reset counters, wherein a region reset counter among the plurality of region reset counters represents the number of times a corresponding region of the memory device has been reset; maintaining a global reset counter for the memory device, wherein the global reset counter represents a measure of the central tendency of the plurality of region reset counters; determining, in response to receiving a write command directed to a target region of the memory device, whether a target portion of the target region is open; comparing, in response to determining that the target portion of the target region is not open, the value of the region reset counter of the target region with the value of the global reset counter; and allocating a first portion from a free block list to the target region in response to determining, based on the comparison, that the value of the region reset counter of the target region is equal to or exceeds the value of the global reset counter, wherein the first portion has the lowest programmable erase count among one or more portions of the free block list.

[0004] In another aspect, this application provides a method comprising: receiving a write command directed to a target region of a memory device by a processing means; executing the write command at the first portion in response to determining that a first portion of the target region is open; identifying a second portion allocated to a media management pool in response to determining that the first portion has reached a threshold capacity, wherein the second portion satisfies a threshold criterion and wherein the media management pool comprises one or more portions; erasing one or more blocks associated with the second portion; and allocating the second portion to a list of free blocks.

[0005] In another aspect, this application provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations including: maintaining a plurality of region reset counters, wherein a region reset counter among the plurality of region reset counters represents the number of times a corresponding region of a memory device has been reset; maintaining a global reset counter for the memory device, wherein the global reset counter represents a measure of the central tendency of the plurality of region reset counters; determining, in response to receiving a write command directed to a target region of the memory device, whether a target portion of the target region is open; comparing, in response to determining that the target portion of the target region is not open, the value of the region reset counter of the target region with the value of the global reset counter; and allocating a first portion from a free block list to the target region in response to determining, based on the comparison, that the value of the region reset counter of the target region is equal to or exceeds the value of the global reset counter, wherein the first portion has the lowest programmable erase count among one or more portions of the free block list. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the particular embodiments, but are for explanation and understanding only.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 Furthermore, some embodiments according to this disclosure will be described in detail. Figure 1 The memory subsystem.

[0009] Figure 3 A block diagram illustrating examples of region mapping data structures according to various embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart of an example method for efficiently allocating blocks in a sequential write memory device according to some embodiments of the present disclosure.

[0011] Figure 5 This is a flowchart of an example method for efficiently erasing blocks in a sequentially written memory device according to some embodiments of the present disclosure.

[0012] Figure 6 A block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0013] This disclosure relates to block allocation and erasure techniques for sequential write memory devices. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following description, in conjunction with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may include high-density non-volatile memory devices, where data needs to be retained when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states associated with the number of bits stored. Logical states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of these values.

[0015] Memory cells can be programmed (written to) by applying a voltage to them, which allows charge to be retained by the cells, thus determining a voltage signal that must be applied to the cell's control electrode or control gate to open the cell to inter-cell current between the source and drain electrodes. A phenomenon observed in memory devices is stored charge loss, or slow charge loss (SCL), sometimes referred to as time-to-voltage shift (TVS), where the threshold voltage distribution shifts to lower voltage levels as charge decreases, for example, with time and / or temperature. SCL affects both programmed memory cells and empty (e.g., recently erased) memory cells. Therefore, block cells that remain in the free block list for extended periods may experience voltage shift. Writing to a memory cell that has already experienced voltage shift can result in an inaccurate representation of the stored data. Therefore, some memory subsystem controllers perform calibration scans to evaluate data state metrics (e.g., voltage shift) of cells within a block before writing to it. If the calibration scan results show that memory cells in a block allocated to the free block list have undergone threshold voltage shifting, the memory subsystem controller may perform a second erase operation on the block before writing to it. Performing a calibration scan and re-erasing the block may affect the latency and efficiency of the memory subsystem.

[0016] A die can also be referred to as a logical unit (LUN). A LUN may contain one or more planes. The memory subsystem can use a striping scheme to process individual datasets into units when performing data operations (e.g., write, read, erase). A LUN stripe is a set of planes that are processed into a unit when writing, reading, or erasing data. Each plane in a LUN stripe can perform the same operation in parallel on all other planes in the LUN stripe. A block stripe is a set of blocks processed into units (one per plane in the LUN stripe). Blocks in a block stripe have the same block identifier (e.g., block number) in their respective planes. A block stripe can be a group of blocks arranged across planes of different dies, such that the blocks are grouped together for data storage purposes. Writing to a block stripe allows more data to be written and read concurrently across multiple dies.

[0017] The memory subsystem controller can receive multiple write requests from the host system and can be configured to execute these write requests in parallel. An instance of a memory subsystem configured to execute multiple write requests in parallel is called a Partition Namespace (ZNS). In a Partition Namespace (ZNS), the address space (e.g., logical block address space) of a memory device (or more than one memory device in a memory subsystem) is divided into multiple regions, allowing for more efficient data management as the capacity of the memory device increases. For example, each region can be designated for use by a specific client application executed by the host system or another system with access to the memory device. One or more partition namespaces can be implemented in a memory device or memory subsystem, and each partition namespace can implement one or more regions. A region can contain multiple memory cells. A memory cell can refer to a plane, block, page, cell, region, area, or any other segment of memory. Each area can be addressed using a portion of the address space of the memory device or memory subsystem.

[0018] Data can be written sequentially and independently of other areas at different rates to specific areas. Some areas within a ZNS can be written to frequently (referred to as "hot areas"), while other areas within the ZNS can remain unchanged for relatively long periods of time (referred to as "cold areas"). Areas are written sequentially within the memory device. Areas can be reset to reuse the blocks allocated to them. A area reset involves erasing all blocks allocated to the area and allocating those blocks to a free block list. Blocks can be allocated to the free block list over an unlimited amount of time.

[0019] For a given region, writes to blocks are managed by the write cursor. The write cursor can operate concurrently in multiple roles. When the memory subsystem controller assigns a block to the write cursor, some memory subsystem controllers may select a block with the lowest program-erase counter (PEC) value from the list of free blocks. The PEC of a block represents the number of times the block has been erased and therefore increments with each erase. Assigning a block with the lowest PEC to a cold region may cause the block to remain untouched for extended periods, potentially leading to inefficient wear leveling.

[0020] The present disclosure addresses the aforementioned and other deficiencies by implementing a memory subsystem controller that allocates blocks to regions based on region usage frequency using a write cursor. The memory subsystem controller maintains a region reset counter for each region, which increments each time a region is reset. The memory subsystem controller also maintains a global reset counter, which can be the average of all region reset counters. Regions with region reset counter values ​​higher than the global reset counter (i.e., higher than the average) are designated as hot regions, while regions with region reset counter values ​​lower than the global reset counter (i.e., lower than the average) are designated as cold regions.

[0021] The memory subsystem controller can also maintain a program-erase counter at the block level. The memory subsystem controller can increment the program-erase counter for a specific block after each block erase operation. When the memory subsystem controller allocates a block to a specific region (or writes to the cursor), it can first identify whether the region is hot or cold. If the region is hot, the memory subsystem controller can allocate a block with a low program-erase counter value (i.e., a cold block). If the region is cold, the memory subsystem can allocate a block with a high program-erase counter value (i.e., a hot block).

[0022] When the memory subsystem controller receives a write command, it can determine whether the region to which the write command points (the "target region") has sufficient space to store the data specified by the write command. In an embodiment, the memory subsystem controller can determine whether the target region has open block stripes. A block stripe is a collection of blocks processed as individual cells. In an embodiment, a block stripe contains blocks from each logical cell (e.g., from each die of the memory device). If the target region has open block stripes, the memory subsystem controller can execute the write command by writing data at the open block stripes.

[0023] The memory subsystem controller can further determine whether a block stripe has reached a threshold capacity level. This indicates that the block stripe is nearing full capacity. In response to a block stripe reaching a threshold capacity level, the memory subsystem controller can transfer the block stripe from the media management pool to the free block list. The media management pool is a list (or a list of blocks) marked for erasure. To avoid threshold voltage shifting while a block is in the media management pool, the memory subsystem controller can maintain two lists: the media management pool and the free block list. Blocks associated with the media management pool can be marked for erasure but are not actually erased. Once the memory subsystem controller has determined that a block (or block stripe) will be written during a period that will avoid threshold voltage shifting, the memory subsystem controller can erase the block (or block stripe) and allocate it from the media management pool to the free block list. Therefore, the memory subsystem controller can select a block stripe from the media management pool, erase the selected block stripe, and transfer the selected block stripe to the free block list. By waiting for the block stripe in the target region to reach the threshold capacity level, and then erasing the block stripe from the media management pool, the block stripe is allocated to the free pool within a relatively short period of time and is unlikely to undergo threshold voltage shift. Therefore, the memory subsystem controller can reduce or eliminate the need to perform calibration scans and / or re-erase previously erased blocks.

[0024] Furthermore, the memory subsystem controller can adjust the threshold capacity to further reduce the likelihood that blocks (or block stripes) will remain in the free block list over extended periods. In some embodiments, the memory subsystem controller can adjust the threshold capacity level based on whether the free block list is empty or full. If the free block list is empty when open block stripes for the target region reach the threshold capacity level, the memory subsystem controller can decrease the threshold capacity level by a certain value to increase the number of block stripes in the free pool list. In some embodiments, the memory subsystem controller can determine that a block strip is being erased even when the free block list is empty, and therefore can decrease the threshold capacity level by a certain percentage (e.g., 2%). If the memory subsystem controller determines that the free block list is empty and a block strip is not being erased, the memory subsystem controller can decrease the threshold capacity level by a factor of two (e.g., 4%). Sometimes, the memory subsystem controller can determine that the free block list is full or that a threshold number of re-erasing operations have been performed on block stripes in the free block list, and can increase the threshold capacity level by a certain percentage (e.g., 2%).

[0025] The advantages of this disclosure include, but are not limited to, efficient wear leveling of the memory device, thereby extending the endurance of the memory device. By allocating blocks in this manner (i.e., allocating hot blocks to cold regions and cold blocks to hot regions), the memory subsystem controller can ensure more efficient wear leveling of blocks within the memory device, which extends the endurance of the memory device. Furthermore, by adjusting the threshold capacity hierarchy in response to the current state of the memory device, aspects of this disclosure reduce latency and extend the lifespan of the memory device by avoiding unnecessary calibration scans and performing double erase operations on empty blocks.

[0026] Figure 1 This section describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such media.

[0027] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a networked commercially available device), or such a computing device containing memory and processing power.

[0029] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0030] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

[0031] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory cells can perform bit storage based on variations in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, local memory 119 may include memory registers that store memory pointers, acquired data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry may translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0041] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] Memory subsystem 110 includes block allocation manager 113, which efficiently allocates and erases blocks for sequential write memory devices. In some embodiments, memory subsystem controller 115 includes at least a portion of block allocation manager 113. In some embodiments, block allocation manager 113 is part of host system 120, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of block allocation manager 113 and is configured to perform the functions described herein.

[0043] Block allocation manager 113 performs efficient block allocation and erasure techniques for sequential write memory devices. In embodiments, block allocation manager 113 maintains a program erase counter (PEC) for each block in the memory device and maintains a region reset counter value for each region in the memory device. Block allocation manager 113 may increment the PEC associated with the block (e.g., 1) each time a block is erased, and may increment the region reset counter associated with the region (e.g., 1) each time a region is reset. A high PEC may indicate that the associated block is a "hot block," and a high region reset counter may indicate that the associated region is a "hot region." Conversely, a low PEC may indicate that the associated block is a "cold block," and a low region reset counter may indicate that the associated region is a "cold region." In embodiments, block allocation manager 113 may determine the PEC of a block stripe by taking the average of the PECs of the blocks associated with the block stripe, or may maintain the PEC for each stripe.

[0044] Block allocation manager 113 may also maintain a global reset counter. The global reset counter may represent a measure of central tendency (e.g., mean, mode, or median) of multiple region reset counters. For example, the global reset counter may be the average of region reset counters associated with the memory device. Block allocation manager 113 may increment the global reset counter after each region reset or in response to a triggering event (e.g., every set minute, or after a set number of region resets). When the memory subsystem controller (e.g., from host system 120) receives a write command pointing to a target region, block allocation manager 113 may determine whether the target region has sufficient space to store the data contained in the write command. That is, the write command may contain a payload (i.e., data to be stored on the memory device) and a logical block address (LBA) for storing the payload. Block allocation manager 113 may, for example, use a region mapping data structure to determine the target region based on the LBA. In some embodiments, the write command may contain a target region for storing the payload, and block allocation manager 113 may, for example, use a region mapping data structure to translate the target region number into an LBA.

[0045] In an embodiment, block allocation manager 113 can determine whether the target region has open block stripes. If the target region has open block stripes, then block allocation manager 113 can execute a write command by writing data (e.g., a payload) at the open block stripe. Block allocation manager 113 controller can further determine whether the block stripe has reached a threshold capacity level. This can indicate that the block stripe is close to full capacity, and the memory subsystem controller can soon assign another block stripe from the free block list to the target region. Thus, in response to the block stripe reaching the threshold capacity level, block allocation manager 113 can execute a block stripe erasure cycle.

[0046] During a block stripe erasure cycle, the block allocation manager 113 transfers block stripes from the media management pool to the free block list. The media management pool is a list of block stripes marked for erasure. That is, upon receiving a region reset command for a specific region, the block allocation manager 113 can allocate the block stripe associated with that specific region to the media management pool and increment the region reset counter associated with that specific region. During a block stripe erasure cycle, the block allocation manager 113 can select a block stripe from the media management pool, erase the selected block stripe, and transfer the selected block stripe to the free block list. A block stripe is allocated to the media management pool in response to a region reset. Blocks associated with the media management pool may be marked for erasure but are not actually erased. Once the block allocation manager 113 has determined that a block stripe will be written during a period that avoids voltage shift (i.e., by determining that the open block stripe has reached a threshold capacity), the block allocation manager 113 can erase the block associated with the block stripe and allocate the block stripe from the media management pool to the free block list.

[0047] When selecting a block stripe from the media management pool, the block allocation manager 113 may select a block stripe with the lowest low programmable erase counter value. In an embodiment, the block allocation manager 113 may select a block stripe within the media management pool that has a PEC value that most closely matches the region reset counter value of the target region (i.e., the region containing the block stripe where the write command is executed). In an embodiment, if the target region is cold, the block allocation manager 113 may select a hot block stripe, and if the target region is hot, a cold block stripe may be selected. The block allocation manager 113 may then erase the blocks associated with the selected block stripe and allocate the block stripe to the free block list.

[0048] If the target region does not have open block stripes, the block allocation manager 113 can allocate block stripes from the free block list to the target region. The free block list can be sorted in descending order of Programmable Erase Count (PEC) values. Therefore, block stripes with the highest PEC values ​​(“hot” block stripes) can be at the top of the list, while block stripes with the lowest PEC values ​​(“cold” block stripes) can be at the bottom of the list. When allocating block stripes from the free block list to the target region, the block allocation manager 113 can compare the value of the region reset counter with the global reset counter to determine whether the target region is hot or cold. If the reset counter value of the target region is higher than the global reset counter value, the memory subsystem controller can determine that the target region is hot. If the reset counter value of the target region is lower than the global reset counter value, the memory subsystem controller can determine that the target region is cold. To support efficient wear leveling, the memory subsystem controller can allocate hot block stripes to cold regions and cold block stripes to hot regions. In other words, if the target region has a reset counter value greater than or equal to the global reset counter value, then the block allocation manager 113 may allocate a block strip with the lowest PEC value from the free block list (i.e., from the bottom of the free block list). Conversely, if the target region has a reset counter value less than the global reset counter value, then the block allocation manager 113 may allocate a block strip with the highest PEC value from the free block list (i.e., from the top of the free block list).

[0049] If the free block list is empty, the block allocation manager 113 may wait until a block stripe is allocated to the free block list, and at that time, allocate the block stripe to the target region. An empty free block list may indicate that the threshold capacity used to determine when to transfer a block stripe from the media management pool to the free block list will be adjusted. The block allocation manager 113 may determine whether a block stripe is currently undergoing a block stripe erasure cycle. If the block allocation manager 113 determines that a block stripe is currently being erased (i.e., the block stripe is undergoing a block stripe erasure cycle), then the block allocation manager 113 may reduce the threshold capacity by a first percentage (or value). If the block allocation manager 113 determines that a block stripe is not currently being erased, then the block allocation manager 113 may reduce the threshold capacity by a second percentage (e.g., twice the first percentage). In an embodiment, the block allocation manager 113 may determine that the free block list is full, and therefore may determine to increase the threshold capacity by a third percentage. The third percentage may be the same as or different from the first and second percentages.

[0050] The following describes further details regarding the operation of block allocation manager 113.

[0051] Figure 2 Furthermore, some embodiments according to this disclosure will be described in detail. Figure 1The memory subsystem 110. The memory subsystem controller may include a block allocation manager 113, which can perform operations related to... Figure 1 The block allocation manager 113 has the same function as the block allocation manager 113. In some embodiments, the block allocation manager 113 may include an erase scheduling unit 250 and a block allocator 252. In some embodiments, the memory subsystem controller 115 may include local volatile memory 125, such as one or a combination of tightly coupled memory (TCM) or volatile memory devices (e.g., SRAM devices). In some embodiments, the local volatile memory 125 may be a separate memory device, such as... Figure 1 The memory device 140. Volatile memory 125 may store a region mapping data structure 201, a media management pool 254, a free pool 256, and a counter 258. In some embodiments, the region mapping data structure 201, media management pool 245, free pool 256, and / or counter 258 may be stored in non-volatile memory. In one embodiment, the region mapping data structure 201 includes a plurality of entries, such that each entry has a block stripe entry identifier that links to an entry within a block stripe mapping data structure (not described). About Figure 3 A more detailed explanation of the region mapping data structure 201.

[0052] The memory subsystem controller 115 is communicatively coupled to the memory device 130. The physical address spaces of multiple dies (e.g., dies A 205 and B 207) can be organized hierarchically by planes, blocks, and pages. Thus, for example, each of dies A 205 and B 207 may contain planes A 221, 261 to planes M 225, 265, and each of planes A 221, 261 to planes M 225, 265 may contain blocks A 221, 271 to blocks N 233, 273. A block stripe can be defined as a group of blocks arranged in a plane across multiple dies of the memory device. As illustrated, the block stripes 244 are arranged into block A 231 containing plane A 221 of die A 205, block A 271 containing plane B 263 of die B 207, etc., for example, also including block A containing plane C of die C, up to other dies (if present and on the line). One or more block stripes may be associated with a region of memory device 130.

[0053] The memory subsystem controller 115 may receive write commands from the host system 120. The write command may include a payload and an indication of where to store the payload. The indication may be a target region and / or the logical block address (LBA) of where the payload will be stored. The payload may contain data to be stored.

[0054] The memory subsystem controller 115 may receive a region reset command from the host system 120. In response to receiving the region reset command, the memory subsystem controller 115 may mark one or more block stripes associated with the region reset as erased, and may allocate one or more block stripes associated with the region reset to the media management pool 254. The memory subsystem controller 115 may also increment the region reset counter value associated with the region reset by a value, such as 1.

[0055] The block allocation manager 113 may include an erase scheduling unit 250 and a block allocator 252. The erase scheduling unit 250 can efficiently erase blocks or block stripes within the memory device 130, and the block allocator 252 can efficiently allocate blocks or block stripes within the memory device 130 to regions.

[0056] The volatile memory 125 may include a region map 201, a media management pool 254, a free pool 256, and a counter 258. The region map 201 may be a region map data structure, such as... Figure 3 Further description. Media management pool 254 may store a list of block stripes marked for erasure (or, in some embodiments, a list of blocks). Free pool 256 may store a list of block stripes that have been erased and are available for allocation to regions (or, in some embodiments, a list of blocks). Counter 258 may store Programmable Erasure Count (PEC) values ​​for blocks and / or block stripes, region reset counter values, global reset counter values, and media management counters associated with memory device 130. In an embodiment, the region reset counter value for each region is stored in region mapping data structure 201.

[0057] In one embodiment, the memory subsystem controller 115 may receive a write command from the host system 120 pointing to a target region. The block allocation manager 113 may determine that the block stripe 244 is associated with the target region (e.g., based on region mapping 201) and that the block stripe 244 is open (i.e., the block stripe 244 is not full, or it has not yet reached a certain capacity). Therefore, the block allocation manager 113 may execute the write command by storing the payload contained in the write command into a block within the block stripe 244. Furthermore, in an embodiment, the block allocation manager 113 may determine that the block stripe 244 has reached a threshold capacity. In response to determining that the block stripe 244 has reached the threshold capacity, the block allocation manager 113 may invoke the erase scheduling unit 250.

[0058] Erasure scheduling unit 250 can select a block stripe from media management pool 254, erase the blocks associated with the selected block stripe, and allocate the selected block stripe to idle pool 256. In response to allocating the selected block stripe to idle pool 256, erasure scheduling unit 250 can release (or remove) the selected block stripe from media management pool 254. Erasure scheduling unit 250 can select a block stripe from media management pool 254 based on the block stripe's Programmable Erasure Count (PEC). In an embodiment, erasure scheduling unit 250 can select a block stripe from media management pool that has a PEC that most closely matches the region reset count value of the target region. In an embodiment, if the target region is "cold," then media management pool 254 can select a "hot" block stripe from media management pool, and if the target region is "hot," then a "cold" block stripe can be selected from media management pool. In other words, if the target region associated with a block stripe that has reached its threshold capacity has a region reset counter value that is higher than or equal to the global reset counter value (i.e., higher than or equal to the average value), then the erase scheduling unit 250 may select a block stripe from the media management pool with a low programmed erase counter value. If the target region associated with a block stripe that has reached its threshold capacity has a region reset counter value that is lower than the global reset counter value, then the erase scheduling unit 250 may select a block stripe from the media management pool with a high programmed erase counter value.

[0059] If a write command received from host system 120 points to a target region (not shown) that does not have open block stripes, then block allocator 252 may select a block stripe from free pool 256 to allocate to the target region. Before writing the newly selected block stripe from free pool 256, block allocator 252 may perform a calibration scan to determine whether any of the blocks in the newly selected block stripe has undergone threshold voltage shift. Performing a calibration scan on the first block stripe may involve determining the value of a voltage distribution metric associated with the newly selected block stripe. If the voltage distribution metric exceeds a threshold criterion, then block allocator 252 may perform a media management operation on the newly selected block stripe; specifically, block allocator 252 may re-erase blocks that have undergone threshold voltage shift. In some embodiments, counter 258 includes a media management counter that tracks the number of re-erase operations performed on memory device 130 within a time period (e.g., 5 minutes or 1 hour). The media management counter may signal when block allocation manager 113 performs a large number of re-erase operations. Therefore, in response to determining that the media management counter exceeds the media management threshold criterion, the block allocation manager 113 may adjust the capacity threshold of the trigger erase scheduler 250. That is, if the calibration scan performed by the block allocator 252 results in a large number of re-erase operations on block stripes within the free pool 256, the block allocation manager 113 may increase the capacity threshold to reduce the number of block stripes that undergo a block stripe erasure cycle performed by the erase scheduler 250.

[0060] Block allocator 252 can select block stripes from free pool 256 to allocate to the target region based on the usage frequency of the target region. Therefore, if the target region is "hot," then block allocator 252 can allocate "cold" block stripes from free pool 256; if the target region is "cold," then block allocator 252 can allocate "hot" block stripes from free pool 256. More specifically, if the region reset counter value associated with the target region is higher than or equal to the global reset counter value, then block allocator 252 can allocate block stripes from free pool 256 with a low (or lowest) program erase count value. If the region reset counter value associated with the target region is lower than the global reset counter value, then block allocator 252 can allocate block stripes from free pool 256 with a high (or highest) program erase count value.

[0061] Figure 3 This is a block diagram illustrating an example of a region-mapped data structure 301 according to various embodiments. The memory subsystem controller 115 can store the region-mapped data structure 301 in... Figure 1 The non-volatile memory device 130. Alternatively or additionally, the memory subsystem controller 115 may store the region mapping data structure 301 in the volatile memory device (e.g., Figure 1 The memory subsystem controller 115 may store at least a portion of the region mapping data structure 301 in local memory. Alternatively or additionally, the host system 120 may store at least a portion of the region mapping data structure 301 in local memory. The memory subsystem controller 115 may use the region mapping data structure 301 itself or in combination with other undescribed data structures to configure or implement media layout (e.g., the layout of where data groups of regions will be located within the physical address space).

[0062] exist Figure 3 In this context, the region mapping data structure 301 is configured to provide memory device layout information for regions within a namespace (e.g., an LBA space used for ZNS operations). The region mapping data structure 301 can be used with... Figure 2The region mapping 201 is the same as that in the previous example. The region mapping data structure 301 may have multiple entries. Each region mapping entry in the region mapping data structure 301 identifies information about a region, such as the region's starting LBA 311, the block stripe identifier 313 associated with the region, the region cursor value 315, the region's state 317, the region reset counter 319, etc. The block stripe identifier 313 may indicate one or more block stripes associated with the region. The region cursor value 315 may indicate the current LAB address used to write received data. In some embodiments, the region mapping data structure 301 may include a data field indicating whether the current block stripe (e.g., associated with the cursor value 315) is open. The state 317 may have values ​​indicating whether the region is empty, full, implicitly open, explicitly open, closed, etc., to track the progress of writing to the region. After each region reset, the region reset counter 319 may increment by a set value (e.g., "1").

[0063] Figure 4 This is a flowchart of an example method 400 for efficiently allocating blocks in a sequential write memory device according to some embodiments of the present disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The block allocation manager 113 executes. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0064] At operation 410, the processing logic maintains multiple region reset counters. Each region reset counter represents the number of times a corresponding region of the memory device has been written in a reset sequence. That is, after a region reset, the processing logic increments the region reset counter associated with that specific region by a certain amount (e.g., 1).

[0065] In an embodiment, the processing logic may receive a region reset command from the host system. Upon receiving a region reset command pointing to a specific region of the memory device, the processing logic may identify one or more portions associated with the specific region. A portion may be a block or a block stripe. To execute the region reset command, the processing logic may add one or more identified portions (i.e., block stripes or blocks) associated with the specific region to a media management pool. The media management pool may store a list of regions marked for erasure. That is, portions allocated to the media management pool contain outdated data and are therefore reusable. The processing logic may also increment a region reset counter associated with the specific region.

[0066] At operation 420, the processing logic maintains a global reset counter for the memory device. The global reset counter represents a measure of the central tendency of multiple region reset counters (e.g., the mean, mode, and / or median of the multiple region reset counters). In some embodiments, the processing logic determines the global reset counter value by calculating the average of the multiple region reset counter values. The processing device may determine the global reset counter value in response to a triggering event (e.g., a number of minutes per set or a number of execution region resets per set).

[0067] At operation 430, in response to receiving a write command (e.g., from the host system) pointing to a target region of the memory device, the processing logic determines whether a portion of the target region is open. If the portion is not full, or if the portion has not yet reached a certain threshold capacity, then the portion is open. In an embodiment, the processing logic maintains a portion identifier (e.g., such as...). Figure 3 The region mapping data structure, as described herein, uses a block stripe identifier and / or cursor value to identify the portion of the target region to be written to (e.g., the cursor value may identify the logical block address (LBA) where the payload of the write command is to be stored, and the portion identifier may identify the portion associated with the LBA). The processing logic determines whether a portion of the target region is open by comparing its used capacity with a threshold capacity. Used capacity refers to the amount of space currently used to store data in the portion. If the used capacity of the portion meets or exceeds the threshold capacity, then the portion may be considered closed (i.e., not open). If the used capacity of the portion is below the threshold capacity, then the portion may be considered open. Alternatively, the processing logic may (e.g., in the region mapping data structure) maintain a data field indicator indicating whether the portion is open. For example, if the used capacity of the portion is below the threshold capacity (indicating the portion is open), the indicator may be a value "0", and if the used capacity of the portion meets or exceeds the threshold capacity, the processing logic may change the value of the indicator to a value "1".

[0068] At operation 440, in response to determining that a portion of the target area is not open, the processing device compares the value of the area reset counter for the target area with the value of the global reset counter. In an embodiment, prior to the comparison, the processing logic may determine the value of the global reset counter by calculating the average of the values ​​of multiple area reset counters.

[0069] At operation 450, in response to the comparison determining that the value of the region reset counter for the target region is equal to or greater than the value of the global reset counter, the processing device allocates a first portion from the free block list to the target region, wherein the first portion has the lowest programmed erase count. The free block list may contain a list of portions (e.g., block stripes or blocks) that have undergone a block stripe erasure cycle. A block stripe erasure cycle is a process logic that selects a portion from the media management pool, erases the block associated with the selected portion, and associates the portion with the free block list. Regarding... Figure 5 The block strip erasure cycle is further described.

[0070] In an embodiment, the processing logic may maintain a Program Erase Count (PEC) for each block of the memory device. After each block is erased, the PEC associated with the block is incremented by an amount (e.g., "1"). Additionally, the processing logic may maintain and / or calculate the PEC for each segment (e.g., each stripe). The PEC for a segment may be the average, mean, and / or median of the PECs associated with one or more blocks associated with that segment. In an embodiment, the processing logic may store segments associated with a free block list in descending order of PEC, in which case the processing logic selects the first segment from the bottom of the free block list as the segment with the lowest PEC. Therefore, the processing logic allocates "cold" segments (i.e., segments with low PECs) to "hot" regions (i.e., regions with region reset counter values ​​equal to or greater than the global reset counter value).

[0071] Alternatively, in response to the comparison determining that the value of the region reset counter for the target region is less than the value of the global reset counter, the processing device allocates a second portion from the free block list to the target region, wherein the second portion has the highest programmable erase count. That is, the processing logic allocates "hot" portions (i.e., portions with high PEC) to "cold" regions (i.e., regions with region reset counter values ​​lower than the global reset counter value). In an embodiment where the processing logic stores portions associated with the free block list in descending order of PEC, the processing logic selects the second portion from the top of the free block list as the portion with the highest PEC.

[0072] In an embodiment, the processing logic may determine that the free block list is empty. That is, the processing logic may determine that there is no portion associated with the free block list. In response to determining that the free block list is empty, the processing logic may determine whether a block stripe erasure cycle has been triggered. The block stripe erasure cycle may be triggered in response to the processing logic determining that the open portion of the target region has reached a threshold capacity. In response to determining that a block stripe erasure cycle has been triggered, the processing logic reduces the threshold capacity by a first value (e.g., a percentage, such as 2%). In response to determining that a block stripe erasure cycle has not yet been triggered, the processing logic reduces the threshold capacity by a second value (e.g., twice the first percentage, such as 4%). That is, if the free blocks are empty when the processing logic attempts to allocate a portion from the free block list to the target region, then the processing logic reduces the threshold capacity that triggers the block stripe erasure cycle. Reducing the threshold capacity that triggers the block stripe erasure cycle allows the free block list to receive portions more quickly, thus avoiding a situation where the free block list is empty when a free portion is needed. The amount of reduction in the threshold capacity may depend on whether a block stripe erasure cycle is in progress. Therefore, if the block stripe erasure cycle is in progress, the processing logic can reduce the threshold capacity by a smaller value (or percentage) compared to the case where the block stripe erasure cycle is not in progress.

[0073] In an embodiment, the processing logic may determine that the free block list is full. The processing logic may have a maximum number of portions that can be allocated to the free block list. In response to determining that the maximum number of portions of the free block list has been reached or exceeded, the processing logic increases the threshold capacity by a certain value (or percentage). The threshold capacity is the capacity level that triggers the block stripe erasure cycle. The value by which the threshold capacity is increased may be the same as or different from the value by which the threshold capacity is decreased (as described above and below). That is, in some embodiments, the processing logic may increase the threshold capacity by 2%, 4%, or some other value or percentage. Increasing the threshold capacity that triggers the block stripe erasure cycle allows a smaller portion to be allocated to the free block list, which is desirable when the free block list is full (i.e., exceeding a certain capacity level).

[0074] In an embodiment, the processing logic may perform a calibration scan on a first and / or second portion of a target region from a list of free blocks. Performing a calibration scan on the first portion may involve determining the value of a voltage distribution metric associated with the first portion. In response to determining that the value of the voltage distribution metric associated with the first portion meets a voltage distribution criterion, the processing logic performs media management operations with respect to one or more blocks associated with the first portion. For example, a comparison of the voltage distribution metric with a threshold criterion may indicate that the threshold voltage of one or more blocks associated with the first portion has shifted. Due to the voltage shift, the processing logic re-erases the blocks associated with the portion before writing to the first portion.

[0075] The processing logic may further maintain a media management counter associated with the memory device. The media management counter represents the number of media management operations (e.g., the number of re-erase operations) performed with respect to one or more portions of the free block list within a given time period. Specifically, whenever the processing logic determines that one or more blocks associated with a portion of the free block list have a voltage distribution metric exceeding a voltage distribution criterion and performs a re-erase operation, the processing logic may increment the media management counter by an amount (e.g., "1"). The media management counter may be reset every specific time period (e.g., 5 minutes or 1 hour) to accurately represent the number of re-erase operations performed within said time period.

[0076] In response to determining that the media management counter meets media management criteria (e.g., exceeding a threshold number of re-erase operations within a time period), the processing logic increases the threshold capacity by a certain value (e.g., a certain percentage). That is, performing more than a certain number of re-erase operations on the portion associated with the free block list can instruct that portion associated with the free block list to wait in the free block list for an extended period of time (indicated by a threshold distribution exceeding a voltage allocation threshold) before being allocated to a target area. To avoid performing re-erase operations on the portion associated with the free block list, the processing logic can adjust the threshold capacity that triggers the block stripe erasure cycle. The processing logic can increase the threshold capacity by a certain percentage (e.g., 2%) to extend the time the portion is associated with the media management pool and reduce the time the portion is associated with the free block list before being allocated to a target area.

[0077] Figure 5 This is a flowchart of an example method 500 for efficiently erasing blocks in a sequentially written memory device according to some embodiments of the present disclosure. Method 500 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The block allocation manager 113 executes. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0078] At operation 510, the processing logic receives a write command pointing to a target region of the memory device. In an embodiment, the processing logic may receive the write command from a host system. The write command may include a payload (i.e., data to be written to the memory device) and a logical block address (LBA) storing the payload. The processing logic may, for example, use a region mapping data structure to determine the target region based on the LBA. In some embodiments, the write command may include a target region number storing the payload instead of a specific LBA, and the processing logic may, for example, use a region mapping data structure to translate the target region number into an LBA.

[0079] At operation 520, in response to determining that a first portion of the target region is open, the processing device executes a write command at the first portion. The processing logic may use, for example, a region mapping data structure to determine whether a portion of the target is open. A portion is open if it is not full, or if it has not yet reached a certain threshold capacity. Executing the write command may involve storing the payload at the portion of the target region.

[0080] At operation 530, in response to determining that the first portion has reached a threshold capacity, the processing logic identifies a second portion allocated to the media management pool. The media management pool contains one or more portions marked for erasure. The processing logic may identify a portion from the media management pool that meets the threshold condition as the second portion. In an embodiment, the portion that meets the threshold condition is based on the PEC of the portion compared to the region erase count of the target region. That is, when identifying the second portion that meets the threshold criterion, the processing logic identifies the value of the region reset counter associated with the target region. The processing logic also identifies the corresponding programmable erase count (PEC) of one or more portions in the media management pool. The processing logic may maintain the PEC of each block in the memory device, and the corresponding PEC of a portion may be the average of the PEC values ​​of the blocks associated with said portion. Alternatively, the processing logic may maintain the PEC of said portion. The processing logic may compare the region reset counter value of the target region to determine whether the target region is "hot" or "cold". If the target region is "hot", then the processing logic may identify the second portion as the portion with the lowest PEC; if the target region is "cold", then the processing logic may identify the second portion as the portion with the highest PEC. If the target region is neither "hot" nor "cold" (i.e., the target region reset counter value matches the global reset counter value), then the processing logic can identify the "cold" part as the second part.

[0081] In this embodiment, the portion that meets the threshold condition is the portion whose PEC value most closely matches the region reset counter of the target region. The processing logic compares the PEC of each portion associated with the media management pool with the region reset counter associated with the target region. The processing logic identifies a second portion from one or more portions associated with the media management pool as the portion with the PEC that most closely matches the region reset counter value of the target region. In this way, the processing logic selects portions from the media management pool that have characteristics similar to the target region reaching full capacity.

[0082] At operation 540, the processing logic erases one or more blocks associated with the second portion. In an embodiment, the processing logic may increment the program erase count associated with the second portion in response to erasing one or more blocks associated with the second portion. That is, the processing logic may maintain a program erase count (PEC) for each portion of the memory device (e.g., each block and / or each stripe). The processing logic may increment the PEC of each portion in response to performing an erase operation on each portion. At operation 550, the processing logic allocates the second portion to a list of free blocks.

[0083] In this embodiment, the processing logic may determine that the media management pool is empty, i.e., there is no part associated with the media management pool. In response to determining that the media management pool is empty, the processing logic reduces the threshold capacity by a certain value (e.g., a certain percentage, such as 3%). The threshold capacity is the capacity that triggers the block stripe erasure cycle. Reducing the threshold capacity by a certain value allows the block stripe erasure cycle to be triggered earlier, thus avoiding an empty media management pool.

[0084] Figure 6 An example machine is described as representing computer system 600, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein can be executed. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of block allocation manager 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0085] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, it should be understood that the term "machine" also includes any set of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any one or more of the methods discussed herein.

[0086] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0087] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0088] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) storing one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0089] In one embodiment, instruction 626 includes instructions for implementing a block allocation manager (e.g., Figure 1The block allocation manager 113) provides functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0090] Some parts of the previously described descriptions have been presented based on algorithms and symbolic representations of operations on data bits within computer memory. Those skilled in the art of data processing use these algorithms to describe and represent the main points of their work in the most effective way to communicate them to others skilled in the art. An algorithm herein is generally considered to be a self-consistent sequence of operations that produce a desired result. These operations are those requiring physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes, primarily for reasons of general use, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0091] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0092] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0093] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0094] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0095] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A system comprising: Memory devices; as well as A processing device operatively coupled to the memory device to perform operations including: Maintain multiple region reset counters, wherein one of the multiple region reset counters represents the number of times a corresponding region of the memory device has been reset; Maintain a global reset counter for the memory device, wherein the global reset counter represents a measure of the central tendency of the plurality of regional reset counters; In response to receiving a write command pointing to a target region of the memory device, determine whether the target portion of the target region is open; In response to determining that the target portion of the target region is not open, the value of the region reset counter of the target region is compared with the value of the global reset counter; as well as In response to determining, based on the comparison, that the value of the region reset counter for the target region is equal to or exceeds the value of the global reset counter, a first portion from the free block list is allocated to the target region, wherein the first portion has the lowest programmed erase count among one or more portions of the free block list.

2. The system according to claim 1, further comprising: In response to determining, based on the comparison, that the value of the region reset counter for the target region is less than the value of the global reset counter, a second portion from the free block list is allocated to the target region, wherein the second portion has the highest programmable erase count among the one or more portions of the free block list.

3. The system according to claim 1, further comprising: In response to receiving a region reset command pointing to a specific region of the memory device, one or more portions associated with the specific region are identified, each of the one or more portions including a block or block stripe allocated to the specific region; Add one or more of the identified portions associated with the specific region to the media management pool; as well as Increment the region reset counter associated with the specific region.

4. The system according to claim 1, further comprising: In response to a trigger event, the value of the global reset counter is determined by calculating the average of the values ​​of the plurality of regional reset counters.

5. The system according to claim 1, further comprising: In response to determining that the list of free blocks is empty, determine whether a block stripe erasure cycle has been triggered; In response to determining that the block stripe erasure cycle has been triggered, the threshold capacity is reduced by a first value, wherein the threshold capacity corresponds to the capacity level of the target portion that triggered the block stripe erasure cycle; as well as In response to determining that the block stripe erasure cycle has not yet been triggered, the threshold capacity is reduced by a second value.

6. The system according to claim 1, further comprising: In response to determining that the free block list is full, the threshold capacity is increased by a certain value, wherein the threshold capacity corresponds to the capacity level of the target portion that triggers the block stripe erasure cycle.

7. The system according to claim 1, further comprising: Determine the value of the voltage distribution metric associated with the first part; as well as In response to determining that the value of the voltage distribution metric associated with the first portion satisfies the voltage distribution criterion, a media management operation is performed with respect to one or more blocks associated with the first portion.

8. The system according to claim 7, further comprising: Maintain a media management counter associated with the memory device, wherein the media management counter represents the number of media management operations performed in one or more portions of the free block list within a certain time period; as well as In response to determining that the media management counter meets the media management criteria, the threshold capacity is increased by a certain value, wherein the threshold capacity corresponds to the capacity level of the target portion that triggers the block stripe erasure cycle.

9. A method comprising: The processing unit receives a write command pointing to a target region of the memory device; In response to determining that a first portion of the target area is open, the write command is executed at the first portion; In response to determining that the first portion has reached the threshold capacity, a second portion is identified as being allocated to the media management pool, wherein the second portion meets the threshold criteria, and wherein the media management pool comprises one or more portions; Erase one or more blocks associated with the second part; as well as The second part is assigned to the list of free blocks.

10. The method of claim 9, further comprising: This increments the program erase count associated with the second part.

11. The method of claim 9, wherein satisfying the threshold criterion comprises: The value of the region reset counter associated with the target region is identified; Identify the corresponding programmable erase count value for one or more portions of the media management pool; as well as Identify the second portion in the media management pool, wherein the second portion has the corresponding programmable erase count value that most closely matches the value of the region reset counter associated with the target region.

12. The method of claim 9, further comprising: In response to determining that the media management pool is empty, the threshold capacity is reduced by a certain value.

13. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: Maintain multiple region reset counters, wherein the region reset counter in the multiple region reset counters represents the number of times a corresponding region of the memory device has been reset; Maintain a global reset counter for the memory device, wherein the global reset counter represents a measure of the central tendency of the plurality of regional reset counters; In response to receiving a write command pointing to a target region of the memory device, determine whether the target portion of the target region is open; In response to determining that the target portion of the target region is not open, the value of the region reset counter of the target region is compared with the value of the global reset counter; as well as In response to determining, based on the comparison, that the value of the region reset counter for the target region is equal to or exceeds the value of the global reset counter, a first portion from the free block list is allocated to the target region, wherein the first portion has the lowest programmed erase count among one or more portions of the free block list.

14. The non-transitory computer-readable storage medium of claim 13, wherein the processing means is configured to perform operations further comprising: In response to determining, based on the comparison, that the value of the region reset counter for the target region is less than the value of the global reset counter, a second portion from the free block list is allocated to the target region, wherein the second portion has the highest programmable erase count among the one or more portions of the free block list.

15. The non-transitory computer-readable storage medium of claim 13, wherein the processing means is configured to perform operations further comprising: In response to receiving a region reset command pointing to a specific region of the memory device, one or more portions associated with the specific region are identified, each of the one or more portions including a block or block stripe allocated to the specific region; Add one or more identified portions associated with the specific region to the media management pool; and Increment the region reset counter associated with the specific region.

16. The non-transitory computer-readable storage medium of claim 13, wherein the processing means is configured to perform operations further comprising: In response to a trigger event, the value of the global reset counter is determined by calculating the average of the values ​​of the plurality of regional reset counters.

17. The non-transitory computer-readable storage medium of claim 13, wherein the processing means is configured to perform operations further comprising: In response to determining that the list of free blocks is empty, determine whether a block stripe erasure cycle has been triggered; In response to determining that the block stripe erasure cycle has been triggered, the threshold capacity is reduced by a first value, wherein the threshold capacity corresponds to the capacity level of the target portion that triggered the block stripe erasure cycle; and In response to determining that the block stripe erasure cycle has not yet been triggered, the threshold capacity is reduced by a second value.

18. The non-transitory computer-readable storage medium of claim 13, wherein the processing means is configured to perform operations further comprising: In response to determining that the free block list is full, the threshold capacity is increased by a certain value, wherein the threshold capacity corresponds to the capacity level of the target portion that triggers the block stripe erasure cycle.

19. The non-transitory computer-readable storage medium of claim 13, wherein the processing means is configured to perform operations further comprising: Determine the value of the voltage distribution metric associated with the first portion; and In response to determining that the value of the voltage distribution metric associated with the first portion satisfies the voltage distribution criterion, a media management operation is performed with respect to one or more blocks associated with the first portion.

20. The non-transitory computer-readable storage medium of claim 19, wherein the processing means is configured to perform operations further comprising: Maintain a media management counter associated with the memory device, wherein the media management counter represents the number of media management operations performed on the one or more portions of the free block list within a certain time period; and In response to determining that the media management counter meets the media management criteria, the threshold capacity is increased by a certain value, wherein the threshold capacity corresponds to the capacity level of the target portion that triggers the block stripe erasure cycle.

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