Apparatus, system, and method for programming data in a non-volatile memory device

Abstract

The present application relates to apparatuses, systems, and methods of programming data in a non-volatile memory device. A memory device includes a memory structure including at least one non-volatile memory cell capable of storing multi-bit data, and a control device configured to perform a program verify after applying a first program pulse to the at least one non-volatile memory cell, determine a program mode of the at least one non-volatile memory cell based on a result of the program verify, and change a level of a pass voltage applied to another non-volatile memory cell coupled with the at least one non-volatile memory cell from a first level to a second level higher than the first level or change a setup time for changing a potential of a bit line coupled to the at least one non-volatile memory cell according to the program mode.

Description

Technical Field

[0001] The embodiments of this disclosure described herein relate to memory devices, and more specifically, to apparatus and methods for storing or programming data in a non-volatile memory device. Background Technology

[0002] Recently, the paradigm of computing environments has shifted to ubiquitous computing, making computer systems accessible almost anytime, anywhere. As a result, the use of portable electronic devices (e.g., mobile phones, digital cameras, laptops, etc.) is rapidly increasing. Each such portable electronic device may use or include a memory system with at least one memory device. The memory system may be a data storage device. The data storage device may serve as the primary or secondary storage device of the portable electronic device.

[0003] Unlike hard drives, this type of data storage device uses non-volatile semiconductor memory, exhibiting greater stability and durability. It lacks mechanical drive components (e.g., robotic arms) and therefore offers high data access speeds and relatively low power consumption. Examples of data storage devices with these advantages include, but are not limited to, Universal Serial Bus (USB) memory devices, memory cards with various interfaces, solid-state drives (SSDs), and the like. Summary of the Invention

[0004] Embodiments of this disclosure can provide apparatus and methods for improving the data input / output speed of a memory device included in a data processing system. Furthermore, embodiments of this disclosure enable improvements in data input / output speed during the process of programming data items into a non-volatile memory device.

[0005] In one embodiment, a memory device may include: a memory structure comprising at least one non-volatile memory cell capable of storing multiple bits of data; and a control device configured to: perform programming verification after applying a first programming pulse to the at least one non-volatile memory cell; determine a programming mode of the at least one non-volatile memory cell based on the result of the programming verification; and, according to the programming mode, change the level of a pass voltage applied to another non-volatile memory cell connected to the at least one non-volatile memory cell from a first level to a second level higher than the first level, or change the setup time for changing the potential of a bit line connected to the at least one non-volatile memory cell. Here, performing programming verification, determining the programming mode, and changing the level of the pass voltage are performed during a data programming operation that applies multiple programming pulses to the at least one non-volatile memory cell to program multiple bits of data.

[0006] The memory structure may include: a first transistor connected between at least one memory cell and a bit line and configured to operate in response to a first control voltage applied to a drain select line (DSL); a second transistor connected between at least one memory cell and a source line and configured to operate in response to a second control voltage applied to a string select line (SSL); and at least one non-volatile memory cell connected between the first and second transistors and configured to store multiple bits of data via a plurality of programming pulses.

[0007] At least one non-volatile memory cell may include N transistors connected in series between the first transistor and the second transistor. The control device may program multiple bits of data into at least one non-volatile memory cell in the order of the transistors connected to the first transistor to the other transistor connected to the second transistor among the N transistors.

[0008] The control device can also be configured to determine the voltage level in response to the temperature of the memory device. The control device can change the voltage level from a first level to a second level by executing an overvoltage drive.

[0009] The control device is also configured to maintain the second level until the potential of the bit line connected to at least one non-volatile memory cell changes according to the programming mode determined based on the results of programming verification.

[0010] The control device may also be configured to apply a pass voltage of a first level to at least one other non-volatile memory cell in an erased state, and to apply a pass voltage of a second level to at least one other non-volatile memory cell that has been programmed.

[0011] The control device can also be configured to increase the level of the through voltage in response to the number of programming pulses applied to at least one non-volatile memory cell during a data programming operation. The setup time can be shortened as the temperature of the memory device increases.

[0012] The control device can determine the programming mode corresponding to the second programming pulse as one of a first mode, a second mode, and a third mode. The control device is also configured to apply the second programming pulse to at least one non-volatile memory cell in the first mode to change or adjust the threshold voltage of the at least one non-volatile memory cell by a first amount equal to or greater than the amount caused by the first programming pulse. The control device is also configured to apply the second programming pulse in the second mode to change or adjust the threshold voltage of the at least one non-volatile memory cell by a second amount less than the amount caused by the first programming pulse. The control device is further configured to apply the second programming pulse to at least one non-volatile memory cell in the third mode where changing the threshold voltage is prohibited.

[0013] When the programming mode is in the second mode, the control device can change the level of the voltage applied. The control device can determine the setup time corresponding to each of the first, second, and third modes.

[0014] The more programming pulses applied to at least one non-volatile memory cell during data programming operations, the shorter the setup time can become.

[0015] In one embodiment, a memory system may include: a memory device comprising a plurality of non-volatile memory cells; and a controller configured to receive write commands and write data from a host, determine the storage location of the write data in the memory device, and transmit the write data to the memory device. The memory device may be configured to: determine a programming mode that causes a change in threshold voltages of the plurality of non-volatile memory cells, and, according to the programming mode, change the level of the pass voltage to other non-volatile memory cells connected to the plurality of non-volatile memory cells from a first level to a second level higher than the first level, or change the setup time for changing the potential of a bit line connected to at least one non-volatile memory cell. Here, the determination and change are performed during a data programming operation that applies a plurality of programming pulses to the plurality of non-volatile memory cells to program the write data.

[0016] Multiple non-volatile memory cells in a memory device can be interconnected via a single word line. Each of the multiple non-volatile memory cells can be connected to a different bit line. The memory device may also include a string comprising: a first transistor configured to operate in response to a first control voltage applied to a drain select line (DSL); a second transistor configured to operate in response to a second control voltage applied to a string select line (SSL); one of the multiple non-volatile memory cells; and other non-volatile memory cells connected in series between the first transistor and the second transistor to the one non-volatile memory cell.

[0017] The memory device can program multiple bits of data into a string in the order of memory cell connected to the first transistor in the string to another memory cell connected to the second transistor.

[0018] The memory device may also be configured to apply a first-level pass voltage to at least one non-volatile memory cell in an erased state located between the second transistor and the one non-volatile memory cell in the plurality of non-volatile memory cells, and to apply a second-level pass voltage to at least one programmed non-volatile memory cell located between the first transistor and the one non-volatile memory cell in the plurality of non-volatile memory cells.

[0019] The memory device can also be configured to determine the voltage level in response to the temperature of the memory device. The memory device can change the first voltage level to a second voltage level by executing an overvoltage drive.

[0020] The memory device can also be configured to maintain a second level until the potential of the bit line of one of the plurality of nonvolatile memory cells changes according to a programming mode determined based on a programming verification operation.

[0021] The memory device may also be configured to apply a pass voltage of a first level to at least one other non-volatile memory cell in an erased state, and to apply a pass voltage of a second level to at least one other non-volatile memory cell that has been programmed.

[0022] The memory device can also be configured to increase the level of the through voltage in response to the number of programming pulses applied to one of the plurality of nonvolatile memory cells during a data programming operation. Setup time can be reduced as the temperature of the memory device increases.

[0023] The programming mode corresponding to the second programming pulse can be determined as one of a first mode, a second mode, and a third mode. The first mode is used to apply the second programming pulse to change or adjust the threshold voltage of the non-volatile memory cell to a first level, which is equal to or greater than the level caused by the first programming pulse. The second mode is used to apply the second programming pulse to change or adjust the threshold voltage of the non-volatile memory cell to a second level, which is less than the level caused by the first programming pulse. The third mode is used to apply the second programming pulse to a non-volatile memory cell where threshold voltage change is prohibited.

[0024] When the programming mode is in the second mode, the memory device can change the level of the voltage applied. The control device can determine the setup time corresponding to each of the first, second, and third modes.

[0025] The more programming pulses applied to at least one non-volatile memory cell during data programming operations, the shorter the setup time becomes.

[0026] In another embodiment, a method for operating a memory device may include the following steps: applying a first programming pulse through a word line to program multiple bits of data into a plurality of nonvolatile memory cells; verifying the programming state of the plurality of nonvolatile memory cells corresponding to the first programming pulse; determining a programming mode that causes a change in the threshold voltage of the plurality of nonvolatile memory cells for a second programming pulse to be applied to the word line; and, before controlling the potential of the bit line according to the programming mode while applying the second programming pulse to the word line, increasing the level of the through voltage to other nonvolatile memory cells connected to the plurality of nonvolatile memory cells from a first level to a second level higher than the first level, or adjusting the setup time for changing the potential of the bit line connected to at least one nonvolatile memory cell according to the programming mode.

[0027] In another embodiment, a method of operating a non-volatile memory device having a string of memory cells connected to bit lines includes: sequentially performing programming operations on the memory cells according to an incremental step pulse programming (ISPP) scheme. The execution may include: applying a programming pulse to a selected cell of the string, simultaneously applying a first through voltage to an unselected and erased cell of the string, and applying a second through voltage to an unselected and programmed cell of the string. The second through voltage may be maintained higher than the first through voltage for a predetermined amount of time to discharge the channel of the string by turning on a drain selection transistor connected to the bit lines before adjusting the potential of the bit lines. Attached Figure Description

[0028] The description herein refers to the accompanying drawings, in which similar reference numerals refer to similar parts throughout the drawings.

[0029] Figure 1 A memory device according to an embodiment of the present disclosure is illustrated.

[0030] Figure 2 A data processing system according to an embodiment of the present disclosure is illustrated.

[0031] Figure 3 An incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is illustrated.

[0032] Figure 4 A method for storing multiple bits of data in a non-volatile memory cell according to an embodiment of the present disclosure is illustrated.

[0033] Figure 5 The programming and verification operations of an incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure are illustrated.

[0034] Figure 6 Programming operations according to embodiments of the present disclosure are illustrated.

[0035] Figure 7 The discharge of the string and bit lines during programming operations according to embodiments of the present disclosure is illustrated.

[0036] Figure 8 An example is illustrated of a programming operation that can be changed based on the discharge of the serial and bit lines according to an embodiment of the present disclosure.

[0037] Figure 9 A method for controlling the discharge of serial and bit lines according to an embodiment of the present disclosure is illustrated.

[0038] Figure 10 An example of a programming operation based on a change in voltage level according to an embodiment of the present disclosure is illustrated.

[0039] Figure 11 An embodiment based on this disclosure is illustrated. Figure 10 The operating state of the voltage is shown in the figure.

[0040] Figure 12 A method for operating a memory device according to an embodiment of the present disclosure is illustrated.

[0041] Figure 13 A table for determining the level of a voltage is illustrated according to an embodiment of the present disclosure.

[0042] Figure 14 An embodiment of a method for operating a memory device is illustrated.

[0043] Figure 15 An embodiment of a method for operating a memory device is illustrated.

[0044] Figure 16 Examples illustrating the correlation between bitline setup time and programming loop and operating environment are provided. Detailed Implementation

[0045] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0046] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “implementation,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or may not necessarily be combined in the same embodiment.

[0047] In this disclosure, the terms “comprising,” “including,” “containing,” and “included in” are open-ended. As used in the appended claims, these terms specify the presence of the mentioned element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the inclusion of additional components (e.g., interface units, circuitry, etc.).

[0048] In this disclosure, various units, circuits, or other components may be described or claimed as being "configured" to perform multiple tasks. In this context, "configured as" is used to imply a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, a block / unit / circuit / component can be referred to as being configured to perform a task even when the specified block / unit / circuit / component is not currently in operation (e.g., not opened or not activated). Blocks / units / circuits / components used with the language "configured as" include hardware—e.g., circuits, memory storing program instructions executable to perform operations, etc. Additionally, "configured as" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the tasks in question. "Configured as" may also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture means (e.g., integrated circuits) suitable for implementing or performing one or more tasks.

[0049] As used in this disclosure, the term "circuit" or "logic" means all of the following: (a) a purely hardware circuit implementation (such as an implementation in analog and / or digital circuits only), and (b) a combination of circuits and software (and / or firmware), such as (if applicable): (i) a combination of processors or (ii) portions of processors / software (including digital signal processors), software, and memory that work together to enable a device (such as a mobile phone or server) to perform various functions, and (c) circuits such as a microprocessor or a portion of a microprocessor that require software or firmware (even if the software or firmware is not physically present) to function. This definition of "circuit" or "logic" applies to all uses of the term in this application (including in any claim). As another example, as used in this application, the term "circuit" or "logic" also covers implementations of processors (or processors) only, or portions of processors and their accompanying software and / or firmware. The term "circuit" or "logic" also covers, for example, and if applicable to a particular claim element, an integrated circuit for a storage device.

[0050] As used herein, the terms “first,” “second,” “third,” etc., serve as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily imply that a first value must precede a second value. Furthermore, while these terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0051] Furthermore, the term "based on" is used to describe factors influencing a determination. This term does not exclude additional factors that may influence the determination. That is, a determination may be based solely on those factors, or at least partially on those factors. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, such a phrase does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely on B.

[0052] Here, a data item, data entry, or data term can be a bit sequence. For example, a data item may include the contents of a file, a portion of a file, a page in memory, an object in object-oriented programming, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a bit sequence. According to one implementation, a data item may include discrete objects. According to another implementation, a data item may include information units within a transmission packet between two different components.

[0053] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein similar reference numerals denote similar elements.

[0054] Embodiments of this disclosure may provide a memory system, a data processing system, and methods for operating the memory system and the data processing system. The data processing system includes components and resources such as a memory system and a host, and is capable of dynamically allocating multiple data paths for data communication between components based on the usage of the components and resources.

[0055] Figure 1 A memory system according to an embodiment of the present disclosure is illustrated. Specifically, Figure 1 A memory cell array circuit of a memory die included in a memory device according to an embodiment of the present disclosure is illustrated schematically.

[0056] Reference Figure 1The memory die may include a memory bank 330, which includes a plurality of non-volatile memory cells. The memory bank 330 may include a plurality of cell strings 340. Each cell string 340 includes a plurality of non-volatile memory cells connected to each of a plurality of bit lines BL0 to BLm-1. Each cell string 340 arranged in each column of the memory bank 330 may include at least one drain-select transistor (DST) and at least one string-select transistor (or source-select transistor) (SST). A plurality of non-volatile memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the drain-select transistor DST and the string-select transistor SST. For example, each of the non-volatile memory cells MC0 to MCn-1 may be configured to store a multi-level cell (MLC) with a data item having multiple bits per cell. Each cell string 340 may be individually electrically connected to a corresponding bit line BL0 to BLm-1.

[0057] Figure 1 A memory bank 330 including NAND flash memory cells is shown as an example. However, the memory bank 330 included in the memory device 150 according to embodiments of the present disclosure is not limited to NAND flash memory. In another embodiment, the memory bank 330 may also be implemented as NOR flash memory, hybrid flash memory combining or mixing at least two different types of memory cells, or monolithic NAND flash memory with the controller embedded in a single memory chip. Additionally, the memory bank 330 according to embodiments of the present disclosure may include flash memory cells including charge trapping flash (CTF) layers having conductive floating gates or insulating layers.

[0058] According to embodiments of this disclosure, Figure 1 The memory group 330 shown may be included in Figure 2 The illustrated memory device 150 includes at least one memory block 152, 154, 156. According to embodiments, the memory device 150 may have a two-dimensional (2D) structure or a three-dimensional (3D) structure. For example, each memory block 152, 154, 156 in the memory device 150 may be implemented as a 3D structure (or a vertical structure). Each memory block 152, 154, 156 may have a three-dimensional structure extending along a first direction to a third direction (e.g., the x-axis direction, the y-axis direction, and the z-axis direction).

[0059] The memory group 330 of the memory device 150, comprising multiple memory blocks 152, 154, and 156, can be connected to multiple bit lines BL, multiple string select lines SSL, multiple drain select lines DSL, multiple word lines WL, multiple dummy word lines DWL (not shown), and multiple common source lines CSL. The memory group 300 may include multiple NAND strings NS, each NAND string NS including multiple memory cells MC. In the memory group 330, each NAND string NS can be connected to each bit line BL. Additionally, the string select transistor SST of each NAND string NS can be connected to the common source line CSL, and the drain select transistor DST of each NAND string NS can be connected to the corresponding bit line BL. Here, the memory cells MC can be arranged between the string select transistor SST and the drain select transistor DST of each NAND string NS.

[0060] Reference Figure 1 The voltage supply circuit 170 in the memory device 150 can supply word line voltages (e.g., object voltages such as programming voltage, read voltage, and pass voltage) via each word line according to the operating mode, or supply voltage to the block body (e.g., a well region) to which each memory block, including the memory cell MC, is formed. In this case, the voltage generation operation of the voltage supply circuit 170 can be performed under the control of a control circuit (not shown). Furthermore, the voltage supply circuit 170 can generate multiple variable read voltages to distinguish multiple data items from each other. In response to the control of the control circuit, one of the memory blocks (or sectors) of the memory cell array can be selected, and one of the word lines of the selected memory block can be selected. Word line voltages can be supplied separately to the selected word line and the unselected word line. The voltage supply circuit 170 may include a voltage generation circuit (see reference) for generating target voltages with various levels. Figures 4 to 8 The voltage supply circuit 170 may be coupled to a first pin or pad that receives a first power supply voltage VCC applied from an external source (e.g., an external device) and a second pin or pad that receives a second power supply voltage VPP applied from an external device. Here, the second power supply voltage VPP may have a voltage level that is twice or higher than the voltage level of the first power supply voltage VCC. For example, the first power supply voltage VCC may have a voltage level of 2.0V to 5.5V, while the second power supply voltage may have a voltage level of 9V to 13V. The voltage supply circuit 170 according to embodiments of this disclosure may include a voltage generation circuit for more quickly generating target voltages of various levels used in the memory bank 330. The voltage generation circuit may use the second power supply voltage VPP to generate a target voltage with a higher voltage level than the second power supply voltage VPP.

[0061] The read / write circuit 320, controlled by the control circuitry of the memory device 150, can operate as a sense amplifier or a write driver depending on the operating mode. For example, in verification and read operations, the read / write circuit 320 can operate as a sense amplifier for reading data items from the memory cell array. Furthermore, in programming operations, the read / write circuit 320 can operate as a write driver for controlling the potential of bit lines based on the data items to be stored in the memory cell array. During programming operations, the read / write circuit 320 can receive data items to be programmed into the cell array from page buffers (not shown). The read / write circuit 320 can drive bit lines based on the input data items. For this purpose, the read / write circuit 320 includes a plurality of page buffers (PB) 322, 324, 326, each page buffer corresponding to each column (or each bit line) or each column pair (or each bit line pair). According to an embodiment, a plurality of latches (not shown) may be included in each of the page buffers 322, 324, 326.

[0062] Although not shown, page buffers 322, 324, and 326 can be connected to data input / output devices (e.g., serialization circuits or serializers) via multiple buses. When each of page buffers 322, 324, and 326 is connected to a data input / output device via a different bus, potential delays in data transmission from page buffers 322, 324, and 326 can be reduced. For example, each of page buffers 322, 324, and 326 can perform data transmission without any waiting time.

[0063] According to the implementation, the memory device 150 can receive a write command, write data, and information about the location where the write data is to be stored (e.g., a physical address). The control circuit 180 causes the voltage supply circuit 170 to generate programming pulses, pass voltages, etc., used in the programming operation performed in response to the write command, as well as various voltages used in the verification operation performed after the programming operation.

[0064] The error rate when programming multiple data items in non-volatile memory cells included in memory bank 330 may be higher than the error rate when storing a single data item in a non-volatile memory cell. For example, errors in non-volatile memory cells may be caused by inter-cell interference (CCI). To reduce errors in non-volatile memory cells, the width (deviation) of the threshold voltage distribution corresponding to the data items stored between non-volatile memory cells should be reduced. For this purpose, memory device 150 can use a programming technique called Incremental Step Pulse Programming (ISPP) operation to effectively narrow the threshold voltage distribution of non-volatile memory cells. Memory device 150 can use ISPP operation for multi-step programming operations. For example, memory device 150 can divide the programming operation into least significant bit (LSB) programming operations and most significant bit (MSB) operations according to a predetermined order between non-volatile memory cells or pages.

[0065] According to embodiments of this disclosure, an apparatus and method can be provided that can accelerate the programming operation of a memory device by reducing the time used to discharge bit lines or channels between programming pulse applications during the operation of programming data by applying multiple programming pulses to memory cells in the memory device. Specifically, in order to discharge bit lines or channels in the memory device, the memory device can determine, control, or adjust the voltage level of the pass voltage applied to unselected word lines based on the operating environment such as temperature or the number of programming pulse applications (e.g., how many programming pulses are applied to the selected word line during the data programming operation).

[0066] Specifically, according to an embodiment, the memory device can perform an overdrive of a pass voltage applied to at least one unselected word line for a predetermined time during a programming operation to discharge the bit lines or channels in the memory device. For example, the memory device 150 can apply a pass voltage of a first level to at least one word line connected to a non-volatile memory cell in an erase state, and apply a pass voltage of a second level to at least one word line connected to a non-volatile memory cell being programmed. Here, the second level is higher than the first level. Therefore, the memory device can reduce the operating margin corresponding to each programming pulse during the operation of programming data by applying multiple programming pulses to the non-volatile memory cell, so that the memory device can reduce the time spent on programming data operations.

[0067] Figure 2 A data processing system 100 according to an embodiment of the present disclosure is illustrated.

[0068] Reference Figure 2The data processing system 100 may include a host 102 that is coupled to or connected to a memory system such as a memory system 110. For example, the host 102 and the memory system 110 may be connected to each other via a data bus, host cable, etc., to perform data communication.

[0069] The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 may be considered as physically separate components or elements. The memory device 150 and the controller 130 may be connected via at least one data path. For example, the data path may include a channel and / or a path.

[0070] According to embodiments, the memory device 150 and the controller 130 may be functionally separated components or elements. Furthermore, according to embodiments, the memory device 150 and the controller 130 may be implemented using a single chip or multiple chips. The controller 130 may perform data input / output operations in response to requests input from external devices. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0071] like Figure 2 As shown, memory device 150 may include a plurality of memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 can be understood as a group of non-volatile memory cells whose data is removed together in a single erase operation. Although not shown, memory blocks 152, 154, and 156 may include pages as a group of non-volatile memory cells that store data together during a single programming operation or output data together during a single read operation. For example, a memory block may include multiple pages.

[0072] For example, memory device 150 may include multiple memory planes or multiple memory dies. According to an embodiment, a memory plane may be considered as a logical or physical partition including at least one memory block, drive circuitry capable of controlling an array including multiple non-volatile memory cells, and buffers that can temporarily store data input to or output from the non-volatile memory cells.

[0073] Additionally, according to an embodiment, a memory die may include at least one memory plane. A memory die can be understood as a collection of components implemented on a physically distinguishable substrate. Each memory die can be connected to the controller 130 via a data path. Each memory die may include an interface for exchanging data items and signals with the controller 130.

[0074] According to an embodiment, the memory device 150 may include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory die. Figure 1 The internal structure of the memory device 150 shown may vary depending on the performance of the memory system 110. Embodiments of this disclosure are not limited to... Figure 2 The internal structure is shown.

[0075] Reference Figure 2 The memory device 150 may include a voltage supply circuit 170 capable of supplying at least some voltages to memory blocks 152, 154, and 156. The voltage supply circuit 170 may include a voltage generation circuit for generating target voltages used in memory blocks 152, 154, and 156, as described above. Figures 4 to 8 The voltage supply circuit 170 can supply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory blocks. For example, during a read operation for reading data stored in the non-volatile memory cells included in memory blocks 152, 154, and 156, the voltage supply circuit 170 can supply the read voltage Vrd to the selected non-volatile memory cell. During a programming operation for storing data in the non-volatile memory cells included in memory blocks 152, 154, and 156, the voltage supply circuit 170 can supply the programming voltage Vprog to the selected non-volatile memory cell. Furthermore, during a read operation or programming operation performed on a selected non-volatile memory cell, the voltage supply circuit 170 can supply the pass voltage Vpass to the unselected non-volatile memory cell. During an erase operation to erase data stored in the non-volatile memory cells included in memory blocks 152, 154, and 156, voltage supply circuit 170 can supply an erase voltage Vers to the memory blocks.

[0076] Memory device 150 may store information about various voltages supplied to memory blocks 152, 154, and 156 based on which operation is performed. For example, when the non-volatile memory cells in memory blocks 152, 154, and 156 can store multiple bits of data, multiple levels of read voltage Vrd may be needed to identify or read multiple data items. Memory device 150 may include a table containing information corresponding to multiple levels of read voltage Vrd for each multiple data item. For example, the table may include bias values ​​stored in registers, each bias value corresponding to a specific level of read voltage Vrd. The number of bias values ​​for read voltage Vrd used for read operations may be limited to a preset range. Furthermore, the bias values ​​may be quantized.

[0077] The host 102 may include a portable electronic device (e.g., a mobile phone, MP3 player, laptop computer, etc.) or a non-portable electronic device (e.g., a desktop computer, game console, television, projector, etc.). According to an embodiment, the host 102 may include the central processing unit (CPU) included in both portable and non-portable electronic devices.

[0078] Host 102 may also include at least one operating system (OS) capable of controlling the functions and operations performed within host 102. The OS can provide interoperability between host 102, which is operationally coupled to memory system 110, and users who wish to store data in memory system 110. The OS can support functions and operations corresponding to user requests. By way of example, and not limitation, OS can be classified as general-purpose operating systems and mobile operating systems based on the mobility of host 102. General-purpose operating systems can be further categorized into personal operating systems and enterprise operating systems based on system requirements or user environment. Compared to personal operating systems, enterprise operating systems can be specifically designed to protect and support high-performance computing.

[0079] The mobile operating system may include services or features that support mobility (e.g., power-saving features). Host 102 may include multiple operating systems. In response to a user's request, host 102 may execute multiple operating systems interlocked with memory system 110. Host 102 may send multiple commands corresponding to the user's request to memory system 110, thereby executing operations corresponding to the multiple commands within memory system 110.

[0080] The controller 130 in the memory system 110 can control the memory device 150 in response to requests or commands input from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102 and can perform a write operation (or programming operation) to store data input from the host 102 in the memory device 150. In order to perform data input / output (I / O) operations, the controller 130 can control and manage internal operations such as reading data, programming data, erasing data, etc.

[0081] According to an implementation, the controller 130 may include a host interface 132, a processor 134, an error correction circuit (ECC) 138, a power management unit (PMU) 140, a memory interface 142, and a memory 144. For example... Figure 2 The components included in the controller 130 shown can vary depending on the structure, function, and operational performance of the memory system 110.

[0082] For example, depending on the host interface protocol, the memory system 110 can be implemented using any of a variety of storage devices that can be electrically connected to the host 102. Non-limiting examples of suitable storage devices include solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), miniature MMCs (RS-MMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, etc. Depending on the implementation of the memory system 110, components can be added to or omitted from the controller 130.

[0083] Both host 102 and memory system 110 may include a controller or interface for sending and receiving signals, data, etc., according to one or more predetermined protocols. For example, host interface 132 in memory system 110 may include devices capable of sending signals, data, etc. to host 102 or receiving signals, data, etc. from host 102.

[0084] The host interface 132 included in controller 130 can receive signals, commands (or requests), and / or data input from host 102. For example, host 102 and memory system 110 can send and receive data therebetween using predetermined protocols. Examples of communication standards, protocols, or interfaces supported by host 102 and memory system 110 for sending and receiving data include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), High-Speed ​​Peripheral Component Interconnect (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. According to embodiments, host interface 132 is a layer for exchanging data with host 102 and is implemented or driven by firmware called the Host Interface Layer (HIL).

[0085] Integrated Drive Electronics (IDE) or Advanced Technology Accessory (ATA) can be used as one of the interfaces for sending and receiving data, and, for example, a cable including 40 wires connected in parallel can be used to support data transmission and reception between host 102 and memory system 110. When multiple memory systems 110 are connected to a single host 102, the multiple memory systems 110 can be classified as master and slave by using the DIP switches or positions to which the multiple memory systems 110 are connected. The memory system 110 set as master can be used as the master memory device. IDE (ATA) can include, for example, Fast-ATA, ATAPI, or Enhanced IDE (EIDE).

[0086] The Serial Advanced Technology Attachment (SATA) interface is a serial data communication interface compatible with various ATA standards for parallel data communication interfaces used by Integrated Drive Electronics (IDE) devices. The 40 pins of the IDE interface can be reduced to 6 pins in the SATA interface. For example, the 40 parallel signals of IDE can be converted into 6 serial signals in the SATA interface. The SATA interface is widely used in host 102 for data transmission and reception due to its faster data transmission and reception rates and lower resource consumption. The SATA interface can connect up to 30 external devices to a single transceiver included in host 102. Furthermore, the SATA interface supports hot-plugging, which allows external devices to be attached to or detached from host 102 even while data communication between host 102 and another device is in progress. Therefore, even when host 102 is powered on, memory system 110 can function as an attachment or port, similar to devices supported by Universal Serial Bus (USB). For example, in a host 102 with an eSATA port, the storage system 110 can be freely attached to or detached from the host 102 like an external hard drive.

[0087] The Small Computer System Interface (SCSI) is a serial data communication interface used to connect a computer or server to other peripheral devices. Compared to other interfaces such as IDE and SATA, SCSI offers high transfer speeds. In SCSI, the host 102 and at least one peripheral device (e.g., memory system 110) are connected in series, but data transmission and reception between the host 102 and each peripheral device can be performed through parallel data communication. In SCSI, devices such as memory system 110 can be easily connected to or disconnected from the host 102. SCSI can support connections of up to 15 other devices to a single transceiver included in the host 102.

[0088] Serial Attached SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, the host 102 and multiple peripheral devices are connected in series, and data transmission and reception between the host 102 and each peripheral device can be performed according to a serial data communication scheme. SAS supports the connection between the host 102 and peripheral devices through serial cables instead of parallel cables, making it easier to manage equipment using SAS and enhancing operational reliability and communication performance. SAS can support connections from up to eight external devices to a single transceiver included in the host 102.

[0089] High-speed non-volatile memory (NVMe) is an interface based at least on High-Speed ​​Peripheral Component Interconnect (PCIe), which is designed to increase the performance and design flexibility of hosts 102, servers, computing devices, etc., equipped with a non-volatile memory system 110. PCIe can use slots or specific cables to connect computing devices (e.g., host 102) and peripheral devices (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one line (e.g., x1, x4, x8, or x16) to achieve high-speed data communication of hundreds of MB / s (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s). Depending on the implementation, PCIe schemes can achieve bandwidths from tens to hundreds of gigabits per second. NVMe can support operating speeds of non-volatile memory systems 110 (such as SSDs) that are faster than hard drives.

[0090] According to one implementation, host 102 and memory system 110 can be connected via Universal Serial Bus (USB). Universal Serial Bus (USB) is a scalable, hot-pluggable, plug-and-play serial interface that provides a cost-effective standard connection between host 102 and peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, cameras, etc. Multiple peripheral devices, such as memory system 110, can be connected to a single transceiver included in host 102.

[0091] Reference Figure 2 Error correction circuit 138 can correct erroneous bits in data read from memory device 150 and may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction encoding on data to be programmed into memory device 150 to generate encoded data with parity bits added, and stores the encoded data in memory device 150. When controller 130 reads data stored in memory device 150, ECC decoder can detect and correct erroneous bits contained in the data read from memory device 150. For example, after performing error correction decoding on data read from memory device 150, error correction circuit 138 determines whether error correction decoding was successful and outputs an indication signal (e.g., a correction success signal or a correction failure signal) based on the result of error correction decoding. Error correction circuit 138 may use parity bits already generated during the ECC encoding process for data stored in memory device 150 to correct erroneous bits in the read data. When the number of erroneous bits is greater than or equal to the number of correctable erroneous bits, error correction circuit 138 may instead output a correction failure signal indicating that error correction failed, instead of correcting the erroneous bits.

[0092] According to embodiments, the error correction circuit 138 can perform error correction operations based on coding modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc. The error correction circuit 138 may include all circuits, modules, systems, and / or devices for performing error correction operations based on at least one of the aforementioned codes. Figure 2 The error correction circuit 138 shown may include at least some of the components included in the controller 130.

[0093] For example, the ECC decoder can perform hard-decision decoding or soft-decision decoding on data sent from memory device 150. Hard-decision decoding can be understood as one of two broadly categorized methods for error correction. Hard-decision decoding may include the operation of correcting erroneous bits by reading digital data "0" or "1" from non-volatile memory cells in memory device 150. Because hard-decision decoding deals with binary logic signals, the circuit / algorithm design or configuration can be simpler and the processing speed can be faster compared to soft-decision decoding.

[0094] Soft-decision decoding can quantize the threshold voltage in a non-volatile memory cell in memory device 150 using two or more quantized values ​​(e.g., multi-bit data, approximations, analog values, etc.) to correct erroneous bits based on the two or more quantized values. Controller 130 can receive two or more letters or quantized values ​​from multiple non-volatile memory cells in memory device 150 and then perform decoding based on information generated by characterizing the quantized values ​​as a combination of information such as conditional probability or likelihood.

[0095] According to the implementation, the ECC decoder can use Low-Density Parity-Generator Matrix (LDPC-GM) codes, which are designed for soft-decision decoding. The LDPC code uses an algorithm that reads the value of data in the memory device 150 as several bits based on reliability, rather than simply 1 or 0 data as in hard-decision decoding, and iteratively repeats this through message exchange to improve the reliability of the value. These values ​​are then ultimately determined as 1 or 0 data. For example, the decoding algorithm using LDPC codes can be understood as probabilistic decoding. In hard-decision decoding, the value output from the non-volatile memory cell is decoded as 0 or 1. Compared to hard-decision decoding, soft-decision decoding can determine the value stored in the non-volatile memory cell based on random information. Regarding bit flips (which can be considered errors that can occur in the memory device 150), soft-decision decoding can provide improved probabilities for correcting errors and recovering data, as well as providing the reliability and stability of the corrected data. The LDPC-GM code can have a scheme where internal LDGM codes can be cascaded with high-speed LDPC codes.

[0096] According to the implementation, the ECC decoder can use, for example, low-density parity-check convolutional codes (LDPC-CC) for soft-decision decoding. LDPC-CC can have a scheme using linear-time coding and pipelined decoding based on variable block length and shift registers.

[0097] According to the implementation, the ECC decoder can use, for example, a log-likelihood ratio Turbo code (LLR-TC) for soft-decision decoding. The log-likelihood ratio (LLR) can be calculated as a non-linear function of the distance between the sampled value and the ideal value. Alternatively, the Turbo code (TC) can include simple two-dimensional or three-dimensional codes (e.g., Hamming codes), and the decoding is repeated in both the row and column directions to improve the reliability of the values.

[0098] The power management unit (PMU) 140 can control the power supplied to the controller 130. The PMU 140 can monitor the power supplied to the memory system 110 (e.g., the voltage supplied to the controller 130) and supply power to the components included in the controller 130. The PMU 140 can not only detect power on or off, but also generate a trigger signal to enable the memory system 110 to perform an emergency backup of its current state when the power supply to the memory system 110 is unstable. According to embodiments, the PMU 140 may include means or components capable of accumulating power that can be used in emergency situations.

[0099] The memory interface 142 can be used as an interface for processing commands and data transferred between the controller 130 and the memory device 150, so as to allow the controller 130 to control the memory device 150 in response to commands or requests input from the host 102. If the memory device 150 is flash memory, the memory interface 142 can generate control signals for the memory device 150 and can process data input to or output from the memory device 150 under the control of the processor 134.

[0100] For example, when the memory device 150 includes NAND flash memory, the memory interface 142 includes a NAND flash memory controller (NFC). The memory interface 142 can provide an interface for handling commands and data between the controller 130 and the memory device 150. According to an embodiment, the memory interface 142 can be implemented or driven by firmware called a flash interface layer (FIL) for exchanging data with the memory device 150.

[0101] According to the implementation, the memory interface 142 may support an Open NAND Flash Interface (ONFi), a toggle mode, etc., for data input / output with the memory device 150. For example, ONFi may use a data path (e.g., channel, path, etc.) that includes at least one signal line capable of bidirectional transmission and reception in units of 8 bits or 16 bits of data. Data communication between the controller 130 and the memory device 150 may be implemented through at least one interface relating to Asynchronous Single Data Rate (SDR), Synchronous Double Data Rate (DDR), Switched Double Data Rate (DDR), etc.

[0102] Memory 144 can be used as working memory for memory system 110 or controller 130, while also temporarily storing transaction data for operations performed in memory system 110 and controller 130. For example, memory 144 can temporarily store read data output from memory device 150 in response to a read request from host 102 before outputting read data to host 102. Additionally, controller 130 can temporarily store write data input from host 102 in memory 144 before programming write data into memory device 150. When controller 130 controls operations such as data read operations, data write or programming operations, and data erase operations of memory device 150, data transferred between controller 130 and memory device 150 of memory system 110 can be temporarily stored in memory 144.

[0103] In addition to reading or writing data, memory 144 may store information (e.g., mapped data, read requests, programming requests, etc.) used for inputting or outputting data between host 102 and memory device 150. Depending on the implementation, memory 144 may include one or more of a command queue, programming memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, mapping buffer / cache, etc. Controller 130 may allocate some storage space in memory 144 for components established to perform data input / output operations. For example, a write buffer established in memory 144 may be used to temporarily store target data undergoing programming operations.

[0104] In implementations, memory 144 can be implemented using volatile memory. For example, memory 144 can be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 An example of a memory 144 located within the controller 130 is illustrated, but the implementation is not limited thereto. The memory 144 may be located inside or outside the controller 130. For example, the memory 144 may be embodied by an external volatile memory having a memory interface for transferring data and / or signals between the memory 144 and the controller 130.

[0105] Processor 134 can control the overall operation of memory system 110. For example, processor 134 can control programming or reading operations of memory device 150 in response to write or read requests from host 102. According to embodiments, processor 134 can execute firmware to control programming or reading operations in memory system 110. In this document, firmware may be referred to as flash translation layer (FTL). According to embodiments, processor 134 can be implemented using a microprocessor, central processing unit (CPU), etc.

[0106] According to an implementation, the memory system 110 can be implemented using at least one multi-core processor. A multi-core processor is a circuit or chip in which two or more cores, considered to be distinct processing regions, are integrated. For example, when multiple cores in a multi-core processor independently drive or execute multiple flash translation layers (FTLs), the data input / output speed (or performance) of the memory system 110 can be improved. According to an implementation, data input / output (I / O) operations in the memory system 110 can be performed independently by different cores in the multi-core processor.

[0107] The processor 134 in the controller 130 can perform operations corresponding to requests or commands input from the host 102. Furthermore, the memory system 110 can perform operations independently of commands or requests input from the host 102. In one case, operations performed by the controller 130 in response to requests or commands input from the host 102 can be considered foreground operations, while operations performed by the controller 130 independently of requests or commands input from the host 102 can be considered background operations. The controller 130 can perform foreground or background operations for reading, writing, or erasing data in the memory device 150. Additionally, parameter setting operations corresponding to setting parameter commands or setting feature commands sent as setting commands from the host 102 can be considered foreground operations. Background operations can be performed without commands sent from the host 102. For example, the controller 130 can perform garbage collection (GC), wear leveling (WL), bad block management for identifying and handling bad blocks, etc.

[0108] According to the implementation, substantially similar operations can be performed as both foreground and background operations. For example, garbage collection can be considered a foreground operation when the memory system 110 performs garbage collection (e.g., manual GC) in response to a request or command input from the host 102. Garbage collection can be considered a background operation when the memory system 110 performs garbage collection (e.g., automatic GC) independently of the host 102.

[0109] When the memory device 150 includes multiple dies (or multiple chips) and each die includes multiple non-volatile memory cells, the controller 130 can perform parallel processing of multiple requests or commands input from the host 102 to improve the performance of the memory system 110. For example, the sent requests or commands can be divided into multiple groups including at least some of the multiple planes, multiple dies, or multiple chips included in the memory device 150, and the multiple groups of requests or commands can be processed individually or in parallel in each plane, each die, or each chip.

[0110] The memory interface 142 in controller 130 can be connected to multiple dies or chips in memory device 150 via at least one channel and at least one path. When controller 130 distributes and stores data in multiple dies via each channel or path in response to a request or command associated with multiple pages including non-volatile memory cells, multiple operations corresponding to the request or command can be executed simultaneously or in parallel in multiple dies or planes. This processing method or scheme can be considered an interleaving method. Because the data input / output speed of memory system 110 is increased by operating in an interleaving method, the data I / O performance of memory system 110 can be improved.

[0111] By way of example, and not limitation, controller 130 can identify the state of multiple channels (or pathways) associated with multiple dies included in memory device 150. Controller 130 can determine the state of each channel or pathway as one of busy, ready, active, idle, normal, and abnormal states. The determination by the controller of which channel or pathway to deliver instructions (and / or data) can be associated with a physical block address. Controller 130 can reference descriptors delivered from memory device 150. A descriptor can include a block or page containing parameters describing certain things about memory device 150. Descriptors can have a predetermined format or structure. For example, descriptors can include device descriptors, configuration descriptors, cell descriptors, etc. Controller 130 can refer to or use descriptors to determine which channel or pathway to use to exchange instructions or data.

[0112] Reference Figure 2 The memory device 150 in the memory system 110 may include a plurality of memory blocks 152, 154, and 156. Each of the plurality of memory blocks 152, 154, and 156 includes a plurality of non-volatile memory cells. According to an embodiment, memory blocks 152, 154, and 156 may be a group of non-volatile memory cells that are erased together. Memory blocks 152, 154, and 156 may include a plurality of pages, which are a group of non-volatile memory cells that are read or programmed together.

[0113] In some embodiments, each memory block 152, 154, or 156 may have a highly integrated three-dimensional stacked structure. Furthermore, the memory device 150 may include multiple dies, each die including multiple planes, and each plane including multiple memory blocks 152, 154, or 156. The configuration of the memory device 150 may be varied depending on the performance of the memory system 110.

[0114] Figure 2 An example of a memory device 150 is shown, comprising multiple memory blocks 152, 154, and 156. Depending on the number of bits that can be stored in a single memory cell, the multiple memory blocks 152, 154, and 156 can be any of a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, etc. An SLC memory block comprises multiple pages implemented by memory cells, each storing one bit of data. SLC memory blocks can have higher data I / O performance and greater endurance than MLC memory blocks. An MLC memory block comprises multiple pages implemented by memory cells, each storing multiple bits of data (e.g., two or more bits of data). Compared to SLC memory blocks, MLC memory blocks can have a larger storage capacity for the same space. From a storage capacity perspective, MLC memory blocks can be highly integrated.

[0115] In one embodiment, the memory device 150 may be implemented using MLC memory blocks such as two-level cell (DLC) memory blocks, three-level cell (TLC) memory blocks, four-level cell (QLC) memory blocks, and combinations thereof. A DLC memory block may include multiple pages implemented by memory cells capable of storing 2 bits of data per memory cell. A TLC memory block may include multiple pages implemented by memory cells capable of storing 3 bits of data per memory cell. A QLC memory block may include multiple pages implemented by memory cells capable of storing 4 bits of data per memory cell. In another embodiment, the memory device 150 may be implemented using blocks comprising multiple pages implemented by memory cells capable of storing five or more bits of data per memory cell.

[0116] According to one implementation, the controller 130 can use an MLC memory block included in the memory device 150 as an SLC memory block, which stores one bit of data in a memory cell. The data input / output speed of a Multilevel Cell (MLC) memory block can be slower than that of an SLC memory block. That is, when an MLC memory block is used as an SLC memory block, a margin for read or programmable operations can be reduced. For example, when an MLC memory block is used as an SLC memory block, the controller 130 can perform data input / output operations at a higher speed. Therefore, the controller 130 can use an MLC memory block as an SLC buffer to temporarily store data, because a buffer may require a high data input / output speed to improve the performance of the memory system 110.

[0117] Furthermore, according to an embodiment, the controller 130 can program data multiple times in the MLC without performing an erase operation on a specific MLC memory block included in the memory device 150. Typically, non-volatile memory cells do not support data overwriting. However, the controller 130 can utilize the characteristic of the MLC to store multiple bits of data to program one bit of data multiple times in the MLC. For an MLC overwrite operation, when programming one bit of data in the MLC, the controller 130 can store the number of programming times as separate operation information. According to an embodiment, an operation to evenly level the threshold voltage of the MLC can be performed before programming another one bit of data in the same MLC where one bit of data has already been stored.

[0118] In one embodiment, the memory device 150 is implemented as a non-volatile memory such as flash memory (e.g., NAND flash memory, NOR flash memory, etc.). In another embodiment, the memory device 150 may be implemented by at least one of phase-change random access memory (PCRAM), ferroelectric random access memory (FRAM), spin-torque random access memory (STT-RAM), and spin-torque magnetic random access memory (STT-MRAM).

[0119] Figure 3 An incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is illustrated.

[0120] Reference Figure 3 Data can be programmed into non-volatile memory cells in an erased state. When a programming pulse is supplied to the word line connected to the non-volatile memory cell, the threshold voltage distribution of the non-volatile memory cell shifts to the right (in the direction of increasing threshold voltage) from the erased state. If programming pulses are continuously supplied to the non-volatile memory cells, the threshold voltage distribution of the non-volatile memory cells can be continuously shifted to the right. Programming pulses can be supplied until most of the multiple non-volatile memory cells in the threshold voltage distribution have a value higher than the target voltage V. TARG Threshold voltage.

[0121] More specifically, when the programming operation begins (operation 212), the memory device 150 may apply programming pulses to a plurality of non-volatile memory cells containing data to be programmed (operation 214). After applying the programming pulses, the memory device 150 may verify that most of the plurality of non-volatile memory cells have a voltage higher than the target voltage V. TARG Threshold voltage V TH (Operation 216). When the verification result FAIL (failure) determines that most of the multiple non-volatile memory cells do not have a voltage higher than the target voltage V. TARG Threshold voltage V TH At this time, memory device 150 applies another programming pulse to the corresponding non-volatile memory cell (operation 214). When it is determined, based on another verification result PASS, that most of the multiple non-volatile memory cells have a voltage higher than the target voltage V. TARG Threshold voltage V TH At this time, the memory device 150 can end the programming operation (operation 218).

[0122] To narrow the threshold voltage distribution of multiple non-volatile memory cells, it is advantageous to slightly shift the threshold voltage distribution of the multiple non-volatile memory cells to the right when a single programming pulse is applied, rather than shifting them significantly to the right. On the other hand, the number of programming pulses applied can be increased when the threshold voltage distribution of the multiple non-volatile memory cells is slightly shifted to the right. According to embodiments, this can be three times or more the number of bits of data that can be stored in the non-volatile memory cell. For example, when 2 bits of data can be stored in a non-volatile memory cell, the non-volatile memory cell can have four programming states corresponding to the 2 bits of data (e.g., "00", "01", "10", and "11"). To form a tighter threshold voltage distribution (i.e., a narrower distribution), the degree to which the threshold voltage distribution of the multiple non-volatile memory cells shifts to the right in response to a single programming pulse can be less than the difference between two adjacent programming states. For example, when two or more programming pulses are applied, it can be designed to shift according to the difference between two adjacent programming states. In this case, the number of programming pulses applied can be eight or more, which is more than four times the number of bits of data.

[0123] According to embodiments of this disclosure, the degree to which the threshold voltage distribution of multiple non-volatile memory cells shifts when a single programming pulse is applied can be understood as the target level. (Refer to...) Figure 6 The target level will be described in more detail.

[0124] Figure 4 A method for storing multiple bits of data in a non-volatile memory cell according to an embodiment of the present disclosure is illustrated. Figure 4 An example of a programming operation performed in a memory device 150 comprising non-volatile memory cells each capable of storing 3 bits of data is illustrated.

[0125] Data stored in non-volatile memory cells can be based on the threshold voltage V of the corresponding memory cell. TH The threshold voltage V of the memory cell is used to distinguish them. TH The threshold voltage V can vary depending on the number of electrons or charges injected into the floating gate of the corresponding memory cell. A single-level cell (SLC) can be divided into two ranges. TH It stores 1-bit data, either "0" or "1". On the other hand, the three-level cell (TLC) in the memory device 150 can have eight threshold voltage ranges.

[0126] Reference Figure 4To reduce the number of programming pulses applied during Incremental Step Pulse Programming (ISPP) operations, the application of programming pulses to the Level 3 Cell (TLC) in response to the data bits stored in the TLC can be controlled differently. The data stored in the TLC can be divided into LSB data, CSB data, and MSB data. When programming LSB data, the number of programming pulses applied can be minimized, while the number of programming pulses applied when programming CSB data can be greater than that applied when programming LSB data. When programming MSB data, the number of programming pulses applied can be maximized.

[0127] In a three-level cell (TLC) memory device, each physical page can be divided into three logical pages: the LSB page, the CSB page, and the MSB page. The programming pulse applied to each page can be different. That is, different positive threshold voltages (V) can be triggered during the programming of the LSB, CSB, and MSB data. TH The distribution shifts. For example, the threshold voltage V of multiple non-volatile memory cells. TH The maximum number of cells can be moved during LSB page programming, and the threshold voltage V of multiple non-volatile memory cells is [not specified]. TH Minimal movement is achieved during MSB page programming. According to the implementation, the shortest latency and lowest power consumption are achieved when the number of programming pulses applied during LSB page programming is minimized. Conversely, increasing the number of programming pulses applied during MSB page programming increases latency and power consumption.

[0128] Figure 5 The programming voltage application operation and verification operation of the ISPP operation according to an embodiment of the present disclosure are illustrated.

[0129] Reference Figure 5 After performing the programming voltage application operation Pgm during ISPP operation, the memory device 150 performs a verification operation Ver corresponding to the programming voltage application operation Pgm. Each programming voltage application operation Pgm can adjust the threshold voltage V of the non-volatile memory cell. TH Increase. For example, each programming voltage applied to operation Pgm will increase the threshold voltage V of the non-volatile memory cell. TH Increase the first potential difference ΔV. After performing the programming voltage application operation Pgm, the threshold voltage V of the non-volatile memory cell... TH It can be compared with the verification voltage during the verification operation. When the threshold voltage V of the non-volatile memory cell... THIf the voltage drops below the verification voltage, another programming voltage application operation Pgm can be performed to add more electrons to the floating gate of the non-volatile memory cell. Thereafter, a verification operation Ver is performed in response to the corresponding programming voltage application operation Pgm. Repeated programming voltage application operations Pgm can be performed until the threshold voltage V of the non-volatile memory cell is reached. TH To achieve the target voltage (e.g., the verification voltage).

[0130] According to the implementation method, the number of repetitions of the programming voltage application operation Pgm and the verification operation Ver can vary depending on standby time or delay time, power consumption, accuracy, etc. When the threshold voltage V of the non-volatile memory cell is finely increased through the programming voltage application operation Pgm... TH This increases the accuracy of the programming voltage application operation. However, because more programming voltage applications can be performed, the latency and power consumption can be longer and greater. On the other hand, when the threshold voltage V of the non-volatile memory cell... TH By significantly increasing the value of each programming voltage application operation Pgm, the power consumption and operation time of the programming voltage application operation Pgm can be reduced and shortened. The operation time Δt of the programming voltage application operation Pgm and the verification operation Ver can be determined based on the target of each programming voltage application operation Pgm (e.g., threshold voltage V). TH (Changes)

[0131] Reference Figure 4 and Figure 5 In a memory device comprising a three-level non-volatile memory cell (TLC), the programming voltage application operation Pgm and the verification operation Ver can be performed differently depending on the purpose and process of programming data in the least significant bit (LSB), center significant bit (CSB), and most significant bit (MSB) of the memory cell. Figure 4 As an example, a memory device including a three-level non-volatile memory cell (TLC) has been described, but the above programming operations can also be applied to memory devices including a four-level non-volatile memory cell (QLC) for storing 4 bits of data, or a non-volatile memory cell capable of storing 5 or more bits of data.

[0132] According to the implementation, for each programming cycle during ISPP operation, the voltage level of the programming pulse applied to the non-volatile memory cell in the programming voltage application operation Pgm can be gradually increased according to a preset voltage ΔV. However, the voltage level of the verification pulse applied to the non-volatile memory cell in the verification operation Ver corresponding to the programming voltage application operation Pgm can be substantially the same (i.e., unchanged). In the verification operation Ver for each programming cycle, substantially the same verification pulse is applied to the non-volatile memory cell, but the time Δt for applying the verification pulse can be changed. Furthermore, when the verification operation is performed by reflecting noise generated according to the operating characteristics of the memory device 150, the memory device 150 can change or adjust the voltage level of the verification pulse.

[0133] Figure 6 Programming operations according to embodiments of this disclosure are illustrated. Figure 6 In this context, a non-volatile memory cell can store a single bit (1 bit) of data. The memory device 150 can be controlled such that the threshold voltage of the non-volatile memory cell changes to either an erase state E or a programmable state P. When referred to... Figure 4 and Figure 5 When performing the incremental step pulse programming (ISPP) operation as described, the threshold voltage of a non-volatile memory cell can be changed from the erase state E to the programming state P.

[0134] Reference Figure 5 Verification can be performed after the programming pulse is applied. (See reference...) Figure 6 The verification operation can use two verification voltages, Vvfp and Vvfym. Specifically, data programming operations supporting Dual Verification Programming (DPGM) can be performed using two verification voltage levels during the verification operation. By using verification operations with two different verification voltage levels, the degree to which a non-volatile memory cell is programmed in response to the next programming pulse can be adjusted. For example, memory device 150 can determine the amount of change in threshold voltage that may be caused by the next programming pulse.

[0135] According to the implementation, the verification voltage may include a pre-verification voltage Vvfyp and a main verification voltage Vvfym. Here, the main verification voltage Vvfym may be a verification voltage corresponding to the target state of the data programming operation, while the pre-verification voltage Vvfyp has a level lower than the main verification voltage Vvfym. In the verification operation, the pre-verification voltage Vvfyp can be used to check the extent to which the data programming operation is performed on the non-volatile memory cell. When the verification operation using the main verification voltage Vvfym detects that the threshold voltage of the non-volatile memory cell has changed to a programming state P, further programming of the non-volatile memory cell is not required via the next programming pulse. Alternatively, when the threshold voltage of the non-volatile memory cell is lower than the pre-verification voltage Vvfyp, the non-volatile memory cell can be programmed via the next programming pulse. If the threshold voltage of a non-volatile memory cell is within the range between the pre-verification voltage Vvfyp and the main verification voltage Vvfym, the non-volatile memory cell may be overprogrammed when it is properly programmed by the next programming pulse (e.g., the threshold voltage of the non-volatile memory cell may rise excessively, i.e., overprogramming). Therefore, the memory device 150 can reduce the amount of change in the threshold voltage. In this case, the memory device 150 can control or adjust the degree to which the non-volatile memory cell is programmed (e.g., the amount of change in the threshold voltage) when the next programming pulse is applied.

[0136] Reference Figure 6When multiple non-volatile memory cells are programmed using programming pulses, and then a verification operation is performed using a pre-verification voltage Vvfyp and a main verification voltage Vvfym, the multiple non-volatile memory cells can be in three different states MC1, MC2, and MC3. For a non-volatile memory cell in the first state MC1, which is lower than the pre-verification voltage Vvfyp, the memory device 150 can apply the next programming pulse to change or shift the threshold voltage of the corresponding memory cell by an amount corresponding to the next programming pulse. This general programming mode (PGM mode) can be referred to as the first programming mode. On the other hand, if a non-volatile memory cell has a third state MC3, which is higher than the main verification voltage Vvfym, the memory device 150 prevents the non-volatile memory cell from being further programmed by the next programming pulse because the threshold voltage of the non-volatile memory cell has already reached the programming state P. Here, prohibiting the non-volatile memory cell from being further programmed can be referred to as the programming prohibition mode. Furthermore, when the non-volatile memory cell is in the second state MC2, the threshold voltage of the non-volatile memory cell may rise excessively when programming the non-volatile memory cell in the first programming mode (PGM mode). Therefore, when the next programming pulse is applied to the non-volatile memory cell in the second programming mode (DPGM mode), the change in threshold voltage can be less than the amount caused in the first programming mode (PGM mode).

[0137] The degree to which a non-volatile memory cell is programmed (e.g., the amount of change in threshold voltage) can be determined based on the timing of the applied programming pulse, the number of programming pulses applied, and the potential difference between the programming pulses. Although a single programming pulse is applied to multiple non-volatile memory cells connected to a single word line, the memory device 150 can change or adjust the amount of threshold voltage change for each non-volatile memory cell connected to the single word line. To change the threshold voltage of the multiple non-volatile memory cells by different amounts, the memory device 150 can change or adjust the potential of the bit lines connected to the individual non-volatile memory cells connected to the single word line.

[0138] For example, during the period when a programming pulse is applied to a word line, a ground voltage can be applied to the bit line of a first memory cell connected to a threshold voltage in a first state MC1, a programming adjustment voltage higher than the ground voltage can be applied to the second bit line of a second memory cell connected to a threshold voltage in a second state MC2, and a programming disable voltage higher than the programming adjustment voltage can be applied to the third bit line of a third memory cell connected to a third memory cell having a third state MC3. In this case, a potential difference exists between the word line and the corresponding first to third bit lines. The smaller the potential difference between the word line and the bit line connected to the non-volatile memory cell, the smaller the change in the threshold voltage of the non-volatile memory cell caused by the programming pulse can be. Furthermore, when the potential difference between the word line and the bit line is lower than a preset level, the non-volatile memory cell will not be programmed. Because the potential difference of the second memory cell having the second state MC2 is smaller than the potential difference of the first memory cell having the first state MC1, the degree to which the second memory cell is programmed by the next programming pulse can be less than the degree to which the first memory cell is programmed. Furthermore, when the next programming pulse is applied to the third memory cell and the potential difference between the programming pulse and the programming inhibit voltage applied to the third memory cell with the third state MC3 is lower than a preset level, the third memory cell with the third state MC3 may not be further programmed even though the next programming pulse has been applied.

[0139] Reference Figure 6 The programming mode can be determined based on the verification result corresponding to the programming operation performed on the non-volatile memory cell. The programming mode can include a first programming mode (PGM mode), a second programming mode (DPGM mode), and a third programming mode (PGM disable mode). For example, a successful verification can indicate that the non-volatile memory cell is read as a cutoff cell in response to the verification voltage. A failed verification can indicate that the non-volatile memory cell is read as a conducting cell in response to the verification voltage. In other words, if the threshold voltage of the non-volatile memory cell is lower than the verification voltage, the non-volatile memory cell is read as a conducting cell. However, if the threshold voltage is equal to or higher than the verification voltage, the non-volatile memory cell is read as a cutoff cell.

[0140] Reference Figure 6In the first programming mode (PGM mode), a non-volatile memory cell can be read as an active cell by both the pre-verification voltage Vvfyp and the main verification voltage Vvfym. In the second programming mode (DPGM mode), another non-volatile memory cell can be read as a deactivated cell by the pre-verification voltage Vvfyp and as an active cell by the main verification voltage Vvfym. In the third programming mode (PGM disabled mode), another non-volatile memory cell can be read as a deactivated cell by both the pre-verification voltage Vvfyp and the main verification voltage Vvfym. Furthermore, because the level of the pre-verification voltage Vvfyp is lower than the level of the main verification voltage Vvfym, there is no situation where a non-volatile memory cell is read as an active cell by the pre-verification voltage Vvfyp but as a deactivated cell by the main verification voltage Vvfym.

[0141] Figure 7 The discharge of the string and bit lines during programming operations according to embodiments of the present disclosure is illustrated.

[0142] Reference Figure 7 The memory device 150 may include a string 340 having a plurality of non-volatile memory cells. The string 340 may include: a first transistor connected to a bit line BL for operation in response to a first control voltage applied via a drain select line DSL; a second transistor connected to a source line SL for operation in response to a second control voltage applied via a string select line SSL; and at least one non-volatile memory cell connected between the first and second transistors. The at least one non-volatile memory cell may be programmed by a programming pulse applied via a word line. Figure 7 The source line SL shown can correspond to the reference. Figure 1 The described common source line CSL, the first transistor may correspond to the drain selection transistor DST, and the second transistor may correspond to the string selection transistor SST. According to the implementation, the first transistor and / or the second transistor may be individually implemented as multiple transistors connected in series with each other.

[0143] As the storage capacity of the memory device 150 increases, the number of non-volatile memory cells connected in series between the first transistor and the second transistor can be increased. (Refer to...) Figure 7 Multiple bits of data can be programmed sequentially in a predetermined order (PGM order) from the non-volatile memory cell connected to the first transistor to another non-volatile memory cell connected to the second transistor. The multiple non-volatile memory cells included in string 340 can be divided into programming states (P, see...) Figure 6 The programmed non-volatile memory cell 342 and the data therein which are erased to maintain an erased state (E, see...) Figure 6The erased nonvolatile memory cell 344. When the next programming operation is performed, a programming pulse can be applied to the selected word line Sel_WL connected to the nonvolatile memory cell located next to the programmed nonvolatile memory cell 342.

[0144] A programming pulse can be applied to the selected word line Sel_WL to selectively program data into the non-volatile memory cell connected to the selected word line Sel_WL. After applying the programming pulse, any remaining charge in string 340 needs to be removed to prepare for either a verification operation corresponding to the programming pulse or a next programming operation corresponding to the next programming pulse. To discharge the bit line BL connected to string 340, a first transistor operated by a first control voltage applied via the drain select line DSL can be turned on. When a programming pulse is applied to the selected word line Sel_WL, a pass voltage Vpass can be applied to the word line connected to the programmed non-volatile memory cell 342 to reduce resistance. As the resistance of the channels (DSL channel, MWL channel) decreases, rapid discharge can occur in the channels (DSL channel, MWL channel) of string 340.

[0145] As programming operations are repeatedly executed, the threshold voltage of the first transistor, operated by the first control voltage applied via the drain select line DSL, can continue to increase. In this case, the first control voltage applied via the drain select line DSL can be changed to be higher than a preset voltage to turn on the first transistor but reduce its resistance, allowing the string 340 to discharge more quickly. When the first control voltage applied via the drain select line DSL for discharge is an overvoltage drive (OVD), the memory device 150 can execute faster than when the first control voltage is not overvoltage driven. Figure 6 The programming pulses described herein correspond to the first, second, or third programming modes for programming the memory cells. This process can improve the programming speed of the memory device 150.

[0146] exist Figure 7 In response to the operation of the first transistor operated by a first control voltage applied via the drain select line DSL during data programming operations, there are three states: a first state (1) in which charge accumulates in the channel of series 340; a second state (2) in which undischarged charge remains in the channel of series 340; and a third state (3) in which charge cannot be discharged when the channel of series 340 is floating. (Refer to...) Figure 8 A more detailed description is given of how these three states occur during data programming operations.

[0147] Figure 8An example is illustrated of a programming operation that can be modified based on the discharge of the serial and bit lines according to an embodiment of the present disclosure. Specifically, Figure 8 An example is illustrated of the discharge of the channel of series 340 through a first transistor during a data programming operation, either before or simultaneously with the application of a programming pulse. This first transistor is operated by a first control voltage applied via the drain select line DSL.

[0148] Reference Figure 8 When a programming pulse is applied to the selected word line Sel_WL, a pass voltage can be applied to the unselected word line Unsel_WL. Before applying the programming pulse, a first control voltage and a second control voltage can be applied separately to the drain select line DSL and the serial select line SSL. Subsequently, when the page buffer control signal PBSENSE is activated, the potential of each bit line BL can be maintained differently. (See reference...) Figure 6 As described, the page buffer control signal PBSENSE can be activated in response to one of three programming modes. For example, when the programming mode for the non-volatile memory cell is the first programming mode (PGM mode, general PGM mode, MPGM), the bit line connected to the non-volatile memory cell remains at ground voltage. In the case of the third programming mode (PGM disable mode), the bit line potential can be increased by a programming disable voltage. When the programming mode for the non-volatile memory cell is the second mode (DPGM), the bit line potential can increase with a time difference. To reduce the extent of data programming in the non-volatile memory cell, the bit line potential is changed simultaneously with the application of the programming pulse. After the programming pulse is applied, the second control voltage applied via the serial select line SSL can be disabled.

[0149] When a data programming operation is performed on the plurality of non-volatile memory cells 342 included in string 340, the threshold voltage of the first transistor operated by the first control voltage applied via the drain select line DSL can be increased. When the level of the through voltage applied to the unselected word line Unsel_WL after the programming pulse is applied exceeds a certain potential (e.g., 4V), the residual charge in the channels of string 340 can be discharged. Because discharge does not occur until the through voltage level exceeds the certain potential, the potential of the channels (DPGM operating channel, MPGM operating channel) in string 340 can continue to increase. Discharging the potential of the channels (DPGM operating channel, MPGM operating channel) in string 340 may be necessary to clearly distinguish the programming degree of the first programming mode and the second programming mode (e.g., the amount of change in the threshold voltage of the first programming mode and the second programming mode) from each other. However, since discharge will not occur until the potential of the voltage exceeds a certain level, it may be difficult to discharge the potential of the channels (DPGM operating channel, MPGM operating channel) in series 340 when the threshold voltage of the first transistor increases, which may result in insufficient time for discharging the potential.

[0150] exist Figure 8 This document describes various cases (α, β, γ, δ, ε) based on the discharge rate of the channel potential (DPGM operating channel, MPGM operating channel) in string 340 as examples. In the first case (α), when a non-volatile memory cell is programmed in the first programming mode, the potential of the channel (MPGM operating channel) in string 340 including the corresponding non-volatile memory cell discharges slowly. However, in the second case (β), when a non-volatile memory cell is programmed in the first programming mode, the potential of the channel (MPGM operating channel) in string 340 including the corresponding non-volatile memory cell discharges rapidly. Furthermore, when a non-volatile memory cell is programmed in the second programming mode, the potential of the channel (DPGM operating channel) in string 340 including that non-volatile memory cell discharges rapidly in the third case (γ) or slowly in the fourth and fifth cases (δ, ε). Although it may be necessary to discharge the channel potential (DPGM operating channel, MPGM operating channel) so that the channel potential corresponds to the ground voltage, the memory cell can be successfully programmed in the second programming mode when the channel potential is lower than the potential of the bit line BL raised by the page buffer control signal PBSENSE.

[0151] In the following situations, it may be difficult to adjust or change the potential of bit line BL to control the degree to which a non-volatile memory cell is programmed (e.g., the amount of change in threshold voltage): First case (α): when the channel potential of string 340 (MPGM operating channel) is slowly discharged while programming the memory cell in a first programming mode; fourth case (δ): when the channel potential of string 340 (DPGM operating channel) is slowly discharged while programming the memory cell in a second programming mode; or fifth case (ε): when the channel of string 340 (DPGM operating channel) is floated by the threshold voltage of the transistor connected to the drain select line DSL. When the potential of bit line BL is not sufficiently discharged, the degree to which the non-volatile memory cell is programmed is below a preset level or a preset amount. Even if the non-volatile memory cell is actually in the first or second programming mode, it may be incorrectly identified as being in a third programming mode (e.g., PGM disabled mode). In this situation, because the non-volatile memory cell is not fully programmed, the memory device 150 can determine that the corresponding non-volatile memory cell is a bad memory cell even if the corresponding non-volatile memory cell is good.

[0152] According to embodiments of this disclosure, a discharge problem can be solved when the memory device 150 is overdriven by the level of the first control voltage applied via the drain select line DSL. Even if the threshold voltage of the first transistor, which operates via the first control voltage applied via the drain select line DSL, may unintentionally increase during programming operations performed on the plurality of non-volatile memory cells 342, over-driving of the first control voltage can prevent slow discharge. However, when the potential difference between the first control voltage and the increased threshold voltage of the first transistor is lower than the potential of the bit line BL, the potential of the bit line BL connected to the memory cell to be programmed in the second programming mode may increase before the channel of the string 340 is fully discharged. In this case, as referred to... Figure 7 As described, because the channel is in a floating state, it may not be possible to successfully program the memory cell in the second programming mode.

[0153] As the storage capacity of the memory device 150 increases, the number of series-connected non-volatile memory cells included in the string 340 can increase. With a larger number of non-volatile memory cells, the number of programming operations performed in the string 340 can be greater. Therefore, it is reasonable for the threshold voltage of the first transistor included in the string 340 to increase according to the number of programming operations. To improve programming operations, the memory device 150 according to embodiments of the present disclosure is capable of controlling or changing the level of the first control voltage applied via the drain select line DSL in response to the number of programming pulses applied from the string 340.

[0154] Figure 9 A method for controlling the discharge of serial and bit lines according to an embodiment of the present disclosure is illustrated.

[0155] Specifically, Figure 9 The data programming operation for a non-volatile memory cell connected to the selected word line Sel_WL is described, including the resistance changes of the programmed non-volatile memory cell 342 in the string and the resistance changes of the first transistor. Here, the resistance change of the programmed non-volatile memory cell 342 can vary based on the level of the through voltage Vpass applied to the multiple word lines MWL connected to the programmed non-volatile memory cell 342. The resistance change of the first transistor can vary based on the level of the first control voltage applied via the drain select line DSL.

[0156] Reference Figure 9 As the voltage level increases, the resistance of the programmed non-volatile memory cell 342 can decrease. Furthermore, as the level of the first control voltage applied via the drain select line DSL increases, the resistance of the first transistor can decrease. Therefore, when the voltage level applied via the pull-in voltage to at least one unselected word line of the programmed non-volatile memory cell increases, the charge in the channel of string 340 can be sufficiently discharged during a preset operating margin period. During data programming operations, the preset operating margin for discharge can be reduced, allowing for faster programming operations.

[0157] Figure 10 An example of a programming operation based on a voltage level change according to an embodiment of the present disclosure is illustrated.

[0158] Reference Figure 10 The memory device 150 can adjust or change the level of the pass voltage to rapidly discharge any remaining charge in the channel of the string 340. According to an embodiment, the memory device 150 can apply pass voltages of different levels to the string 340 through different word lines.

[0159] Reference Figure 9 and Figure 10String 340 may include non-volatile memory cells that can be programmed with data according to the data programming operation. The non-volatile memory cells may be connected to the selected word line Sel_WL. String 340 may include two groups. One group includes at least one non-volatile memory cell 342 that has been programmed with data, while the other group includes at least one non-volatile memory cell 344 whose data has been erased (i.e., at least one non-volatile memory cell 344 is in an erased state). In the case of first programming data into string 340, string 340 may not include the non-volatile memory cell 342 that has been programmed with data. In another case of last programming data into string 340, string 340 may not include the non-volatile memory cell 344 that is in an erased state. Different levels of pass voltage Vpass can be applied to the first word line (Sel upper side Unsel_WL, programmed WL) connected to the non-volatile memory cell 342 that has been programmed with data and the second word line (Sel lower side Unsel_WL, erased WL) connected to the non-volatile memory cell 344 that has not been programmed with data.

[0160] During data programming operations, when a programming pulse is applied to the selected word line Sel_WL, a pass voltage Vpass can be applied to the unselected word lines (e.g., the first word line and the second word line). For example, the memory device 150 can apply a pass voltage Vpass having a preset first level to the second word line. On the other hand, the memory device 150 can apply a pass voltage Vpass having a second level higher than the first level to the first word line. (Refer to...) Figure 10 The pass voltage Vpass applied to the first word line may have a second level higher than the first level in segment A. Here, segment A is the amount of time or time gap between the first timing point and the second timing point. The first timing point is the time when a programming pulse and pass voltage are applied to the selected word line and the unselected word line, and the pass voltage rises to the first level. The second timing point is the time when the potential of the bit line increases by the activated page buffer control signal PBSENSE to reduce the degree of rise of the threshold voltage of the non-volatile memory cell connected to the selected word line and in the second programming mode (DPGM). Segment A can be considered as the marginal time spent discharging the channel in string 340. After segment A, data can be programmed to the non-volatile memory cell connected to the selected word line according to either the first programming mode MPGM or the second programming mode DPGM.

[0161] According to an embodiment, as the number of programming pulses applied increases, the memory device 150 can increase the level of the pass voltage (VPASS increases). Furthermore, the memory device 150 can adjust the level of the pass voltage according to the operating environment (e.g., the internal temperature of the memory device 150). For example, according to an embodiment, the range of a second level higher than a first level for the pass voltage Vpass applied to the first word line can be determined based on the operating environment (e.g., temperature). Additionally, the maximum value to which the second level of the pass voltage Vpass can be increased can be determined in response to the operating characteristics of the non-volatile memory cells included in the memory device 150.

[0162] According to the implementation method, refer to Figure 10 As the number of programming pulses applied increases, the difference between the first level and the second level of the pass voltage Vpass applied to the first word line can decrease. Because the second level is determined based on the operating environment of the memory device 150 (e.g., temperature), the memory device 150 may increase the first level instead of changing or adjusting the second level as the number of programming pulses applied increases.

[0163] Figure 11 An embodiment based on this disclosure is illustrated. Figure 10 The operating state of the voltage is shown in the figure.

[0164] Reference Figure 11 The multiple non-volatile memory cells included in a string in memory device 150 can be programmed with data in the order of non-volatile memory cells connected to the drain select line (DSL) to those connected to the string select line (SSL). Before any non-volatile memory cells are programmed, the string included in the free block may not have any programmed non-volatile memory cells. After data is programmed into the first non-volatile memory cell connected to the drain select line (DSL), the first non-volatile memory cell is in a programmed state (PGMed), but the other non-volatile memory cells in the string may be in an erased state (ERSed).

[0165] like Figure 10 As described, the word line Sel_WL can be selected to program the second non-volatile memory unit of the string. (See reference...) Figure 9While the second non-volatile memory cell is being programmed, as the level of the pass voltage Vpass applied to the unselected word line Unsel_WL connected to the first non-volatile memory cell with programmed data increases, the resistance of the programmed non-volatile memory cell 342 in the programmed state PGMed can decrease. This operation can accelerate the discharge of residual charge in the channel in the string, allowing the channel voltage level to drop from the second non-volatile memory cell connected to the selected word line Sel_WL where the programming pulse is applied to the bit line BL. Therefore, referring to... Figure 8 Before performing programming operations on memory cells in the second programming mode (DPGM), the potential of the channels in the string can be quickly reduced. This operation can improve the speed of data programming operations.

[0166] Figure 12 A method for operating a memory device according to an embodiment of the present disclosure is illustrated.

[0167] Reference Figure 12 When the memory device 150 receives a programming command and programming data transmitted from the controller 130, a data programming operation can begin (operation 710). When it is determined that the programming data has been programmed into the non-volatile memory cell ("Yes" in operation 722), the data programming operation can be terminated (operation 726). Here, the data programming operation can be performed via an ISPP operation. Multiple programming pulses can be applied to program data into the non-volatile memory cell, and a verification operation can be performed after the programming pulses are applied. The programming operation of applying programming pulses and the verification operation corresponding to the applied programming pulses can be considered a single cycle or period.

[0168] When a data programming operation begins, the memory device 150 can determine, in response to the operating environment (e.g., temperature), how much higher than a preset level to drive a pass voltage Vpass applied to at least one unselected word line (operation 712). For example, this can be achieved by referencing a reference... Figure 13 The described table determines how to drive the memory device 150 to a level higher than the initial value of the voltage Vpass and / or a preset level (e.g., a first level) (e.g., a second level).

[0169] When memory device 150 determines that the second level (OVD level) of the pass voltage Vpass is greater than the first level Vpass ("Yes" in operation 714), memory device 150 may activate the circuitry for overdriving the pass voltage Vpass (operation 718). However, if memory device 150 determines that the second level (OVD level) of the pass voltage Vpass is equal to or less than the first level Vpass ("No" in operation 714), memory device 150 may not activate the circuitry for overdriving the pass voltage Vpass (operation 716). Through these processes, as described in reference... Figure 10 As described, the memory device 150 can change and adjust the level of the voltage Vpass.

[0170] When the level of the pass voltage Vpass applied to at least one unselected word line is determined (e.g., whether it is an overdrive pass voltage Vpass) (operation 718 or 716), the memory device 150 can perform a programming operation that applies a programming pulse to a non-volatile memory cell coupled to the selected word line and a verification operation corresponding to the programming pulse (operation 720). For example, it can be based on a reference Figures 3 to 6 The program selects one of the multiple programming modes and performs an ISPP operation to apply a programming pulse and perform a verification operation corresponding to the programming pulse.

[0171] After performing a programming operation that applies a programming pulse, if the result of a verification operation corresponding to the programming pulse determines that data has been programmed into the non-volatile memory cell ("Yes" in operation 722), the memory device 150 may terminate the data programming operation (operation 726). Conversely, if the result of a verification operation performed after performing the programming operation that applies the programming pulse determines that data has not yet been programmed into the non-volatile memory cell ("No" in operation 722), the memory device 150 may perform the next programming operation. See also... Figure 10 The first level of the pass voltage Vpass corresponding to the next programming pulse can be increased (operation 724). According to an embodiment, the first level of the pass voltage Vpass can be gradually increased each time in response to the number of programming pulses applied, or it can be increased in a stepwise mode (e.g., increased once every predetermined number of times). Thereafter, the memory device 150 can compare the second level (OVD level) of the pass voltage Vpass with the first level Vpass (operation 714).

[0172] Figure 13 A table for determining the level of a voltage is illustrated according to an embodiment of the present disclosure. Figure 13 Some of the values ​​shown may indicate ratios rather than absolute values. Because... Figure 13The values ​​shown can be changed according to the characteristics of the memory device 150, so the embodiments of this disclosure are not subject to change. Figure 13 The numerical limits shown are as follows.

[0173] According to the implementation method, refer to Figure 1 The described control circuit 180 or voltage supply circuit 170 can be based on reference Figure 13 The table described determines the level of the pass voltage Vpass applied via at least one unselected word line Unsel_WL.

[0174] Reference Figure 13 The table can store various second levels of the pass voltage Vpass. For example, the pass voltage Vpass applied via the unselected word line Unsel_WL in string 340 can be 7.5V at -40 degrees Celsius and 7.1V at 40 degrees Celsius. Furthermore, according to an embodiment, the table can store increments of the pass voltage Vpass based on the operating environment of the memory device 150 (e.g., internal temperature) (e.g., the difference between the first and second levels), or the ratio used for overvoltage drive pass voltage Vpass.

[0175] Reference Figure 12 and Figure 13 Before the memory device 150 applies a programming pulse to the selected word line to program data into the non-volatile memory cell connected to the selected word line and in a first programming mode or a second programming mode, the memory device 150 may increase the level of the pass voltage Vpass applied via the unselected word line Unsel_WL, thereby accelerating the discharge rate of the charge in the channel of string 340. In response to the programming pulse supplied via the selected word line Sel_WL in string 340, the memory device 150 can precisely control the degree to which the non-volatile memory cell in the first programming mode or the second programming mode is programmed in response to the programming pulse. (See reference...) Figure 8 The discussion focuses on how to more accurately perform programming operations on non-volatile memory cells in both the first and second programming modes.

[0176] Figure 14An embodiment of a method for operating a memory device is illustrated, the method may include: starting a programming operation (810), checking information about the setup time according to the current cycle of the applied programming pulse during a data programming operation (812), setting or changing the potential of the bit line BL based on a programming mode (e.g., a second programming mode, DPGM) (814), applying a programming pulse to program data into a non-volatile memory cell (816), verifying the programming result corresponding to the programming pulse (818), determining whether to terminate the data programming operation based on the verification result (820), and terminating the data programming operation (822) when it is determined that the data has been programmed ("yes" in operation 820).

[0177] The memory device 150 can store data or information in registers or the like regarding adjustments or changes to the setup time during programming operations. (Return to reference) Figure 10 The setup time indicates the period of operation between the timing of applying the programming pulse and the voltage pass, and the timing of adjusting or changing the potential of the bit line. See below for further details. Figure 16 Describe information about the creation time.

[0178] Return to reference Figure 5 Data programming can be performed by applying multiple programming pulses to a non-volatile memory cell. After applying the programming pulses, the data programmed into the non-volatile memory cell in response to the programming pulses can be verified. (Return to reference) Figure 6 Based on the verification results, memory device 150 can determine the programming mode to be performed on the non-volatile memory cell in the next cycle for which the next programming pulse is applied. (Return to reference) Figure 8 When the programming cycle begins, the bit line BL is maintained at the ground voltage used to program data into the non-volatile memory cell (e.g., increasing the threshold voltage of the non-volatile memory cell). However, if data is not programmed into the non-volatile memory cell (e.g., there is no need to increase the threshold voltage of the non-volatile memory cell), the memory device 150 can execute a programming disable mode by raising the potential of the bit line BL to a preset level.

[0179] The memory device 150 can execute two different programming modes when increasing the threshold voltage of the non-volatile memory cell. In the first programming mode (PGM, MPGM), the memory device 150 can maintain the potential of the bit line BL at ground voltage. On the other hand, in the second programming mode (DPGM), the memory device 150 can adjust or change the potential of the bit line BL at the timing of the applied programming pulse.

[0180] According to an embodiment, the memory device 150 may, in response to a programming cycle, check a lookup table (LUT) (812) storing setup times for adjusting and changing the potentials of bit lines connected to non-volatile memory cells, and, in response to the setup time corresponding to the programming cycle, change or adjust the potential of the bit line BL corresponding to the non-volatile memory cell to which the second programming mode DPGM is to be executed (814). After determining the setup time of the second programming mode DPGM (814), the memory device 150 may apply a programming pulse (816) to the non-volatile memory cell.

[0181] After performing the programming operation corresponding to the programming pulse (816), the memory device 150 can perform the verification operation (818) corresponding to the programming pulse. According to an embodiment, this can be based on a reference... Figures 3 to 6 The description includes various programming modes and ISPP operations to perform programming and verification operations corresponding to programming pulses.

[0182] After applying a programming pulse to perform a programming operation, if the result of a verification operation determines that data has been programmed into a non-volatile memory cell ("Yes" in operation 820), the memory device 150 may terminate the data programming operation (822). Conversely, if the result of a verification operation performed after the programming operation determines that data has not yet been programmed into a non-volatile memory cell ("No" in operation 820), the memory device 150 may return to the next programming cycle. After each programming cycle, the memory device 150 may, in response to the programming cycle, check a lookup table (812) containing setup times for adjusting and changing the potentials of the bit lines connected to the non-volatile memory cells.

[0183] Figure 15 An embodiment of a method for operating a memory device is illustrated, which may include: starting a programming operation (610), selecting a bit line BL (612) whose potential is to be changed in response to a programming mode (e.g., a second programming mode, DPGM), applying a programming pulse to a non-volatile memory cell to program data (614), verifying the programming result (616), determining whether to terminate the programming operation based on the verification result (618), and terminating the programming operation (620) when it is determined that data has been programmed in the non-volatile memory cell ("yes" in operation 618).

[0184] In some implementations, if it is determined that the non-volatile memory cell data has not yet been programmed (No in operation 618), the setup time used to adjust or change the potential of the bit line connected to the non-volatile memory cell can be reduced by a preset time (622). After adjusting the setup time (622), the memory device 150 can check whether the adjusted setup time is greater than the minimum time min_A (624). Return to reference Figure 8 The setup time for changing the bit line potential to execute the second programming mode DPGM should not be less than the minimum time required to discharge the charge in the channel of string 340. If the minimum time required to discharge the charge in the channel of string 340 cannot be guaranteed, the bit line potential may not be sufficiently reduced, so that data may not be adequately programmed into the non-volatile memory cells as scheduled or planned.

[0185] If the adjusted setup time is greater than the minimum time min_A ("Yes" in operation 624), the memory device 150 may change the potential of the bit line BL corresponding to the programming mode (e.g., the second programming mode, DPGM) (612). If the adjusted setup time is equal to or less than the minimum time min_A ("No" in operation 624), the memory device 150 may determine the adjusted setup time as the minimum time min_A (626). After setting the adjusted setup time to the minimum time min_A (626), the memory device 150 may change the potential of the bit line BL corresponding to the programming mode (e.g., the second programming mode, DPGM) (612).

[0186] Reference Figure 14 and Figure 15 Before applying programming pulses to non-volatile memory cells, memory device 150 can determine the setup time for adjusting the potential of bit line BL for the second programming mode DPGM. According to an embodiment, the setup time can be set to a value corresponding to the operating environment of memory device 150 and the number of programming pulses applied (programming cycles). Furthermore, the initial value of the setup time can be decreased when a predetermined number of programming pulses are applied, or whenever a programming pulse is applied. According to an embodiment, the data or information stored in the registers of memory device 150 can be set or established differently based on the characteristics of memory device 150. For example, memory device 150 can store the initial value of the setup time and a changed value that decreases in response to at least one programming cycle.

[0187] Figure 16 An example illustrating the relationship between setup time, programming loop, and operating environment for changing the potential of a bit line in order to execute the second programming mode (DPGM). Figure 16 The values ​​shown are merely examples and are not intended to limit the implementation to these specific values.

[0188] Reference Figure 16 The setup time can be set in response to the programming cycle and operating environment (e.g., temperature) of the memory device 150. For example, the setup time for controlling programming operations can be set in response to the characteristics of the non-volatile memory cells included in the memory device 150.

[0189] According to the implementation, as the programming cycle increases, the setup time for changing the bit line potential to execute the second programming mode DPGM can be shortened. Furthermore, as the operating temperature of the memory device 150 increases, the setup time for changing the bit line potential to execute the second programming mode DPGM can be shortened. The memory device 150 can activate the page buffer signal PBSENSE in response to the setup time.

[0190] One or more embodiments include a semiconductor device that can divide non-volatile memory cells into three groups—subject to normal programming (MPGM), dual-verified programming (DPGM), and programming disabled (PGM disabled)—in response to programming verification results during incremental step pulse programming (ISPP) operations. After determining the applied programming pulse based on the programming state, the semiconductor device can change or adjust the control voltage level applied to the bit line select line or drain select line (DSL) according to the programming pulse and the operating environment, thereby reducing the time spent on bit line or channel discharge.

[0191] One or more additional embodiments include a semiconductor device capable of changing or adjusting the setup time for adjusting the potential of the bit lines during incremental step pulse programming (ISPP) operation based on a programming mode determined in response to programming verification results. After determining the programming pulse applied to a non-volatile memory cell, the programming operation speed can be improved by adjusting or changing the setup time to adjust the potential of the bit lines.

[0192] One or more additional embodiments include a semiconductor device capable of determining, during incremental step pulse programming (ISPP) operation, which programming mode—normal programming (MPGM), dual-verification programming (DPGM), or programming-inhibited (PGM-inhibited)—to program data into a non-volatile memory cell in response to a programming verification result. To perform dual-verification programming on the non-volatile memory cell, the semiconductor device can reduce the setup time for adjusting the potential of the bit line connected to the non-volatile memory cell after applying a programming pulse to the word line connected to the non-volatile memory cell, based on the number of programming pulses applied and the operating environment of the semiconductor device.

[0193] While the teachings have been illustrated and described with reference to specific embodiments, it will be apparent to those skilled in the art, based on this disclosure, that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined in the appended claims. Furthermore, embodiments can be combined to form additional embodiments.

[0194] Cross-reference to related applications

[0195] This patent application claims priority to Korean Patent Application No. 10-2021-0098925, filed on July 28, 2021, and Korean Patent Application No. 10-2021-0102602, filed on August 4, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: A memory structure comprising at least one non-volatile memory cell capable of storing multiple bits of data; as well as The control device: Programming verification is performed after the first programming pulse is applied to the at least one non-volatile memory cell. Based on the results of the programming verification, the programming mode of the at least one non-volatile memory cell is determined, and According to the programming mode, the level of the through voltage applied to another non-volatile memory cell connected to the at least one non-volatile memory cell is changed from a first level to a second level higher than the first level, or the setup time for changing the potential of the bit line connected to the at least one non-volatile memory cell is changed. The execution, determination, and change are performed during a data programming operation that applies multiple programming pulses to the at least one non-volatile memory cell to program multi-bit data. The setup time becomes shorter as the number of programming pulses applied to the at least one non-volatile memory cell during the data programming operation increases.

2. The memory device according to claim 1, wherein, The memory structure includes: A first transistor is connected between the at least one non-volatile memory cell and a bit line and operates in response to a first control voltage applied to the drain select line DSL; A second transistor, connected between the at least one non-volatile memory cell and the source line and operating in response to a second control voltage applied to the string select line SSL; and The at least one non-volatile memory cell is connected between the first transistor and the second transistor and stores the multi-bit data through the plurality of programming pulses.

3. The memory device according to claim 2, in, The at least one non-volatile memory cell comprises N transistors connected in series between the first transistor and the second transistor, and The control device programs the multi-bit data into the at least one non-volatile memory cell in the order of the transistor connected to the first transistor to the other transistor connected to the second transistor among the N transistors.

4. The memory device according to claim 1, in, The control device also determines the level of the through voltage in response to the temperature of the memory device, and The control device changes the level of the through voltage from the first level to the second level by executing an overvoltage drive.

5. The memory device according to claim 4, wherein, The control device also maintains the second level until the potential of the bit line connected to the at least one non-volatile memory cell changes according to the programming mode determined based on the results of the programming verification.

6. The memory device according to claim 1, wherein, The control device also applies a pass voltage having the first level to at least one other non-volatile memory cell in the erase state, and applies a pass voltage having the second level to at least one other non-volatile memory cell that has been programmed.

7. The memory device according to claim 1, wherein, The control device also increases the level of the through voltage in response to the number of programming pulses applied to the at least one non-volatile memory cell during the data programming operation, and The setup time decreases as the temperature of the memory device increases.

8. The memory device according to claim 1, in, The control device determines the programming mode corresponding to the second programming pulse as one of the first mode, the second mode, and the third mode. In the first mode, the control device also applies the second programming pulse to the at least one non-volatile memory cell to change or adjust the threshold voltage of the at least one non-volatile memory cell by a first amount, which is equal to or greater than the amount caused by the first programming pulse. In the second mode, the control device further applies the second programming pulse to change or adjust the threshold voltage of the at least one non-volatile memory cell by a second amount, which is less than the amount caused by the first programming pulse. In the third mode, the control device also applies the second programming pulse to at least one non-volatile memory cell that is prohibited from changing its threshold voltage.

9. The memory device according to claim 8, wherein, When the programming mode is the second mode, the control device changes the level of the applied voltage, and The control device determines the setup time corresponding to each of the first mode, the second mode, and the third mode.

10. A memory system comprising: A memory device comprising a plurality of non-volatile memory cells; as well as The controller receives write commands and write data from the host, determines the storage location of the write data in the memory device, and transmits the write data to the memory device. Wherein, the memory device: Determine the programming mode that causes a change in the threshold voltage of the plurality of non-volatile memory cells, and According to the programming mode, the level of the through voltage applied to other non-volatile memory cells connected to the plurality of non-volatile memory cells is changed from a first level to a second level higher than the first level, or the setup time for changing the potential of the bit line connected to at least one of the plurality of non-volatile memory cells is changed. The determination and the change are performed during a data programming operation that applies multiple programming pulses to the plurality of non-volatile memory cells to program the written data. The setup time becomes shorter as the number of programming pulses applied to the plurality of non-volatile memory cells during the data programming operation increases.

11. The memory system according to claim 10, in, The plurality of non-volatile memory cells in the memory device are interconnected via a single word line. Each of the plurality of non-volatile memory cells is connected to a different bit line, and The memory device further includes a string, which includes: A first transistor operates in response to a first control voltage applied to the drain select line DSL; The second transistor operates in response to a second control voltage applied to the string select line SSL; One of the plurality of non-volatile memory cells; and The other non-volatile memory cells are connected in series between the first transistor and the second transistor to the one non-volatile memory cell, and The memory device programs multiple bits of data into the string in the order of memory cells connected to the first transistor connected to the string and another memory cell connected to the second transistor connected to the string.

12. The memory system according to claim 11, wherein, The memory device further applies the pass voltage having the first level to at least one non-volatile memory cell in an erased state located between the second transistor and the one non-volatile memory cell of the plurality of non-volatile memory cells, and applies the pass voltage having the second level to at least one non-volatile memory cell that has been programmed located between the first transistor and the one non-volatile memory cell of the plurality of non-volatile memory cells.

13. The memory system according to claim 11, in, The memory device also determines the level of the through voltage in response to the temperature of the memory device, and The memory device changes the first level to the second level by performing an overvoltage drive.

14. The memory system according to claim 13, wherein, The memory device also maintains the second level until the potential of the bit line of one of the plurality of nonvolatile memory cells changes according to the programming mode determined based on the results of programming verification.

15. The memory system according to claim 10, wherein, The memory device also applies a pass voltage having the first level to at least one other non-volatile memory cell in an erased state, and applies the pass voltage having the second level to at least one other non-volatile memory cell that has been programmed.

16. The memory system according to claim 11, wherein, The memory device also increases the level of the through voltage in response to the number of programming pulses applied to one of the plurality of non-volatile memory cells during the data programming operation, and The setup time decreases as the temperature of the memory device increases.

17. The memory system according to claim 16, wherein, When the programming mode is the second mode, the memory device changes the level of the passed voltage, and The memory device determines the setup time corresponding to each of the first mode, the second mode, and the third mode.

18. A method for operating a memory device, the method comprising the steps of: A first programming pulse is applied via word lines to program multiple bits of data into multiple non-volatile memory cells; Verify the programming status of the plurality of non-volatile memory cells corresponding to the first programming pulse; For a second programming pulse to be applied to the word line, determine the programming mode that causes a change in the threshold voltage of the plurality of non-volatile memory cells; Before controlling the potential of the bit line according to the programming mode while applying the second programming pulse to the word line, the level of the pass voltage applied to other non-volatile memory cells connected to the plurality of non-volatile memory cells is increased from a first level to a second level higher than the first level according to the programming mode, or the setup time for changing the potential of the bit line connected to at least one of the plurality of non-volatile memory cells is adjusted according to the programming mode. The setup time becomes shorter as the total number of programming pulses applied to the plurality of non-volatile memory cells during data programming operations increases.

Images