Fast bit erasure for upper tail tightening of threshold voltage distribution

Abstract

This application relates to fast bit erase for upper tail tightening of threshold voltage distribution. A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, and a word line coupled with the first pillar and the second pillar. Control logic is to cause the word line to discharge after a program pulse is applied to a selected word line, cause a supply voltage to be applied to the second data line to cause a voltage float of the second pillar, cause a ground voltage to be applied to the first data line to inhibit soft erase through the first pillar, cause non-selected word lines to be charged to raise a pass voltage in a memory cell coupled with the second pillar, and cause one of the ground voltage or a negative voltage to be applied to the selected word line to increase a soft erase voltage between a pass of a memory cell coupled with the second pillar and the selected word line, causing threshold voltages stored in the memory cell to be erased.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to fast bit erasure for upper-tail tightening of threshold voltage distribution. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this application relates to a memory device comprising: a memory array including: a first data line; a first post coupled to the first data line; a second data line; a second post coupled to the second data line; and a plurality of word lines coupled to the first post and the second post; and control logic operably coupled to the memory array, the control logic being configured to perform operations including: causing the plurality of word lines to discharge after a programming pulse is applied to program one or more memory cells coupled to a selected word line of the plurality of word lines; causing a power supply voltage to be applied to the second data line to cause a voltage fluctuation at the second post; causing a ground voltage to be applied to the first data line to suppress soft erase via the first post; causing a non-selected word line of the plurality of word lines to charge to increase a channel voltage in a memory cell coupled to the second post; and causing one of the ground voltage or a negative voltage to be applied to the selected word line to increase a soft erase voltage between a channel of a memory cell coupled to the second post and the selected word line, thereby causing a threshold voltage stored in the memory cell to be partially erased.

[0004] In another aspect, this application relates to a method comprising: discharging a plurality of word lines of a memory device after programming one or more memory cells coupled to selected word lines of the plurality of word lines with a programming pulse; initially charging non-selected word lines of the plurality of word lines to a first voltage level to increase a channel voltage in a memory cell coupled to a second post, wherein the first post is coupled to a first data line, the second post is coupled to a second data line, and the plurality of word lines are coupled to both the first and second posts; after a certain period of time, charging the non-selected word lines to a second voltage level higher than the first voltage level; applying a power supply voltage to the second data line to cause a voltage fluctuation in the second post; initially applying a ground voltage to the first data line to suppress soft erase via the first post; during the time period, switching to applying the power supply voltage to the first data line to also cause a voltage fluctuation in the first post; and applying either the ground voltage or a negative voltage to the selected word line to increase the soft erase voltage between the channel of the memory cell coupled to the second post and the selected word line, thereby causing a threshold voltage stored in the memory cell to be partially erased.

[0005] In another aspect, this application relates to a method comprising: causing a plurality of word lines to discharge after programming one or more memory cells coupled to a selected word line of the plurality of word lines via a programming pulse; causing a ground voltage to be applied to a first data line to suppress soft erase via a first post coupled to the first data line and the plurality of word lines; causing a power supply voltage to be applied to a second data line to cause a voltage float of a second post coupled to the plurality of word lines and the first data line; causing a non-selected word line of the plurality of word lines to charge to increase a channel voltage in a memory cell coupled to the second post; and causing one of the ground voltage or a negative voltage to be applied to the selected word line to increase a soft erase voltage between a channel of the memory cell coupled to the second post and the selected word line, thereby causing a threshold voltage stored in the memory cell to be partially erased. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of some embodiments thereof.

[0007] Figure 1A An example computing system including a memory subsystem is shown according to some embodiments.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 2This is a schematic block diagram of a portion of a memory device comprising a memory array having strings of memory cells and associated selection circuitry and selection lines, according to some embodiments.

[0010] Figure 3 According to some embodiments Figure 2 A side view of the structure of a portion of a memory device.

[0011] Figure 4 This is a conceptual depiction of the threshold voltage distribution of a plurality of memory cells in a memory array according to an embodiment.

[0012] Figures 5A-5B It is a conceptual depiction of the threshold voltage distribution of multiple memory cells at different stages after they have been programmed for use with various embodiments.

[0013] Figure 6 This is a simplified perspective, magnified view of the two pillars and the selected letter lines according to the embodiment.

[0014] Figure 7 This is a graph illustrating the fast bit erasure at the upper tail of one of a set of highest threshold voltage distributions according to an embodiment.

[0015] Figure 8 This is a graph illustrating the waveform associated with bit erasure according to an embodiment.

[0016] Figure 9 This is a flowchart illustrating an operation that can be used to perform a fast bit erasure according to an exemplary embodiment.

[0017] Figure 10 This is a simplified perspective, magnified view of the two pillars and the selected letter lines according to the embodiment.

[0018] Figure 11 This is a graph illustrating the fast bit erasure at the upper tail of any of a set of threshold voltage distributions according to an embodiment.

[0019] Figure 12 This describes the execution according to the embodiments and Figure 10 A graph of a set of waveforms associated with fast bit erasure.

[0020] Figure 13 It is a simplified perspective, magnified view of the columns coupled to the selected letter lines and many non-selected letter lines according to some embodiments.

[0021] Figure 14 This is a flowchart of an example method for performing a fast bit erasure operation on one of the highest voltage threshold voltage distributions according to some embodiments.

[0022] Figure 15This is a flowchart of an example method for performing a fast bit erasure operation on any threshold voltage distribution according to some embodiments.

[0023] Figure 16 This is a block diagram of an example computer system in which embodiments of the present disclosure may operate. Detailed Implementation

[0024] Embodiments of this disclosure relate to fast bit erasure with a top-tail-tightening of threshold voltage distribution within memory cells of, for example, a memory device. For example, the memory device may be a non-volatile memory device, such as a NAND memory device. The memory device may consist of memory cells arranged in a two-dimensional (2D) or (3D) three-dimensional grid, wherein each memory cell may store a threshold voltage corresponding to one or more logic bits. The memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines or data lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells.

[0025] In some embodiments of 3D NAND, physical conductive pillars can be formed within the semiconductor layer to provide the primary conductive path between data lines and sub-blocks of memory cells. For example, a string of memory cells can be coupled to the pillars so that it can be jointly controlled from data lines also coupled to the pillars, as will be discussed in more detail. In some memory devices, several pillars can be combined to form blocks of memory cells. Typically, erasing memory cells is performed at the physical block level to prepare those memory cells for programming new data. Subsequently, when programming memory cells, charge is injected from the pillars into the memory cells so that each memory cell stores a certain level of charge.

[0026] In at least some embodiments, memory cell groups are programmed to store charge-encoded levels of logic bits for data. Typically, a memory cell group is a page of memory cells coupled to the same word line. More specifically, each memory cell may store charge levels belonging to one of a variety of threshold voltage ranges to form a threshold voltage (Vt) distribution. Each Vt range represents a data state corresponding to a bit pattern of several logic bits, depending on how many different states can be stored in each memory cell. For example, in a three-level cell (TLC), the Vt distribution may correspond to one of eight different logic states (each representing a different combination of three bits). Additionally, in a four-level cell (QLC), the Vt distribution may correspond to one of 16 different logic states (each representing a different combination of four bits). Furthermore, in a five-level cell (PLC), the Vt distribution may correspond to one of 32 different logic states (each representing a different combination of five bits). The threshold voltage range can become narrower when the cell is segmented into additional threshold voltage ranges to capture additional logic bit patterns.

[0027] In various embodiments, the charge levels of the remaining memory cells after programming multiple memory cells (e.g., memory cell pages, memory cell strings, sub-blocks of memory cells, or blocks of memory cells) can form a Vt distribution. The Vt distribution may represent a portion of the distribution of threshold voltage ranges at the time of programming completion, thus encoding data within the multiple memory cells that can be read later. Adjacent Vt distributions may be separated by a tolerance (or dead zone space), sometimes referred to as the read window budget (RWB), because the tolerance provides a separation that can be used to measure the threshold voltage distributions individually. Rapid charge loss and long-term charge loss can cause the threshold voltage distributions to widen and at least partially overlap, thereby reducing the RWB and making it more difficult to measure the separated threshold voltage distributions, such as measurements typically performed at the upper tail portion of each threshold voltage distribution.

[0028] In some memory devices, the tolerance or RWB between threshold voltage distributions can be increased (e.g., by tightening the threshold voltage distribution) by performing incremental programming of memory cells and performing programming verification operations between programming pulses. Once a memory cell has been verified to have reached the threshold voltage value associated with the programming verification voltage, it is considered programmed and may be suppressed during further programming. Despite performing this type of incremental programming, some degree of overprogramming can still occur, specifically because using too many programming verification operations can adversely affect the overall programming time. The effects of overprogramming may worsen over time as the memory array reaches the end of its lifespan.

[0029] The aspects of this disclosure address the above and other drawbacks by allowing a certain amount of overprogramming of the memory cells to occur simultaneously before or after performing a fast bit erase (also referred to herein as a soft erase) on the programmed cells before or after programming verification. Each fast bit erase can be performed on one or more individual memory cells to, for example, tighten the upper tail of a threshold voltage distribution, which is typically a portion of the threshold voltage distribution measured later during a read operation. Fast bit erases can be performed more than once and incrementally on one or more memory cells to reduce the upper tail by referencing a bit erase verification voltage associated with the threshold voltage level being erased.

[0030] In these embodiments, the memory device may include control logic coupled to a memory array for controlling selective fast bit erasure of specific memory cells. For example, the memory array may include a first post coupled to a first data line, a second post coupled to a second data line, and a plurality of word lines coupled to the first and second posts. The control logic may cause the word lines to discharge after a programming pulse is applied to program one or more memory cells coupled to a selected word line among the plurality of word lines. The control logic may further cause a power supply voltage to be applied to the second data line to cause a voltage fluctuation at the second post. The control logic may further cause a ground voltage to be applied to the first data line to suppress soft erasure via the first post. The control logic may then cause non-selected word lines to be charged to increase the channel voltage in the memory cell coupled to the second post. The control logic may further cause either a ground voltage or a negative voltage to be applied to the selected word line to increase the soft erase voltage between the channel of the memory cell coupled to the second post and the selected word line. In the disclosed embodiments, the soft erase voltage causes a threshold voltage stored in the memory cell to be partially erased, for example, by losing some charge via the second post. In at least some embodiments, the threshold voltage stored in the memory cell contributes to the top tail of at least two of the highest threshold voltage distributions in a set of highest threshold voltage distributions of a set of multi-level memory cells. Another variation of this approach can be used to further perform a fast bit erase to tighten the top tail of any threshold voltage distribution in the set of multi-level memory cells, which will be discussed in more detail.

[0031] Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, mitigating over-programming at the upper tail of the threshold voltage distribution. For example, individual cells can be erased instead of only block-level erasure. Tightening the upper tail of the threshold voltage distribution can improve RWB for better robustness, or can be applied to PLCs to improve programming accuracy when each cell is encoded with five bits. Other advantages of programming multi-level cells discussed below will be apparent to those skilled in the art.

[0032] Figure 1AAn example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure is illustrated. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such media or memory devices. The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules.

[0033] Memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. A non-volatile memory device is a package of one or more dies. Each die may contain one or more planes. Planes may be divided into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits being stored. Logic states may be represented as binary values, such as “0” and “1”, or combinations of such values.

[0034] Memory device 130 may consist of bits arranged in a two-dimensional or three-dimensional grid, also referred to as a memory array. Memory cells are etched onto a silicon wafer in the form of column (hereinafter also referred to as bit lines) and row (hereinafter also referred to as word lines) arrays. A word line may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate the address of each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell.

[0035] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0036] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., an airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing power.

[0037] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1A An example of a host system 120 coupled to a memory subsystem 110 is shown. The host system 120 can provide data to be stored at the memory subsystem 110 and can request data to be retrieved from the memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0038] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and read data from memory subsystem 110.

[0039] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface can provide an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0040] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0041] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory cells can perform bit storage based on variations in volume resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, crosspoint non-volatile memories can perform in-place write operations, where non-volatile memory cells can be programmed without prior erasing. NAND flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0042] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell, for example, by means of an additional threshold voltage range. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages that refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0043] Although non-volatile memory components, such as 3D cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0044] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0045] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0046] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1A The example memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0047] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0048] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0049] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0050] In some embodiments, the control logic of the local media controller 135 may be adapted to program memory cells via data lines and word lines within a memory structure, which will be discussed in more detail below. The control logic may further employ incremental programming of different versions of the memory cells, including incremental step programming paths (ISPP) and incremental step erasures of the programmed memory cells. ISPP-based programming may employ programming verification operations between programming pulses to gradually bring the threshold voltage of the memory cell to a programming verification voltage level. In some embodiments, the control logic may direct the execution of incremental step erasures of the memory cells to gradually (via at least one intermediate erase operation) tighten the upper tail of the threshold voltage distribution until, for example, the upper tail is within the threshold of the bit erase verification voltage used for the threshold voltage distribution. Although the discussion herein refers to upper tail tightening, lower tail tightening may also be performed using the same or similar methods.

[0051] Figure 1B The first device in the form of a presenting memory device 130 and the presenting memory subsystem (e.g., according to the embodiment) are presenting memory devices 130. Figure 1A A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0052] Memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells arranged in logical rows are typically connected to the same access line (e.g., a word line), while memory cells arranged in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1B (Not shown in the image) can be programmed to one of at least two target data states.

[0053] Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 111 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0054] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 111 to control them in response to addresses.

[0055] The local media controller 135 also communicates with cache register 118 and data register 121. Cache register 118 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 104 is busy writing or reading other data. During a programming operation (e.g., a write operation), data can be transferred from cache register 118 to data register 121 for transmission to the memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache register 118. During a read operation, data can be transferred from cache register 118 to I / O control circuitry 112 for output to memory subsystem controller 115; then, new data can be transferred from data register 121 to cache register 118. Cache register 118 and / or data register 121 may form a page buffer for memory device 130 (e.g., at least a portion thereof). The page buffer may further include sensing devices (e.g., a sensing amplifier) ​​to sense the data status of the memory cells of the memory cell array 104, for example by sensing the status of the data lines connected to the memory cells. The status register 122 may communicate with the I / O control circuitry system 112 and the local media controller 135 to latch status information for output to the memory subsystem controller 115.

[0056] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0057] For example, commands can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to command register 124. Addresses can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to address register 114. Data can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 118. Data can then be written to data register 121 for programming memory cell array 104.

[0058] In this embodiment, cache register 118 may be omitted, and data may be written directly to data register 121. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0059] Those skilled in the art will understand that additional circuitry and signals can be provided, and the process has been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device can be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Additionally, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0060] Figure 2 This is a schematic block diagram of a portion of a memory device 200 including a memory array 201 having memory cell strings and associated selection circuitry and select lines, according to some embodiments. The memory device 200 may correspond to... Figure 1A-1B The memory device 130. For example, the memory array 201 can be formed Figure 1B A portion of the memory cell array 104.

[0061] like Figure 2 As shown, memory device 200 may include blocks (blocks of memory cells) BLK0, BLK1 to BLKi. Three blocks are shown as an example. Memory device 200 may include many blocks (e.g., up to thousands or more blocks). In the physical structure of memory device 200, blocks may be arranged (e.g., formed) so that one block is adjacent to another, such that each block may have neighboring blocks. Adjacent blocks are blocks positioned adjacent to (e.g., neighboring) each other. For example, in the physical structure of memory device 200, blocks BLK0 and BLK1 may be adjacent blocks.

[0062] Each of the blocks BLK0, BLK1 through BLKi in the memory device 200 may contain (e.g., may be divided into) sub-blocks. For example, each of the blocks BLK0 and BLK1 may contain sub-blocks SB0 and SB1. Block BLKi may contain sub-block SB0 (and sub-block SB1, not shown). Blocks BLK0, BLK1 through BLKi may contain the same number of sub-blocks. Figure 2 An instance is shown in which each of blocks BLK0, BLK1 to BLKi can contain two sub-blocks (e.g., SB0 and SB1). However, each of blocks BLK0, BLK1 to BLKi can have more than two blocks (e.g., SB0, SB1, SB2, SB3, etc.).

[0063] like Figure 2 As shown, each sub-block (e.g., SB0 or ​​SB1) has its own memory cell strings, and each of these memory cell strings can be associated with (e.g., coupled to) selection circuitry. For example, sub-block SB0 of block BLK0 has memory cell strings 231a, 232a, and 233a and associated selection circuitry (e.g., drain selection circuitry) 241a, 242a, and 243a, as well as selection circuitry (e.g., source selection circuitry) 241'a, 242'a, and 243'a. Sub-block SB1 of block BLK0 has memory cell strings 234a, 235a, and 236a and associated selection circuitry (e.g., drain selection circuitry) 244a, 245a, and 246a, as well as selection circuitry (e.g., source selection circuitry) 244'a, 245'a, and 246'a.

[0064] Sub-block SB0 of block BLK1 has memory cell strings 231b, 232b, and 233b and associated selection circuits (e.g., drain selection circuits) 241b, 242b, and 243b, as well as selection circuits (e.g., source selection circuits) 241'b, 242'b, and 243'b. Sub-block SB1 of block BLK1 has memory cell strings 234b, 235b, and 236b and associated selection circuits (e.g., drain selection circuits) 244b, 245b, and 246b, as well as selection circuits (e.g., source selection circuits) 244'b, 245'b, and 246'b.

[0065] Sub-block SB0 of BLKi has memory cell strings 231c, 232c, and 233c and associated selection circuits (e.g., drain selection circuits) 241c, 242c, and 243c, as well as selection circuits (e.g., source selection circuits) 241'c, 242'c, and 243'c. Sub-blocks of blocks of memory device 200 (e.g., blocks BLK0, BLK1 to BLKi) may have the same number of memory cell strings and associated selection circuits.

[0066] Figure 2 An example of three memory cell strings and their associated circuitry in a sub-block (e.g., sub-block SB0) is shown. The number of memory cell strings and their associated selection circuitry in each sub-block of blocks BLK0, BLK1 through BLKi can vary. Memory device 200 may include data lines 270, 271, and 272 carrying signals BL0, BL1, and BL2, respectively. Each of data lines 270, 271, and 272 may be constructed as a conductive line (containing a conductive material). The memory cell strings of blocks BLK0, BLK1 through BLKi may share data lines 270, 271, and 272.

[0067] For example, memory cell strings 231a and 234a (of block BK0), memory cell strings 231b and 234b (of block BLK1), and memory cell string 231c (of block BLKi) can share data line 270. Memory cell strings 232a and 235a (of block BK0), memory cell strings 232b and 235b (of block BK1), and memory cell string 232c (of block BLKi) can share data line 271. Memory cell strings 233a and 236a (of block BK0), memory cell strings 233b and 236b (of block BK1), and memory cell string 233c (of block BKi) can share data line 272. Figure 2 Three data lines, 270, 271, and 272, are shown as examples. The number of data lines can vary.

[0068] Memory device 200 may include a line 299 capable of carrying a signal SRC (e.g., a source line signal). Line 299 may be constructed as a conductive line (containing a conductive material) and may form part of a source (e.g., a source line) of memory device 200. Blocks BLK0, BLK1 to BLKi may share line 299. Alternatively, each of blocks BLK0, BLK1 to BLKi may have its own line (e.g., a source) similar to line 299.

[0069] Memory device 200 may include access lines in blocks BLK0, BLK1 to BLKi, wherein the access lines are electrically isolated from each other within the same block and electrically isolated between blocks. For example... Figure 2 As shown, each of blocks BLK0, BLK1, BLK2, and BLK3 may include its own access lines associated with signals (e.g., word line signals) WL0, WL1, WL2, and WL3. For example, in block BLK0, memory device 200 includes access lines (which may be or may include word lines) 2200, 2210, 2220, and 2230 (e.g., access line groups) that can respectively carry corresponding signals (e.g., word line signals) WL00, WL10, WL20, and WL30.

[0070] In block BLK1, memory device 200 includes access lines (which may be or may include word lines) 2201, 2211, 2221, and 2231 (e.g., access line groups) capable of carrying corresponding signals (e.g., word line signals) WL01, WL11, WL21, and WL31, respectively. In block BLKi, memory device 200 includes WL0... i WL1 i WL2 i and WL3 i Access lines (which may or may include word lines) 220 i 221 i 222 i and 223 i .

[0071] Access lines 2200 to 2230, 2201 to 2231 and 2201 to 2231 may be constructed as conductive access lines (containing conductive material), which may form part of the corresponding access lines of the memory device 200 for accessing memory cells in the corresponding block. Figure 2 Four access lines (2200 to 2230, 2201 to 2231, or 2201 to 2231) in each of blocks BLK0, BLK1 to BLKi are shown as examples. The number of access lines can vary.

[0072] In subblock SB0 of block BK0, memory device 200 includes select lines (e.g., drain select lines) 2800, 2810, 2820, and 2830 that can be shared by select circuits 241a, 242a, and 243a. In subblock SB1 of block BK0, memory device 200 includes select lines (e.g., drain select lines) 2801, 2811, 2821, and 2831 that can be shared by select circuits 244a, 245a, and 246a. Block BLK0 may include select lines (e.g., source select lines) 284, 285, and 286 that can be shared by select circuits 241'a, 242'a, 243'a, 244'a, 245'a, and 246'a.

[0073] In subblock SB0 of block BLK1, memory device 200 includes select lines (e.g., drain select lines) 2800, 2810, 2820, and 2830 that can be shared by select circuits 241b, 242b, and 243b. In subblock SB1 of block BLK1, memory device 200 includes select lines (e.g., drain select lines) 2801, 2811, 2821, and 2831 that can be shared by select circuits 244b, 245b, and 246b. Block BLk1 may include select lines (e.g., source select lines) 284, 285, and 286 that can be shared by select circuits 241'b, 242'b, 243'b, 244'b, 245'b, and 246'b. In the sub-block SB0 of block BLKi, memory device 200 includes select lines (e.g., drain select lines) 2800, 2810, 2820 and 2830 that can be shared by select circuits 241c, 242c and 243c; and select lines (e.g., source select lines) 284, 285 and 286 that can be shared by select circuits 241'c, 242'c and 243'c.

[0074] Figure 2 An example is shown in which the memory device 200 includes four drain select lines (e.g., 2800, 2810, 2820, and 2830) associated with drain select circuitry (e.g., 241a, 242a, or 243a) in a sub-block (e.g., sub-block SB0 of block BLK0). However, the memory device 200 may include more or fewer than four drain select lines associated with drain select circuitry. Similarly, Figure 2 An example is shown in which the memory device 200 includes three source select lines (e.g., 284, 285, and 286) associated with a source select circuit (e.g., 241'a, 242'a, or 243'a) in a sub-block (e.g., sub-block SB0 of block BLK0). However, the memory device 200 may include more or fewer than three source select lines associated with the source select circuit.

[0075] The memory device 200 may include select lines 280'0, 2810, 282'0, 283'0, 280'1, 2811, 282'1, and 283'1, each of which may electrically connect two corresponding select lines. Figure 2 The diagram shows the selection lines 280'0, 2810, 282'0, 283'0, 280'1, 2811, 282'1, and 283'1 themselves to avoid... Figure 2 The components shown are crowded. Figure 2 Selection line 280'0 is shown to indicate selection line 2800 (sometimes referred to as selection line 2800 / SB0 / BLK0) of sub-block SB0 of block BLK0, and selection lines 2800 (sometimes referred to as selection lines 2800 / SB0 / BLK1) of sub-block SB0 of block BLK1 can be electrically contacted (e.g., electrically connected) with each other through selection line 280'0. Therefore, in memory device 200, selection lines 2800 / SB0 / BLK0 and 2800 / SB0 / BLK1 can have (e.g., be applied) the same signal. This also means that selection lines 2800 / SB0 / BLK0 and 2800 / SB0 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0076] Figure 2 Selection line 281'0 is shown to indicate selection line 2810 (sometimes referred to as selection line 2810 / SB0 / BLK0) of sub-block SB0 of block BLK1, and selection lines 2810 (sometimes referred to as selection line 2810 / SB0 / BLK1) of sub-block SB0 of block BLK1 can be electrically contacted (e.g., electrically connected) with each other through selection line 281'0. Therefore, in memory device 200, selection lines 2810 / SB0 / BLK0 and 2810 / SB0 / BLK1 can have (been applied) the same signal. This also means that selection lines 2810 / SB0 / BLK0 and 2810 / SB0 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0077] Figure 2Selection line 282'0 is shown to indicate selection line 2820 (sometimes referred to as selection line 2820 / SB0 / BLK0) of sub-block SB0 of block BLK1, and selection lines 2820 (sometimes referred to as selection line 2820 / SB0 / BLK1) of sub-block SB0 of block BLK1 can be electrically contacted (e.g., electrically connected) with each other through selection line 282'0. Therefore, in memory device 200, selection lines 2820 / SB0 / BLK0 and 2820 / SB0 / BLK1 can have (been applied) the same signal. This also means that selection lines 2820 / SB0 / BLK0 and 2820 / SB0 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0078] Figure 2 Selection line 283'0 is shown to indicate selection line 2830 (sometimes referred to as selection line 2830 / SB0 / BLK0) of sub-block SB0 of block BLK0, and selection line 2831 (sometimes referred to as selection line 2831 / SB0 / BLK0) of sub-block SB0 of block BLK0 can be electrically contacted (e.g., electrically connected) with each other through selection line 283'0. Therefore, in memory device 200, selection lines 2830 / SB0 / BLK0 and 2831 / SB0 / BLK0 can have (been applied) the same signal. This also means that selection lines 2830 / SB0 / BLK0 and 2831 / SB0 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0079] Figure 2 Selection line 280'1 is shown to indicate selection line 2801 (sometimes referred to as selection line 2801 / SB1 / BLK0) of sub-block SB1 of block BLK1, and selection lines 2801 (sometimes referred to as selection line 2801 / SB1 / BLK1) of sub-block SB1 of block BLK1 can be electrically contacted (e.g., electrically connected) to each other through selection line 281'1. Therefore, in memory device 200, selection lines 2801 / SB1 / BLK0 and 2801 / SB1 / BLK1 can have (been applied) the same signal. This also means that selection lines 2801 / SB1 / BLK0 and 2801 / SB1 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0080] Figure 2Selection line 281'1 is shown to indicate selection line 2811 (sometimes referred to as selection line 2811 / SB1 / BLK0) of sub-block SB1 of block BLK1, and selection lines 2811 (sometimes referred to as selection line 2811 / SB1 / BLK1) of sub-block SB1 of block BLK1 can be electrically contacted (e.g., can be electrically connected to each other). Therefore, in memory device 200, selection lines 2811 / SB1 / BLK0 and 2811 / SB1 / BLK1 can have (been applied) the same signal. This also means that selection lines 2811 / SB1 / BLK0 and 2811 / SB1 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0081] Figure 2 Selection line 282'1 is shown to indicate selection line 2821 (sometimes referred to as selection line 2821 / SB1 / BLK0) of sub-block SB1 of block BLK1, and selection lines 2821 (sometimes referred to as selection line 2821 / SB1 / BLK1) of sub-block SB1 of block BLK1 can be electrically contacted (e.g., electrically connected) to each other through selection line 282'1. Therefore, in memory device 200, selection lines 2821 / SB1 / BLK0 and 2821 / SB1 / BLK1 can have (been applied) the same signal. This also means that selection lines 2821 / SB1 / BLK0 and 2821 / SB1 / BLK1 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0082] Figure 2 Selection line 283'1 is shown to indicate selection line 2831 (sometimes referred to as selection line 2831 / SB0 / BLK0) of sub-block SB0 of block BLK0, and selection lines 2831 (sometimes referred to as selection line 2831 / SB0 / BLK0) of sub-block SB0 of block BLK0 can be electrically contacted (e.g., electrically connected) to each other through selection line 283'1. Therefore, in memory device 200, selection lines 2831 / SB0 / BLK0 and 2831 / SB0 / BLK0 can have (been applied) the same signal. This also means that selection lines 2831 / SB0 / BLK0 and 2831 / SB0 / BLK0 can receive the same signal during operation of memory device 200 (e.g., read, write, or erase operations).

[0083] In the structure of memory device 200, each of select lines 280'0, 2810, 282'0, 283'0, 280'1, 2811, 282'1, and 283'1 may contain a conductive material formed to make electrical contact with the materials of the two corresponding select lines. For example, select line 283'0 may contain a conductive material formed to make electrical contact with the materials forming select lines 2830 / SB0 / BLK0 and 2831 / SB0 / BLK0. In another example, select line 282'0 may contain a conductive material formed to make electrical contact with the materials forming select lines 2820 / SB0 / BLK0 and 2821 / SB0 / BLK0.

[0084] The material of each of the select lines 280'0, 2810, 282'0, 283'0, 280'1, 2811, 282'1, and 283'1 may include metal, doped polysilicon, or other conductive materials. Each of the drain select circuits in memory device 200 may include multiple series-connected drain select gates (e.g., four series-connected transistors) between the corresponding data line and the corresponding memory cell string. The drain select gate may be controlled by the corresponding drain select line (e.g., turned on or off) based on the voltage of a signal provided to the corresponding drain select line. Each of the source select circuits in memory device 200 may include multiple series-connected source select gates between line 299 and the corresponding memory cell string. The source select gate may be controlled by the corresponding source select line (e.g., turned on or off) based on the voltage of a signal provided to the corresponding source select line.

[0085] exist Figure 2 In this memory device 200, each of the memory cell strings has memory cells arranged in a string (e.g., coupled in series with each other) to store information. During operation of the memory device 200 (e.g., read, write, or erase operations), the memory cell strings can be individually selected to access memory cells in the selected memory cell string in order to store information in or read information from the selected memory cell string. One or both selection circuits (drain selection circuit and source selection circuit) associated with the selected memory cell string may be activated depending on which operation the memory device 200 performs on the selected memory cell string (e.g., by turning on the selection gate (e.g., transistor) in the selection circuit (or the selected circuit)).

[0086] Activating a specific selection circuit within the selection circuitry of the memory device 200 during operation may include providing (e.g., applying) a voltage of a certain value to a selection line associated with the specific selection circuit. When a specific drain selection circuit of the memory device 200 is activated, it can electrically connect the selected memory cell string associated with the specific selection circuit to a corresponding data line (e.g., one of data lines 270, 271, or 272) (e.g., forming a current path from the selected memory cell string to the corresponding data line). When a specific source selection circuit is activated, it can electrically connect the selected memory cell string associated with the specific selection circuit to a source (e.g., line 299) (e.g., forming a current path from the selected memory cell string to the source).

[0087] Figure 3 According to some embodiments Figure 2 A side view of the structure of a portion of the memory device 200. (See attached image.) Figure 3 As shown, the memory device 200 may include a substrate 390, and memory cells 210, 211, 212, and 213 of memory cell strings 231a, 234a, 231b, and 234b of corresponding sub-blocks SB0 and SB1 of blocks BLK0 and BLK1 may be formed above the substrate (e.g., vertically formed in the z-direction relative to line 299 and substrate 390). The memory device 200 includes different levels 307 to 317 relative to the z-direction. Levels 307 to 317 are internal device levels between the substrate 390 and the data line 270.

[0088] The substrate 390 of the memory device 200 may comprise a single-crystal (also referred to as a single-crystal) semiconductor material. For example, the substrate 390 may comprise single-crystal silicon (also referred to as single-crystal silicon). The single-crystal semiconductor material of the substrate 390 may contain impurities, such that the substrate 390 may have a specific conductivity type (e.g., n-type or p-type).

[0089] Memory device 200 may include a drive circuit system 319 to provide signals (e.g., drain and source select line signals) to corresponding select lines of memory device 200. The drive circuit system 319 may correspond to... Figure 1A-1B The local media controller 135 is either included in or is part of the local media controller. Although Figure 3 Not shown, but substrate 390 may contain circuitry located directly below line 299. Such circuitry may include sense amplifiers, buffers (e.g., page buffers), decoders, and other circuitry components of memory device 200. Figure 3As shown, the drive circuit system 319 may include drivers (driver circuits) 380, 381, 382, ​​and 383 to provide corresponding signals (e.g., drain select line signals SGD0, SGD1, SGD2, and SGD3), and may include drivers (driver circuits) 384, 385, and 386 to provide corresponding signals (e.g., source select line signals SGS0, SGS1, and SGS2). Figure 3 For simplicity, only some of the drain and source selection signals are shown in the diagram.

[0090] exist Figure 3 In this context, each of the drivers 380 to 386 may contain two transistors: an N-channel transistor (e.g., an NMOS) and a P-channel transistor (e.g., a p-channel MOS (PMOS)). For simplicity, Figure 3 Details of only one of drivers 380 to 384 are shown. Each of drivers 380 to 386 may include an output node, such as a node located between transistors N and P and electrically connected to transistors N and P, to provide (e.g., drive) a corresponding signal (e.g., a drain select line signal or a source select line signal). The output node of each of drivers 380 to 386 may be coupled (e.g., electrically connected) to a corresponding drain select line or a corresponding source select line of memory device 200. This allows drain and source select line signals (e.g., SGD0, SGD1, SGD2, SGD3, SGS0, SGS1, and SGS2) from drive circuitry 319 to the corresponding drain and source select lines of memory device 200, as referenced above. Figure 2 and Figure 3 As described.

[0091] Figure 3 Examples are shown where each of drivers 380 to 386 may have two transistors of different transistor types (e.g., NMOS and PMOS) coupled in a complementary MOS (CMOS) interconnect. However, each of drivers 380 to 386 may have two transistors of the same type (e.g., two NMOS transistors or two PMOS transistors) and two separate transistor gate signals. Furthermore, the number of transistors in each of drivers 380 to 386 may be different from two.

[0092] like Figure 3 As shown, the data line 270 may have a length extending in the y direction (e.g., in...). Figure 3 As shown in the diagram, the y-direction is perpendicular to both the z-direction and the x-direction. Data line 270 may contain a conductive material (e.g., conductively doped polysilicon, metal, or other conductive material). Additionally, line 299 may contain a conductive material and may have a length extending in the y-direction. Figure 3An example is shown where a line 299 (e.g., a source) may be formed over a portion of substrate 390 (e.g., by depositing a conductive material over substrate 390). Alternatively, line 299 may be formed in or on a portion of substrate 390 (e.g., by doping a portion of substrate 390).

[0093] In at least some embodiments, the selection lines (e.g., drain selection lines) 2800, 2810, 2820, and 2830 for each of blocks BLK0 and BLK1 may be located in corresponding levels 314, 315, 316, and 317. The selection lines (e.g., drain selection lines) 2801, 2811, 2821, and 2831 for each of blocks BLK0 and BLK1 may be located in corresponding levels 314, 315, 316, and 317.

[0094] In at least some embodiments, memory cells 210, 211, 212, and 213 of memory cell strings 231a, 234a, 231b, and 234b may be located in levels 310, 311, 312, and 313, respectively. Access lines 2200, 2210, 2220, and 2230 of block BLK0 (associated with memory cells 210, 211, 212, and 213, respectively) may be located in levels 310, 311, 312, and 313, respectively. Access lines 2201, 2211, 2221, and 2231 of block BLK1 (associated with memory cells 210, 211, 212, and 213, respectively) may be located in levels 310, 311, 312, and 313, respectively.

[0095] The selection lines (e.g., source selection lines) 284, 285, and 286 of each of blocks BLK0 and BLk1 may be located in different layers (e.g., layers 307, 308, and 309, respectively) between the substrate 390 and the memory cell strings 231a, 232a, and 233a. The memory device 200 may also include a dielectric material interleaved with other elements in the different layers of the memory device 200. Figure 3(Not marked in the original text). For example, memory device 200 may include a dielectric material (e.g., silicon dioxide) located between layers 314 and 317 and intersecting (within the space between the select lines) with select lines 2800, 2810, 2820, and 2830 of each of blocks BLK0 and BLK1. In another example, memory device 200 may include a group of dielectric materials (e.g., silicon dioxide) located between layers 310 and 313 and intersecting (within the space between the access lines) with access lines 2200, 2210, 2220, and 2230 of block BLK0. In yet another example, memory device 200 may include a group of dielectric materials (e.g., silicon dioxide) located between layers 310 and 313 and intersecting (within the space between the access lines) with access lines 2201, 2211, 2221, and 2231 of block BLK1.

[0096] In another example, memory device 200 includes a dielectric material (e.g., silicon dioxide) located between layers 307 and 309 and intersecting with select lines 284, 285, and 286 (located in the space between the select lines). The material of select lines 2800, 2810, 2820, 2830, 2801, 2811, 2821, 2831, 284, 285, and 286 may comprise conductive-doped polysilicon, metal, or other conductive materials, and may be the same as the conductive material of access lines 2200, 2210, 2220, 2230, 2201, 2211, 2221, and 2231. Figure 3 As shown, the memory device 200 may include pillars (conductive pillars) 341, 342, 343, and 344 in corresponding sub-blocks SB0 and SB1 of blocks BLK0 and BLK1. Each of pillars 341, 342, 343, and 344 may have an outward (e.g., vertically extending in the z-direction and perpendicular to the y-direction) length. Each of pillars 341, 342, 343, and 344 may contact a conductive region of the material forming a portion of data line 270 and a conductive region of the material forming a portion of line 299.

[0097] Each of pillars 341, 342, 343, and 344 may contain a material (or materials) to form a conductive path (e.g., a channel) between data line 270 and line 299. Such material (e.g., undoped or doped polysilicon) in each of pillars 341, 342, 343, and 344 may be a channel for the corresponding pillar in pillars 341, 342, 343, and 344. Figure 3 (Not shown in the image)

[0098] like Figure 3As shown, memory device 200 may include a structure 330 that is adjacent to and extends continuously along the length of the respective pillar among adjacent pillars 341, 342, 343, and 344. Structure 330 is also an adjacent portion of the respective access line (2200, 2210, 2220, and 2230, or access lines 2201, 2211, 2221, and 2231). The structure 330 adjacent to the respective pillar is located between the portion of the respective pillar and the portion of the respective access line (access lines 2200, 2210, 2220, and 2230, or access lines 2201, 2211, 2221, and 2231). Structure 330 may include portions 301, 302, and 303. The portion of structure 330 along a particular pillar may form part of each of the memory cells in a string of memory cells adjacent to said particular pillar. For example, the structure 330 adjacent to post 342 can form a portion of each of the memory cells 210, 211, 212, and 213 of the memory cell string 234a. Therefore, each of the memory cells 210, 211, 212, and 213 of the memory cell string can include a portion of the structure 330 (parts 301, 302, and 303) located between one of the access lines (access lines 2200, 2210, 2220, 2230, 2201, 2211, 2221, and 2231) and the corresponding post. For example, memory cell 212 of the memory cell string 234a (adjacent to post 342) can include a portion of each of the portions 301, 302, and 303 located between access line 2220 and post 342.

[0099] Structure 330 may be part of a TANOS (TaN, Al2O3, Si3N4, SiO2, Si) structure. For example, portion 301 (e.g., a polycrystalline silicon interlayer dielectric) may include a charge-blocking material (e.g., a dielectric material, such as TaN and Al2O3) capable of blocking charge tunneling. Portion 302 may include a charge storage element (e.g., a charge storage material, such as Si3N4) that can provide charge storage functionality (e.g., charge trapping) to represent the value of information stored in memory cells 210, 211, 212, or 213. Portion 303 may include a dielectric, such as a tunneling dielectric material (e.g., SiO2), capable of allowing charge (e.g., electrons) tunneling. As an example, portion 303 may allow electrons to tunnel from portion 304 to portion 302 during a write operation and allow electrons to tunnel from portion 302 to portion 304 during an erase operation of the memory device 200. Furthermore, portion 303 may allow holes to tunnel from portion 304 to portion 302, thereby compensating for the recombination of trapped electrons during erase operations of the memory device 200. In an alternative arrangement of the memory device 200, structure 330 may be part of a SONOS (Si, SiO2, Si3N4, SiO2, Si) structure. In another alternative arrangement, structure 330 may be part of a floating gate structure (e.g., portion 302 may be polysilicon and each of portions 301 and 303 may be a dielectric (e.g., SiO2)).

[0100] like Figure 3 As shown, the select line (e.g., 2800) is a sheet (e.g., a single layer) of conductive material (e.g., polysilicon, metal, or other conductive material). As described above, the select line may carry a signal (e.g., signal SGD10), but it does not function as a switch (e.g., a transistor). The select gate (e.g., 260) may include a portion of the corresponding select line (e.g., a portion of the conductive material sheet forming the corresponding select line) and additional structures to perform a function (e.g., the function of a transistor). For example, in Figure 3 In this embodiment, the selection gate 260 of sub-block SB0 of block BLK0 may include a portion of the selection line 2800 of sub-block SB0 of block BLK0 and a portion of the structure 330 (along pillar 341) of the selection line 2800 of the adjacent sub-block SB0 of block BLK0. In another embodiment, the selection gate 261 of sub-block SB0 of block BLK0 may include a portion of the selection line 2810 of sub-block SB0 of block BLK0 and a portion of the structure 330 (along pillar 341) of the selection line 2810 of the adjacent sub-block SB0 of block BLK0.

[0101] Figure 3An example is shown in which select gates 261 to 266 have the same structure as memory cells 210, 211, 212, and 213 (e.g., a TANOS structure). Alternatively, select gates 260, 261, 262, and 263 (e.g., drain-select gates), select gates 264, 265, and 266 (e.g., source-select gates), or select gates 260 to 266 can have different structures, such as FET structures. As is known to those skilled in the art, an FET typically includes a transistor gate, a transistor body channel, and a gate oxide between the transistor gate and the transistor body channel, the gate oxide being in direct contact with the transistor gate and the transistor body channel.

[0102] Figure 4 It is a conceptual description of the threshold voltage range of multiple memory cells. Figure 4 An example is shown of the threshold voltage ranges and their distribution for a group of sixteen-level memory cells, such as QLC memory cells. For example, such memory cells can be programmed to fall within sixteen different threshold voltage ranges of 4300-4300. 15 The threshold voltage (Vt) within each of these ranges represents the data state corresponding to a four-bit bit pattern. The width of the threshold voltage range 4300 is typically greater than the width of the other threshold voltage ranges 4301-4300. 15 Because the memory cells are generally all in a data state corresponding to the threshold voltage range of 4300, a subset of those memory cells are then programmed to have a data state in the threshold voltage range of 4301-4300. 15 The threshold voltage is one of the threshold voltages. Because programming operations are generally controlled in more incremental ways compared to erasing operations, these threshold voltages range from 4301 to 4301. 15 They may tend to have a denser distribution.

[0103] Threshold voltage ranges: 4300, 4301, 4302, 4303, 4304, 4305, 4306, 4307, 4308, 4309, 430 10 430 11 430 12 430 13 430 14 and 430 15Each of these can represent a corresponding data state, for example, L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15. For example, if the threshold voltage of the memory cell is within the first threshold voltage range of sixteen threshold voltage ranges 4300, the memory cell can store data state L0 with a data value of logic '1111', which is usually referred to as the erase state of the memory cell. If the threshold voltage is within the second threshold voltage range of sixteen threshold voltage ranges 4301, the memory cell can store data state L1 with a data value of logic '0111'. If the threshold voltage is within the third threshold voltage range of sixteen threshold voltage ranges 4302, the memory cell can store data state L2 with a data value of logic '0011', and so on. Table 1 provides one possible correspondence between data states and their corresponding logical data values. Other assignments of data states to logical data values ​​are known or conceivable. As used herein, a memory cell that remains in the lowest data state (e.g., erase state or L0 data state) will be considered programmed to the lowest data state.

[0104] L0 1111 L8 1100 L1 0111 L9 0100 L2 0011 L10 0000 L3 1011 L11 1000 L4 1001 L12 1010 L5 0001 L13 0010 L6 0101 L14 0110 L7 1101 L15 1110

[0105] Table 1

[0106] Figure 5A It is a conceptual depiction of the threshold voltage distribution of multiple memory cells following a programming operation (e.g., immediately after the programming operation), while Figure 5B It is a conceptual depiction of the distribution of those same threshold voltages at a later time after the programming operation. Figure 5A and Figure 5B Threshold voltage distribution 530 d -530 d+1 This can indicate when the programming operation of the memory cell is completed. Figure 4 The threshold voltage range is 4300-430. 15 Some parts of the distribution.

[0107] refer to Figure 5A Upon completion of programming, adjacent threshold voltage distributions 530 are typically separated by some tolerance 532 (e.g., dead space). The control gates of multiple memory cells to which a sensed voltage (e.g., a read voltage) within the tolerance 532 is applied can be used to distinguish those with threshold voltage distributions 530. d (and any lower threshold voltage distribution) memory cells with a threshold voltage distribution of 530 d+1 (And any memory cell with a higher threshold voltage distribution) is conceivable and error-free.

[0108] refer to Figure 5B The adjacent threshold voltage distributions may have been widened, resulting in a threshold voltage distribution of 530. d and threshold voltage distribution 530 d+1 They can be merged (or overlapped), as represented by curve 534, which indicates the sum of two adjacent threshold voltage distributions. Curve 534 may have local minima 536. In the case of such merging of adjacent threshold voltage distributions, the distinction is made between the given threshold voltage distribution 530. d The memory cell and the predetermined threshold voltage distribution 530 d+1 Memory cells typically generate some errors. For example, applying a sense voltage (having a voltage level corresponding to local minimum 536) to the control gate of multiple memory cells is expected to produce a minimum number of memory cells with data states other than their target (e.g., predetermined) data states, but a certain number of errors will generally be unavoidable. Applying a sense voltage higher or lower than the voltage level corresponding to local minimum 536 is expected to produce a larger number of errors. While applying a sense voltage having a voltage level corresponding to local minimum 536 of curve 534 produces a minimum number of errors, it may be difficult to determine at what voltage level this local minimum 536 occurs.

[0109] Figure 6 This is a simplified perspective, magnified view of two pillars and selected word lines according to an embodiment. For example, memory array 604 may include a first data line 6700 and a first pillar 6410 coupled to the first data line 6700. Memory array 604 may further include a second data line 6701 and a second pillar 6411 coupled to the second data line 6701. Memory array 604 may further include multiple word lines coupled to the first pillar 6410 and the second pillar 6411; only selected word lines 623 (e.g., WLn) are shown for simplified explanation. However, as... Figure 3 As shown, memory array 604 may include a plurality of pillars and a plurality of coupled word lines, with a plurality of memory cells, such as a plurality of memory cells in a group of memory cell strings, coupled between the pillars and the plurality of coupled word lines.

[0110] In at least some embodiments, to selectively erase memory cells, control logic (e.g., control logic of the local media controller 135) couples a first data line 6700 to ground (e.g., to 0 V) ​​to suppress floating of the first pillar 6410, and couples a second data line 6701 to a high voltage Vhigh (e.g., to Vdd) to allow the voltage of the second pillar 6411 to float. Simultaneously, the control logic may charge non-selected word lines to increase the channel voltage of the second pillar 6411. Figure 3A number of access lines 2200-2230 are shown, and therefore, all but one of these word lines will be considered "unselected". Additionally, the control logic can cause either a ground voltage (e.g., 0 V) ​​or a negative voltage (e.g., -Vlow, such as between -1 V and -2.5 V) to be applied to the selected word line 623, while the voltage of the second pillar 6411 remains high due to the high pillar capacitance. A pillar can connect up to tens or hundreds of NAND cells in the vertical direction, so a WL discharge will not significantly affect the pillar voltage. Furthermore, the selected cell will have a high erase polarity voltage, such as a high soft erase voltage between the channel of the selected cell and the selected word line.

[0111] In various embodiments, applying either a ground voltage or a negative voltage to the selected word line 623 may include discharging the selected word line 623 along with charging a non-selected word line, and once the non-selected word line is charged, discharging the selected word line until the ground voltage or negative voltage is applied. If a negative voltage is applied, an optional negative charge pump 692 may be used to reduce the voltage level on the selected word line 623.

[0112] In at least some embodiments, because the channel voltage of the memory cell coupled between the selected word line 623 and the second post 6411 is in erase polarity, the erase polarity causes the threshold voltage (e.g., Vt charge) stored in the memory cell to be partially erased via the second post 6411, for example, a soft erase occurs. In one embodiment, the control logic may further cause the memory cell or another memory cell coupled to the selected word line 623 to be erased in incremental step erase until the upper tail of the threshold voltage distribution is within the threshold of the bit erase verification voltage.

[0113] When erasing a memory cell, the soft erase stress between the second post 6411 and the selected word line 623 can be Vhigh - (-Vlow), or in other words, Vhigh + Vlow. Therefore, for illustrative purposes only, if Vhigh is about 8 V and -Vlow is about -2 V, the soft erase stress on the memory cell will be about 10 V. Figure 7 This is a graph illustrating the fast bit erasure of the upper tail of one of a set of highest threshold voltage distributions according to an embodiment (e.g., L15 in a QLC). The soft erase stress or voltage will be sufficient to erase at least two of the highest threshold voltage distributions of the multilevel memory cell (e.g., L6 or L7 in a TLC, and L14 or L15 in a QLC).

[0114] In these embodiments, the memory array 604 further includes a first drain select transistor 6620 coupled to a first pillar 6410 and a second drain select transistor 6621 coupled to a second pillar 6411. The memory array 604 may further include a drain select gate line 680 coupled to the gates of the first drain select transistor 6620 and the second drain select transistor 6621. Control logic may then perform an operation as part of a bit erase process, the operation including sending a drain select signal to the drain select gate line 680 to turn on the first drain select transistor 6620 and the second drain select transistor 6621.

[0115] Additionally, in these embodiments, the memory array 604 includes a first source select transistor 6660 coupled to a first pillar 6410 and a second source select transistor 6661 coupled to a second pillar 6411. The memory array 604 may further include a source select gate line 684 coupled to the gates of the first source select transistor 6660 and the second source select transistor 6661. Control logic may then perform an operation as part of a bit erase process, which includes sending a source select signal to the source select gate line 684 to turn off the first source select transistor 6660 and the second source select transistor 6661.

[0116] In at least one embodiment, the threshold voltage stored in the memory cell is erased after the programming pulse and after programming verification is performed on the memory cell. In at least another embodiment, for example, the threshold voltage stored in the memory cell is erased between the programming pulse and the programming verification performed on the memory cell.

[0117] Figure 8 This is a graph illustrating the waveform associated with performing a bit erase according to an embodiment, for example, just referenced. Figure 6-7 As discussed. For example, the waveform includes a first waveform (V) for non-selected word lines. WLs_unselect The voltage transitions from ground voltage (e.g., 0 V) ​​to a high voltage, such as Vhigh, which could be approximately 10 V. The second waveform illustrates the suppression voltage (V) in the first column 6410. channel It also transitions from ground voltage to high voltage (Vhigh). The third waveform is used for the selected word line (V). WL_select This indicates that the selected word line is held at ground voltage or pushed to a negative voltage (e.g., -Vlow). The fourth waveform is used for the soft erase voltage (erase bit V) of the second post 6411. channel The soft erase voltage transitions from ground voltage to a high voltage plus a negative voltage, for example, approximately 12 V plus Vlow. In one embodiment, the soft erase voltage is approximately 10 V. The last waveform is an optional waveform (V) for the selected word line.WL_select It can also go high with the non-selected word line before discharging to 0 V or a negative voltage (e.g., -Vlow).

[0118] Figure 9 This is a flowchart 900 illustrating operations that can be performed to execute a fast bit erase according to an exemplary embodiment. For example, these operations can be performed to perform a bit erase between a programming pulse and a programming verification performed on a memory cell. In various embodiments, the operations are explained and described with reference to non-selected word lines (WLn-1, WLn-2, ​​etc.) programmed below and before the selected word line (WLn), the selected word line (WLn) itself, and word lines (WLn+1, WLn+2, etc.) above and after the selected word line (WLn). There is also an option to program the WL from top to bottom. If programming is performed from top to bottom, WLn-1, WLn-2, ​​etc. can still be referred to as programmed WLs before the selected word line (WLn), but they will be positioned above the selected word line (WLn). Therefore, in some embodiments, n-1, n-2, ... WL can be interchanged with n+1, n+2, ... WL.

[0119] In at least some embodiments, during a first operation (e.g., Op_1), the control logic causes all word lines (WL) coupled to the first post 6410 and the second post 6411 to discharge. During a second operation (e.g., Op_2), the control logic may assert that the drain-select gate line 680 (e.g., turning on the first drain-select transistor 6620 and the second drain-select transistor 6621) will pass the power supply voltage of the second data line 6701 to the second post 6411 and the ground voltage on the first data line 6700 to the first post 6410. In the disclosed embodiments, this power supply voltage causes the voltage of the second post 6411 to float, and the ground voltage suppresses soft erases via the first data line 6700 and the first post 6410.

[0120] In at least some embodiments, during the third operation (e.g., Op_3), the control logic can cause the non-selected word line (WLn-1) located below the selected word line (WLn) to charge to a high voltage (e.g., Vhigh, which may be between 8 V and 10 V) or remain at ground voltage (e.g., 0 V). Simultaneously, the control logic can cause the remaining portion of the word line (including the selected word line (WLn) and the non-selected word line (WLn+1) located above the selected word line (WLn)) to charge to Vhigh.

[0121] Additionally, in these embodiments, during the fourth operation (e.g., Op_4), the control logic can cause the voltages previously applied to the non-selected word line (WLn-1) below the selected word line (WLn) and the non-selected word line (WLn+1) above the selected word line to be maintained, for example, maintained at 0 V and Vhigh respectively in one embodiment, or both maintained at Vhigh in another embodiment. Simultaneously, the control logic can cause the selected word line (WLn) to discharge until either a ground voltage or a negative voltage is applied, which generates a soft erase voltage between the memory cell channel and the selected word line. This soft erase voltage (e.g., erase polarity) can cause partial erasure of the memory cell's threshold voltage if it is sufficiently high.

[0122] Figure 10 This is a simplified perspective, magnified view of the two pillars and the selected letter line according to an embodiment. For example, the two pillars and the selected letter line can be a reference. Figure 6 The structural design of the memory array 604 discussed herein will not be described in further detail here. However, please refer to other references. Figure 12 The order and level of the voltages applied to the first data line 6700, the second data line 6701, the unselected word line, and the selected word line (WLn) can be changed to adjust the channel voltage (V) of the memory cell to be erased. channel The voltage rises to a still relatively high level (e.g., at or above 18 V). For example, if the channel voltage of a memory cell (V... channel The word line voltage (V) is approximately 20 V and the selected word line is... WL If the voltage is between 0 V and -2.5 V, then the target erase polarity voltage (V) is... target The voltage can be between approximately 18 V and 20 V. These higher erase voltages may be necessary to erase a portion of the lower voltage Vt distribution (e.g., to tighten the upper tail), and thus along... Figure 6-9 The method, or the method used in conjunction with the described method, is capable of erasing memory cells that contribute to most or all of the multiple threshold voltage distributions, for example... Figure 11 The QLC shown contains L0 to L15, or the PLC contains L0 to L31.

[0123] In at least some embodiments, raising the channel voltage of the memory cell to be erased to such a high voltage level presents additional challenges in avoiding programming interference on non-selected word lines. These programming interference risks can be mitigated by stepping the voltage of the non-selected word line and the channel voltage of the first pillar (or other pillars coupled to the non-selected word line) to higher voltages, since the channel voltage of the memory cell to be erased is also increased in steps, as referenced... Figure 10 and Figure 12This is discussed in detail. This ensures that the difference between the voltage of the unselected word line and the channel voltage of the selected word line (WLn) does not exceed the intermediate level voltage (V). mid The voltage difference can be approximately 8-10 volts in various embodiments.

[0124] Figure 12 This describes the execution according to the embodiments and Figure 10 A graph showing a set of waveforms associated with fast bit erasure. Therefore, please refer to the following: Figure 10 The control logic can cause multiple word lines of the memory device to discharge after a programming pulse programs one or more memory cells coupled to a selected word line 623 among the multiple word lines. Therefore, the word lines start from, for example, a ground voltage of 0 V. The control logic initially causes the non-selected word lines among the multiple word lines to charge to a first voltage level (e.g., V). mid This raises the channel voltage in the memory cell coupled to the second pillar 6411. Since the voltage on the first data line 6700 (e.g., suppressor BL) starts at 0 V, when the first drain select transistor 6620 is turned on, there is conduction between the first data line 6700 and the first pillar 6410, causing any voltage on the first pillar 6410 to also discharge to approximately 0 V. After a period of time, for example... Figure 12 The time interval between stage 1 and stage 2 shown indicates that the control logic can charge the non-selected word line to a second voltage level (V) higher than the first voltage level. higher ), for example, "V" WLs_unselect The waveform is shown. In at least some embodiments, the second voltage level is approximately twice the first voltage level.

[0125] In various embodiments, the control logic further causes a power supply voltage (e.g., VDD) to be applied to the second data line 6701 so that, after the second drain select transistor 6621 is turned on, the voltage of the second pillar 6411 floats, for example... Figure 12 "Erase bit V" BL The waveform is shown. Since the power supply voltage is applied to the second data line 6701 throughout phases 1 and 2, the channel voltage of the memory cell to be partially erased can also be stepped up to V. mid Then continue stepping to V higher For example, approximately the first voltage level and the second voltage level, for example Figure 12 "Erase bit V" channel "As shown in the waveform. In this way, the stress between the unselected WL and the suppression channel is close to the intermediate voltage V." mid This avoids programming interference to the memory cells connected to the first post 6410. If the suppressor bit post (e.g., the first post 6410) is not in V... midIn the voltage range, connecting a unit to a non-selected WL or a unit to the selected WL may cause programming or erasure interference.

[0126] In at least some embodiments, during a time period (e.g., the transition between phase 1 and phase 2), the control logic may transition to causing a power supply voltage (e.g., VDD) to be applied to the first data line 6700, and also causing the voltage of the first pillar 6410 to float, for example, "suppressing VDD". BL The waveform is shown. Because the high voltage on the first data line 6700 keeps the first drain-select transistor 6620 on, the first pillar 6410 floats. In different embodiments, this transition can cause the channel voltage of the first pillar 6410 (“suppression V”) to be lowered. channel The voltage is increased from ground to an intermediate level (e.g., Vhigher - V). mid For example, between 8 V and 10 V. Therefore, higher voltages (V) higher ) and V mid The difference between them can be related to V mid They are roughly the same, and therefore insufficient to cause programming interference on non-selected word lines.

[0127] As mentioned earlier, the control logic can also enable ground voltage (0 V) or negative voltage -V. low One of (e.g., -1 V to -2.5 V) is applied to the selected word line 623 (WLn) to increase the soft erase voltage (e.g., stress) between the channel of the memory cell coupled to the second post 6411 and the selected word line WLn. In these embodiments, this soft erase voltage causes a threshold voltage (Vt) stored in the memory cell to be partially erased, for example, via the second post 6411. As discussed, the soft erase voltage is the channel voltage (Vt). higher ) and the selected word line voltage (V WL_select The difference between the voltages, which in the current embodiment may be, for example, between about 18 V and 20 V, allows the threshold voltage within a memory cell that is in a lower Vt state to be erased.

[0128] In some embodiments, applying either a ground voltage or a negative voltage to the selected word line 623 includes charging the selected word line 623 along with charging the non-selected word line. Additionally, after a predetermined time has elapsed since charging the non-selected word line was completed (or in response to the end of charging), for example, after Vhigher (… Figure 12 ) or Vhigh ( Figure 6 After that, the selected word line 623 is discharged until either a ground voltage or a negative voltage is applied. If a negative voltage is applied, an optional negative charge pump 692 can be used to reduce the voltage level on the selected word line 623.

[0129] Figure 13 This is a simplified perspective, magnified view of the pillar coupled to the selected word line 623 and a number of non-selected word lines according to some embodiments. In these embodiments, due to the negative impact of capacitance built up when the word line-to-word line voltage difference is too large, certain restrictions can be imposed on the voltage applied to non-selected word lines adjacent to the selected word line 623, regardless of whether the non-selected word line is above or below the selected word line. Thus, for example, the non-selected word lines are charged to a second voltage (V). higher It can include retaining a subset of non-selected word lines at the first voltage (V). mid In this configuration, a subset of the non-selected word lines comprises word lines that are closely adjacent (e.g., adjacent) to the selected word line 623. In some embodiments, the subset of non-selected word lines is between two and six non-selected word lines that are closely adjacent to the selected word line 623. In one embodiment, the subset of non-selected word lines comprises four non-selected word lines that are adjacent to the selected word line 623. This allows for a level-grading of the voltage across the word lines to prevent dielectric breakdown between the word lines.

[0130] Figure 14 This is a flowchart of an example method 1400 for performing a fast bit erasure operation on one of the highest voltage threshold voltage distributions according to some embodiments. Method 1400 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, by Figure 1A-1B The control logic of the local media controller 135 executes the method 1400. Although shown in a specific order or sequence, the order of processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0131] At operation 1410, word lines are discharged. For example, the processing logic causes multiple word lines of the memory device to discharge after a programming pulse programs one or more memory cells coupled to a selected word line among the multiple word lines.

[0132] At operation 1420, a ground voltage is applied to the first data line. For example, the processing logic causes the ground voltage to be applied to the first data line to suppress soft erases via the first post coupled to the first data line and multiple word lines.

[0133] At operation 1430, a power supply voltage is applied to the second data line. For example, the processing device causes the power supply voltage to be applied to the second data line to cause a voltage fluctuation in the second post, wherein the second post is coupled to a plurality of word lines and the second data line.

[0134] At operation 1440, the non-selected word lines are charged. For example, the processing logic causes the non-selected word lines among a plurality of word lines to charge to increase the channel voltage in the memory cell coupled to the second pillar.

[0135] At operation 1450, a low voltage is applied to the selected word line. For example, the processing logic causes either a ground voltage or a negative voltage to be applied to the selected word line to increase the soft erase voltage between the channel of the memory cell coupled to the second post and the selected word line. In the disclosed embodiment, the soft erase voltage causes a threshold voltage stored in the memory cell to be partially erased, for example, via the second post.

[0136] Figure 15 This is a flowchart of an example method 1500 for performing a fast bit erasure operation on any threshold voltage distribution according to some embodiments. Method 1500 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, by Figure 1A-1B The control logic of the local media controller 135 executes the method 1500. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0137] At operation 1510, word lines are discharged. For example, the processing logic causes multiple word lines of the memory device to discharge after a programming pulse programs one or more memory cells coupled to a selected word line among the multiple word lines.

[0138] At operation 1520, the non-selected word lines are initially charged. For example, the processing logic initially causes the non-selected word lines among the plurality of word lines to be charged to a first voltage level to increase the channel voltage in the memory cell coupled to the second pillar, wherein the first pillar is coupled to the first data line, the second pillar is coupled to the second data line, and the plurality of word lines are coupled to the first pillar and the second pillar.

[0139] At operation 1530, the non-selected word line is further charged. For example, after a certain period of time, the processing logic causes the non-selected word line to be charged to a second voltage level higher than the first voltage level. This period of time can be between transitions in stages where the word line voltage is further increased.

[0140] At operation 1540, a power supply voltage is applied to the second data line. For example, control logic causes the power supply voltage to be applied to the second data line to cause a voltage fluctuation in the second pin.

[0141] At operation 1550, a ground voltage is applied to the first data line. For example, the control logic initially causes the ground voltage to be applied to the first data line to suppress soft erases via the first post.

[0142] At operation 1560, a power supply voltage is applied to the first data line. For example, during the time period, the processing logic changes to cause the power supply voltage to be applied to the first data line to also cause a voltage fluctuation in the first pillar.

[0143] At operation 1570, a low voltage is applied to the selected word line. For example, the processing logic causes either a ground voltage or a negative voltage to be applied to the selected word line to increase the soft erase voltage between the channel of the memory cell coupled to the second post and the selected word line. In the disclosed embodiment, the soft erase voltage causes a threshold voltage stored in the memory cell to be erased, for example, via the second post.

[0144] Figure 16 An example machine of computer system 1600 is shown, within which a set of instructions can be executed to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 1600 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A The memory subsystem 110), or may be used to perform controller operations (e.g., to execute an operating system, thereby executing commands corresponding to...). Figure 1A (Operation of the memory subsystem controller 115). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a client-server network environment as a server or client machine in a cloud computing infrastructure or environment.

[0145] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is shown, the term "machine" should also be considered to include any set of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any one or more of the methods discussed herein.

[0146] Example computer system 1600 includes processing device 1602, main memory 1604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 1610 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage system 1618, which communicate with each other via bus 1630.

[0147] Processing device 1602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or a combination of instruction sets. Processing device 1602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1602 is configured to execute instructions 1628 for performing the operations and steps discussed herein. Computer system 1600 may further include a network interface device 1612 communicating via network 1620.

[0148] Data storage system 1618 may include machine-readable storage medium 1624 (also referred to as computer-readable medium) on which one or more sets of instructions 1628 or software embodying any one or more methods or functions described herein are stored. Data storage system 1618 may further include the previously discussed local media controller 135, page buffer 152 or 352, and queue 131. Instructions 1628 may also reside wholly or at least partially within main memory 1604 and / or processing device 1602 during execution by computer system 1600, which also constitute machine-readable storage medium. Machine-readable storage medium 1624, data storage system 1618, and / or main memory 1604 may correspond to... Figure 1AThe memory subsystem 110.

[0149] In one embodiment, instruction 1628 includes instructions for implementing a controller (e.g., Figure 1A The memory subsystem controller 115) provides functional instructions. Although the machine-readable storage medium 1624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of storage instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing a set of instructions executable by a machine or encoding said set of instructions and causing a machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0150] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, considered as a self-consistent sequence of operations that produce the desired result. These operations are those requiring physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, quantities, etc.

[0151] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate data represented as physical (electronic) quantities in the registers and memories of the computer system and transform said data into other data similarly represented as physical quantities in the memory or registers or other such information storage systems of the computer system.

[0152] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or the apparatus may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0153] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0154] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0155] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A memory device comprising: Memory array, comprising: First data line; The first pillar is coupled to the first data line; Second data line; The second pillar, which is coupled to the second data line; and Multiple word lines, coupled to the first post and the second post; and Control logic operably coupled to the memory array, the control logic being configured to perform operations including: This causes the plurality of word lines to discharge after a programming pulse is applied to program one or more memory cells coupled to a selected word line among the plurality of word lines; This causes the power supply voltage to be applied to the second data line, resulting in a voltage fluctuation in the second pillar; This causes a ground voltage to be applied to the first data line to suppress soft erases via the first post; This causes the non-selected word lines among the plurality of word lines to charge, thereby increasing the channel voltage in the memory cell coupled to the second pillar; and This causes either the ground voltage or the negative voltage to be applied to the selected word line to increase the soft erase voltage between the channel of the memory cell coupled to the second post and the selected word line, thereby causing the threshold voltage stored in the memory cell to be partially erased.

2. The memory device of claim 1, wherein the threshold voltage stored in the memory cell facilitates the upper tail of at least two of a set of highest threshold voltage distributions of a plurality of multilevel memory cells coupled to the selected word line.

3. The memory device of claim 1, wherein the partial erasure of the threshold voltage stored in the memory cell occurs under one of the following conditions: After the programming pulse and after performing programming verification on the memory cell; or Between the programming pulse and the programming verification performed on the memory cell.

4. The memory device of claim 1, wherein the memory array further comprises: A first drain-select transistor is coupled to the first pillar; The second drain-select transistor is coupled to the second pillar; as well as A drain-select gate line is coupled to the gates of the first drain-select transistor and the second drain-select transistor; and The operation further includes sending a drain select signal to the drain select gate line to turn on the first drain select transistor and the second drain select transistor.

5. The memory device of claim 1, wherein the memory array further comprises: A first source selection transistor is coupled to the first pillar; The second source selection transistor is coupled to the second pillar; A source-select gate line is coupled to the gates of the first source-select transistor and the second source-select transistor; and The operation further includes sending a source select signal to the source select gate line to turn on the first source select transistor and the second source select transistor.

6. The memory device of claim 1, wherein applying one of the ground voltage or the negative voltage to the selected word line comprises: This causes the selected word line to be charged, along with the non-selected word line to be charged. as well as In response to completing the charging of the non-selected word line, the selected word line is discharged until one of the ground voltage or the negative voltage is applied.

7. The memory device of claim 1, wherein the operation further comprises causing another memory cell coupled to the selected word line to be partially erased in incremental step erasure until the upper tail of the threshold voltage distribution is within the threshold of the bit erase verification voltage.

8. The memory device of claim 1, further comprising a negative charge pump for applying the negative voltage to the selected word line.

9. A method for memory operations, comprising: This causes multiple word lines of the memory device to discharge after a programming pulse programs one or more memory cells coupled to a selected word line among the multiple word lines; Initially, the non-selected word lines among the plurality of word lines are charged to a first voltage level to increase the channel voltage in the memory cell coupled to the second pillar, wherein the first pillar is coupled to a first data line, the second pillar is coupled to a second data line, and the plurality of word lines are coupled to the first pillar and the second pillar; After a certain period of time, the non-selected word line is charged to a second voltage level higher than the first voltage level; This causes the power supply voltage to be applied to the second data line, resulting in a voltage fluctuation in the second pillar; Initially, a ground voltage is applied to the first data line to suppress soft erases via the first post; During the time period, the power supply voltage is applied to the first data line to cause voltage fluctuations in the first column. as well as This causes either the ground voltage or the negative voltage to be applied to the selected word line to increase the soft erase voltage between the channel of the memory cell coupled to the second post and the selected word line, thereby causing the threshold voltage stored in the memory cell to be partially erased.

10. The method of claim 9, wherein the threshold voltage stored in the memory cell facilitates the upper tail of any of a plurality of threshold voltage distributions of a plurality of multilevel memory cells coupled to the selected word line.

11. The method of claim 9, wherein the partial erasure of the threshold voltage stored in the memory cell occurs under one of the following conditions: After the programming pulse and after performing programming verification on the memory cell; or Between the programming pulse and the programming verification performed on the memory cell.

12. The method of claim 9, further comprising sending a drain select signal to a drain select line to turn on a first drain select transistor coupled to the first post and a second drain select transistor coupled to the second post.

13. The method of claim 9, further comprising sending a source select signal to a source select line to turn off a first source select transistor coupled to the first pillar and a second source select transistor coupled to the second pillar.

14. The method of claim 9, wherein applying one of the ground voltage or the negative voltage to the selected word line comprises: This causes the selected word line to be charged, along with the non-selected word line to be charged. as well as In response to completing the charging of the non-selected word line, the selected word line is charged until one of the ground voltage or the negative voltage is applied.

15. The method of claim 9, wherein charging the non-selected word lines to the second voltage comprises retaining a subset of the non-selected word lines at the first voltage, wherein the subset of the non-selected word lines includes those word lines that are closely adjacent to the selected word lines.

16. The method of claim 15, wherein the subset of the non-selected word lines is between two and six non-selected word lines.

17. A method for memory operations, comprising: This causes multiple word lines to discharge after programming one or more memory cells coupled to selected word lines among the multiple word lines with a programming pulse; This causes a ground voltage to be applied to the first data line to suppress soft erases via a first post coupled to the first data line and the plurality of word lines; This causes a power supply voltage to be applied to the second data line to cause a voltage fluctuation at the second post, which is coupled to the plurality of word lines and the first data line; This causes the non-selected word lines among the plurality of word lines to be charged to increase the channel voltage in the memory cell coupled to the second pillar; as well as This causes either the ground voltage or the negative voltage to be applied to the selected word line to increase the soft erase voltage between the channel of the memory cell coupled to the second post and the selected word line, thereby causing the threshold voltage stored in the memory cell to be partially erased.

18. The method of claim 17, wherein the threshold voltage stored in the memory cell facilitates the upper tail of at least two of a set of highest threshold voltage distributions of a plurality of multilevel memory cells coupled to the selected word line.

19. The method of claim 17, wherein the partial erasure of the threshold voltage stored in the memory cell occurs under one of the following conditions: After the programming pulse and after performing programming verification on the memory cell; or Between the programming pulse and the programming verification performed on the memory cell.

20. The method of claim 17, further comprising causing another memory cell coupled to the selected word line to be partially erased in incremental step erasure until the upper tail of the threshold voltage distribution is within the threshold of the in-bit erase verification voltage.

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