Method for manufacturing semiconductor device and semiconductor manufacturing apparatus

Abstract

Provided is a method for manufacturing a semiconductor device capable of suppressing fluctuations in the thickness of an oxide film between a plurality of SiC wafers. Also provided is a semiconductor manufacturing apparatus. After a first inorganic film is formed on the lower surfaces of a plurality of silicon carbide wafers, etching is performed on the plurality of silicon carbide wafers in such a manner that the thickness of the first inorganic film remains greater than or equal to 750 nm, and after the etching, a thermal oxidation process is performed to form an oxide film on the upper surfaces of the plurality of silicon carbide wafers. The thermal oxidation process is performed in a state in which at least one wafer, which includes at least any one of a dummy wafer or a monitor wafer, and the plurality of silicon carbide wafers are arranged in one direction with the upper surfaces of the plurality of silicon carbide wafers facing in one direction. In the state of the thermal oxidation process, a first silicon carbide wafer of the plurality of silicon carbide wafers is disposed directly below any one of the at least one wafer, and a second silicon carbide wafer of the plurality of silicon carbide wafers is disposed directly below a third silicon carbide wafer of the plurality of silicon carbide wafers.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device and a semiconductor manufacturing apparatus. Background Technology

[0002] Patent Documents 1 and 2 disclose a method for suppressing the thickness fluctuation of the oxide film between multiple silicon carbide (hereinafter also referred to as SiC) wafers when forming an oxide film on multiple SiC wafers.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2014-165348

[0004] Patent Document 2: Japanese Patent No. 6141130

[0005] Existing methods may not be sufficient for suppressing the thickness fluctuations of thermal oxide films between multiple SiC wafers. Summary of the Invention

[0006] The present invention was proposed to solve the above-mentioned problems, and its purpose is to provide a method for manufacturing a semiconductor device capable of suppressing the thickness fluctuation of oxide films between multiple SiC wafers.

[0007] The semiconductor device manufacturing method of the present invention involves forming a first inorganic film on the lower surface of a plurality of silicon carbide wafers, etching the plurality of silicon carbide wafers after the formation of the first inorganic film, etching such that the residual thickness of the first inorganic film on the plurality of silicon carbide wafers after etching is greater than or equal to 750 nm, performing a thermal oxidation process using a semiconductor manufacturing apparatus after etching to form an oxide film on the upper surface of the plurality of silicon carbide wafers, performing the thermal oxidation process in a state in which at least one wafer and the plurality of silicon carbide wafers are arranged in one direction and the upper surfaces of the plurality of silicon carbide wafers are oriented in one direction, wherein the at least one wafer includes at least one of a dumb wafer or a monitoring wafer and is different from the plurality of silicon carbide wafers, and in the state of thermal oxidation, the first silicon carbide wafer among the plurality of silicon carbide wafers is disposed directly below any one of the at least one wafer, and the second silicon carbide wafer among the plurality of silicon carbide wafers is disposed directly below the third silicon carbide wafer among the plurality of silicon carbide wafers.

[0008] The effects of the invention

[0009] According to the present invention, a method for manufacturing a semiconductor device is provided that can suppress fluctuations in the thickness of oxide films between multiple SiC wafers. Attached Figure Description

[0010] Figure 1 This is a diagram showing the vertical batch diffusion furnace of embodiment 1.

[0011] Figure 2This is a cross-sectional view showing the state of the area near the SiC wafer during thermal oxidation.

[0012] Figure 3 This is a schematic diagram illustrating the crystal structure of a SiC wafer.

[0013] Figure 4 This is a diagram showing the interior of a unit in the semiconductor device according to Embodiment 1.

[0014] Figure 5 This is a diagram showing the outer periphery of a unit in the semiconductor device of Embodiment 1.

[0015] Figure 6 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0016] Figure 7 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0017] Figure 8 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0018] Figure 9 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0019] Figure 10 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0020] Figure 11 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0021] Figure 12 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0022] Figure 13 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0023] Figure 14 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0024] Figure 15 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0025] Figure 16 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0026] Figure 17 This is a flowchart of the manufacturing method of the semiconductor device according to Embodiment 1.

[0027] Figure 18 This is a graph showing the relationship between the thickness of the interlayer insulating film formed on the C-side of the SiC wafer and the fluctuation of the thickness of the gate oxide film between SiC wafers.

[0028] Figure 19 This is a diagram showing the configuration of the wafers in Embodiment 2.

[0029] Figure 20 This is a diagram showing the vertical batch diffusion furnace of embodiment 3.

[0030] Figure 21 This is a diagram showing the vertical batch diffusion furnace of embodiment 4.

[0031] Figure 22 This is a diagram illustrating an example of a vertical batch diffusion furnace according to embodiment 5.

[0032] Figure 23 This is a diagram illustrating an example of a vertical batch diffusion furnace according to embodiment 5. Detailed Implementation

[0033] <Prerequisite Technology>

[0034] Figure 1 This is a diagram illustrating the structure of an example of a vertical batch diffusion furnace used in various embodiments, namely a vertical batch diffusion furnace 80. In the embodiments described later, for example, a vertical batch diffusion furnace 80 is used... Figure 1 The vertical batch diffusion furnace 80 shown forms an oxide film on a SiC wafer 50 that becomes a silicon carbide semiconductor device.

[0035] The vertical batch diffusion furnace 80 includes a tube 81, a crystal boat 82, and a gas introduction line 83. The crystal boat 82 has multiple support sections 82a for supporting the wafers. The tube 81 is a container for thermal oxidation treatment. In the vertical batch diffusion furnace 80, multiple wafers are supported in one direction by the multiple support sections 82a, with the main surfaces of the multiple wafers facing in one direction.

[0036] like Figure 1 As shown, in the thermal oxidation process, multiple SiC wafers 50 are supported by support portions 82a and arranged in the tube 81 with intervals between them. Hereinafter, a collection of multiple SiC wafers 50 processed simultaneously by the vertical batch diffusion furnace 80 is referred to as a batch. The gas introduction line 83 is a line for introducing oxidizing gas into the tube 81. An opening 830 is provided in the gas introduction line 83, through which the oxidizing gas is introduced into the tube 81. The oxidizing gas is a gas used in the thermal oxidation process, such as oxygen (O2) or ozone (O3).

[0037] For example, in the case of SiC wafer 50, one main surface is a carbon (C) surface and the other main surface is a silicon (Si) surface.

[0038] exist Figure 1 An example of the configuration of the SiC wafer 50 during thermal oxidation is shown.

[0039] The SiC wafer 50 is held in the boat 82 with the carbon (C) side facing down and the silicon (Si) side facing up. The SiC wafers 50 are stacked with gaps between each other in a direction that intersects with the main surface of the SiC wafer 50, for example, in a direction perpendicular to the main surface of the SiC wafer 50.

[0040] Before thermal oxidation, an inorganic film 90 is formed on the lower surface (C-surface 12) of each SiC wafer 50 (see reference). Figure 2 and Figure 3 ).

[0041] Above the topmost SiC wafer 50, a SiC dummy wafer 51 is disposed at a distance from the topmost SiC wafer 50. Above the SiC dummy wafer 51, a Si monitoring wafer 52 is disposed at a distance from the SiC dummy wafer 51.

[0042] On the lower surface of the SiC dummy wafer 51, with Figure 2 Similarly, an inorganic film 90 is formed on the lower surface of the SiC wafer 50. The reason for setting up the SiC dummy wafer 51 will be explained later.

[0043] By measuring the thickness of the oxide film on the Si monitoring wafer 52 after the thermal oxidation process, it is possible to confirm whether there are any problems with the oxide film formed on each SiC wafer 50.

[0044] The thermal oxidation reaction at SiC wafer 50, when O2 is used as the oxidizing gas, is presumably represented by the following equation (1). In the equations shown below, "(↑)" refers to the generated gas.

[0045] SiC + 2O₂ = SiO₂ + CO₂ (↑)...(1)

[0046] As shown in equation (1), in the thermal oxidation reaction at SiC wafer 50, a silicon dioxide (SiO2) film is formed and carbon dioxide (CO2) gas is generated. It is assumed that the generated CO2 gas is reversibly decomposed in the high-temperature environment inside tube 81, undergoing the reaction shown in equation (2), thereby releasing carbon monoxide (CO) gas and generating O2 gas again.

[0047] 2CO2=2CO(↑)+O2(↑)…(2)

[0048] Figure 2 This is a cross-sectional view showing the state of the SiC wafer near 50 during thermal oxidation. Figure 3 This is a schematic diagram illustrating the crystal structure of a SiC wafer 50.

[0049] like Figure 3 As shown, the crystal structure of the SiC wafer 50 is composed of silicon (Si) atoms 45 and carbon (C) atoms 46. One main surface of the SiC wafer 50 is the C surface 12 with exposed C atoms 46, and the other main surface is the Si surface 13 with exposed Si atoms 45.

[0050] like Figure 2 As shown, when O2 gas is supplied to the SiC wafer 50 to form an oxide film 5a, CO2 gas is generated through the reaction of formula (1). Figure 3 As shown, the C-side 12 of the SiC wafer 50 has 46 more C atoms than the Si-side 13. Therefore, it can be inferred that the C-side 12 produces more CO2 gas compared to the Si-side 13.

[0051] As described above, an inorganic film 90 is formed on the C-surface 12 of the SiC wafer 50. The inorganic film 90 provided on the C-surface 12 of the SiC wafer 50 has the effect of suppressing the reaction (1) at the C-surface 12 of the SiC wafer 50. When the inorganic film 90 is thin, the effect of suppressing the reaction of the aforementioned formula (1) is small, and therefore the degree of suppression of the reaction of formula (2) is small. Directly below the C-surface 12 of the SiC wafer 50, the effect of increasing the oxygen concentration through the reaction of formula (2) is large. Therefore, as Figure 2 As shown, when the C-surface 12 of the SiC wafer 50 faces the Si-surface 13 of the adjacent SiC wafer 50, it is conceivable that the oxide film 5a formed by thermal oxidation at the Si-surface 13 of the SiC wafer 50 directly below the SiC wafer 50 becomes thicker. Furthermore, the effect of oxygen generated by the reaction in (2) varies depending on its position within the wafer surface, thus the degree of oxidation reaction becomes uneven within the surface. Therefore, it is conceivable that the thickness of the oxide film 5a formed by thermal oxidation at the SiC wafer 50 directly below the SiC wafer 50 varies depending on its position within the surface.

[0052] exist Figure 1 In this configuration, it is conceivable that the inorganic film 90 is formed on the C-side 12 of the SiC wafer 50, and no SiC dummy wafer 51 is placed between the Si monitoring wafer 52 and the SiC wafer 50. That is, in Figure 1In this case, it is conceivable that a SiC wafer 50 is also placed at the position of the SiC dummy wafer 51. Since the reaction of formula (1) does not occur at the Si monitoring wafer 52, the reaction of formula (2) will not occur and O2 gas will not be generated due to the presence of the Si monitoring wafer 52. In this case, the oxide film 5a formed by thermal oxidation is thinner at the SiC wafer 50 directly below the SiC monitoring wafer 52 compared to the case of the SiC wafer 50 directly below the SiC wafer 50. Thus, the thickness of the oxide film 5a formed on the upper surface of the SiC wafer 50 becomes uneven among the SiC wafers 50 in the batch.

[0053] like Figure 1 As shown, by setting a SiC dummy wafer 51 with an inorganic film 90 formed on the C-surface 12 between the Si monitoring wafer 52 and the SiC wafer 50, it is possible to suppress the unevenness of the thickness of the oxide film 5a formed by thermal oxidation treatment among the SiC wafers 50 in a batch.

[0054] An inorganic film 90 is formed on the C-surface 12 of the SiC dummy wafer 51. The inorganic film 90 on the C-surface 12 of the SiC dummy wafer 51 has, for example, the same thickness as the inorganic film 90 on the C-surface 12 of the SiC wafer 50. In this case, since an equal amount of CO2 gas is generated from the C-surface 12 of the SiC dummy wafer 51 as from the C-surface 12 of the SiC wafer 50, it is possible to suppress the unevenness in the thickness of the oxide film 5a formed by the thermal oxidation process between SiC wafers 50 in a batch.

[0055] However, by repeatedly using the SiC dummy wafer 51, a thick thermal oxide film is formed on the C-surface 12 of the SiC dummy wafer 51, and the inorganic film 90 becomes thicker. Therefore, the amount of O2 generated at the C-surface 12 of the SiC dummy wafer 51 is less than that at the C-surface 12 of the SiC wafer 50. The oxide film 5a formed by thermal oxidation on the upper surface of the SiC wafer 50 directly below the SiC dummy wafer 51 is thinner than the oxide film 5a formed by thermal oxidation on the upper surface of the SiC wafer 50 directly below the SiC wafer 50. As a result, the thickness of the oxide film 5a formed by thermal oxidation becomes uneven among the SiC wafers 50 in the batch.

[0056] As will be described later, in the semiconductor device manufacturing method of embodiments 1 to 5, during the thermal oxidation process, since a thick inorganic film 90 is formed on the C surface 12 of the SiC wafer 50, the unevenness of the thickness of the oxide film 5a formed by the thermal oxidation process among the SiC wafers 50 in the batch is suppressed.

[0057] In the above description, the description is based on the presumption that the reaction is caused by Formula (1) and Formula (2). However, the effects of the method for manufacturing a semiconductor device according to Embodiments 1 to 5 are not limited to suppressing the influence caused by the reactions of Formula (1) and Formula (2). The environment on the upper side of a certain SiC wafer 50 may vary depending on whether the wafer on the upper side of the SiC wafer 50 is a Si monitoring wafer 52, a SiC dummy wafer 51, or a SiC wafer 50. In the method for manufacturing a semiconductor device according to Embodiments 1 to 5, it is possible to suppress the thickness unevenness of the oxide film 5a formed by thermal oxidation treatment among the SiC wafers 50 within a batch caused by such environmental changes.

[0058] <A. Embodiment 1>

[0059] <A-1. Structure>

[0060] By the method for manufacturing a silicon carbide semiconductor device according to the present embodiment, for example, MOSFETs, pn diodes, SBDs (Schottky Barrier diodes), BJTs (Bipolar Junction Transistors), JFETs (Junction FETs), or IGBTs (Insulated Gate Bipolar Transistors) are manufactured.

[0061] Hereinafter, description will be given on the assumption that the semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device according to the present embodiment is the MOSFET 100 shown in Figure 4 and Figure 5 . Figure 4 shows the inside of a cell of the MOSFET 100. Figure 5 shows the cell periphery of the MOSFET 100. In the following description, the conductivity types of the semiconductor layers may be interchanged.

[0062] As shown in Figure 4 and Figure 5 , the MOSFET 100 comprises a SiC substrate 1, a SiC drift layer 2, a base region 3, a source region 4, a gate oxide film 5, a gate wiring 6, a source electrode 7, a drain electrode 8, an interlayer insulating film 9, and a gate electrode 10.

[0063] The upper surface of the SiC substrate 1 is a Si surface. In addition, the SiC substrate 1 is a single-crystal n-type substrate having a 4H crystal structure.

[0064] The SiC drift layer 2 is formed on the upper surface of the SiC substrate 1.

[0065] The base region 3 is selectively formed in the surface layer portion of the upper surface of the SiC drift layer 2. The base region 3 is a p-type semiconductor layer, and contains, for example, aluminum (Al) as a p-type impurity.

[0066] The source region 4 is selectively formed in the surface layer portion of the upper surface of the base region 3 inside the cell. The source region 4 is an n-type semiconductor layer. The source region 4 contains, for example, nitrogen (N) as an n-type impurity.

[0067] The gate oxide film 5 is formed across the source region 4, the base region 3, and the region 2a between two adjacent source regions 4 in the SiC drift layer 2. A gate wiring 6 is formed on the gate oxide film 5. In addition, a drain electrode 8 is formed on the lower surface of the SiC substrate 1, that is, the C-plane. The gate wiring 6 and the source electrode 7 are separated by an interlayer insulating film 9. The gate wiring 6 is led from the inside of the cell to the outer periphery of the cell, and is connected to the gate electrode 10 at the outer periphery of the cell.

[0068] in Figure 4 it is shown that the MOSFET 100 has a planar gate structure, but the MOSFET 100 may also be of a trench gate type.

[0069] <A-2. Manufacturing Method>

[0070] Figure 17 is a flow chart of the manufacturing method of the semiconductor device of the present embodiment.

[0071] Figures 6-11 is a cross-sectional view showing a state in the middle of manufacturing the MOSFET 100. Hereinafter, according to Figures 6-11 the manufacturing process of the MOSFET will be described. Figure 6 is a diagram corresponding to both the inside of the cell and the outer periphery of the cell. Figures 7-9 , 11, 13 and 15 are diagrams corresponding to the inside of the cell. Figure 10 , 12 , 14 and 16 are diagrams corresponding to the outer periphery of the cell.

[0072] First, in step S1, a silicon carbide substrate 1 is prepared.

[0073] Next, in step S2, the SiC drift layer 2 is epitaxially grown on the upper surface of the silicon carbide substrate 1 by CVD (refer to Figure 6 ). The n-type impurity concentration of the SiC drift layer 2 is 1×10 15 cm -3 to 1×10 17 cm -3 , and the thickness is 5 to 50 μm.

[0074] Next, in step S3, a mask 41 is formed on the upper surface of the SiC drift layer 2, and Al, as a p-type impurity, is implanted into the SiC drift layer 2 using the mask 41 (see reference). Figure 7 At this point, the depth of Al ion implantation is approximately 0.5–3 μm, not exceeding the thickness of the SiC drift layer 2. Furthermore, the impurity concentration of the ion-implanted Al falls within 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 Within this range, the concentration of n-type impurities is higher than that of SiC drift layer 2. The region in SiC drift layer 2 where Al ions have been implanted and transformed into p-type forms the base region 3. After Al ion implantation, mask 41 is removed.

[0075] Then, in step S3, after removing the mask 41, a mask 42 is formed on the upper surface of the SiC drift layer 2, and ions are implanted into the surface portion of the SiC drift layer 2 using the mask 42 as an n-type impurity (see reference). Figure 8 In step S3, the region in SiC drift layer 2 where Al ions were implanted in step S3 is also included and referred to as SiC drift layer 2. The depth of N ion implantation is shallower than the thickness of the base region 3. Furthermore, the impurity concentration of N during ion implantation falls below 1 × 10⁻⁶. 18 cm -3 ~1×10 21 cm -3 Within the range, the p-type impurity concentration exceeds that of the base region 3. The n-type region within the N-implanted SiC drift layer 2 becomes the source region 4. After N ion implantation, the mask 42 is removed.

[0076] Next, in step S4, the N and Al implanted in step S3 are activated by annealing at 1300-1900°C for 30 seconds to 1 hour in an inert gas environment such as argon (Ar) using a heat treatment device.

[0077] Next, in step S5, an interlayer insulating film formation process is performed to form the interlayer insulating film 9 by CVD (see reference). Figure 9 and Figure 10When the gate wiring 6, formed through subsequent processes, is wound to the outer periphery of the cell and connected to the gate electrode 10, it is insulated from the gate wiring 6 by the interlayer insulating film 9, the SiC drift layer 2, the base region 3, and the source region 4. Preferably, the thickness of the interlayer insulating film 9 is 1–3 μm to avoid affecting the gate capacitance and to prevent damage from switching and surges. The inorganic film, i.e., the interlayer insulating film 9, is made of materials such as BPSG (Boro-Phospho Silicate Glass), PSG (Phospho Silicate Glass), or TEOS (Tetraethylorthosilicate). Figure 8 The structure shown consists of a SiC substrate 1, a SiC drift layer 2, a base region 3, and a source region 4. Figure 1 The SiC wafer 50 is equivalent to this. Additionally, the interlayer insulating film 9 is similar to... Figure 2 The inorganic membrane is equivalent to 90%.

[0078] Interlayer insulating film 9 is formed on the upper surface of SiC wafer 50, namely Si surface 13 (i.e., the main surface on the side of source region 4) and the lower surface, namely C surface 12 (i.e., the main surface on the side of the lower surface of SiC substrate 1). The interlayer insulating film 9 on C surface 12 is an example of a first inorganic film, and the interlayer insulating film 9 on Si surface 13 is an example of a second inorganic film.

[0079] Next, in step S6, an etching process is performed. In the etching process of step S6, through patterning, dry etching, and wet etching, the interlayer insulating film 9 on the Si surface 13 side is removed inside the cell, and the interlayer insulating film 9 at the desired position on the Si surface 13 side is also removed at the outer periphery of the cell (see reference). Figure 9 and Figure 10 ).

[0080] In step S6, the interlayer insulating film 9 on the Si surface 13 side is etched. However, according to the etching method, the interlayer insulating film 9 on the C surface 12 side of the SiC wafer 50 is also etched, resulting in a thinner interlayer insulating film 9 on the C surface 12 side of the SiC wafer 50. In subsequent steps, it is preferable that the thickness of the interlayer insulating film 9 on the C surface side of the SiC wafer 50 is greater than or equal to 0.75 μm, i.e., greater than or equal to 750 nm. Therefore, in this embodiment, the etching process in step S6 is performed such that, after the etching in step S6, the remaining interlayer insulating film 9 on the C surface 12 side of the SiC wafer 50 is greater than or equal to 0.75 μm. The reasons why it is preferable that the remaining interlayer insulating film 9 on the C surface 12 side of the SiC wafer 50 is greater than or equal to 0.75 μm after the etching in step S6 will be explained later. After etching in step S6, the thickness of the interlayer insulating film 9 remaining on the C-side 12 of the SiC wafer 50 can be greater than or equal to 1.2 μm, or greater than or equal to 1.6 μm.

[0081] In step S6, for example, the residual thickness of the interlayer insulating film 9 on the C-side of the SiC wafer 50 at the central portion when viewed from above is greater than or equal to 0.75 μm. Furthermore, in step S6, for example, the residual thickness of the interlayer insulating film 9 is greater than or equal to 0.75 μm across the entire C-side of the SiC wafer 50. Additionally, in step S6, for example, the average residual thickness of the interlayer insulating film 9 on the C-side of the SiC wafer 50 is greater than or equal to 0.75 μm. Here, the average thickness of the interlayer insulating film 9 refers to the average of the thicknesses measured at a large number of points, for example, greater than or equal to 100, evenly distributed points within the surface of the SiC wafer 50.

[0082] For example, as a method to ensure that the interlayer insulating film 9 on the C-side 12 of the SiC wafer 50 has a residual thickness greater than or equal to 0.75 μm after etching in step S6, examples include forming a thicker interlayer insulating film 9 on the C-side 12 of the SiC wafer 50 beforehand, or forming a protective film on the interlayer insulating film 9 on the C-side 12 of the SiC wafer 50 before step S6 to make it difficult to etch the interlayer insulating film 9 on the C-side 12 of the SiC wafer 50. For example, if wet etching by immersion is performed in step S6 without forming a protective film, not only the interlayer insulating film 9 on the Si-side 13 is etched, but the interlayer insulating film 9 on the C-side 12 is also etched. By performing wet etching via immersion after forming a protective film on the interlayer insulating film 9 on the C-side 12 of the SiC wafer 50, costs can be reduced, and the interlayer insulating film 9 on the C-side 12 of the SiC wafer 50 can, for example, remain at a thickness greater than or equal to 0.75 μm.

[0083] Next, in step S7, thermal oxidation is performed, such as... Figure 11 and Figure 12 As shown, a thermal oxide film, namely a gate oxide film 5, is formed in the region on the upper surface of the SiC wafer 50 where the interlayer insulating film 9 is not formed. In this thermal oxidation process, as described above, an oxidizing gas, such as O2 or O3, is used. The gate oxide film 5 and... Figure 2 The oxide film in 5a is equivalent. Figure 2 An inorganic film 90 is shown on the lower surface of the SiC wafer 50, and an oxide film 5a is shown on the upper surface of the SiC wafer 50. However, in step S7 of this embodiment, an interlayer insulating film 9 may also be formed on a portion of the upper surface of the SiC wafer 50.

[0084] The details of step S7 will be explained below. In step S7, by using... Figure 1 The vertical batch diffusion furnace 80 shown performs thermal oxidation treatment on SiC wafer 50 to form gate oxide film 5.

[0085] In step S7, firstly, a SiC wafer 50 with a residual interlayer insulating film 9 of greater than or equal to 0.75 μm on the C-surface 12 is formed. Figure 1 The arrangement shown is within a vertical batch diffusion furnace 80. The SiC wafer 50 and the SiC dummy wafer 51 are configured with their C-surface 12 facing downwards. Furthermore, in... Figure 1 The illustration of interlayer insulating film 9 is omitted.

[0086] Next, the Si surface 13 of the SiC wafer 50 is thermally oxidized at a temperature greater than or equal to 1200°C and less than or equal to 1300°C, forming a thermal oxide film on the Si surface 13 of the SiC wafer 50. At this time, a thermal oxide film, namely a gate oxide film 5, is formed in the region of the Si surface 13 of the SiC wafer 50 where the interlayer insulating film 9 is not formed (i.e., the region where the interlayer insulating film 9 is removed in step S6). The thicker the interlayer insulating film 9 remaining on the C surface 12 side of the SiC wafer 50, the more O2 gas is blocked by the interlayer insulating film 9 and it is difficult for it to reach the C surface 12. Therefore, the amount of O2 gas generated from the C surface 12 by the above reactions (1) and (2) is reduced, and it is difficult for an oxidation reaction caused by this O2 gas to occur at the SiC wafer 50 directly below the SiC wafer 50.

[0087] use Figure 18 The thickness of the gate oxide film 5 formed in step S7 will be described in detail. Figure 18 This is a graph showing the relationship between the thickness of the interlayer insulating film 9 formed on the C-side 12 of the SiC wafer 50 and the fluctuation of the thickness of the gate oxide film 5 between the SiC wafers 50. Figure 18 The horizontal axis represents the average thickness of the interlayer insulating film 9 formed on the C-surface 12 of a SiC wafer 50. Figure 18The horizontal axis represents the thickness of the interlayer insulating film 9 formed on the C-side 12 of a representative SiC wafer 50, but each SiC wafer 50 in the batch has an interlayer insulating film 9 of approximately the same thickness formed on its C-side 12. Figure 18 The vertical axis represents the difference between the maximum and minimum thicknesses of the gate oxide film 5 formed on the Si surface 13 of each SiC wafer 50 within the batch during the thermal oxidation treatment in step S7. Figure 18 In this document, the measured values ​​are the results obtained from actual thermal oxidation treatment, while the calculated values ​​are the results obtained from numerical simulation. Among the SiC wafers 50 in the batch, the SiC wafer 50 directly below the SiC dummy wafer 51 has the thinnest gate oxide film 5 formed on the Si surface 13.

[0088] Figure 18 The result shown is using Figure 1 The result is obtained during thermal oxidation in the vertical batch diffusion furnace 80 shown. In this thermal oxidation process, a gate oxide film 5 of approximately 45-50 nm is formed on the upper surface of a 4-inch SiC wafer 50. Before this thermal oxidation process, an interlayer insulating film 9 of sufficient thickness, considered to be sufficient to prevent the generation of O2 gas through formulas (1) and (2), is formed on the C-side 12 of the SiC dummy wafer 51. The inorganic film, i.e., the interlayer insulating film 9, is formed on the C-side 12 of the SiC dummy wafer 51 to be thicker than the interlayer insulating film 9 formed on the C-side 12 of each SiC wafer 50 in the batch.

[0089] like Figure 18 As shown, the thicker the interlayer insulating film 9 formed on the C-surface 12 of the SiC wafer 50, the smaller the variation in the thickness of the gate oxide film 5 formed in step S7 between SiC wafers 50 within a batch. This can be attributed to the fact that the thicker the interlayer insulating film 9 formed on the C-surface 12 of the SiC wafer 50, the better it can suppress the generation of O2 gas from the C-surface 12 of the SiC wafer 50 caused by the reactions shown in equations (1) and (2).

[0090] During step S7, since an interlayer insulating film 9 of sufficient thickness to prevent the generation of O2 gas through formulas (1) and (2) is formed on the SiC dummy wafer 51, even when the SiC dummy wafer 51 is not set and the Si monitoring wafer 52 is directly above the SiC wafer 50, a similar effect will be obtained. Figure 18The same result is achieved. That is, by setting the thickness of the interlayer insulating film 9 on the C-side 12 of the SiC wafer 50 to be greater than or equal to 0.75 μm, fluctuations in the thickness of the gate oxide film 5 between SiC wafers 50 within a batch are suppressed even without the SiC dumb wafer 51. Therefore, by setting the thickness of the interlayer insulating film 9 on the C-side 12 of the SiC wafer 50 to be greater than or equal to 0.75 μm, it is also possible to achieve the same result. Figure 1 SiC wafer 50 is placed at the position where SiC dummy wafer 51 is placed.

[0091] As described above, through in-depth research, it has been newly discovered that if the thickness of the interlayer insulating film 9 remaining on the lower surface of the SiC wafer 50 is set to be greater than or equal to 0.75 μm in step S6, the difference in thickness of the gate oxide film 5 formed in step S7 between SiC wafers 50 in a batch can be suppressed to be less than or equal to 0.8 nm.

[0092] Furthermore, if the interlayer insulating film 9 on the C-plane 12 of the SiC wafer 50 is thin, the thickness of the interlayer insulating film 9 on the C-plane 12 of the SiC wafer 50 will be uneven in-plane. Therefore, the deviation of O2 generation with the in-plane position will increase, and the in-plane uniformity of the gate oxide film 5 of the SiC wafer 50 directly below the SiC wafer 50 will deteriorate. If the residual interlayer insulating film 9 of the SiC wafer 50 is greater than or equal to 0.75 μm, the generation of O2 gas can be suppressed, and thus the in-plane uniformity of the gate oxide film 5 formed on the Si-plane 13 of the SiC wafer 50 directly below the SiC wafer 50 will be improved.

[0093] If the thickness of the interlayer insulating film 9 on the C-side 12 of the SiC wafer 50 is set to be greater than or equal to 1.2 μm, the thickness difference of the gate oxide film 5 between SiC wafers 50 in a batch can be suppressed to be less than or equal to 0.3 nm. If the thickness of the interlayer insulating film 9 on the C-side 12 of the SiC wafer 50 is set to be greater than or equal to 1.6 μm, the thickness difference of the gate oxide film 5 between SiC wafers 50 in a batch can be suppressed to be less than or equal to 0.1 nm. Therefore, it is more preferable to leave 1.2 μm of the interlayer insulating film 9 in step S6, and even more preferable to leave 1.6 μm of the interlayer insulating film 9 in step S6.

[0094] In step S7, after the thermal oxide film is formed, it is used to... Figure 1 The same wafer configuration is used to perform post-annealing to reduce the interface states at the SiO2-SiC interface. Post-annealing is performed in oxidizing gas environments such as humid (WET), nitrogen oxide (NO or N2O), and POCl3, or reducing gas environments such as H2 or NH3.

[0095] Next, in step S8, gate wiring 6 is formed on the gate oxide film 5. After forming a conductive polycrystalline silicon film by depressurized CVD, the gate wiring 6 is formed by patterning the polycrystalline silicon film. Then, an interlayer insulating film 9 with a thickness of about 1.0 to 3.0 μm is additionally formed using a CVD apparatus to cover the gate wiring 6.

[0096] Next, in step S9, the interlayer insulating film 9 and the polysilicon film on the lower surface of the SiC wafer 50 are removed by wet etching or dry etching. Thus, a... Figure 13 and Figure 14 The state shown.

[0097] Next, in step S10, the source electrode 7 and the gate electrode 10 are formed.

[0098] In step S10, firstly, the interlayer insulating film 9 in the region where the source electrode 7 is formed is removed by patterning and dry etching. Additionally, after a silicide layer is formed in the region where the source electrode 7 is formed, the interlayer insulating film 9 in the region that makes contact with the gate wiring 6 is removed by patterning and dry etching (see reference). Figure 15 and Figure 16 Next, a source electrode 7 electrically connected to the source region 4 and a gate electrode 10 electrically connected to the gate wiring 6 are formed. After an Al alloy film is deposited on the upper surface of the SiC wafer 50 by sputtering, the film is shaped by patterning and wet etching to form the source electrode 7 and the gate electrode 10.

[0099] Next, in step S11, a drain electrode 8 is formed on the lower surface side of the SiC wafer 50. The material of the drain electrode 8 is, for example, an Al alloy.

[0100] After the above steps, the process is complete. Figure 4 and Figure 5 The vertical MOSFET 100 is shown.

[0101] If the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1 described above is summarized, it is as follows. A plurality of SiC wafers 50 are prepared, an interlayer insulating film 9 serving as a first inorganic film is formed on the lower surfaces of the plurality of SiC wafers 50, and after forming the first inorganic film, etching of the plurality of SiC wafers 50 is performed. The etching is performed such that the thickness of the first inorganic film of the plurality of SiC wafers 50 remains 0.75 µm or more after the etching. Next, in step S7, thermal oxidation treatment is performed using a vertical batch diffusion furnace 80 to form a gate oxide film 5 on the upper surfaces of the plurality of SiC wafers 50. The thermal oxidation treatment is performed in a state where at least one wafer and the plurality of SiC wafers 50 are arranged along one direction, with the upper surfaces of the plurality of SiC wafers 50 oriented in one direction, wherein the at least one wafer includes at least any one of a Si monitoring wafer 52 or a SiC dummy wafer 51 and is different from the plurality of SiC wafers 50. In the state of the thermal oxidation treatment, a first SiC wafer 50 among the plurality of SiC wafers 50 is arranged directly below any one of the at least one wafer including at least any one of the Si monitoring wafer 52 or the SiC dummy wafer 51, and a second SiC wafer 50 among the plurality of SiC wafers 50 is arranged directly below a third SiC wafer 50 among the plurality of SiC wafers 50.

[0102] In step S7, by setting the thickness of the interlayer insulating film 9 on the C-plane 12 side of the SiC wafer 50 to 0.75 µm or more, gas generated from the C-plane 12 of the SiC wafer 50 is suppressed, so the thickness of the gate oxide film 5 is uniformized among the SiC wafers 50 in the batch. In addition, since the gas generated from the C-plane 12 of the SiC wafer 50 is suppressed, it is also possible to omit the arrangement of the SiC dummy wafer 51.

[0103] The same structure as step S7 of the manufacturing method of the present embodiment can also be applied to other processes in which heat treatment is performed in a batch-type apparatus, such as a heat treatment process for metal electrodes. In addition, the same structure as step S7 can also be applied to processes for forming an oxide film other than the gate oxide film 5.

[0104] <B. Embodiment 2>

[0105] Figure 19 is a diagram showing the method for arranging wafers in the vertical batch diffusion furnace 80 in step S7 (see Figure 17 ) of the manufacturing method of the semiconductor device according to Embodiment 2. In step S7 of the present embodiment, SiC wafers 50 and Si dummy wafers 51a are alternately arranged on a wafer boat 82. Other than that, the manufacturing method of the semiconductor device according to the present embodiment is the same as the manufacturing method of the semiconductor device according to Embodiment 1.

[0106] By Figure 19A wafer is configured in such a manner that diffusion of O₂ gas generated from the C-plane 12 of the SiC wafer 50 is blocked by a Si dummy wafer 51a disposed directly thereunder. The amount of O₂ gas that diffuses to other SiC wafers 50 is reduced. Therefore, oxidation caused by O₂ gas generated from the C-plane 12 of another SiC wafer 50 is less likely to occur in the SiC wafer 50 directly under the Si dummy wafer 51a, and variation in the thickness of the gate oxide film 5 among SiC wafers 50 in a batch is suppressed.

[0107] Furthermore, since generation of O₂ gas can be suppressed, in-plane uniformity of the thickness of the gate oxide film 5 formed on the Si-plane 13 of each SiC wafer 50 in a batch in step S7 is improved. Instead of the Si dummy wafer 51a, another dummy wafer that hardly generates O₂ gas on its lower surface and hardly causes uneven oxidation reaction to the SiC wafer 50 directly thereunder can be used. Said another dummy wafer is, for example, a SiC dummy wafer 51 having an inorganic film with a thickness greater than or equal to 0.75 μm formed on the lower surface thereof.

[0108] If the interlayer insulating film 9 with a thickness greater than or equal to 0.75 μm remains on the lower surface of the SiC wafer 50, the amount of O₂ gas generated from the lower surface of the SiC wafer 50 in step S7 is reduced, so the amount of O₂ gas that bypasses the Si dummy wafer 51a and diffuses to other SiC wafers 50 is also reduced, and variation in the thickness of the gate oxide film 5 among SiC wafers 50 in a batch can be suppressed with higher accuracy.

[0109] <C. Embodiment 3>

[0110] Figure 20 is a diagram showing the structure of a vertical batch-type diffusion furnace 80c used in the present embodiment. Compared with the method for manufacturing a semiconductor device according to Embodiment 1, the method for manufacturing a semiconductor device of the present embodiment is different in that in step S7 (see Figure 17 ), a vertical batch-type diffusion furnace 80c is used instead of the vertical batch-type diffusion furnace 80. In Figure 20 , a case where no SiC dummy wafer 51 is used is shown, but in the present embodiment, similarly to the case of Embodiment 1, a SiC dummy wafer 51 may be disposed between a Si monitor wafer 52 and a SiC wafer 50. Other than that, the method for manufacturing a semiconductor device of the present embodiment is the same as that of Embodiment 1.

[0111] Compared with the vertical batch-type diffusion furnace 80 used in Embodiments 1 and 2, the vertical batch-type diffusion furnace 80c of the present embodiment includes a support portion 82b instead of the support portion 82a. Other than that, the vertical batch-type diffusion furnace 80c is the same as the vertical batch-type diffusion furnace 80.

[0112] In the vertical batch diffusion furnace 80 according to Embodiment 1, the support portions 82a of the wafer boat 82 are claw-shaped, only the end portions of the wafer are in contact with the support portions 82a, and the wafer is supported by the support portions 82a in a state where the central portion does not overlap with the support portions 82a in a top view.

[0113] On the other hand, in the vertical batch diffusion furnace 80c of the present embodiment, the support portions 82b are plate-shaped. A SiC wafer 50 is placed on the plate-shaped support portion 82b with its C-face 12 facing downward. The SiC wafer 50 is placed on the plate-shaped support portion 82b, for example, in such a manner that the entire wafer overlaps the plate-shaped support portion 82b in a top view. The SiC wafer 50 is placed on the plate-shaped support portion 82b, for example, in a state where a part of the SiC wafer 50 including the center in top view or the entire SiC wafer 50 in top view is in contact with the support portion 82b.

[0114] In the vertical batch diffusion furnace 80c, a certain SiC wafer 50 and the SiC wafer 50 directly below the certain SiC wafer 50 are separated from each other by the plate-shaped support portion 82b. Therefore, the diffusion of O₂ gas generated from the C-face 12 of the certain SiC wafer 50 through the reactions of formula (1) and formula (2) to the SiC wafer 50 directly below it is suppressed, and excessive occurrence of oxidation reaction caused by O₂ gas in the SiC wafer 50 directly below the certain SiC wafer 50 can be suppressed. In the vertical batch diffusion furnace 80c, for example, adjacent SiC wafers 50 are each separated from each other by the plate-shaped support portions 82b.

[0115] In this way, by using the vertical batch diffusion furnace 80c, variation in the thickness of the gate oxide film 5 among SiC wafers 50 in a batch can be suppressed. Furthermore, since the influence of O₂ gas generated through the reactions of formula (1) and formula (2) can be suppressed, the in-plane uniformity of the thickness of the gate oxide film 5 formed on the Si-face 13 of each SiC wafer 50 in the batch is improved.

[0116] If in step S6 (see Figure 17 ), the interlayer insulating film 9 of 0.75 µm or more remains on the lower surface of the SiC wafer 50, then in step S7 (see Figure 17 ), the amount of O₂ gas generated from the lower surface of the SiC wafer 50 is reduced. Therefore, less O₂ gas diffuses by bypassing the plate-shaped support portions 82b, and variation in the thickness of the gate oxide film 5 among SiC wafers 50 in a batch can be suppressed with higher accuracy.

[0117] <D. Embodiment 4>

[0118] Figure 21This diagram illustrates the structure of the vertical batch diffusion furnace 80d used in this embodiment. The semiconductor device manufacturing method of this embodiment differs from the semiconductor device manufacturing method of Embodiment 1 in that step S7 (refer to…) Figure 17 The vertical batch diffusion furnace 80d is used instead of the vertical batch diffusion furnace 80. Figure 21 The illustration shows a case where the SiC dummy wafer 51 is not used, but in this embodiment, the SiC dummy wafer 51 can also be disposed between the Si monitoring wafer 52 and the SiC wafer 50 in the same manner as in Embodiment 1. Apart from this, the semiconductor device manufacturing method of this embodiment is the same as that of Embodiment 1.

[0119] Compared to the vertical batch diffusion furnace 80 used in embodiments 1 and 2, the vertical batch diffusion furnace 80d of this embodiment also has a partition 84. Otherwise, the vertical batch diffusion furnace 80d is the same as the vertical batch diffusion furnace 80.

[0120] In the vertical batch diffusion furnace 80d, wafers supported by a certain support portion 82a and wafers supported by support portions 82a of adjacent layers are separated by partitions 84. In the vertical batch diffusion furnace 80d, for example, adjacent SiC wafers 50 are each separated by partitions 84.

[0121] By using the partition 84, the diffusion of O2 gas generated from the lower surface of the SiC wafer 50 in step S7 to the SiC wafer 50 directly below it is suppressed, thereby suppressing the oxidation reaction caused by O2 gas at the SiC wafer 50 directly below it. This suppresses fluctuations in the thickness of the gate oxide film 5 between SiC wafers 50 within a batch. Furthermore, since the diffusion of O2 gas is suppressed, the in-plane uniformity of the gate oxide film 5 thickness on the Si surface 13 of each SiC wafer 50 within a batch is improved.

[0122] If in step S6 (refer to) Figure 17 If, in step S7, the interlayer insulating film 9 remaining on the lower surface of the SiC wafer 50 is greater than or equal to 0.75 μm, then in step S7 (refer to...) Figure 17 The amount of O2 gas generated from the lower surface of the SiC wafer 50 is reduced. Therefore, the amount of O2 gas diffusing around the separator 84 is reduced, which enables more precise suppression of the thickness fluctuation of the gate oxide film 5 between SiC wafers 50 in a batch.

[0123] To prevent gas generated from the SiC wafer 50 from diffusing around the separator 84, the size of the separator 84 is preferably the same as or larger than the size of the wafer. For example, in step S7 (refer to...) Figure 17In , the SiC wafer 50 is supported by the supporting portion 82a in such a configuration that the entirety of the SiC wafer 50 overlaps the partition plate 84 when viewed from above.

[0124] The partition plate 84 can be integrated with the boat 82, or can be detached from the boat 82.

[0125] If the partition plate 84 can be detached from the boat 82, the circulation of the boat 82 becomes easy, and the arrangement and maintenance of the vertical batch diffusion furnace 80d become easy.

[0126] <E. Embodiment 5>

[0127] Figure 22 It is a diagram showing the structure of the vertical batch diffusion furnace 80e used in the present embodiment and the arrangement of wafers in step S7 (see Figure 17 ). Compared with the manufacturing method of the semiconductor device in Embodiment 1, the difference of the manufacturing method of the semiconductor device in the present embodiment is that in step S7, the vertical batch diffusion furnace 80e is used instead of the vertical batch diffusion furnace 80. In Figure 22 , a case where a SiC dummy wafer 51 is not used is shown. Besides that, the manufacturing method of the semiconductor device in the present embodiment is the same as the manufacturing method of the semiconductor device in Embodiment 1.

[0128] Compared with the vertical batch diffusion furnace 80 used in Embodiments 1 and 2, the difference is that in addition to the gas introduction line 83, the vertical batch diffusion furnace 80e further comprises a gas introduction line 83a. The vertical batch diffusion furnace 80e can supply more O2 gas or O3 gas through the gas introduction line 83a to the area between a certain group of adjacent supporting portions 82a in the stacking direction of the plurality of wafers than to the area between another group of adjacent supporting portions 82a in the stacking direction of the plurality of wafers.

[0129] In the manufacturing method of the semiconductor device according to the present embodiment, in step S7 (see Figure 17 ), in addition to supplying oxygen through the gas introduction line 83, O2 gas or O3 gas is selectively supplied through the gas introduction line 83a between the Si monitor wafer 52 and the SiC wafer 50. Thereby, more O2 gas or O3 gas is supplied to the area between the Si monitor wafer 52 and the SiC wafer 50 than to the area between the SiC wafers 50. In the case where a dummy wafer is used in step S7 (see Figure 17 ), O2 gas or O3 gas is supplied through the gas introduction line 83a to the area between the dummy wafer and the SiC wafer 50. Thereby, more O2 gas or O3 gas is supplied to the area between the dummy wafer and the SiC wafer 50 than to the area between the SiC wafers 50.

[0130] As described above, in Embodiment 1 Figure 18 In the results shown, in step S7 (refer to...) Figure 17 In step S7 (refer to...), the gate oxide film 5 formed on the SiC wafer 50 disposed directly below the monitoring wafer or the dumb wafer is compared with the gate oxide film 5 formed on the SiC wafer 50 disposed directly below the monitoring wafer or the dumb wafer. Figure 17 In the SiC wafer 50, a thin gate oxide film 5 is formed on the SiC wafer 50 located directly below the SiC wafer 50.

[0131] In the semiconductor device manufacturing method of this embodiment, O2 or O3 gas is preferentially supplied from the gas introduction line 83a to the upper surface of the SiC wafer 50 disposed directly below the monitoring wafer or the dummy wafer. An oxidation reaction caused by this O2 or O3 gas easily occurs on the upper surface of the SiC wafer 50 disposed directly below the monitoring wafer or the dummy wafer. Therefore, fluctuations in the thickness of the gate oxide film 5 between SiC wafers 50 within a batch are suppressed.

[0132] The vertical batch diffusion furnace 80e may also lack a gas inlet line 83a. In this case, in the gas inlet line 83, such as Figure 23 As shown, in addition to the opening 830, an opening 831 is provided on the side of the tube 81. By preferentially supplying O2 or O3 gas to the area between the monitoring wafer or the dumb wafer and the SiC wafer 50 disposed directly below the monitoring wafer or the dumb wafer through the opening 831, the fluctuation of the thickness of the gate oxide film 5 between the SiC wafers 50 in a batch is suppressed.

[0133] In Implementation 1, it was explained that if in step S6 (refer to...) Figure 17 If the interlayer insulating film 9 remaining at the lower surface of the SiC wafer 50 is greater than or equal to 0.75 μm, then in step S7, the thickness difference of the gate oxide film 5 between SiC wafers 50 in a batch can be suppressed to less than or equal to 0.8 nm. However, by using embodiment 5 in conjunction with it, the variation in the thickness of the gate oxide film 5 between SiC wafers 50 in a batch can be suppressed with higher precision. In this case, in step S7 (refer to embodiment 5)... Figure 17 In step S7, the amount of oxidizing gas supplied from the gas introduction line 83a is adjusted according to the thickness of the interlayer insulating film 9 formed on the lower surface of the SiC wafer 50. Furthermore, when the SiC dumb wafer 51 is disposed between the SiC wafer 50 and the Si monitoring wafer 52, in step S7 (see...) Figure 17 In this process, the amount of oxidizing gas supplied from the gas introduction line 83a is adjusted in accordance with the thickness of the interlayer insulating film 9 formed on the lower surface of the SiC wafer 50 and the thickness of the interlayer insulating film 9 formed on the lower surface of the SiC dummy wafer 51.

[0134] Furthermore, the various implementation methods can be freely combined, and appropriate modifications or omissions can be made to each implementation method.

[0135] Explanation of the label

[0136] 1. SiC substrate, 2. SiC drift layer, 3. Base region, 4. Source region, 5. Gate oxide film, 5a. Oxide film, 6. Gate wiring, 7. Source electrode, 8. Drain electrode, 9. Interlayer insulating film, 10. Gate electrode, 12. C surface, 13. Si surface, 41, 42. Masks, 45. Si atoms, 46. C atoms, 50. SiC wafer, 51. SiC dummy wafer, 51a. Si dummy wafer, 52. Si monitoring wafer, 80, 80c, 80d, 80e. Vertical batch diffusion furnace, 81. Tube, 82. Crystal boat, 82a, 82b. Support, 83, 83a. Gas introduction line, 84. Separator, 90. Inorganic film, 830, 831. Opening.

Claims

1. A method for manufacturing a semiconductor device, wherein, A first inorganic film is formed on the lower surface of multiple silicon carbide wafers. After the formation of the first inorganic film, the etching of the plurality of silicon carbide wafers is performed. The etching is performed such that the residual thickness of the first inorganic film on the plurality of silicon carbide wafers after etching is greater than or equal to 750 nm. After etching, a thermal oxidation process is performed using a semiconductor manufacturing apparatus to form an oxide film on the upper surface of the plurality of silicon carbide wafers. The thermal oxidation process is performed on at least one wafer and the plurality of silicon carbide wafers arranged in one direction with their upper surfaces facing that direction. The at least one wafer comprises at least one of a dumb wafer or a monitoring wafer and is different from the plurality of silicon carbide wafers. In the state described by the thermal oxidation treatment, the first silicon carbide wafer among the plurality of silicon carbide wafers is disposed directly below any of the at least one wafer, and the second silicon carbide wafer among the plurality of silicon carbide wafers is disposed directly below the third silicon carbide wafer among the plurality of silicon carbide wafers. The upper surface of each of the plurality of silicon carbide wafers is a Si surface, and the lower surface is a C surface. The thickness difference of the oxide film formed by the thermal oxidation process between the plurality of silicon carbide wafers within a batch is suppressed to less than or equal to 0.8 nm. The etching is performed by wet etching via immersion.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, A second inorganic film is formed on the upper surface of the plurality of silicon carbide wafers. The second inorganic film on the upper surface of the plurality of silicon carbide wafers is etched during the etching process.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein, The oxide film is a gate oxide film.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein, The thermal oxidation process is performed using oxygen or ozone gas.

5. A method for manufacturing a semiconductor device, wherein, A first inorganic film is formed on the lower surface of multiple silicon carbide wafers. After the formation of the first inorganic film, the etching of the plurality of silicon carbide wafers is performed. The etching is performed such that the residual thickness of the first inorganic film on the plurality of silicon carbide wafers after etching is greater than or equal to 750 nm. After etching, a thermal oxidation process is performed using a semiconductor manufacturing apparatus to form an oxide film on the upper surface of the plurality of silicon carbide wafers. The thermal oxidation process is performed on at least one wafer and the plurality of silicon carbide wafers arranged in one direction with their upper surfaces facing that direction. The at least one wafer comprises at least one of a dumb wafer or a monitoring wafer and is different from the plurality of silicon carbide wafers. In the state described by the thermal oxidation treatment, the first silicon carbide wafer among the plurality of silicon carbide wafers is disposed directly below any of the at least one wafer, and the second silicon carbide wafer among the plurality of silicon carbide wafers is disposed directly below the third silicon carbide wafer among the plurality of silicon carbide wafers. The upper surface of each of the plurality of silicon carbide wafers is a Si surface, and the lower surface is a C surface. The thickness difference of the oxide film formed by the thermal oxidation process between the plurality of silicon carbide wafers within a batch is suppressed to less than or equal to 0.8 nm. In the thermal oxidation process, more oxygen or ozone gas is supplied to the region between any of the at least one wafer and the first silicon carbide wafer than to the region between the second and third silicon carbide wafers.

6. The method for manufacturing a semiconductor device according to claim 5, wherein, The semiconductor manufacturing apparatus includes a container for performing the thermal oxidation process, and a first introduction line and a second introduction line for introducing oxygen or ozone gas into the container. In the thermal oxidation process, the second inlet line selectively supplies oxygen or ozone gas to the region between either of the at least one wafer and the first silicon carbide wafer.

7. The method for manufacturing a semiconductor device according to claim 5, wherein, The semiconductor manufacturing apparatus includes a container for performing the thermal oxidation process and an inlet line for introducing oxygen or ozone gas into the container. The inlet line has an opening on the side of the inlet line within the container. In the thermal oxidation process, the opening is located in one direction between any of the at least one wafer and the first silicon carbide wafer, through which oxygen or ozone gas is supplied to the container.

8. A method for manufacturing a semiconductor device, wherein, A first inorganic film is formed on the lower surface of multiple silicon carbide wafers. After the formation of the first inorganic film, the etching of the plurality of silicon carbide wafers is performed. The etching is performed such that the residual thickness of the first inorganic film on the plurality of silicon carbide wafers after etching is greater than or equal to 750 nm. After etching, a thermal oxidation process is performed using a semiconductor manufacturing apparatus to form an oxide film on the upper surface of the plurality of silicon carbide wafers. The thermal oxidation process is performed on at least one wafer and the plurality of silicon carbide wafers arranged in one direction with their upper surfaces facing that direction. The at least one wafer comprises at least one of a dumb wafer or a monitoring wafer and is different from the plurality of silicon carbide wafers. In the state described by the thermal oxidation treatment, the first silicon carbide wafer among the plurality of silicon carbide wafers is disposed directly below any of the at least one wafer, and the second silicon carbide wafer among the plurality of silicon carbide wafers is disposed directly below the third silicon carbide wafer among the plurality of silicon carbide wafers. The upper surface of each of the plurality of silicon carbide wafers is a Si surface, and the lower surface is a C surface. The thickness difference of the oxide film formed by the thermal oxidation process between the plurality of silicon carbide wafers within a batch is suppressed to less than or equal to 0.8 nm. The at least one chip may be multiple chips. In the state of the thermal oxidation treatment, the plurality of wafers and the plurality of silicon carbide wafers are arranged alternately in one direction.

9. A method for manufacturing a semiconductor device, wherein, A first inorganic film is formed on the lower surface of multiple silicon carbide wafers. After the formation of the first inorganic film, the etching of the plurality of silicon carbide wafers is performed. The etching is performed such that the residual thickness of the first inorganic film on the plurality of silicon carbide wafers after etching is greater than or equal to 750 nm. After etching, a thermal oxidation process is performed using a semiconductor manufacturing apparatus to form an oxide film on the upper surface of the plurality of silicon carbide wafers. The thermal oxidation process is performed on at least one wafer and the plurality of silicon carbide wafers arranged in one direction with their upper surfaces facing that direction. The at least one wafer comprises at least one of a dumb wafer or a monitoring wafer and is different from the plurality of silicon carbide wafers. In the state described by the thermal oxidation treatment, the first silicon carbide wafer among the plurality of silicon carbide wafers is disposed directly below any of the at least one wafer, and the second silicon carbide wafer among the plurality of silicon carbide wafers is disposed directly below the third silicon carbide wafer among the plurality of silicon carbide wafers. The upper surface of each of the plurality of silicon carbide wafers is a Si surface, and the lower surface is a C surface. The thickness difference of the oxide film formed by the thermal oxidation process between the plurality of silicon carbide wafers within a batch is suppressed to less than or equal to 0.8 nm. In the state described by the thermal oxidation treatment, the second silicon carbide wafer and the third silicon carbide wafer are separated by a partition that overlaps with the central portion of the second silicon carbide wafer when viewed from above. Only one silicon carbide wafer can be placed between adjacent partitions.

10. The method of manufacturing a semiconductor device according to claim 9, wherein, The partition plate is a support portion that supports the second silicon carbide wafer.

11. The method of manufacturing a semiconductor device according to claim 9, wherein, The partition is different from the support portion that supports the second silicon carbide wafer.

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