A method to improve the performance and reliability of RF LDMOS
By using polysilicon combined with N-type ion filling at the drain of the RF LDMOS to form a concentration gradient and drop contact holes on the polysilicon, the problems of leakage current and large output capacitance are solved, thereby improving the reliability and performance of the RF LDMOS.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2022-11-22
- Publication Date
- 2026-08-04
AI Technical Summary
Existing RF LDMOS has the problems of leakage risk and large drain output capacitance, which affect its RF performance and reliability.
The method of combining polycrystalline silicon with N-type ion filling is adopted. By forming a concentration gradient in the drain region and placing it on the polycrystalline silicon at the contact hole, the influence on the drain junction is avoided. Combined with the heat treatment process, a drain polycrystalline silicon N-type ion structure is formed.
It effectively improves the hot carrier effect, reduces the drain output capacitance, enhances product reliability and performance, avoids leakage risks, and improves device efficiency and gain.
Smart Images
Figure CN115692204B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the performance and reliability of RF LDMOS. Background Technology
[0002] RFLDMOS is widely used in high-power radio frequency fields such as base stations and broadcast television transmission. By using power arrays and multi-chip synthesis, the output power of the products can reach more than 500 watts. The contradiction between the radio frequency performance and reliability of RFLDMOS is the focus of research.
[0003] On-resistance and output capacitance are the main factors affecting the efficiency of RF LDMOS transistors. Reducing on-resistance and output capacitance can decrease the power loss caused by these two factors, thereby improving the device's efficiency and gain.
[0004] Reducing the input / output capacitance and feedback capacitance can effectively improve the characteristic frequency, maximum oscillation frequency, and gain of the device.
[0005] Currently, the drain of RFLDMOS is achieved by using a polysilicon structure combined with N-type ion implantation and contact hole lead-out. On the one hand, the regularity between N-type polysilicon / source-base / contact hole determines that the N-type polysilicon must be wide enough, so the drain output capacitance is large. On the other hand, in order to reduce the gate resistance and improve efficiency, a relatively thick silicide is required for the gate / source / drain, but this will cause the drain to have the risk of leakage.
[0006] Therefore, the design of the drain terminal is an extremely important factor in the RF performance of RFLDMOS. Summary of the Invention
[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving the performance and reliability of RF LDMOS, thereby solving the problem of leakage risk in RF LDMOS in the prior art.
[0008] To achieve the above and other related objectives, the present invention provides a method for improving the performance and reliability of RF LDMOS, comprising at least:
[0009] Step 1: Provide a silicon substrate and form a first oxide layer on the silicon substrate;
[0010] Step 2: Define the gate location and the source region located on one side of the gate location, and remove the first oxide layer in the source region;
[0011] Step 3: Form a gate oxide layer, which covers the silicon substrate and the first oxide layer in the source region;
[0012] Step 4: Form a gate polysilicon layer on the gate oxide layer; then etch the gate polysilicon layer to form a gate polysilicon structure at the gate location;
[0013] Step 5: Form a P-type body region within the silicon substrate in the source region; form a P+ region within the P-type body region; form an N+ region within the P-type body region between the P+ region and the gate polysilicon structure; define a drain region on the silicon substrate on the side of the gate polysilicon structure away from the P-type body region; and form an NLDD region within the silicon substrate between the drain region and the gate polysilicon structure.
[0014] Step 6: Form a second oxide layer, which continuously covers the source region, the gate polysilicon structure, and the side of the gate polysilicon structure away from the source region.
[0015] Step 7: Etch away the second oxide layer and the first oxide layer in the drain region to form a groove, the bottom of the groove exposing the silicon substrate;
[0016] Step 8: Cover the source region, the gate polysilicon structure, and the side of the gate polysilicon structure away from the source region with a polysilicon layer, wherein the thickness of the polysilicon layer is greater than the thickness of the gate polysilicon structure.
[0017] Step 9: Etch the polysilicon layer until the second oxide layer on top of the gate polysilicon structure is exposed;
[0018] Step 10: Define the morphology of the drain polysilicon structure, etch the polysilicon layer to form a drain polysilicon structure covering the groove in the drain region;
[0019] Step 11: Form sidewalls on the sidewalls of the gate polysilicon structure and the drain polysilicon structure, respectively; then form a drain N+ region in the silicon substrate of the drain region.
[0020] Step 12: Perform heat treatment on the source region and the drain region;
[0021] Step 13: Forming a metal silicide covering the source region, the top of the gate polysilicon structure, and the top of the drain polysilicon structure;
[0022] Step 14: Form a third oxide layer, which continuously covers the source region, the gate polysilicon structure, and the drain polysilicon structure.
[0023] Step 15: Form a shielding cover that begins at the sidewall of the gate polysilicon structure and extends to the third oxide layer between the drain polysilicon structure and the gate polysilicon structure.
[0024] Preferably, in step two, the gate position is defined by photolithography using photoresist.
[0025] Preferably, after etching the gate polysilicon layer in step four to form the gate polysilicon structure, all gate polysilicon layers outside the gate polysilicon structure are removed.
[0026] Preferably, in step five, the upper surfaces of the P-type body region, P+ region, NLDD region, and N+ region are all flush with the upper surface of the silicon substrate; and the N+ region located within the P-type body region is connected to the P+ region; the depth of the NLDD region within the silicon substrate is less than the depth of the P-type body region within the silicon substrate; and one side of the gate polysilicon structure covers the top of one side of the P-type body region.
[0027] Preferably, the width of the groove in step seven is smaller than the width of the drain end region.
[0028] Preferably, in step ten, photoresist is used to define the morphology of the drain-end polysilicon structure by photolithography.
[0029] Preferably, the width of the drain polysilicon structure in step ten is greater than the width of the drain region.
[0030] Preferably, the method for forming the sidewall in step eleven is as follows: first, deposit an oxide layer, and then remove the oxide layer except for the sidewall of the gate polysilicon structure and the sidewall of the drain polysilicon structure, while the second oxide layer except for the sidewall of the gate polysilicon structure and the sidewall of the drain polysilicon structure is also removed.
[0031] Preferably, the method further includes step sixteen: forming a dielectric layer covering the source region, the gate polysilicon structure, and the drain polysilicon structure; then forming a contact hole in the dielectric layer that connects the drain polysilicon structure and the top of the source region; next, filling the contact hole with metal; covering the dielectric layer with a metal layer; and finally etching the metal layer to form a metal line connected to the metal-filled contact hole.
[0032] As described above, the method for improving the performance and reliability of RF LDMOS according to the present invention has the following beneficial effects: In the method of the present invention, the drain terminal adopts a polysilicon combined with N-type ion filling method. After subsequent heat treatment, a concentration gradient will naturally form between the drain terminal and the LDD region, which can effectively improve the hot carrier effect. Moreover, the contact hole falls on the polysilicon of the drain terminal and will not affect the junction of the drain terminal, so there is no risk of leakage current, which can effectively improve the reliability of the product. At the same time, due to the adoption of the drain terminal polysilicon N-type ion bonding process, the drain terminal size is significantly reduced, which can effectively reduce the output capacitance and improve product performance. Attached Figure Description
[0033] Figures 1 to 14 The diagram shows the structure formed at each stage of the RFLDMOS fabrication process in this invention.
[0034] Figure 15 The diagram shows a flowchart of the method for improving the performance and reliability of RF LDMOS according to the present invention. Detailed Implementation
[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0036] Please see Figures 1 to 15 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0037] Step 1: Provide a silicon substrate, and form a first oxide layer on the silicon substrate; such as... Figure 1 As shown, in step one, a silicon substrate 01 is provided, and a first oxide layer 02 is formed on the silicon substrate 01. Forming the first oxide layer on the silicon substrate includes forming the first oxide layer on the back side of the silicon substrate as well.
[0038] Step 2: Define the gate location and the source region located on one side of the gate location, and remove the first oxide layer in the source region;
[0039] Furthermore, in step two of this embodiment, the gate location is defined using photoresist photolithography. For example... Figure 2 As shown, step two defines the gate location and the source region located on one side of the gate location, and removes the first oxide layer in the source region; in step two of this embodiment, the gate location is defined using photoresist 03 photolithography (i.e., Figure 2 The boundary between the photoresist in the middle and the area without photoresist on its left, which is the area of the first oxide layer that has been removed, is the source region. The boundary between this source region and the area of the first oxide layer covering it on its right is the gate position.
[0040] Step 3: Form a gate oxide layer, which covers the silicon substrate and the first oxide layer in the source region; as shown below. Figure 3As shown, step three forms a gate oxide layer 04, which covers the silicon substrate 01 and the first oxide layer 02 in the source region.
[0041] Step 4: Form a gate polysilicon layer on the gate oxide layer; then etch the gate polysilicon layer to form a gate polysilicon structure at the gate location;
[0042] Furthermore, in step four of this embodiment, after etching the gate polysilicon layer to form the gate polysilicon structure, all gate polysilicon layers outside the gate polysilicon structure are removed. For example... Figure 4 As shown, in step four, a gate polysilicon layer 05 is formed on the gate oxide layer 04; then, the gate polysilicon layer 05 is etched to form a gate polysilicon structure 06 at the gate location (e.g., ...). Figure 5 As shown in the figure, after etching the gate polysilicon layer to form the gate polysilicon structure in step four of this embodiment, all gate polysilicon layers other than the gate polysilicon structure are removed.
[0043] Step 5: Form a P-type body region within the silicon substrate in the source region; form a P+ region within the P-type body region; form an N+ region within the P-type body region between the P+ region and the gate polysilicon structure; define a drain region on the silicon substrate on the side of the gate polysilicon structure away from the P-type body region; and form an NLDD region within the silicon substrate between the drain region and the gate polysilicon structure.
[0044] In a further embodiment of the present invention, the upper surface of the P-type body region, the upper surface of the P+ region, the upper surface of the NLDD region, and the upper surface of the N+ region in step five are all flush with the upper surface of the silicon substrate; and the N+ region located in the P-type body region is connected to the P+ region; the depth of the NLDD region in the silicon substrate is less than the depth of the P-type body region in the silicon substrate; and one side of the gate polysilicon structure covers the upper side of the P-type body region.
[0045] like Figure 6 As shown, in step five, a P-type body region 07 is formed in the silicon substrate of the source region; a P+ region 08 is formed in the P-type body region; an N+ region 09 is formed in the P-type body region between the P+ region and the gate polysilicon structure; a drain region A is defined on the silicon substrate on the side of the gate polysilicon structure away from the P-type body region; and an NLDD region 10 is formed in the silicon substrate between the drain region and the gate polysilicon.
[0046] Step 6: Form a second oxide layer, which continuously covers the source region, the gate polysilicon structure, and the side of the gate polysilicon structure away from the source region; as shown below. Figure 7As shown, step six forms a second oxide layer 11, which continuously covers the source region, the gate polysilicon structure, and the side of the gate polysilicon structure away from the source region.
[0047] Step 7: Etch away the second oxide layer and the first oxide layer in the drain region to form a groove, the bottom of the groove exposing the silicon substrate;
[0048] Furthermore, in step seven of this embodiment, the width of the groove is smaller than the width of the drain end region. For example... Figure 8 As shown, in step seven, etching removes the second oxide layer and the first oxide layer in the drain region to form a groove B. The bottom of the groove exposes the silicon substrate, and the width of the groove is smaller than the width of the drain region A.
[0049] Step 8: Cover the source region, the gate polysilicon structure, and the side of the gate polysilicon structure away from the source region with a polysilicon layer, the thickness of which is greater than the thickness of the gate polysilicon structure; as shown Figure 9 As shown, in step eight, a polysilicon layer 13 is covered on the source region, the gate polysilicon structure, and the side of the gate polysilicon structure away from the source region, and the thickness of the polysilicon layer 13 is greater than the thickness of the gate polysilicon structure.
[0050] Step 9: Etch the polysilicon layer until the second oxide layer on top of the gate polysilicon structure is exposed; as follows Figure 10 As shown, step nine involves etching the polysilicon layer until the second oxide layer on top of the gate polysilicon structure is exposed.
[0051] Step 10: Define the morphology of the drain polysilicon structure, etch the polysilicon layer to form a drain polysilicon structure covering the groove in the drain region;
[0052] Furthermore, in step ten of this embodiment, photoresist is used to define the morphology of the drain-end polysilicon structure via photolithography. For example... Figure 11 As shown, step ten defines the morphology of the drain polysilicon structure, etches the polysilicon layer to form a drain polysilicon structure 14 covering the groove in the drain region, and defines the morphology of the drain polysilicon structure 14 using photoresist and photolithography. The morphology of the drain polysilicon structure 14 is defined using photoresist 15 and photolithography.
[0053] Furthermore, in step ten of this embodiment, the width of the drain polysilicon structure 14 is greater than the width of the drain region A.
[0054] Step 11: Form sidewalls on the sidewalls of the gate polysilicon structure and the drain polysilicon structure, respectively; then form a drain N+ region in the silicon substrate of the drain region.
[0055] Further, in step eleven of this embodiment, the method for forming the sidewall is as follows: first, an oxide layer is deposited, and then the oxide layer other than the gate polysilicon structure sidewall and the drain polysilicon structure sidewall is removed. Simultaneously, the second oxide layer other than the gate polysilicon structure sidewall and the drain polysilicon structure sidewall is also removed. Figure 12 As shown, in step eleven, a sidewall 16 is formed on the sidewall of the gate polysilicon structure, and a sidewall 17 is formed on the sidewall of the drain polysilicon structure; then, a drain N+ region 18 is formed in the silicon substrate of the drain region.
[0056] Step 12: Perform heat treatment on the source region and the drain region;
[0057] Step 13: Forming a metal silicide covering the source region, the top of the gate polysilicon structure, and the top of the drain polysilicon structure; such as Figure 13 As shown, step thirteen involves forming a metal silicide 18 covering the source region, the top of the gate polysilicon structure, and the top of the drain polysilicon structure.
[0058] Step fourteen: Form a third oxide layer, which continuously covers the source region, the gate polysilicon structure, and the drain polysilicon structure; as shown below. Figure 14 As shown, in step fourteen, the third oxide layer 19 continuously covers the source region, the gate polysilicon structure, and the drain polysilicon structure.
[0059] Step 15: Form a shielding layer that begins at the sidewall of the gate polysilicon structure and extends to the third oxide layer between the drain polysilicon structure and the gate polysilicon structure. Figure 14 As shown, step fifteen forms a shield 20, which starts at the sidewall of the gate polysilicon structure and extends to the third oxide layer between the drain polysilicon structure and the gate polysilicon structure.
[0060] The method further includes step sixteen: forming a dielectric layer covering the source region, the gate polysilicon structure, and the drain polysilicon structure; then forming a contact hole in the dielectric layer that connects the drain polysilicon structure and the top of the source region; next, filling the contact hole with metal; covering the dielectric layer with a metal layer; and finally etching the metal layer to form a metal line connected to the metal-filled contact hole.
[0061] In summary, the drain terminal of this invention employs a polycrystalline silicon-based N-type ion-filling method. After subsequent heat treatment, a concentration gradient naturally forms between the drain terminal and the LDD region, effectively improving the hot carrier effect. Furthermore, the contact holes fall on the polycrystalline silicon of the drain terminal, without affecting the junction, thus eliminating the risk of leakage and effectively improving product reliability. Simultaneously, due to the N-type ion-bonding process for the drain terminal, the drain size is significantly reduced, effectively lowering the output capacitor cost and improving product performance. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.
[0062] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for improving the performance and reliability of RF LDMOS, characterized in that, At least including: Step 1: Provide a silicon substrate and form a first oxide layer on the silicon substrate; Step 2: Define the gate location and the source region located on one side of the gate location, and remove the first oxide layer in the source region; Step 3: Form a gate oxide layer, which covers the silicon substrate and the first oxide layer in the source region; Step 4: Form a gate polysilicon layer on the gate oxide layer; then etch the gate polysilicon layer to form a gate polysilicon structure at the gate location; Step 5: Form a P-type body region within the silicon substrate in the source region; form a P+ region within the P-type body region; form an N+ region within the P-type body region between the P+ region and the gate polysilicon structure; define a drain region on the silicon substrate on the side of the gate polysilicon structure away from the P-type body region; and form an NLDD region within the silicon substrate between the drain region and the gate polysilicon structure. Step 6: Form a second oxide layer, which continuously covers the source region, the gate polysilicon structure, and the side of the gate polysilicon structure away from the source region. Step 7: Etch away the second oxide layer and the first oxide layer in the drain region to form a groove, the bottom of the groove exposing the silicon substrate; Step 8: Cover the source region, the gate polysilicon structure, and the side of the gate polysilicon structure away from the source region with a polysilicon layer, wherein the thickness of the polysilicon layer is greater than the thickness of the gate polysilicon structure. Step 9: Etch the polysilicon layer until the second oxide layer on top of the gate polysilicon structure is exposed; Step 10: Define the morphology of the drain polysilicon structure, etch the polysilicon layer to form a drain polysilicon structure covering the groove in the drain region; Step 11: Form sidewalls on the sidewalls of the gate polysilicon structure and the drain polysilicon structure, respectively; then form a drain N+ region in the silicon substrate of the drain region. Step 12: Perform heat treatment on the source region and the drain region; Step 13: Forming a metal silicide covering the source region, the top of the gate polysilicon structure, and the top of the drain polysilicon structure; Step 14: Form a third oxide layer, which continuously covers the source region, the gate polysilicon structure, and the drain polysilicon structure. Step 15: Form a shielding cover that begins at the sidewall of the gate polysilicon structure and extends to the third oxide layer between the drain polysilicon structure and the gate polysilicon structure.
2. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: In step two, the gate position is defined by photolithography using photoresist.
3. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: After etching the gate polysilicon layer in step four to form the gate polysilicon structure, all gate polysilicon layers outside the gate polysilicon structure are removed.
4. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: In step five, the upper surfaces of the P-type body region, P+ region, NLDD region, and N+ region are all flush with the upper surface of the silicon substrate; and the N+ region located within the P-type body region is connected to the P+ region; the depth of the NLDD region within the silicon substrate is less than the depth of the P-type body region within the silicon substrate; one side of the gate polysilicon structure covers the top of one side of the P-type body region.
5. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: In step seven, the width of the groove is less than the width of the leak end region.
6. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: In step ten, photoresist is used to define the morphology of the drain-end polysilicon structure through photolithography.
7. The method for improving the performance and reliability of RF LDMOS according to claim 6, characterized in that: In step ten, the width of the drain polysilicon structure is greater than the width of the drain region.
8. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: The method for forming the sidewall in step eleven is as follows: first, an oxide layer is deposited, and then the oxide layer other than the gate polysilicon structure sidewall and the drain polysilicon structure sidewall is removed. At the same time, the second oxide layer other than the gate polysilicon structure sidewall and the drain polysilicon structure sidewall is also removed.
9. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: The method further includes step sixteen: forming a dielectric layer covering the source region, the gate polysilicon structure, and the drain polysilicon structure; then forming a contact hole in the dielectric layer that connects the drain polysilicon structure and the top of the source region; and then filling the contact hole with metal. A metal layer is covered on the dielectric layer, and finally the metal layer is etched to form a metal line that connects to the contact hole filled with metal.