Method of assembling a semiconductor device and corresponding semiconductor device

Abstract

Various embodiments of the invention relate to a method of assembling a semiconductor device and a corresponding semiconductor device. A leadframe comprises a die pad on which a first semiconductor die is arranged, wherein a conductive strap extends over the first semiconductor die. The first semiconductor die is located in between the leadframe and the conductive strap. A second semiconductor die is mounted on the conductive strap for providing a stacked arrangement of the second semiconductor die and the first semiconductor die on the same die pad, wherein at least one conductive strap is in between the first semiconductor die and the second semiconductor die. The package size reduction can thus be achieved without significantly impacting the device assembly flow.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Italian Patent Application No. 102021000020552, filed on July 30, 2021, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This specification relates to semiconductor devices.

[0004] One or more embodiments can be advantageously applied to power semiconductor devices. Background Technology

[0005] In various power semiconductor devices (including, for example, power semiconductor devices in square flat no-lead (QFN) packages), one or more power integrated circuit chips or dies are arranged side by side with driver integrated circuit chips or, for example, chips manufactured using BCD (Bipolar-CMOS-DMOS) technology.

[0006] These chips (or dies: the terms “chip” and “die” are used as synonyms in this document) can be mounted on the corresponding adjacent die pads or pads in the leadframe.

[0007] Wire bonding is used to provide die-to-die or die-to-lead frame connections (e.g., signal, ground), and the so-called “band” of the wires wedge-bonded to the lead frame is used to provide a conductor or path suitable for carrying high current.

[0008] In this arrangement, the different die pads or solder pads used to mount various power and driver chips or dies occupy a large amount of substrate (lead frame) space.

[0009] There is a need in this field to contribute to the proper handling of such problems. Summary of the Invention

[0010] One or more embodiments relate to methods.

[0011] One or more embodiments relate to corresponding semiconductor devices. Examples of such devices include power devices comprising multiple mutually coupled semiconductor integrated circuit chips or dies.

[0012] One or more embodiments involve stacking at least one die (e.g., a driver or controller die) onto another die (e.g., a power die) by using one or more strip segments for attachment.

[0013] In this way, the overall package height increases (slightly), but this increase is largely compensated by a significant reduction in package footprint. This can result in smaller leadframes, smaller packages, and a smaller footprint when ultimately mounted on a substrate such as a printed circuit board (PCB).

[0014] Therefore, one or more embodiments rely on unexpected insights, such as that the strip, which is typically used to provide a current path or channel in a semiconductor power device, is sufficiently robust to adequately support one or more semiconductor chips attached thereto.

[0015] One or more embodiments offer one or more of the following advantages: compatibility with existing wire bonding machines; a plug-and-play process in which the number of assembly steps remains substantially unchanged; broad applicability to a variety of leadframe packages; reduced package size; cost savings due to the reduced package size; and selectivity due to the ability to customize wires and strips to desired specifications.

[0016] As is the case in arrangements that include stacked chips, a chip (e.g., a smaller chip) can be placed "on top" of at least one other chip by using strips arranged between them as a support structure.

[0017] One or more embodiments thus help to reduce the overall X and Y dimensions of semiconductor chip packages and have the ability to utilize possible synergistic combinations of die bonding, wire bonding, and band bonding (plus chip or die stacking) in the manufacture of semiconductor devices. Attached Figure Description

[0018] One or more embodiments will now be described by way of example only, with reference to the accompanying drawings, in which:

[0019] Figure 1 and Figure 2 It is a plan view of a semiconductor device comprising multiple semiconductor chips arranged on a substrate having strips that provide power connection channels or paths;

[0020] Figure 3 This is a plan view of a semiconductor device according to an embodiment of this specification;

[0021] Figure 4 This is a plan view of another semiconductor device according to an embodiment of this specification;

[0022] Figure 5 This is a plan view of yet another semiconductor device according to an embodiment of this specification;

[0023] Figure 6 This is a plan view of yet another semiconductor device according to an embodiment of this specification; and

[0024] Figure 7 yes Figure 6 Exemplary floor plan diagrams of possible variations of the example shown. Detailed Implementation

[0025] Unless otherwise indicated, the corresponding reference numerals in different figures usually refer to the corresponding parts.

[0026] The accompanying drawings are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0027] The feature edges drawn in the figure do not necessarily indicate the end of the feature range.

[0028] In the following description, various specific details are illustrated to provide a thorough understanding of various examples of embodiments according to this specification. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been illustrated or described in detail so that various aspects of the embodiments are not obscured.

[0029] References to "embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described in relation to an embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in one embodiment," etc., that may appear at various points in this specification do not necessarily refer exactly to the same embodiment. Furthermore, specific configurations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0030] The headings / reference numerals used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of embodiments.

[0031] like Figure 1 and Figure 2 The semiconductor device 10 illustrated may include a plurality of semiconductor integrated circuit chips (or dies) C1, C2, regardless of their number and function, which are arranged at corresponding adjacent die pads or bonding pads 12A in a substrate 12 such as a lead frame.

[0032] The term “lead frame” (or “lead frame”) is currently (see, for example, the USPC Comprehensive Glossary) used to refer to a metal frame that provides support for an integrated circuit chip or die, and electrical leads that interconnect the integrated circuit in the die or chip with other electrical components or contacts.

[0033] Essentially, the leadframe includes an array of conductive structures (leads) 12B extending inward from the outline location along the direction of the semiconductor chip or die, thereby forming an array of conductive structures from one or more die pads or solder pads 12A, the array of conductive structures being configured to have at least one semiconductor chip or die attached thereto.

[0034] At least one semiconductor chip or die-to-die pad attachment can be performed via a known material such as a die attachment adhesive (e.g., die attachment film or DAF).

[0035] Leadframes are typically created using techniques such as photolithography. Using this technique, a metal material in the form of foil or strip (e.g., copper) is etched on the top and bottom sides to create various pads and leads.

[0036] Substrates such as lead frames are advantageously provided in pre-molded form, wherein an insulating resin (e.g., epoxy resin) fills the blank space between die pads 12A and leads 12B.

[0037] Therefore, the pre-molded lead frame 12 is a substantially flat layered substrate in which the pre-molded material (resin) fills the spaces in the conductive structure of the lead frame (e.g., made of a metallic material such as copper), which has been given an engraved appearance including blank spaces during molding, for example by etching.

[0038] The total thickness of the pre-molded lead frame is the same as the thickness of the engraved conductive structure.

[0039] exist Figure 1 and Figure 2 In the figure, reference numeral 14 indicates the so-called “strip” (i.e., a narrow strip of conductive material, copper being an example of such material), which provides a conductive line extending above the power die C2 and configured to carry current from the power die C2 to one or more electrical loads (not visible in the figure).

[0040] like Figure 1 and Figure 2 As shown, band 14 can present a wavy (wave-like) pattern that facilitates welding using ultrasonic bonding.

[0041] Figure 1 and Figure 2 The power package illustrated herein comprises at least two chips or dies.

[0042] These may include, for example, one or more “power” dies C2 that provide the power segment of device 10; and at least one smaller die C1 that serves as a controller and is connected to both the one or more power dies C2 and the external leads 12B in the substrate (lead frame) 12.

[0043] As mentioned earlier, stripes such as 14 are primarily used for “heavy-duty” wires, while one or more controller die C1s typically use fine wires for wire bonding.

[0044] In such Figure 1 and Figure 2 In the conventional arrangement shown, each die C1, C2 is placed on the corresponding die pad 12A.

[0045] Therefore, the final package size is determined by the number and size of the die pads provided to support the dies C1 and C2.

[0046] From a packaging perspective, as the number of dies increases, this translates to a larger package size, as is currently the case with power applications that include multi-die packages.

[0047] In other words, in Figure 1 and Figure 2 In the arrangement shown, dies C1 and C2 are arranged adjacent to each other. The increase in the number of dies C1 and C2 leads to the need for more space and larger X and Y dimensions of the device package, which inevitably increases the final package size.

[0048] In a complementary way, the number of available die mounting positions in the leadframe is directly related to the size of a single die, and there are only more positions available in the leadframe when smaller dies are present.

[0049] If the die size is smaller, the available space in the leadframe can be increased, but it is still limited by the device package size, which is related to the number of dies per device.

[0050] The final packaging cost is related to the package size.

[0051] The possibility of stacking chips or dies (e.g., by stacking smaller dies on top of larger dies) is well known in the art.

[0052] On the other hand, check Figure 1 and Figure 2 And considering, for example, stacking die C1 on die C2 or one of die C2, it would necessarily be concluded that the strip 14 extending above die C2 is not conducive to this solution.

[0053] This is especially true if we consider the general wave pattern applied to band 14 to facilitate its bonding (e.g., by means of ultrasonic bonding).

[0054] Contrary to this expectation, the inventors discovered that it was used to manufacture things like Figure 1 and Figure 2The strip 14 of the power semiconductor device shown can be made strong enough (rigid and durable) to serve as a mounting surface for semiconductor dies (such as driver die C1).

[0055] If (as from) Figure 3 As shown in the initial figure, the strip 14 or each of the strips 14 for mounting the die C1 thereon is shaped (in other ways known to those skilled in the art of strip bonding) as shown. Figures 3 to 7 This is especially true of the flat surface illustrated at location 14A.

[0056] Note again that throughout these figures, there is a connection to the already combined... Figure 1 and Figure 2 Similar or analogous parts or elements discussed are indicated by the same reference numerals; for the sake of brevity, corresponding detailed descriptions will not be repeated.

[0057] Figure 3 The illustration shows the possibility of mounting (attaching) a smaller integrated circuit die (such as a controller die C1) on such a flat strip surface 14A.

[0058] This can occur via conventional bonding materials (“adhesives”) known to those skilled in the art.

[0059] Figure 3 The illustration shows a smaller die C1 that can be fully accommodated on the flat surface 14A provided in a single strip 14.

[0060] By Figure 3 and Figure 1 A comparison might reveal that, as one of the strips 14 is mounted on a die C1, it extends sequentially over one or more dies C2, as... Figure 3 As shown, in Figure 1 A portion of the substrate (lead frame) 12 that houses the die C1 (including die pad 12A on the right side of the figure) is no longer used to mount the die C1.

[0061] This portion of the substrate (lead frame) 12 can be eliminated or used for bonding. Figure 7 Another objective discussed.

[0062] Figure 4 The dimensions of the die C1 arranged (attached) on the band 14 are not strictly bound, because the die C1 (e.g., the relatively large one) as shown in the dashed outline can be “astride” or “bridge” across two adjacent bands 14 (e.g., between two corresponding flat portions 14A).

[0063] The die, such as C1, can be bonded to the top of the tape 14 using an attachment material such as adhesive or tape, which can be conductive or non-conductive depending on the desired application.

[0064] like Figure 4 The bridge-like mounting illustrated can be employed (e.g., using a conductive material to attach die C1 to strip 14) to create a conductive path coupling two adjacent strips 14. Such an arrangement is disclosed in U.S. Patent Application No. 17 / 848,958, filed June 24, 2022 (which claims priority to Italian Patent Application No. 102021000017207, filed June 30, 2021), the disclosure of which is incorporated herein by reference. Adjacent strips can also be associated with two different dies C2a and C2b (typically as indicated by arrows). In other words, adjacent semiconductor die pairs C2a and C2b are arranged with conductive strip pairs 14, such that a conductive strip extends on the corresponding semiconductor die. Semiconductor die C1 is then attached in a bridge-like manner across the conductive strip in the conductive strip pair. Each of semiconductor dies C2a and C2b is then located between the substrate and the corresponding conductive strip in the conductive strip pair.

[0065] Figure 5 This is a possible example of mounting multiple dies C1 on two (not necessarily adjacent) corresponding attachment surfaces 14A of band 14.

[0066] Regardless of the arrangement used for attachment. Figures 3 to 5 The solution shown illustrates (through with) Figure 1 and Figure 2 (Direct comparison) significantly reduces the likelihood of the overall X and Y dimensions of the final package.

[0067] This size reduction allows for an increase in the number of available package locations on a given lead frame 12 and may reduce the final package cost.

[0068] Figure 6 and Figure 7 The comparison examples illustrate this possibility.

[0069] Figure 6 The illustration shows how to "eliminate" Figure 1 The right side portion of the middle substrate (lead frame) 12 is bridging or bridged between the two strips 14 with the lead core C1 (along, for example...). Figure 4 (The line) and utilize the space advantage achieved through stacked chips C1 and C2 to provide the possibility of overall reduction in device packaging.

[0070] Figure 7 It maintains the space advantage achieved by stacking chips C1 and C2. Figure 1An example of the possibility of mounting one or more additional chips or dies (as indicated by reference numeral C3) on the right side portion of the middle substrate (lead frame) 12 and in the dashed outline.

[0071] Essentially similar methods can be applied Figure 2 The arrangement, in which the “idle” position of die C1 mounted on one or more strips 14 on the left side of the figure may be used to mount another die.

[0072] also, Figure 6 This is an example of the possibility of electrically coupling the controller die C1 to the power die C2 via conventional wire bonding 16.

[0073] Figure 7 The diagram illustrates alternative possibilities: the power die C2 is electrically coupled to the external lead 12B of the lead frame via a further wire bond 18; and the controller die C1 is electrically coupled to the external lead 12B of the lead frame via another wire bond 20.

[0074] It should be understood that referring to dies C1 and C2 as controller and power dies is purely exemplary: one or more embodiments can actually be applied regardless of the nature and type of the chip or die involved.

[0075] While “functional” stripes such as 14 (i.e., stripes designed to provide a high current flow path for device 10) have been exemplified herein, some examples may consider providing “dummy” stripes (i.e., stripes on which any electrical connection is not inherently required) to facilitate the placement of chips or dies, which may be arranged in a bridge-like configuration with “functional” stripes. Such “dummy” stripes may, for example, be used for another function in the package, such as heat dissipation.

[0076] It has been found that the conventional metallic materials currently used to provide strips in semiconductor power devices (e.g., aluminum, copper, or gold) are sufficient for the embodiments, that is, sufficient to produce strips that are strong enough to support semiconductor dies such as C1 mounted thereon, and that the strips have the ability to form flat portions such as 14A therein.

[0077] The examples in this article have no significant impact on the assembly process of device 10.

[0078] In fact, after die bonding is performed on one or more strips (as previously formed to provide power lines as needed), the wire bonding process (such as...) Figure 7 The wire bonding wires (illustrated as 16, 18 and 20) can be used to perform and continue with other assembly steps (molding and packaging, monolithization, etc.).

[0079] Without prejudice to the fundamental principles, details and embodiments may vary, even significantly, from the content described by way of example only, without departing from the scope of the embodiments.

[0080] The claims are an integral part of the technical teachings provided herein regarding the embodiments.

[0081] The scope of protection is determined by the appended claims.

Claims

1. A method for assembling a semiconductor device, comprising: At least one first semiconductor die having at least one conductive strip is disposed on a die pad in a substrate, the at least one conductive strip extending on the at least one first semiconductor die, wherein the at least one first semiconductor die is located between the substrate and the at least one conductive strip; as well as At least one second semiconductor die is attached to the at least one conductive strip to provide a stacked arrangement of the at least one second semiconductor die and the at least one first semiconductor die on the die pad, wherein the at least one conductive strip is located between the at least one first semiconductor die and the at least one second semiconductor die. The arrangement includes: arranging adjacent first semiconductor die pairs having conductive band pairs on the substrate, wherein each conductive band extends on one of the first semiconductor dies, wherein each of the first semiconductor dies is located between the substrate and a corresponding conductive band in the conductive band pair; and The attachment includes: attaching the at least one second semiconductor die in a bridge-like manner across the conductive strips in the conductive strip pair to provide a stacked arrangement of the at least one second semiconductor die, wherein each conductive strip in the conductive strip pair is located between a corresponding end of a first semiconductor die and a second semiconductor die in the first semiconductor die.

2. The method of claim 1, wherein the at least one conductive strip has a wavy pattern, and the method further comprises providing at least one flat portion in the conductive strip, wherein, Attachments include: The at least one second semiconductor die is attached to the at least one flat portion of the conductive strip.

3. The method according to claim 1, further comprising: Another die pad adjacent to the die pad is provided in the substrate, and At least one third semiconductor die is attached to the pad of the other die.

4. The method according to claim 1, further comprising: Using a first wire bonding pattern, the at least one first semiconductor die and the at least one second semiconductor die are coupled to each other in the stacked arrangement of the at least one second semiconductor die and the at least one first semiconductor die.

5. The method according to claim 1, further comprising: Using a second wire bonding pattern, the at least one first semiconductor die is coupled to a conductive structure in an array of conductive structures provided around the die pads in the substrate.

6. The method according to claim 1, further comprising: Using a third wire bonding pattern, the at least one second semiconductor die is coupled to a conductive structure in an array of conductive structures provided around the die pads in the substrate.

7. The method of claim 1, further comprising using a conductive attachment material to attach the at least one second semiconductor die across the conductive strips of the conductive strip pair in a bridge-like manner.

8. The method of claim 1, wherein the conductive strips are electrically coupled to each other through the at least one second semiconductor die.

9. A method for assembling a semiconductor device, comprising: At least one first semiconductor die having at least one conductive strip is disposed on a die pad in a substrate, the at least one conductive strip extending on the at least one first semiconductor die, wherein the at least one first semiconductor die is located between the substrate and the at least one conductive strip; as well as At least one second semiconductor die is attached to the at least one conductive strip to provide a stacked arrangement of the at least one second semiconductor die and the at least one first semiconductor die on the die pad, wherein the at least one conductive strip is located between the at least one first semiconductor die and the at least one second semiconductor die. The arrangement includes: arranging a pair of conductive strips to extend over the at least one first semiconductor die, wherein the first semiconductor die is located between the substrate and the pair of conductive strips; and The attachment includes: attaching the at least one second semiconductor die in a bridge-like manner across the conductive strips in the conductive strip pair to provide a stacked arrangement of the at least one second semiconductor die, wherein each conductive strip in the conductive strip pair is between the at least one first semiconductor die and the at least one second semiconductor die.

10. The method of claim 9, further comprising using a conductive attachment material to attach the at least one second semiconductor die across the conductive strips of the conductive strip pair in a bridge-like manner.

11. A semiconductor device, comprising: A substrate, including a die pad, on which at least one first semiconductor die is disposed, wherein at least one conductive strip extends on the at least one first semiconductor die, wherein the at least one first semiconductor die is located between the substrate and the at least one conductive strip, and At least one second semiconductor die, on the at least one conductive strip, to provide a stacked arrangement of the at least one second semiconductor die and the at least one first semiconductor die on the die pad, wherein the at least one conductive strip is between the at least one first semiconductor die and the at least one second semiconductor die. The at least one first semiconductor die includes a pair of adjacent first semiconductor dies disposed on the substrate; The at least one conductive strip comprises a pair of conductive strips, each conductive strip extending on one of the first semiconductor dies; Each of the first semiconductor dies is located between the substrate and the corresponding conductive strip in the conductive strip pair; as well as The at least one second semiconductor die is attached in a bridge-like manner across the conductive strips in the conductive strip pair to provide a stacked arrangement of the at least one second semiconductor die, wherein each conductive strip in the conductive strip pair is located between a corresponding end of a first semiconductor die and a second semiconductor die in the first semiconductor die.

12. The device of claim 11, wherein the at least one conductive strip has a wavy pattern, wherein the conductive strip has at least one flat portion, and wherein the at least one second semiconductor die is attached to the at least one flat portion of the conductive strip.

13. The device of claim 11, further comprising: Another die pad is provided in the substrate adjacent to the die pad; as well as At least one third semiconductor die is attached to the pad of the other die.

14. The device according to claim 11, further comprising: A first wire bonding pattern couples the at least one first semiconductor die and the at least one second semiconductor die to each other in the stacked arrangement of the at least one second semiconductor die and the at least one first semiconductor die.

15. The device according to claim 11, further comprising: A second wire bonding pattern couples the at least one first semiconductor die to a conductive structure in an array of conductive structures provided around the die pads in the substrate.

16. The device according to claim 11, further comprising: A third wire bonding pattern couples the at least one second semiconductor die to a conductive structure in an array of conductive structures provided around the die pads in the substrate.

17. The device of claim 11, further comprising a conductive attachment material for attaching the at least one second semiconductor die across the conductive strips of the conductive strip pair in a bridge-like manner.

18. The device of claim 11, wherein the conductive strips of the conductive strip pair are electrically coupled to each other via the at least one second semiconductor die.

19. A semiconductor device, comprising: At least one first semiconductor die having at least one conductive strip is disposed on a die pad in a substrate, the at least one conductive strip extending on the at least one first semiconductor die, wherein the at least one first semiconductor die is located between the substrate and the at least one conductive strip; as well as At least one second semiconductor die is attached to the at least one conductive strip to provide a stacked arrangement of the at least one second semiconductor die and the at least one first semiconductor die on the die pad, wherein the at least one conductive strip is located between the at least one first semiconductor die and the at least one second semiconductor die. The at least one conductive strip comprises a pair of conductive strips extending on the at least one first semiconductor die; The at least one first semiconductor die is located between the substrate and the conductive strip pair; as well as The at least one second semiconductor die is attached in a bridge-like manner across the conductive strips of the conductive strip pair to provide a stacked arrangement of the at least one second semiconductor die, wherein each conductive strip of the conductive strip pair is between the at least one first semiconductor die and the at least one second semiconductor die.

20. The device of claim 19, further comprising a conductive attachment material for attaching the at least one second semiconductor die across the conductive strips of the conductive strip pair in a bridge-like manner.

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