A method for improving metal trench defects in downstream processes

Abstract

This invention provides a method for improving metal trench defects in back-end processes. The semiconductor structure includes, from bottom to top, a PMD layer, an NDC layer, a TEOS layer, and a ULK layer; a stacked layer on the ULK layer, the stacked layer consisting of a first NFDARC layer, a TiN layer, and a second NFDARC layer from bottom to top; etching the stacked layer and the ULK layer to expose the upper surface of the TEOS layer; forming a first trench of a first width after etching the stacked layer; etching the ULK layer to form a second trench of a second width; forming a first step at the ramp of the first and second trenches; depositing a protective layer covering the second NFDARC layer, the sidewalls of the first and second trenches, the first step, and the exposed TEOS layer; removing the protective layer on the second NFDARC layer and the exposed TEOS layer; simultaneously etching the ULK layer, the TEOS layer, and the NDC layer along the protective layer on the sidewalls of the first and second trenches until the PMD layer is exposed, forming a third trench of a first width and a via of a second width; and removing the remaining protective layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving metal trench defects in back-end processes. Background Technology

[0002] In the copper interconnect process of the back-end metal (BEOL M1) of advanced semiconductor manufacturing, a metal hard mask method is used to simultaneously etch metal trenches and vias vias using an AIO process, followed by copper filling. In the AIO process, after the second nitrogen-free antireflective coating (NFDARC) layer is etched, ultra-low k dielectric (ULK) film etching is performed. However, due to the porous structure of ULK, it has a higher etching rate than the NFDARC film layer, easily forming kink defects near the NFDARC interface in the ULK. This results in thin or discontinuous barrier layer thickness at the kink during subsequent barrier layer deposition, and the kink cannot be fully filled during copper plating, forming void defects. These defects can lead to broken copper interconnects and other defects, causing the circuit to malfunction. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving metal trench defects in back-end processes, which solves the problem that kink-like defects are easily formed at the interface between the ultra-low dielectric layer and the nitrogen-free anti-reflective coating in the back-end metal processing.

[0004] To achieve the above and other related objectives, the present invention provides a method for improving metal trench defects in downstream processes, comprising at least:

[0005] Step 1: Provide a semiconductor structure, the semiconductor structure comprising: a PMD layer; an NDC layer located on the PMD layer; a TEOS layer located on the NDC layer; a ULK layer located on the TEOS layer; and a stacked layer on the ULK layer, the stacked layer comprising, from bottom to top, a first NFDARC layer, a TiN layer and a second NFDARC layer;

[0006] Step 2: Etch the stacked layers and the ULK layer until the upper surface of the TEOS layer is exposed; and after etching the stacked layers, a first trench of a first width is formed; the ULK layer is etched to form a second trench of a second width; the first width is greater than the second width; and the first and second trenches are connected, forming a first step at the slope of the first and second trenches;

[0007] Step 3: Deposit a protective layer on the semiconductor structure, the protective layer covering the upper surface of the second NFDARC layer, the sidewalls of the first and second trenches, the first step, and the exposed upper surface of the TEOS layer;

[0008] Step 4: Trace back the protective layer to remove the protective layer from the upper surface of the second NFDARC layer and the exposed upper surface of the TEOS layer;

[0009] Step 5: Perform AIO etching, which includes simultaneously etching the ULK layer, the TEOS layer, and the NDC layer along the protective layer on the sidewall of the first trench and the protective layer on the sidewall of the second trench until the upper surface of the PMD layer is exposed, forming a third trench of a first width and a via of a second width; after the AIO etching, the remaining protective layer adheres to the stacked sidewall of the third trench and the ULK layer sidewall of the via;

[0010] Step 6: Perform wet cleaning to remove the remaining protective layer.

[0011] Preferably, after etching to form the first and second trenches in step two, the semiconductor structure is wet-cleaned to remove etching byproducts.

[0012] Preferably, step three involves depositing the protective layer using physical vapor deposition.

[0013] Preferably, the thickness of the protective layer deposited in step three is 15 to 20 angstroms.

[0014] Preferably, the protective layer in step three is TaN or TiN.

[0015] Preferably, after the protective layer is etched back in step four, the semiconductor structure is cleaned to remove the byproducts from the etch-back process.

[0016] Preferably, during the wet cleaning process in step six, the etching byproducts from step five are also removed simultaneously.

[0017] As described above, the method of the present invention for improving metal trench defects in the back-end process has the following beneficial effects: The present invention improves the Kink defect phenomenon by depositing a protective layer with a low etching rate on the trench sidewall after the ULK is etched open. The protective layer with a low etching rate slows down the etching gas etching of the ULK near the NFDRAC interface. Attached Figure Description

[0018] Figure 1 The diagram shows a schematic of the semiconductor structure after etching and stacking in this invention.

[0019] Figure 2The diagram shows a schematic of a structure in which a protective layer is formed on a semiconductor structure in this invention.

[0020] Figure 3 The diagram shows the semiconductor structure after the protective layer has been etched back in this invention.

[0021] Figure 4 The diagram shows the structure of the semiconductor structure in this invention after AIO etching.

[0022] Figure 5 The diagram shows the semiconductor structure after wet cleaning according to the present invention.

[0023] Figure 6 The flowchart shown is a method for improving metal trench defects in the downstream process according to the present invention. Detailed Implementation

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] Please see Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0026] This invention provides a method for improving metal trench defects in downstream processes, such as... Figure 6 As shown, Figure 6 The flowchart shown is a method for improving metal trench defects in downstream processes according to the present invention, which includes at least:

[0027] Step 1: Provide a semiconductor structure, the semiconductor structure comprising: a PMD layer; an NDC layer located on the PMD layer; a TEOS layer located on the NDC layer; a ULK layer located on the TEOS layer; and a stacked layer on the ULK layer, the stacked layer comprising, from bottom to top, a first NFDARC layer, a TiN layer and a second NFDARC layer;

[0028] Step 2: Etch the stacked layers and the ULK layer until the upper surface of the TEOS layer is exposed; and after etching the stacked layers, a first trench of a first width is formed; the ULK layer is etched to form a second trench of a second width; the first width is greater than the second width; and the first and second trenches are connected, forming a first step at the slope of the first and second trenches; as shown Figure 1 As shown, Figure 1 The diagram shows a semiconductor structure after etching the stacked layers in this invention. Step two involves etching the stacked layers (first NFDARC layer 01, TiN layer (TiN), second NFDARC layer 02) and the ULK layer (ULK) until the upper surface of the TEOS layer (TEOS) is exposed; and etching the stacked layers forms a first trench A of a first width; etching the ULK layer forms a second trench B of a second width; the first width is greater than the second width; and the first and second trenches are interconnected, forming a first step C at the slope of the first and second trenches.

[0029] In a further step of this invention, after etching to form the first and second trenches in step two of this embodiment, the semiconductor structure is wet-cleaned to remove etching byproducts.

[0030] Step 3: Deposit a protective layer on the semiconductor structure, the protective layer covering the upper surface of the second NFDARC layer, the sidewalls of the first and second trenches, the first step, and the exposed upper surface of the TEOS layer;

[0031] Furthermore, in this embodiment, step three involves depositing the protective layer using physical vapor deposition.

[0032] Furthermore, in this embodiment, the thickness of the protective layer deposited in step three is 15–20 angstroms.

[0033] Furthermore, in this embodiment, the protective layer described in step three is TaN or TiN.

[0034] like Figure 2 As shown, Figure 2 This diagram illustrates the formation of a protective layer on a semiconductor structure according to the present invention. Step three involves depositing a protective layer 03 on the semiconductor structure. This protective layer 03 covers the upper surface of the second NFDARC layer 02, the sidewalls of the first trench A and the second trench B, the first step C, and the exposed upper surface of the TEOS layer. The protective layer is deposited using physical vapor deposition; the thickness of the deposited protective layer is 15–20 angstroms; and the protective layer is TaN or TiN.

[0035] Step 4: Trace back the protective layer to remove the protective layer from the upper surface of the second NFDARC layer and the exposed upper surface of the TEOS layer;

[0036] In a further step of this invention, after the protective layer is etched back in step four, the semiconductor structure is cleaned to remove the byproducts from the etch-back process.

[0037] like Figure 3 As shown, Figure 3 The diagram shows the semiconductor structure after the protective layer has been etched back in this invention. Step four involves etching back the protective layer 03, removing it from the upper surface of the second NFDARC layer 02 and the exposed upper surface of the TEOS layer. After etching back the protective layer, the semiconductor structure is cleaned to remove byproducts. The protective layer at the level of the first step is also removed during the etching back process.

[0038] Step 5: Perform AIO etching, which includes simultaneously etching the ULK layer, the TEOS layer, and the NDC layer along the protective layer on the sidewall of the first trench and the protective layer on the sidewall of the second trench until the upper surface of the PMD layer is exposed, forming a third trench of a first width and a via of a second width; after the AIO etching, the remaining protective layer adheres to the stacked sidewall of the third trench and the ULK layer sidewall of the via;

[0039] like Figure 4 As shown, Figure 4 The diagram shows the structure of the semiconductor structure after AIO etching in this invention. Step five involves AIO etching, which includes simultaneously etching the ULK layer, the TEOS layer, and the NDC layer along the protective layer 03 on the sidewall of the first trench A and the protective layer 03 on the sidewall of the second trench B until the upper surface of the PMD layer is exposed, forming a third trench D with a first width and a via E with a second width. After AIO etching, the remaining protective layer is attached to the stacked sidewall of the third trench D and the ULK layer sidewall of the via E.

[0040] Step Six: Perform wet cleaning to remove the remaining protective layer. For example... Figure 5 As shown, Figure 5 The diagram shows the semiconductor structure after wet cleaning according to the present invention. Step six involves wet cleaning to remove the remaining protective layer 03, forming the structure shown below. Figure 5 The structure shown.

[0041] Furthermore, in step six of this embodiment, during the wet cleaning process, the etching byproducts from step five are also removed simultaneously.

[0042] In summary, this invention improves the Kink defect phenomenon by depositing a protective layer with a low etching rate on the trench sidewall after the ULK is etched open. This low-etch-rate protective layer slows down the etching gas's etching effect on the ULK near the NFDRAC interface, thus mitigating the Kink defect phenomenon. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0043] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving metal trench defects in downstream processes, characterized in that, At least including: Step 1: Provide a semiconductor structure, the semiconductor structure comprising: a PMD layer; an NDC layer located on the PMD layer; a TEOS layer located on the NDC layer; a ULK layer located on the TEOS layer; and a stacked layer on the ULK layer, the stacked layer comprising, from bottom to top, a first NFDARC layer, a TiN layer and a second NFDARC layer; Step 2: Etch the stacked layers and the ULK layer until the upper surface of the TEOS layer is exposed; and after etching the stacked layers, a first trench of a first width is formed; the ULK layer is etched to form a second trench of a second width; the first width is greater than the second width; and the first and second trenches are connected, forming a first step at the junction of the first and second trenches; Step 3: Deposit a protective layer on the semiconductor structure. The protective layer covers the upper surface of the second NFDARC layer, the sidewalls of the first and second trenches, the first step, and the exposed upper surface of the TEOS layer. The protective layer is TaN or TiN. Step 4: Trace back the protective layer to remove the protective layer from the upper surface of the second NFDARC layer and the exposed upper surface of the TEOS layer; Step 5: Perform AIO etching, which includes simultaneously etching the ULK layer, the TEOS layer, and the NDC layer along the protective layer on the sidewall of the first trench and the protective layer on the sidewall of the second trench until the upper surface of the PMD layer is exposed, forming a third trench of a first width and a via of a second width; after the AIO etching, the remaining protective layer adheres to the stacked sidewall of the third trench and the ULK layer sidewall of the via; Step 6: Perform wet cleaning to remove the remaining protective layer.

2. The method for improving metal trench defects in downstream processes according to claim 1, characterized in that: After etching to form the first and second trenches in step two, the semiconductor structure is wet-cleaned to remove etching byproducts.

3. The method for improving metal trench defects in downstream processes according to claim 1, characterized in that: Step 3 involves depositing the protective layer using physical vapor deposition.

4. The method for improving metal trench defects in downstream processes according to claim 1, characterized in that: The thickness of the protective layer deposited in step three is 15–20 angstroms.

5. The method for improving metal trench defects in downstream processes according to claim 1, characterized in that: Step four involves re-etching the protective layer and then cleaning the semiconductor structure to remove byproducts from the re-etching process.

6. The method for improving metal trench defects in downstream processes according to claim 1, characterized in that: During the wet cleaning process in step six, the etching byproducts from step five are also removed simultaneously.

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