Chip package structure and manufacturing method thereof

Abstract

The application provides a chip packaging structure and a manufacturing method thereof. The packaging structure comprises a chip and a plastic packaging layer covering the chip. The chip comprises a passivation layer arranged on a functional surface side of the chip and a bonding pad distributed in the passivation layer. In the manufacturing process, a top layer metal above a cutting path is removed, at least one recess is formed on a side of the passivation layer after cutting, and the plastic packaging layer covers the recess. By removing the top layer metal of the cutting path, the problems such as metal layer winding and chip front surface collapse during wafer cutting can be reduced. Since the plastic packaging layer is filled in the recess, a nested structure is formed between the plastic packaging layer and the chip, the bonding force between the plastic packaging layer and the chip is increased, and the risk of internal cracking of the passivation layer is reduced.

Description

Technical Field

[0001] This invention relates to the field of packaging technology, and more specifically to a chip packaging structure and its manufacturing method. Background Technology

[0002] In the chip manufacturing process, test structures are generally set up on the wafer dicing kerf for process monitoring. The test structures are usually composed of multiple layers of metal, with the top layer metal being the thickest due to performance requirements, sometimes reaching several micrometers. However, the excessive thickness of the top layer metal at the dicing kerf can easily lead to problems such as metal lifting or wire drawing, chip breakage, internal chip delamination, and abnormal wear of the dicing blade when cutting the wafer along the dicing kerf, resulting in low production yield. Furthermore, the chips obtained by direct cutting have flat sides and low adhesion to the plastic encapsulation layer covering them, which can easily lead to problems such as internal cracking of the passivation layer and metal layer lifting. Summary of the Invention

[0003] The purpose of this invention is to provide a chip packaging structure and its manufacturing method.

[0004] This invention provides a chip packaging structure, including a chip and a molding compound covering the chip. The chip includes a passivation layer disposed on its functional surface and pads distributed within the passivation layer. The invention is characterized in that...

[0005] The passivation layer has at least one recess on its side, and the encapsulation layer covers the recess.

[0006] As a further improvement of the present invention, the recess has two sidewalls and a top wall and an inner wall connecting the two sidewalls of the recess, and the distance between the side surface of the top wall of the recess and the side surface of the encapsulation layer on the same side is greater than 0.

[0007] As a further improvement of the present invention, the chip further includes at least one dielectric layer disposed between the functional surface and the passivation layer, and an inner metal wiring layer is distributed in each dielectric layer, and the recessed portion and the dielectric layer surround to form a cavity with an opening facing the side.

[0008] As a further improvement of the present invention, the thickness of the recess is greater than the thickness of each inner metal layer.

[0009] As a further improvement of the present invention, it also includes at least one redistribution layer and an external connector disposed on the redistribution layer. Each redistribution layer includes an insulating layer and a metal wiring layer distributed within the insulating layer. The external connector is electrically connected to the pad through the metal wiring layer.

[0010] As a further improvement of the present invention, the molding layer covers at least one of the four sides of the chip and one of the upper surface of the passivation layer.

[0011] As a further improvement of the present invention, the molding compound covers the four sides of the chip and exposes the upper surface of the passivation layer. The molding compound extends laterally into the recess and is nested in the passivation layer. The redistribution layer is disposed on the passivation layer.

[0012] As a further improvement of the present invention, the molding layer at least covers the upper surface of the passivation layer, the molding layer extends downward into the recess and is nested in the passivation layer, and the redistribution layer is disposed on the molding layer.

[0013] As a further improvement of the present invention, an internal connector is provided within the encapsulation layer covering the upper surface of the passivation layer, the internal connector being electrically connected to the pad and the redistribution layer respectively.

[0014] This invention also provides a method for fabricating a chip packaging structure, comprising the following steps:

[0015] A wafer is provided, the wafer being divided into a plurality of chips, with cleavage lines formed between adjacent chips;

[0016] A top metal layer is formed on the surface of the wafer, and the top metal layer is patterned to form pads on the chip and dicing top metal on the dicing track;

[0017] A passivation layer is formed on the wafer, exposing the pads and the top metal of the dicing track.

[0018] Remove the top layer of metal from the cut surface;

[0019] The wafer is cut along the dicing track to obtain a single chip. The passivation layer forms a recess in the top metal region of the original dicing track, and the chip is encapsulated, with the encapsulation layer filling the recess.

[0020] As a further improvement of the present invention, "removing the metal layer" specifically includes:

[0021] A protective layer is formed on the surface of the pads, the protective layer exposing the top layer metal of the cut track;

[0022] Etching removes the top layer of metal from the cut surface;

[0023] Remove the protective layer.

[0024] As a further improvement of the present invention, before the step of "forming pads and top layer metal of the dicing track on the wafer" the step of further comprising:

[0025] At least one inner metal wiring layer and a dielectric layer are formed on the wafer.

[0026] As a further improvement of the present invention, the thickness of the top layer metal of the cutting channel is greater than the thickness of the inner metal wiring layer.

[0027] As a further improvement of the present invention, the step of "molding the chip and filling the recess with the molding layer" specifically includes:

[0028] A temporary carrier is provided, and the chip is disposed on the temporary carrier with the pads facing the temporary carrier.

[0029] The chip is encapsulated such that the encapsulation layer covers at least one side of the chip.

[0030] The temporary carrier is peeled off.

[0031] As a further improvement of the present invention, after the step of "peeling off the temporary carrier", the following step is also included:

[0032] At least one layer of metal wiring and insulating layer electrically connected to the pads is formed on the chip to constitute a redistribution layer;

[0033] An external connector electrically connected to the metal wiring layer is formed on the redistribution layer.

[0034] As a further improvement of the present invention, the following step is included before the step of "molding the chip and filling the recess with the molding layer":

[0035] An internal connector is provided on the pad.

[0036] As a further improvement of the present invention, the step of "molding the chip and filling the recess with the molding layer" specifically includes:

[0037] The chip is encapsulated to form an intermediate encapsulation layer, which covers the upper surface of the passivation layer and the internal interconnect, and exposes the upper surface of the internal interconnect.

[0038] As a further improvement of the present invention, the step of "molding the chip and filling the recess with the molding layer" specifically includes:

[0039] A temporary carrier is provided, and the chip with its internal connector is positioned on the temporary carrier in a direction facing the temporary carrier.

[0040] The chip is encapsulated to form an encapsulation layer, such that the encapsulation layer covers the chip and the intermediate encapsulation layer;

[0041] The temporary carrier is peeled off.

[0042] As a further improvement of the present invention, the step of "molding the chip and filling the recess with the molding layer" specifically includes:

[0043] A temporary carrier is provided, and the chip with its internal connector facing upwards is positioned on the temporary carrier.

[0044] The chip is encapsulated to form an encapsulation layer, which covers the chip and the internal interconnects.

[0045] The temporary carrier is peeled off.

[0046] As a further improvement to the present invention, the following steps are also included:

[0047] At least one layer of metal wiring and insulating layer electrically connected to the internal connector is formed on the molding layer to constitute a redistribution layer;

[0048] An external connector electrically connected to the metal wiring layer is formed on the redistribution layer.

[0049] The beneficial effects of this invention are: by removing the top layer metal of the dicing channel, this invention can reduce problems such as metal layer wire curling and chip front-side chipping that occur during wafer dicing. Furthermore, after dicing, a recess is formed on the side of the passivation layer of the chip, and the molding compound is filled in the recess. The molding compound and the chip form a nested structure, which increases the bonding force between the molding compound and the chip, reduces the risk of internal cracking of the passivation layer, and helps to improve yield and reduce packaging costs. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the chip packaging structure in Embodiment 1 of the present invention.

[0051] Figure 2a This is a three-dimensional structural diagram of the passivation layer recess in Embodiment 1 of the present invention.

[0052] Figure 2b yes Figure 1 An enlarged diagram of point A in the diagram.

[0053] Figures 3a to 3b This is a schematic diagram of the chip packaging structure in Embodiment 2 of the present invention.

[0054] Figure 4 This is a schematic diagram of the chip packaging structure in Embodiment 3 of the present invention.

[0055] Figures 5a to 5b This is a schematic diagram of the chip packaging structure in Embodiment 4 of the present invention.

[0056] Figure 6 This is a schematic diagram of the chip packaging structure in Embodiment 5 of the present invention.

[0057] Figure 7 This is a schematic diagram of a chip packaging structure fabrication method according to one embodiment of the present invention.

[0058] Figures 8 to 11c This is a schematic diagram of the steps in a chip packaging structure fabrication method according to an embodiment of the present invention.

[0059] Figure 12 This is a schematic diagram of step S5 in the chip packaging structure fabrication method of Embodiment 6 of the present invention.

[0060] Figures 13a to 13e This is a schematic diagram illustrating the specific steps of step S5 in the chip packaging structure fabrication method of Embodiment 6 of the present invention.

[0061] Figure 14 This is a schematic diagram of step S5 in the chip packaging structure fabrication method of Embodiment 7 of the present invention.

[0062] Figures 15a to 15d This is a schematic diagram illustrating the specific steps of step S5 in the chip packaging structure fabrication method of Embodiment 7 of the present invention.

[0063] Figure 16 This is a schematic diagram of step S5 in the chip packaging structure fabrication method of Embodiment 8 of the present invention.

[0064] Figures 17a to 17d This is a schematic diagram illustrating the specific steps of step S5 in the chip packaging structure fabrication method of Embodiment 8 of the present invention.

[0065] Figure 18 This is a schematic diagram of step S5 in the chip packaging structure fabrication method of Embodiment 9 of the present invention.

[0066] Figures 19a to 19e This is a schematic diagram illustrating the specific steps of step S5 in the chip packaging structure fabrication method of Embodiment 9 of the present invention. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0068] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0069] For ease of explanation, this document uses terms indicating relative spatial position, such as "above," "below," "behind," and "front," to describe the relationship of one unit or feature shown in the accompanying drawings relative to another unit or feature. Terms indicating relative spatial position can include different orientations of the device during use or operation besides those shown in the figures. For example, if the device in the figures is flipped, a unit described as being "below" or "above" other units or features will be located "below" or "above" other units or features. Therefore, the exemplary term "below" can encompass both "below" and "above" spatial orientations.

[0070] like Figure 1 As shown in Figure 2, the chip packaging structure provided in Embodiment 1 of the present invention includes a chip 1, a molding layer 2, a redistribution layer 3, and an external connector 4 disposed on the redistribution layer 3.

[0071] Chip 1 has opposing functional and non-functional surfaces. Chip 1 includes a passivation layer 11 disposed on its functional surface and pads 12 distributed within the passivation layer 11. At least one recess 111 is formed on the side of the passivation layer 11, and a molding compound 2 covers the recess 111. Before dicing the wafer to obtain a single chip 1, a relatively thick top metal layer is disposed on the wafer surface. This top metal layer is etched and patterned to form pads 12 on the chip and dicing top metal on the dicing track. The dicing top metal is used to monitor performance during wafer manufacturing. The passivation layer 11 partially covers and exposes the dicing top metal. The dicing top metal is removed by etching, forming an upward-opening cavity. When the wafer is diced along the dicing track, the complete cavity is cut open, forming two recesses 111 opening towards the side.

[0072] The passivation layer 11 is typically an insulating material such as silicon oxide or silicon nitride, covering the surface of chip 1 to provide insulation and protection. The metal layer is a metallic material with excellent conductivity, such as copper.

[0073] The molding compound 2 covers the recess 111 and is nested within the passivation layer 11. The material used for the molding compound 2 is such as an organic polymer resin with inorganic fillers, or an organic polymer resin with fiberglass cloth and fillers, or a polymer composite material with fillers such as epoxy resin, polyimide (PI), or dry film. It covers the chip 1 and plays a role in protecting the chip 1 and providing structural support for the electrical connection structure.

[0074] like Figure 2a and Figure 2bAs shown, the recess 111 further comprises two sidewalls 1111 and a top wall 1112 and an inner wall 1113 connecting the two sidewalls 1111. That is, the passivation layer 11 originally covering the top metal of the cutting channel forms the top wall 1112 of the recess. The distance between the side of the top wall 1112 of the recess and the side of the molding compound on the same side is greater than 0. That is, an opening 112 is also formed at the top wall 1112 of the recess, which cooperates with the recess 111 facing the side. Thus, whether it is only the side of the molding compound chip 1 or only the passivation layer 11 on the top surface of the molding compound chip 1, the molding compound can be filled into the recess 111.

[0075] Specifically, in this embodiment, the chip packaging structure is a fan-out packaging structure. The redistribution layer 3 is disposed on the passivation layer 11 and fans out to the outside of the functional surface area of ​​the chip 1. The molding layer 2 covers the four sides of the chip 1 and exposes the upper surface of the passivation layer 11. The molding layer 2 extends laterally into the recess 111 and is nested in the passivation layer 11.

[0076] Here, since the molding layer 2 is filled into the recess 111, the contact surface between it and the chip 1 changes from a planar structure in the conventional structure to a nested structure, so that the passivation layer 11 and the molding layer 2 play a mutually restrictive role in the vertical direction, which can increase the bonding force between the molding layer 2 and the chip 1 and reduce the risk of cracking inside the passivation layer 11.

[0077] Furthermore, since the top layer of metal on the dicing surface is usually presented as multiple square metal sheets spaced apart on each dicing surface, after removing all metal layers and cutting to obtain a single chip 1, multiple recesses 111 are formed on the four sides of the passivation layer 11. Thus, on each side, multiple nested structures can be formed between the molding layer 2 and the passivation layer 11, further enhancing the bonding force between the molding layer 2 and the chip 1.

[0078] Chip 1 also includes at least one dielectric layer 14 disposed between the functional surface and the passivation layer 11. An inner metal wiring layer 13 is distributed within each dielectric layer 14. The recessed portion and the dielectric layer form a cavity with an opening facing the side. The functional surface of chip 1 is electrically connected to the pad 12 through the inner metal wiring layer 13. The dielectric layer 14 is typically an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0079] Furthermore, since the top metal layer is used for electrical interconnection with the outside world, outputting electrical signals, and needs to maintain a certain mechanical strength, its thickness is usually greater than the thickness of each inner metal wiring layer 13, that is, the thickness of the recess 111 is greater than the thickness of each inner metal wiring layer 13. Here, by forming a thicker recess 111, more molding compound 2 can be filled inside it, thereby increasing the mechanical strength of the nested structure of the molding compound 2 within the passivation layer 11, and further enhancing the bonding force between the molding compound 2 and the chip 1.

[0080] In Embodiment 1, at least one redistribution layer 3 is formed on the passivation layer 11 and the molding compound 2. The redistribution layer 3 includes an insulating layer 31 and a metal wiring layer 32 distributed within the insulating layer 31. An external connector 4 disposed on the redistribution layer 3 is electrically connected to the pad 12 through the metal wiring layer 32. The molding compound 2 covers the bottom surface of the chip 1 and the four sides of the chip 1.

[0081] The insulating layer 31 is a polymer insulating layer such as polyimide, epoxy resin, acrylate, or nano-filled phenolic resin. The metal wiring layer 32 is a metal with excellent conductivity, such as copper. The external connector 4 includes a metal layer under the ball and solder balls or metal bumps disposed thereon, used to form an electrical connection between the chip package structure and the external circuit.

[0082] Furthermore, the chip packaging structure may also include a support layer disposed on the back of the molding layer 2, which serves as a support to reduce the warpage of the chip packaging structure.

[0083] like Figure 3a and Figure 3b As shown, this is the chip packaging structure provided in Embodiment 2 of the present invention. The difference between this structure and Embodiment 1 is that the molding compound 2 covers the four sides of the chip 1 and the passivation layer 11, and selectively covers the bottom surface of the chip 1. The redistribution layer 3 is formed on the molding compound 2. When the packaging structure has high heat dissipation requirements, the non-functional surfaces of the chip can be exposed to enhance heat dissipation. An internal connector 5 is also provided within the molding compound 2 located on the upper surface of the passivation layer 11. The internal connector 5 is electrically connected to the pads 12 and the redistribution layer 3, and is an electrical connection structure such as a solder ball or a metal bump.

[0084] like Figure 4 , Figure 5a and Figure 5b As shown, the chip packaging structures provided in Embodiments 3 and 4 of the present invention are fan-in packaging structures, which are similar to those in Embodiments 1 and 2, respectively. The difference is that the redistribution layer 3 is disposed within the functional surface area of ​​the chip 1.

[0085] like Figure 6As shown, this is the chip packaging structure provided in Embodiment 5 of the present invention. The difference between the structure and Embodiment 4 is that the molding layer 2 only fills the area between the chip 1 and the redistribution layer 3, covers the passivation layer 11, extends downward along the opening 112 into the recess 111, and is nested in the passivation layer 11.

[0086] In addition to the above embodiments, the nested structure of the molding layer 2 and passivation layer 11 in the chip packaging structure provided by the present invention can also be applied to other wafer-level chip packaging structures, or flip-chip packaging structures such as ball grid array packaging, or traditional wire bonding packaging structures such as wire bonding packaging. The present invention does not impose specific limitations on these.

[0087] like Figure 7 As shown, the present invention also provides a method for fabricating a chip packaging structure, comprising the following steps:

[0088] S1: As Figure 8 As shown, a wafer 1a is provided, which is divided into multiple chips 1, and dicing channels 1b are formed between adjacent chips 1.

[0089] It should be noted that the cutting channel 1b between adjacent chips 1 is only a blank area reserved between the two chips 1 for cutting, and there is no actual boundary line between the cutting channel 1b and the chips 1 on both sides.

[0090] S2: As Figure 9 As shown, a top metal layer is formed on the surface of wafer 1a, and the top metal layer is patterned to form pads 12 on the chip and dicing top metal 16 on the dicing track.

[0091] Specifically, a top metal layer is deposited on the surface, and pads 12 and cut-out top metal 16 are etched on the top metal layer.

[0092] Furthermore, prior to step S2, at least one inner metal wiring layer 13 and a dielectric layer 14 are formed on wafer 1a. The thickness of the top metal layer is greater than the thickness of the inner metal wiring layer 13.

[0093] S3: As Figure 10 As shown, a passivation layer 11 is formed on wafer 1a, exposing pads 12 and top metal 16 of the dicing track.

[0094] S4: Remove the top layer of metal from the cut track 16.

[0095] Specifically, step S4 includes:

[0096] S41: As Figure 11aAs shown, a protective layer is formed on the surface of the pad 12. The protective layer 6 exposes the top metal 16 of the dicing channel. The protective layer is made of photoresist or the like. The required shape is formed by photolithography. The protective layer 6 is set to avoid damage to the pad 12 in subsequent steps.

[0097] S42: As Figure 11b As shown, corrosion removes the top layer of metal 16 from the cut surface;

[0098] S43: As Figure 11c As shown, remove protective layer 6.

[0099] S5: Cut wafer 1a along dicing 1b to obtain a single chip 1. Passivation layer 11 forms a recess 111 with a lateral opening in the original metal layer region. Moldulate chip 1 and fill the recess 111 with molding layer 2.

[0100] Depending on the process requirements, mechanical cutting or laser cutting methods can be selected. Furthermore, since the top layer metal 16 of the cutting channel with a relatively large thickness is removed, the cutting process can be carried out more smoothly regardless of the cutting method chosen, thereby greatly reducing the problems of chip 1 cracking and passivation layer 11 delamination that occur when cutting wafer 1a.

[0101] Depending on the different packaging structures, the specific steps in step S5 may vary. The following describes several embodiments in detail. The steps before step S5 in the following embodiments are the same as the steps described above, and will not be repeated here.

[0102] like Figure 12 As shown, Example 6 is used to fabricate a fan-out package structure in which the molding compound 2 covers the four sides and bottom of the chip 1. Step S5 specifically includes:

[0103] S5a1: such as Figure 13a As shown, a single chip 1 is obtained by cutting wafer 1a along the cutting path 1b;

[0104] S5a2: such as Figure 13b As shown, a temporary carrier 7 is provided, and the chip 1 is disposed on the temporary carrier 7 with the pads 12 facing the temporary carrier 7.

[0105] S5a3: such as Figure 13c As shown, the chip 1 is encapsulated, and the encapsulation layer 2 covers at least one side of the chip 1;

[0106] S5a4: such as Figure 13d As shown, the temporary carrier 7 is stripped off.

[0107] S5a5: such as Figure 13eAs shown, at least one layer of metal wiring layer 32 and insulating layer 31 electrically connected to pad 12 are formed on chip 1 to form redistribution layer 3, and an external connector 4 electrically connected to metal wiring layer 32 is formed on redistribution layer 3.

[0108] like Figure 14 As shown, Example 7 is used to fabricate a fan-out package structure with an internal connector 5 and a molding layer that only covers the upper surface of the passivation layer 11. Step S5 specifically includes:

[0109] S5b1: As Figure 15a As shown, an inner connector 5 is provided on pad 12.

[0110] S5b2: such as Figure 15b As shown, the molded chip 1 forms an intermediate molding layer 2a, which covers the upper surface of the passivation layer 11 and the internal connector, and exposes the upper surface of the internal connector.

[0111] S5b3: such as Figure 15c As shown, a single chip is obtained by cutting along the cutting path.

[0112] S5b41: As Figure 15d As shown, at least one layer of metal wiring layer 32 and insulating layer 31 electrically connected to pad 12 are formed on the intermediate molding layer 2 to form a redistribution layer 3, and an external connector 4 electrically connected to the metal wiring layer 32 is formed on the redistribution layer 3.

[0113] like Figure 16 As shown, Example 8 is used to fabricate a fan-out package structure with internal connectors 5 and a molding compound covering multiple sides of the chip 1. The preceding steps in step S5 are the same as in Example 7, but the difference lies in the steps following S5b3, including:

[0114] S5b42: such as Figure 17a As shown, a temporary carrier 7 is provided, and the internal connector 5 of the chip 1 is disposed on the temporary carrier 7 in a direction facing the temporary carrier 7.

[0115] S5b43: such as Figure 17b As shown, the chip 1 is encapsulated to form a molding layer 2, so that the molding layer 2 covers the chip 1 and the intermediate molding layer 2;

[0116] S5b44: such as Figure 17c As shown, the temporary carrier 7 is stripped off.

[0117] S5b45: such as Figure 17dAs shown, at least one metal wiring layer 32 and an insulating layer 31 electrically connected to the pads 12 are formed on the intermediate molding compound 2, constituting a redistribution layer 3. An external connector 4 electrically connected to the metal wiring layer 32 is formed on the redistribution layer 3. The area of ​​the redistribution layer 3 can be selected as needed to form a fan-in or fan-out chip package structure.

[0118] like Figure 18 As shown, Example 9 is used to fabricate a fan-out package structure having an internal connector 5 and a molding compound covering multiple sides of the chip 1. Step S5 includes:

[0119] S5c1: such as Figure 19a As shown, an internal connector 5 is provided on the pad 12, and a single chip 1 is obtained by cutting along the dicing path.

[0120] S5c2: such as Figure 19b As shown, a temporary carrier 7 is provided, and the connector 5 inside the chip 1 is positioned upward on the temporary carrier 7.

[0121] S5c3: such as Figure 19c As shown, the plastic-encapsulated chip forms a plastic layer 2, which covers the internal connector 5 of the chip 1.

[0122] S5c4: such as Figure 19d As shown, the temporary carrier 7 is stripped off.

[0123] S5c5: such as Figure 19e As shown, at least one metal wiring layer 32 and an insulating layer 31 electrically connected to the pads 12 are formed on the intermediate molding compound 2, constituting a redistribution layer 3. An external connector 4 electrically connected to the metal wiring layer 32 is formed on the redistribution layer 3. The area of ​​the redistribution layer 3 can be selected as needed to form a fan-in or fan-out chip package structure.

[0124] In addition to the above embodiments, the chip packaging structure manufacturing method provided by the present invention can also be applied to other wafer 1a level chip packaging structures, or chip 1 flip packaging structures such as ball grid array packaging, or traditional wire bonding packaging structures such as wire bonding packaging. In different packaging structure manufacturing processes, by removing the top layer metal 16 of the dicing channel, it can also prevent the residual top layer metal 16 of the dicing channel from falling onto the circuit board and causing a short circuit, or the residual top layer metal 16 of the dicing channel from lifting up and touching the lead wire, causing a short circuit or leakage. The present invention does not impose specific limitations on this.

[0125] In summary, by removing the top layer metal of the dicing channel, this invention can reduce problems such as metal layer wire curling and chip front-side chipping that occur during wafer dicing. Furthermore, the diced chip forms a recess on the side of the passivation layer, and the molding compound fills the recess. The molding compound and the chip form a nested structure, which increases the bonding force between the molding compound and the chip and reduces the risk of cracking inside the passivation layer.

[0126] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0127] The detailed descriptions listed above are merely specific descriptions of feasible implementations of the present invention and are not intended to limit the scope of protection of the present invention. All equivalent implementations or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip packaging structure, comprising a chip and a molding compound covering the chip, wherein the chip includes a passivation layer disposed on its functional surface side and pads distributed within the passivation layer, characterized in that, At least one recess is formed on the side of the passivation layer, and the molding layer covers the recess. The recess has two sidewalls and a top wall and an inner wall connecting the two sidewalls of the recess. The distance between the sidewall of the top wall of the recess and the sidewall of the encapsulation layer on the same side is greater than 0. The sidewall of the top wall of the recess is located between the sidewall of the encapsulation layer on the same side and the inner wall. The chip further includes at least one dielectric layer disposed between the functional surface and the passivation layer, and an inner metal wiring layer is distributed in each dielectric layer. The recess and the dielectric layer surround to form a cavity with an opening facing the side. The chip packaging structure includes at least one redistribution layer, the redistribution layer is located on the side of the pad away from the dielectric layer, and the redistribution layer and the pad are electrically connected; The molding layer covers at least one of the four sides of the chip and one of the upper surfaces of the passivation layer; The molding compound covers the four sides of the chip and exposes the upper surface of the passivation layer. The molding compound extends laterally into the recess and is nested within the passivation layer. The redistribution layer is disposed on the passivation layer. Alternatively, the molding layer may at least cover the upper surface of the passivation layer, extend downward into the recess, be nested within the passivation layer, and the redistribution layer may be disposed on the molding layer.

2. The chip packaging structure according to claim 1, characterized in that, The thickness of the recess is greater than the thickness of each inner metal wiring layer.

3. The chip packaging structure according to claim 1, characterized in that, It also includes external connectors disposed on the redistribution layers, each redistribution layer including an insulating layer and a metal wiring layer distributed within the insulating layer, the external connectors being electrically connected to the pads through the metal wiring layers.

4. The chip packaging structure according to claim 1, characterized in that, An internal connector is also provided within the molding compound covering the upper surface of the passivation layer. The internal connector is electrically connected to the pad and the redistribution layer, respectively.

5. A method for fabricating a chip packaging structure, characterized in that, Including the following steps: A wafer is provided, the wafer being divided into a plurality of chips, with cleavage lines formed between adjacent chips; At least one inner metal wiring layer and a dielectric layer are formed on the wafer; A top metal layer is formed on the surface of the wafer, and the top metal layer is patterned to form pads on the chip and dicing top metal on the dicing track; The pads and the top metal of the cut track are disposed on the inner metal wiring layer and the dielectric layer; A passivation layer is formed on the wafer, exposing the pads and the top metal of the dicing track. Remove the top layer of metal from the cut surface; The wafer is cut along the dicing track to obtain a single chip, and the passivation layer forms a recess in the top metal region of the original dicing track; The chip is encapsulated, and the encapsulation layer fills the recess; wherein the recess has two sidewalls and a top wall and an inner wall connecting the two sidewalls of the recess, the distance between the side of the top wall of the recess and the side of the encapsulation layer on the same side is greater than 0, and the side of the top wall of the recess is located between the side of the encapsulation layer on the same side and the inner wall; the recess and the dielectric layer surround to form a cavity with an opening facing the side. The encapsulated chip specifically includes: A temporary carrier is provided, and the chip is disposed on the temporary carrier with the pads facing the temporary carrier. The chip is encapsulated such that the encapsulation layer covers at least one side of the chip, and the encapsulation layer extends at least laterally or downward into the recess. Peel off the temporary carrier; After the temporary carrier is stripped off, at least one layer of metal wiring layer and insulating layer electrically connected to the pads is formed on the chip, constituting a redistribution layer; An external connector electrically connected to the metal wiring layer is formed on the redistribution layer.

6. The chip packaging structure fabrication method according to claim 5, characterized in that, "Removing the top layer of metal from the cut track" specifically includes: A protective layer is formed on the surface of the pads, the protective layer exposing the top layer metal of the cut track; Etching removes the top layer of metal from the cut surface; Remove the protective layer.

7. The method for fabricating a chip packaging structure according to claim 5, characterized in that, The thickness of the top metal layer is greater than the thickness of the inner metal wiring layer.

8. The method for fabricating a chip packaging structure according to claim 5, characterized in that, The step preceding the step of "molding the chip and filling the recess with the molding layer" includes the following step: An internal connector is provided on the pad.

9. The method for fabricating a chip packaging structure according to claim 8, characterized in that, The step "molding the chip and filling the recess with the molding layer" specifically includes: The chip is encapsulated to form an intermediate encapsulation layer, which covers the upper surface of the passivation layer and the internal interconnect, and exposes the upper surface of the internal interconnect.

10. The method for fabricating a chip packaging structure according to claim 9, characterized in that, The step "molding the chip and filling the recess with the molding layer" further includes: A temporary carrier is provided, and the chip with its internal connector is positioned on the temporary carrier in a direction facing the temporary carrier. The chip is encapsulated to form an encapsulation layer, such that the encapsulation layer covers the chip and the intermediate encapsulation layer; The temporary carrier is peeled off.

11. The method for fabricating a chip packaging structure according to claim 8, characterized in that, The step "molding the chip and filling the recess with the molding layer" specifically includes: A temporary carrier is provided, and the chip with its internal connector facing upwards is positioned on the temporary carrier. The chip is encapsulated to form an encapsulation layer, which covers the chip and the internal interconnects. The temporary carrier is peeled off.

12. The method for fabricating a chip packaging structure according to any one of claims 9 to 11, characterized in that, It also includes the following steps: At least one layer of metal wiring and insulating layer electrically connected to the internal connector is formed on the molding layer to constitute a redistribution layer; An external connector electrically connected to the metal wiring layer is formed on the redistribution layer.

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