Power rail mid-of-line (MOL) wiring

Abstract

The present disclosure relates to power rail mid-of-line (MOL) wiring. In certain aspects, a semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also includes a first gate contact electrically coupled to the first gate, where the first gate contact is formed from a first mid-of-line (MOL) metal layer, and a second gate contact electrically coupled to the second gate, where the second gate contact is formed from the first MOL metal layer. The semiconductor die further includes an interconnect formed from a second MOL metal layer, where the interconnect is electrically coupled to the first and second gate contacts, and at least a portion of the interconnect is under the power rail.

Description

[0001] Cross-references to related applications

[0002] This application is a divisional application of the invention patent application with an international filing date of October 11, 2016, international application number PCT / US2016 / 056472, which entered the Chinese national phase on May 7, 2018, Chinese national application number 201680064949.5, and entitled "Middle of Electric Rail Entry Line (MOL) Wiring". Technical Field

[0003] The aspects of this disclosure generally relate to wiring on a die, and more particularly to wiring in the middle of the line (MOL) on a die. Background Technology

[0004] A semiconductor die can include many semiconductor devices (e.g., transistors). Semiconductor devices can be interconnected through one or more metal layers to form an integrated circuit. As device size shrinks, wiring congestion on the die increases, making it more difficult to interconnect the devices on the die. Summary of the Invention

[0005] The following is a simplified overview of one or more embodiments to provide a basic understanding of such embodiments. This overview is not a comprehensive overview of all contemplated embodiments and is neither intended to identify key or essential elements of all embodiments nor to define the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that follows.

[0006] According to one aspect, a semiconductor die is provided. The semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die further includes: a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed by a first center-of-line (MOL) metal layer; and a second gate contact electrically coupled to a second gate, wherein the second gate contact is formed by the first MOL metal layer. The semiconductor die further includes an interconnect formed by a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, and at least a portion of the interconnect is below the power rail.

[0007] The second aspect relates to a semiconductor die. The semiconductor die includes a power rail, a gate, and a source. The semiconductor die also includes a gate contact electrically coupled to the gate, wherein the gate contact is formed by a first center-of-line (MOL) metal layer. The semiconductor die also includes an interconnect formed by a second MOL metal layer, wherein the interconnect is electrically coupled to the gate contact and the source, and at least a portion of the interconnect is below the power rail.

[0008] The third aspect relates to a semiconductor die. The semiconductor die includes a power rail, a first unit, and a second unit. The first unit includes a first plurality of gates and a first plurality of source / drain electrodes, and the second unit includes a second plurality of gates and a second plurality of source / drain electrodes. The semiconductor unit further includes: a first gate contact electrically coupled to one of the first plurality of gates, wherein the first gate contact is formed by a first center-of-line (MOL) metal layer; and a second gate contact electrically coupled to one of the second plurality of gates, wherein the second gate contact is formed by the first MOL metal layer. The semiconductor die also includes an interconnect formed by a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts and is wired below the power rail. Attached Figure Description

[0009] Figure 1 A side view of an exemplary semiconductor die according to certain aspects of this disclosure is shown.

[0010] Figure 2 A side view of an exemplary structure for coupling a gate to a metal layer according to certain aspects of this disclosure is shown.

[0011] Figure 3 A side view of an exemplary structure for coupling a source / drain to a metal layer according to certain aspects of this disclosure is shown.

[0012] Figure 4 A top view of an exemplary semiconductor die according to certain aspects of this disclosure is shown.

[0013] Figure 5 An exemplary local interconnection formed by a metal layer M1 according to certain aspects of this disclosure is shown.

[0014] Figure 6A and Figure 6B Some aspects of this disclosure are shown. Figure 5 A side view of an exemplary local interconnection section.

[0015] Figure 7 A top view of an exemplary interconnect formed by a metal layer M1 and used for wiring between cells, according to certain aspects of this disclosure, is shown.

[0016] Figure 8A and Figure 8B A top view of an exemplary interconnection providing wiring under a metal M1 power rail, according to certain aspects of this disclosure, is shown.

[0017] Figure 9 Some aspects of this disclosure are shown. Figure 8A and Figure 8B Side view of the interconnection section.

[0018] Figure 10A and Figure 10B A top view of another exemplary interconnection providing wiring under a metal M1 power rail, according to certain aspects of this disclosure, is shown.

[0019] Figure 11 Some aspects of this disclosure are shown. Figure 10A and Figure 10B Side view of the interconnection section.

[0020] Figure 12 A circuit diagram of a plurality of transistors according to certain aspects of the present disclosure is shown, wherein the source and gate of the transistors are ligated to provide an electrical barrier.

[0021] Figure 13A and Figure 13B The present disclosure illustrates certain aspects of its implementation. Figure 12 A top view of the interconnection section of the circuit below the metal M1 power rail.

[0022] Figure 14 Some aspects of this disclosure are shown. Figure 13A and Figure 13B Side view of the interconnection section. Detailed Implementation

[0023] The following detailed description with reference to the accompanying drawings is intended as a description of various configurations and is not intended to imply that the concepts described herein can be practiced in only the configurations in which they are implemented. This detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0024] Figure 1 A simplified example of a semiconductor die (chip) 110 is shown. The semiconductor die 110 includes multiple interconnect metal layers, wherein adjacent interconnect metal layers are separated by one or more insulating layers. Different interconnect metal layers may be interconnected using vias and / or other structures, which are not shown for illustrative purposes. Figure 1 As shown in the diagram, the bottommost interconnect metal layer is labeled M1. The interconnect metal layer immediately above interconnect metal layer M1 is labeled M2, the interconnect metal layer immediately above metal layer M2 is labeled M3, and so on. In this example, semiconductor die 110 includes nine interconnect metal layers labeled M1-M9.

[0025] Interconnect metal layers M1-M9 are used to couple various components of the die to each other, to one or more off-die devices, and / or to one or more power supplies. Typically, as discussed further below, metal layer M1 is formed on top of a semiconductor device (e.g., a transistor) on the die and coupled to the semiconductor device using contact structures. Metal layer M1 can be used to provide power rails for the semiconductor devices on the die, couple semiconductor devices on the die to each other, and / or couple semiconductor devices on the die to higher metal layers. At this point, Figure 1 An example of a transistor 120 (e.g., a field-effect transistor) under a metal layer M1 is shown. The transistor 120 is formed on a substrate 150 of a die before metals M1-M9 are deposited on it. The transistor 120 includes a gate 130, a first source / drain 140a, and a second source / drain 140b. The gate 130 may comprise polysilicon and / or other materials. As used herein, the term "source / drain" indicates that the corresponding structure can function as either a source or a drain. Although for the sake of simplicity... Figure 1 The image shows a single transistor 120, but it will be understood that the semiconductor die 110 comprises a plurality of transistors. It will also be understood that... Figure 1 It is not drawn to scale, and the thickness of metal layers M1-M9 and the space between adjacent metal layers can vary on the die.

[0026] Transistor 120 can be formed on the die using either planar technology or FinFET technology. Figure 1 An example of transistor 120 being formed using a planar process is shown. In this example, transistor 120 includes a gate dielectric 145 (e.g., gate oxide) between the gate and the channel of the transistor. For a transistor (not shown) formed using a FinFET process, the transistor may include one or more fins for forming a channel between a first source / drain and a second source / drain, and a gate formed on the fins. In either case, the transistor includes a gate, a first source / drain, and a second source / drain. Therefore, it will be understood that aspects of this disclosure are applicable to transistors formed using both planar and FinFET processes.

[0027] Figure 2 An exemplary contact structure 250 for coupling the gate 230 of a transistor (e.g., transistor 120) to a metal layer M1 is shown. In this example, the contact structure 250 is disposed between the gate 230 and the metal layer M1, and electrically couples the gate 230 to the metal layer M1. The contact structure 250 includes a first line center (MOL) metal layer (in... Figure 2The gate contact 252 is formed by the metal layer M1 (marked as "CB"). As used herein, the term "MOL" refers to the layer beneath the metal layer M1. The first MOL metal layer (CB) may include tungsten, copper, and / or other conductive materials. Figure 2 As shown, the gate contact 252 can contact the top of the gate 230. The contact structure 250 also includes a via 255 disposed between the gate contact 252 and the metal layer M1. The via 255 electrically couples the gate contact 252 to the metal layer M1.

[0028] Figure 3 An exemplary contact structure 350 is shown for coupling the source / drain 340 of a transistor (e.g., transistor 120) to a metal layer M1. In this example, the contact structure 350 is disposed between the source / drain 340 and the metal layer M1, and electrically couples the source / drain to the metal layer M1. The contact structure 350 includes a first source / drain contact portion 352 formed on top of the source / drain 340. The first source / drain contact portion 352 may be formed of a trench silicide (TS) layer. In this example, the first source / drain contact portion 352 may be formed by etching a trench in a dielectric material and filling the trench with a silicide material. The contact structure 350 also includes a second MOL metal layer (in Figure 3 The second source / drain contact 355 is formed by a layer of metal (CA). The second MOL metal layer (CA) may include tungsten, copper, and / or other conductive materials. Figure 2 In the example, the second source / drain contact 355 is stacked on top of the first source / drain contact 352. The contact structure 350 further includes a via 357 disposed between the second source / drain contact 355 and the metal layer M1. The via 357 electrically couples the second source / drain contact 355 to the metal layer M1. Figure 2 and Figure 3 Via 255 and via 357 can be formed from the same conductive layer.

[0029] Therefore, the first and second MOL metal layers (CB and CA) are conventionally used to couple the gate and source / drain to metal layer M1 and / or other higher metal layers, respectively. The first and second MOL metal layers (CB and CA) are not conventionally used to form global features. As used herein, "global feature" can refer to a structure shared by multiple cells. As discussed further below, an example of a global feature is a power rail formed by metal layer M1.

[0030] Figure 4An exemplary top view of die 110 with metal layers M2-M9 removed for illustrative simplicity is shown. In this example, die 110 includes a first power rail 410 formed of metal layer M1, a second power rail 412 formed of metal layer M1, and a third power rail 414 formed of metal layer M1. Power rail 412 can be formed from metal layer M1 using any metal etching process known in the art. The first and third power rails 410 and 414 can have a supply voltage Vdd, and the second power rail 412 can have a supply voltage Vss, where Vdd can be a positive voltage and Vdd can be approximately zero volts (e.g., ground) or another voltage below Vdd. Alternatively, the first and third power rails 410 and 414 can have a supply voltage Vss, and the second power rail 412 can have a supply voltage Vdd. It will be understood that each of power rails 410, 412, and 414 can be more than Figure 4 The one shown is longer. Figure 4 In the diagram, the structures below power rails 410, 412, and 414 are shown in dashed lines.

[0031] The die includes a first unit 450 and a second unit 455. Figure 4 In the example, the boundary between the first unit 450 and the second unit 455 is located below the second power rail 412, but it will be understood that this is not necessary. It will be understood that the die may include... Figure 4 More units are shown in the diagram.

[0032] The first unit 450 includes a plurality of gates 420a-420f (e.g., polysilicon gates) and a plurality of source / drain electrodes 430a-430j, which form a plurality of transistors within the first unit 450. At this point, Figure 4 An example of a transistor 460 formed by a gate 420b, a source / drain 430a, and a source / drain 430b is shown. Figure 4 In the example, gates 420a-420f are extended and arranged parallel to one or more source / drain electrodes between adjacent gates. For examples where gates 420a-420f comprise polysilicon, the gate may be referred to as a polysilicon conductor (PC).

[0033] The transistors within the first unit 450 can be connected via local interconnects ( Figure 4(Not shown) interconnected to form an integrated circuit performing one or more functions. For example, transistors can be interconnected to form circuits performing logic functions ("AND" gates, "OR" gates, "XOR" gates, etc.), circuits performing storage functions (flip-flops, latches, etc.), circuits performing multiplexing functions (e.g., multiplexers), etc. As discussed above, the transistors within the first unit 450 can be powered by first and second power rails 410 and 412 providing voltages Vdd and Vss. At this point, one or more transistors in the first unit 450 can be interconnected via one or more contact structures (e.g., Figure 2 and Figure 3 The contact structures 250 and 350 shown are coupled to the power rail.

[0034] The second unit 455 includes multiple gates 420b-420d, 420g, 420h, and 420i (e.g., polysilicon gates) and multiple source / drain electrodes 430k-430t, which form multiple transistors within the second unit 455. Figure 4 In the example shown, gates 420b-420d in the first cell 450 extend into the second cell 455 below the second power rail 412. Figure 4 In the example, gates 420b-420d, 420g, 420h and 420i are extended and arranged in parallel with one or more source / drain gates between adjacent gates.

[0035] The transistors within the second unit 455 can be connected via local interconnects ( Figure 4 (not shown) interconnected to form an integrated circuit performing one or more functions (e.g., any of the functions discussed above). As discussed above, the transistors within the second unit 455 can be powered by second and third power rails 412 and 414 providing voltages Vdd and Vss. At this point, one or more transistors in the second unit 455 can be connected via one or more contact structures (e.g., Figure 2 and Figure 3 The contact structures 250 and 350 shown are coupled to the power rail.

[0036] As discussed above, the transistors within a cell can be interconnected to form a circuit. In this respect, Figure 5 An example of a first local interconnect 510 and a second local interconnect 550 in the first unit 450 is shown, wherein each local interconnect is formed by a metal layer M1. For simplicity of explanation, from Figure 5 The middle part is omitted Figure 4 The reference numerals shown are for source / drain 430a-430t.

[0037] In this example, a first local interconnect 510 couples gates 420d and 420e, wherein the first local interconnect 510 is coupled to gate 420d via a first contact structure 520 and to gate 420e via a second contact structure 525. At this point, Figure 6A A side view of the first partial interconnect 510 is shown, wherein the first contact structure 520 includes a first gate contact 652a and a first via 655a, and the second contact structure 520 includes a second gate contact 652b and a second via 655b.

[0038] Return to Figure 5 The second local interconnect 550 couples the gate 420b and the source / drain 430b, wherein the second local interconnect 550 is coupled to the gate 420d through a third contact structure 555 and to the source / drain 430b through a fourth contact structure 560. In this respect, Figure 6B A side view of the second partial interconnect 550 is shown, wherein the third contact structure 555 includes a gate contact 662 and a first via 665, and the fourth contact structure 560 includes a first source / drain contact 672 (e.g., TS), a second source / drain contact 675, and a second via 678.

[0039] Generally, the metal layer M1 can be used to form local interconnects that interconnect gates, connect one or more gates to one or more source / drain terminals, interconnect source / drain terminals, and so on. Therefore, the metal layer M1 can be patterned to form local interconnects that interconnect transistors within cells to form circuits. As discussed further below, the metal layer M1 can also be used to form global interconnects between two or more cells.

[0040] Figure 7 An example is shown in which a metal layer M1 is used to form an interconnect 710, which couples transistors in first and second cells 450 and 455. In this example, the interconnect 710 is coupled to a gate 420b in the first cell 450 via a first contact structure 720 and to a gate 420d in the second cell 455 via a second contact structure 725. Each of the first and second contact structures 720 and 725 may include... Figure 2 The contact structure 250 is shown in the diagram. For example... Figure 7 As shown, the interconnect 710 provides wiring between the first unit 450 and the second unit 455. Therefore, the metal layer M1 can be used for both local wiring and global wiring.

[0041] However, the disadvantage of using metal layer M1 for interconnect 710 is that, Figure 7As shown, it requires an interruption in the second power rail 412 to pass through the second power rail 412. This is because the interconnect 710 and the second power rail 412 are formed of the same metal layer (i.e., metal layer M1). Figure 7 In the example, the second power rail 412 is interrupted into a first portion 412a and a second portion 412b to accommodate the interconnect 710. The interruption in the power rail causes power integrity degradation, which can lead to failure of time-sensitive circuitry. Power integrity degradation can include increased IR voltage drop in the power network and / or electromagnetic emissions. Another disadvantage is that the interconnect 710 occupies a significant area, causing congestion in the metallic wiring.

[0042] Generally, the wiring of metal layer M1 is restricted when it conflicts with a structure formed by metal layer M1 (such as a power rail, e.g., the second power rail 412). In this case, the wiring of metal layer M1 must be routed around the structure (which may be impossible in many cases), or the structure must be interrupted to allow the wiring of metal layer M1 to pass through (which may cause one or more of the problems discussed above).

[0043] As discussed further below, aspects of this disclosure provide wiring using first and second MOL metal layers (CA and CB) that avoid one or more of the disadvantages described above.

[0044] Figure 8A and Figure 8B A top view of an exemplary interconnection section 810 according to certain aspects of this disclosure is shown. Figure 8A The interconnection section 810, together with the second power rail 412, is shown, and Figure 8B The second power rail 412 is shown to provide an unobstructed view of the interconnection section 810. Figure 9 A side view of the interconnection section 810 is shown.

[0045] Interconnect 810 provides wiring below the second power rail 412 between gate 420b and gate 420d. Interconnect 810 is formed of a second MOL metal layer (CA), as discussed above, which is the same metal layer used to form source / drain contacts (e.g., source / drain contact 355). Figure 9 As shown, the interconnect portion 810 extends between and contacts the gate contacts 820 and 825 on the gates 420b and 420d, respectively. In this respect, the interconnect portion 810 acts as a bridge between the gate contacts 820 and 825. Figure 9 In the example, interconnect 810 contacts the sidewalls of gate contacts 820 and 825.

[0046] Therefore, the interconnect portion 810 (formed by the second MOL metal layer (CA)) and the gate contacts 820 and 825 (formed by the first MOL metal layer (CB)) electrically couple the gates 420b and 420d. Since the first MOL metal layer (CA) and the second MOL metal layer (CB) are formed at a horizontal plane lower than metal layer M1, the interconnect portion 810 and the gate contacts 820 and 825 can provide wiring between gates 420b and 420d below the second power rail 412. Therefore, it is not necessary to interrupt the second power rail 412. Figure 8A and Figure 9 As shown, the second power rail 412 is continuous without interruption. Furthermore, since the interconnect 810 and gate contacts 820 and 825 are below the metal layer M1, they do not interfere with the metal layer M1, thus reducing wiring congestion. As a result, area efficiency is improved.

[0047] Therefore, aspects of this disclosure use first and second MOL metal layers (CB and CA) to provide MOL wiring (e.g., between transistors). Since the first and second MOL metal layers (CB and CA) are formed at a lower level than metal layer M1, the MOL wiring is not subject to the same limitations as the wiring in metal layer M1. For example, MOL wiring can pass under a structure (e.g., a power rail) formed by metal layer M1 without requiring an interruption in the structure. In contrast, when metal layer M1 wiring conflicts with a metal layer M1 structure (e.g., a power rail), the metal layer M1 wiring must be routed around the structure (which may be impossible in many cases), or the structure must be interrupted to allow the metal layer M1 wiring to pass through. Therefore, the MOL wiring according to aspects of this disclosure can be advantageously used where the wiring using metal layer M1 would be highly restricted.

[0048] Although not in Figure 8A and Figure 8B It is clearly shown, but it will be understood, that the die may also include partial interconnects (e.g., such as...). Figure 5 The local interconnects 510 and 550 shown are used to interconnect transistors in the first unit 450 and the second unit 455 to form an integrated circuit.

[0049] Figure 10A and Figure 10B A top view of another exemplary interconnection 1010 according to certain aspects of this disclosure is shown. Figure 10A The interconnection section 1010 together with the second power rail 412 is shown, and Figure 10B The second power rail 412 is shown to provide an unobstructed view of the interconnection section 1010. Figure 11 A side view of the interconnection section 1010 is shown.

[0050] In this example, gate 420b in Figure 8 is interrupted as gate 420b-1 in the first unit 450 and gate 420b-2 in the second unit 455, gate 420c in Figure 8 is interrupted as gate 420c-1 in the first unit 450 and gate 420c-2 in the second unit 455, and gate 420d in Figure 8 is interrupted as gate 420d-1 in the first unit 450 and gate 420d-2 in the second unit 455.

[0051] In this example, interconnect 1010 provides wiring between gate 420b-1 and gate 420d-2 below the second power rail 412. Interconnect 1010 is formed of a second MOL metal layer (CA), as discussed above, which is the same metal layer used to form the source / drain contacts (e.g., source / drain contact 355). Figure 11 As shown, the interconnect portion 1010 extends between and contacts the gate contacts 1020 and 1025 on the gates 420b-1 and 420d-2, respectively. In this respect, the interconnect portion 1010 acts as a bridge between the gate contacts 1020 and 1025.

[0052] Therefore, the interconnect portion 1010 (which is formed of a second MOL metal layer (CA)) and the gate contacts 1020 and 1025 (which are formed of a first MOL metal layer (CB)) provide wiring between the gate 420b-1 in the first cell 450 and 420d-2 in the second cell. Figure 11 In the example, interconnect 1010 contacts the sidewalls of gate contacts 1020 and 1025. Since the first MOL metal layer (CA) and the second MOL metal layer (CB) are formed at a horizontal plane lower than metal layer M1, interconnect 1010 and gate contacts 1020 and 1025 can provide wiring below the second power rail 412.

[0053] It will be understood that aspects of this disclosure are not limited to the specific examples discussed. Generally, aspects of this disclosure use interconnects formed by a second MOL metal layer (CA) to provide wiring between cells below the metal M1 power rails (e.g., power rail 412). For example, the interconnects can couple a first gate in one cell to a second gate in another cell by extending between and contacting gate contacts on the first and second gates, wherein the gate contacts can be formed by the first MOL metal layer (CB). In this respect, the interconnects act as a bridge between the gate contacts. Since the second MOL metal layer (CA) is formed at a lower level than the metal layer M1, the interconnects can pass under the metal M1 power rails and therefore do not require interruptions in the metal M1 power rails.

[0054] In some respects, one or more transistors can be tie-off to provide electrical isolation between semiconductor devices (transistors). In these respects, the transistor is tie-off by coupling the source and gate of the transistor together. This permanently turns off the transistor, allowing it to act as an electrical barrier between semiconductor devices on opposite sides of the transistor.

[0055] On this point, Figure 12 This is a circuit diagram illustrating an example where transistors M1-M4 are bundled together to provide electrical isolation between nodes 1205, 1210, 1215, and 1220. In this example, the gates G1-G4 and sources S1-S4 of transistors M1-M4 are all connected to node 1230, which is coupled to the supply voltage Vdd. This effectively turns off transistors M1-M4 while providing an electrical barrier between nodes 1205, 1210, 1215, and 1220 (which may correspond to the drains D1-D4 of transistors M1-M4). As a result, a device (e.g., a transistor) coupled to one of nodes 1205, 1210, 1215, and 1220 is electrically isolated from the other nodes 1205, 1210, 1215, and 1220. Figure 12 In the example, transistors M1-M4 are p-type field-effect transistors (PFETs). However, it will be understood that transistors M1-M4 can be replaced by n-type field-effect transistors (NFETs), and the gate and source of the NFET are connected to ground.

[0056] Figure 13A and Figure 13B A top view of an exemplary interconnect 1310 is shown, which provides wiring below the second power rail 412 for implementation. Figure 12 The exemplary circuit shown is illustrated in the figure. Figure 13A The interconnection section 1310 together with the second power rail 412 is shown, and Figure 13B The second power rail 412 is shown to provide an unobstructed view of the interconnection section 1310. Figure 14 A side view of the interconnect portion 1310 is shown. As discussed further below, the interconnect portion 1310 may be formed of a second MOL metal layer (CA).

[0057] In this example, gate 420c and source / drain 430h can provide the gate G1 and source S1 of transistor M1, gate 420c and source / drain 430m can provide the gate G2 and source S2 of transistor M2, gate 420d and source / drain 430h can provide the gate G3 and source S3 of transistor M3, and gate 420d and source / drain 430m can provide the gate G4 and source S4 of transistor M4. Therefore, gate 420c can provide gates G1 and G2 for both transistors M1 and M2, and gate 420 can provide gates G3 and G4 for both transistors M3 and M4. Similarly, source / drain 430h can provide sources S1 and S3 for both transistors M1 and M3, and source / drain 430m can provide sources S2 and S4 for both transistors M2 and M4. The source / drain types 430g, 430l, 430i, and 430n can respectively provide the drains D1-D4 of transistors M1-M4.

[0058] In this example, interconnect 1310 extends and contacts gate contacts 1320 and 1325 on gates 420c and 420d, respectively. As a result, interconnect 1310 and gate contacts 1320 and 1325 couple the gates G1-G4 of transistors M1-M4 together. Figure 14 In the example shown, interconnect 1310 contacts the sidewalls of gate contacts 1320 and 1325.

[0059] Interconnect 1310 is also coupled to source / drain 430h and source / drain 430m. In this example, interconnect 1310 is coupled to source / drain 430h via a source / drain contact 1340 (e.g., TS source / drain contact) disposed between interconnect 1310 and source / drain 430h, and is coupled to source / drain 430m via a source / drain contact 1342 (e.g., TS source / drain contact) disposed between interconnect 1310 and source / drain 430m. Figure 14 In the example shown, interconnect 1310 contacts the top of source / drain contacts 1340 and 1342 (e.g., TS source / drain contacts).

[0060] Therefore, the interconnect 1310 couples the gates G1-G4 of transistors M1-M4 together, and also couples the sources S1-S4 of transistors M1-M4 together. As a result, the gates G1-G4 and sources S1-S4 of transistors M1-M4 are all coupled together.

[0061] Interconnect 1310 is also coupled to the second power rail 412 via a via 1350 disposed between interconnect 1310 and the second power rail 412. In one example, the second power rail 412 provides a supply voltage Vdd, and transistors M1-M4 are PFETs. As a result, in this example, the gates G1-G4 and sources S1-S4 of transistors M1-M4 are connected to Vdd. This effectively turns off transistors M1-M4, while providing an electrical barrier between the first cell 450 and the second cell 455, and more particularly between the source / drain terminals 430g, 430l, 430i, and 430n.

[0062] Therefore, the interconnect portion 1310 (which is formed of a second MOL metal layer (CA)) provides wiring under the second power supply 412 for binding transistors M1-M4 to form an electrical barrier. It will be understood that aspects of this disclosure are not limited to... Figures 12-14 Examples are shown below. Generally, aspects of this disclosure can be used to junction one or more transistors by using interconnects formed of a second MOL metal layer (CA), wherein the interconnects are coupled to the gate and source of each transistor. The interconnects can also be coupled to the metal M1 power rail via vias between the interconnects and the power rail. For the example where one or more transistors are PFETs, the power rail can provide a supply voltage Vdd. For the example where one or more transistors are NFETs, the power rail can provide a supply voltage Vss.

[0063] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will readily be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor die, comprising: A power rail, the power rail being formed of a first metal layer; First gate; Second gate; A first gate contact portion is electrically coupled to the first gate, wherein the first gate contact portion is formed by a first line center MOL metal layer, and the first MOL layer is below the first metal layer; A second gate contact portion is electrically coupled to the second gate, wherein the second gate contact portion is formed by the first MOL metal layer; as well as An interconnect portion is formed by a second MOL metal layer below the first metal layer. The interconnect portion is electrically coupled to the first gate contact portion and the second gate contact portion. The interconnect portion is substantially parallel to the power rail and directly below the power rail, and the power rail is continuous without interruption.

2. The semiconductor die according to claim 1, wherein the interconnect portion contacts the sidewall of the first gate contact portion and the sidewall of the second gate contact portion.

3. The semiconductor die according to claim 1, further comprising: The transistor source, wherein the interconnect is electrically coupled to the transistor source; as well as Through-holes, electrical coupling occurs between the interconnect and the power rail.

4. The semiconductor die according to claim 3, further comprising a source contact portion disposed between the transistor source and the interconnect portion.

5. The semiconductor die according to claim 4, wherein the source contact comprises trench silicide.

6. The semiconductor die of claim 3, wherein the transistor source and the first gate are part of a p-type field-effect transistor (PFET), and the power rail has a supply voltage Vdd.

7. The semiconductor die of claim 3, wherein the transistor source and the first gate are part of an n-type field-effect transistor (NFET), and the power rail is grounded.

8. The semiconductor die according to claim 1, further comprising: A first source, wherein the first source and the first gate are part of a first transistor; The second source, wherein the second source and the second gate are part of a second transistor, and the interconnect is electrically coupled to the first source and the second source; as well as Through-holes, electrical coupling occurs between the interconnect and the power rail.

9. The semiconductor die according to claim 1, further comprising: Transistor source / drain; Source / drain contacts are electrically coupled to the source / drain of the transistor, wherein the source / drain contacts are formed by the second MOL metal layer; as well as Through the via, electrical coupling occurs between the source / drain contact and the power rail.

10. A semiconductor die, comprising: A power rail, the power rail being formed of a first metal layer; Gate; Source pole; A gate contact portion electrically coupled to the gate, wherein the gate contact portion is formed by a first line center MOL metal layer, the first MOL metal layer being below the first metal layer; The source contact portion is coupled to the source electrode; as well as An interconnect portion is formed by a second MOL metal layer below the first metal layer. The interconnect portion is electrically coupled to the gate contact portion and the source contact portion. The interconnect portion is substantially parallel to the power rail and directly below the power rail, and the power rail is continuous without interruption.

11. The semiconductor die of claim 10, wherein the source contact comprises trench silicide.

12. The semiconductor die of claim 10, wherein the interconnect portion contacts the sidewall of the gate contact portion.

13. The semiconductor die of claim 10, further comprising a via electrically coupled between the interconnect and the power rail.

14. A semiconductor die, comprising: A power rail, the power rail being formed of a first metal layer; The first unit includes a first plurality of gates and a first plurality of source / drain electrodes; The second unit includes a second plurality of gates and a second plurality of source / drain electrodes; A first gate contact portion is electrically coupled to one of the first plurality of gates, wherein the first gate contact portion is formed by a first line center MOL metal layer, and the first MOL metal layer is below the first metal layer; A second gate contact is electrically coupled to one of the second plurality of gates, wherein the second gate contact is formed by the first MOL metal layer; as well as The interconnect portion, formed by a second MOL metal layer below the first metal layer, is electrically coupled to the first gate contact portion and the second gate contact portion and is substantially parallel to the power rails. It is wired directly below the power rails, and the power rails are continuous without interruption. The boundary between the first unit and the second unit is located directly below the power rail.

15. The semiconductor die of claim 14, wherein the interconnect portion contacts the sidewall of the first gate contact portion and the sidewall of the second gate contact portion.

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