Stacked structure of radio frequency chip module and packaging method thereof

Abstract

The application discloses a kind of stacking structure of radio frequency chip module and its packaging method, including package, chip and buried substrate, the chip of the package encapsulates flip chip in the chip carrying area of buried substrate, the package is also encapsulated with: inductive layer, the inductive layer is formed in package by electroplating and is located just above chip, the layer of the inductive layer is connected by the metal column of electroplating electrically between layer and layer;Line, the line is formed by electroplating to realize the electrical connection of inductive layer and buried substrate, the line is located around chip, the application adopts buried substrate and the inductive layer connection of electroplating, reasonably utilize space, adopt flip chip technology, parasitic inductance is small, reduce package size, applicable to consumer terminal, the layer number of electroplated inductive layer is adjustable, layer spacing is adjustable, frequency adaptation range is wide, from low frequency to high frequency can be adjusted and used, process is simple, cost is low.

Description

Technical Field

[0001] This invention application belongs to the field of chip packaging technology, and particularly relates to a stacking structure of an RF chip module and its packaging method. Background Technology

[0002] With the continuous advancement of integrated circuit packaging technology, the integration level of integrated circuits is increasing and their functions are becoming more and more abundant. Radio frequency (RF) chip packaging technology is one of the integrated circuit packaging technologies. In order to reduce the area of ​​RF chips on printed circuit boards, modularization of RF chips will be the main development trend.

[0003] Most RF chip modules use pre-packaged RF chips and a large number of passive RF components such as capacitors and inductors to be surface-mounted on printed circuit boards using surface mount technology. Inductors and capacitors are discrete components.

[0004] In signal processing, inductors are among the most important components. They typically perform several key functions, including circuit tuning, impedance matching, high-pass and low-pass filtering, and RF chokes. The characteristics of an inductor are the opposite of those of a capacitor; it blocks alternating current (AC) while allowing direct current (DC) to pass through. When a DC signal passes through the coil, the resistance is minimal due to the resistance of the conductor itself. However, when an AC signal passes through the coil, a self-induced electromotive force (EMF) is generated across the coil. This EMF is opposite to the direction of the applied voltage, thus hindering the AC signal. Therefore, an inductor's characteristic is to pass DC and block AC. The higher the frequency, the greater the coil impedance. Inductors are often used in circuits alongside capacitors to form LC filters, LC oscillators, and other similar components.

[0005] After inductors and capacitors are surface-mounted, electrical connections between the RF chip and the inductors and capacitors are achieved through processes such as wire bonding, enabling the RF chip to have specific current characteristics or emit signals. Then, it is packaged with encapsulant. The overall structure after packaging is very large. The main reasons for this large size are: first, the large number of passive components such as capacitors and inductors, and the large size of each individual component, resulting in a large overall package size; second, the strong parasitic effects of capacitors and inductors on the chip, occupying package space and hindering the miniaturization and thinning of electronic devices. Summary of the Invention

[0006] To address the problems in the prior art, this invention provides a stacked structure for an RF chip module and a packaging method thereof.

[0007] To achieve the above objectives, this invention application proposes a stacked structure for an RF chip module, comprising a package, a chip, and a buried capacitor substrate. The package encapsulates the chip, which is flip-chip mounted on the chip carrier region of the buried capacitor substrate. The package also encapsulates: An inductor layer is formed in the package by electroplating and is located directly above the chip. The layers of the inductor layer are electrically connected to each other by electroplated metal pillars. The circuit is formed by electroplating to achieve electrical connection between the inductor layer and the buried capacitor substrate, and the circuit is located around the chip; The capacitor is embedded inside the embedded capacitor substrate, and circuitry is plated inside the embedded capacitor substrate to achieve electrical connection between the inductor and the chip and the capacitor.

[0008] Furthermore, the upper surface of the embedded capacitor substrate is provided with a line-carrying area, which is located around the chip-carrying area to achieve electrical connection with the line.

[0009] Furthermore, the lower surface of the embedded capacitor substrate is provided with exposed external leads to enable circuit lead-out of the package.

[0010] Furthermore, the flip-chip mounting involves connecting the chip pins to the chip carrier area using solder paste.

[0011] Furthermore, the package is formed by multiple encapsulation processes using injection molding.

[0012] Furthermore, the inductor layer is a square spiral shape in a top view perpendicular to the flip chip surface of the buried capacitor substrate.

[0013] Furthermore, the inductor layer has a comb-like shape in a top view perpendicular to the flip chip surface of the buried capacitor substrate.

[0014] A semiconductor device includes the above-described package with a double-sided heat dissipation structure.

[0015] A method for packaging an RF chip module includes the following steps: Flip-chip mounting process: Provide an embedded capacitor substrate and flip-chip onto the chip carrier area on the embedded capacitor substrate; Electroplating inductor steps: Electroplating an inductor layer on the back of the chip to replace the inductor component; electroplating the circuit, which electrically connects the circuit carrying area of ​​the buried capacitor substrate and the inductor layer. Packaging steps: The chip, circuit, and inductor layer on the buried capacitor substrate are encapsulated in the package body, and the external pins of the buried capacitor substrate are exposed.

[0016] Furthermore, in the flip-chip mounting step, solder paste is applied to the chip carrier area of ​​the buried capacitor substrate, the chip is mounted with its front side facing the buried capacitor substrate, and the chip pins are soldered to the chip carrier area.

[0017] Furthermore, the encapsulation step includes a first encapsulation after the flip-chip bonding step. After the first encapsulation, holes are drilled in the encapsulation material to form vias to expose the circuit carrying area on the buried capacitor substrate. The circuits are electroplated at the vias.

[0018] Furthermore, the encapsulation step also includes layer-by-layer encapsulation during the electroplating of the inductor layer, wherein the inductor layers are electrically connected through metal pillars electroplated at both ends.

[0019] Furthermore, the inductor layer is a square spiral shape in a top view perpendicular to the flip chip surface of the buried capacitor substrate.

[0020] Furthermore, the inductor layer has a comb-like shape in a top view perpendicular to the flip chip surface of the buried capacitor substrate.

[0021] This invention application utilizes a buried capacitor substrate connected to an electroplated inductor layer, with the chip located inside the package, below the inductor layer, and the circuitry positioned around the chip. This design makes efficient use of space, reduces package size, employs a flip-chip process, minimizes parasitic inductance, eliminates the need for externally purchased discrete inductors and capacitors, and results in a small package size suitable for consumer devices. The number of electroplated inductor layers and the interlayer spacing are adjustable, providing a wide frequency range from low to high frequencies. The process is simple and cost-effective. Attached Figure Description

[0022] Figure 1 A cross-sectional view of a stacked structure for an RF chip module is provided for this invention. Figure 2 This application provides a product appearance drawing of a stacked structure for an RF chip module. Figure 3 A top view of an embodiment of the inductor layer of a stacked structure for an RF chip module according to this invention application; Figure 4 A top view of an embodiment 2 of an inductor layer in a stacked structure of a radio frequency chip module according to this invention application; Figure 5 This invention relates to a process flow diagram of a packaging method for an RF chip module.

[0023] The markings in the diagram are as follows: 1. Package; 2. Inductor layer; 3. Circuit; 4. Chip; 5. Embedded capacitor substrate; 6. Chip carrier area; 7. Circuit carrier area; 8. External pin. Detailed Implementation

[0024] To better understand the purpose, structure, and function of this invention application, the following description is provided in conjunction with the appendix. Figure 1-5 The present invention provides a more detailed description of the stacking structure and packaging method of the radio frequency chip module proposed in this application.

[0025] In the packaging process, to reduce the package size of RF chips, they need to be modularly stacked. Currently, RF chip stacking generally involves attaching a large number of passive components, such as purchased or self-produced inductors and capacitors, to the chip and then electrically connecting them via metal wire bonding. Finally, the chips are packaged to form a modular package. Alternatively, to reduce the package size, metal conductive blocks or electroplated circuit layers are used to achieve electrical connections. In general, inductors and capacitors are packaged separately, then mounted to achieve electrical connections, and finally encapsulated into a whole. The overall package size cannot be adjusted, and the packaged product size cannot meet the size requirements of some consumer terminals. Different types of RF chips require different inductors and capacitors to be selected according to the frequency range, resulting in low flexibility. Existing methods to further reduce the package size include embedding capacitors into the substrate to form a buried capacitor substrate, and then mounting the inductors and chips. However, the parasitic effects of inductors and the package size problem still exist.

[0026] Example 1 Please see Figure 1 , Figure 1 This invention provides a cross-sectional view of a stacked structure for an RF chip module (the inductor layer 2 in the figure is an example of Embodiment 2), including a package 1, a chip 4, and a buried capacitor substrate 5. The package 1 encapsulates the chip 4, which is flip-chip mounted on the chip carrier region 6 of the buried capacitor substrate 5. The package 1 also encapsulates: Inductor layer 2 is formed in the package 1 by electroplating and is located directly above the chip 4. The layers of inductor layer 2 are electrically connected to each other by electroplated metal pillars. Line 3 is formed by electroplating to achieve electrical connection between inductor layer 2 and buried capacitor substrate 5. Line 3 is located around chip 4. The capacitor is embedded inside the embedded capacitor substrate 5, and the embedded capacitor substrate 5 is electroplated with circuitry to achieve electrical connection between the inductor and the chip 4 and the capacitor.

[0027] Please see Figure 5 , Figure 5 This invention provides a process flow diagram of a packaging method for an RF chip module, comprising the following steps: S1: A buried capacitor substrate 5 is provided, on which a chip carrier area 6 and a line carrier area 7 are formed, and an external pin 8 is formed at the bottom of the buried capacitor substrate 5. S2: Flip-chip solder chip 4 to chip carrier area 6, and encapsulate it for the first time using molding compound; S3: Drill holes in the encapsulated material to expose the line-carrying area 7 of the buried capacitor substrate 5, and electroplate the vias to form lines 3. S4: Etch coil grooves into the encapsulation material, and then electroplate a spiral inductor layer 2; S5: Electroplated metal pillars achieve electrical connection between inductor layer 2 and circuit 3; S6: Re-encapsulate with molding compound to form package 1; Please see Figure 1 S1, the embedded capacitor substrate 5, also known as the built-in capacitor substrate, is a substrate in which the capacitor is made and encapsulated in the circuit board during the production and lamination process, thereby saving circuit board space and improving electrical performance. The embedded capacitor substrate 5 used in this application is an epoxy resin-based built-in capacitor substrate material (ECM) developed by 3M. Because the substrate is required as a carrier support in the packaging process, and the purchased capacitor components are then mounted, the embedded capacitor substrate 5 is used directly here, which can meet the needs of the packaging support carrier and the functional needs of the capacitor components, saving space for the subsequent packaging. The chip carrier area 6 and the circuit carrier area 7 are formed on the buried capacitor substrate 5 by etching grooves on the surface to be mounted on the buried capacitor substrate 5, and then electroplating pads as carrier areas. The physical parameters such as position, quantity and size of the pads are matched with the chip 4 to be mounted and the circuit 3 to be electroplated later. The electroplating material is consistent with the material of the chip pins and the circuit 3 to ensure the bonding force between them during soldering. The circuit carrier area 7 is set around the chip carrier area 6 to facilitate the routing of the circuit 3. The routing of the circuit 3 can make reasonable use of space and save packaging space. In this process, exposed external leads 8 are electroplated on the opposite side of the embedded capacitor substrate 5 to be mounted. Inside, according to actual production needs, leads are electroplated to electrically connect the bearing area and the external leads 8. This ensures that the circuit of the package body 1 is brought out after packaging, which is convenient for subsequent mounting onto the circuit board for secondary packaging at the packaging technology level.

[0028] Please see Figure 1 S2 and Chip 4 refer to the wafer package after the transistors have been integrated. The chip has multiple pins, and this application has four. Only two are visible in the cross-sectional view, and the other two are obscured. To ensure the soldering quality, one end of the chip pin is treated with tin plating, that is, a layer of tin is plated on the copper chip pin to ensure the firmness of the soldering effect. Then, the side of the chip 4 with the chip pins (the active side of the chip) is mounted facing the buried capacitor substrate 5. Before the chip is mounted, the buried capacitor substrate 5 has been printed with solder paste and solder resist on the area to be soldered (chip carrier area 6) using solder paste printing technology. After the chip pins are mounted corresponding to the chip carrier area 6, they are fixed firmly by reflow soldering. After soldering, the flip-chip mounting of chip 4 is completed. Multiple chips 4 can be mounted on a large area of ​​buried capacitor substrate 5 and then cut into a single finished product. Alternatively, a small number of chips 4 can be mounted on a small area of ​​buried capacitor substrate 5 and then packaged without cutting. Flip-chip 4 saves space and has low parasitic inductance. The first encapsulation is performed using molding compound. After encapsulation, the overall structure is a cuboid or cube. The sides of the buried capacitor substrate 5 and the bottom surface with the external leads 8 plated on are exposed to the molding compound.

[0029] Please see Figure 1 In addition to S3, this application uses laser drilling to form vias. The laser drills holes in the molding compound at the positions corresponding to the line carrier area 7 on the buried capacitor substrate 5 to expose the line carrier area 7. Then, the line 3 is formed at the via by electroplating. The bottom of the line 3 is plated together with the line carrier area 7 to form a stable electrical connection. The line 3 can ensure the electrical connection between the upper inductor layer 2 and the capacitor in the lower buried capacitor substrate 5.

[0030] Please see Figure 1 Following S4, the coil grooves are formed on the surface of the first encapsulation material through laser etching using photolithography and electroplating processes. Metal is then electroplated inside the coil grooves. After layer-by-layer encapsulation, etching, and electroplating, a spiral inductor layer 2 is finally formed. Alternatively, the coil grooves can be skipped and electroplating can be performed directly on the encapsulation material to improve process efficiency. In other words, the inductor layer 2 is formed by layer-by-layer electroplating of redistribution lines (RDLs). The number of layers in the inductor layer 2 can be selected according to actual production needs and the overall structure and frequency characteristics of the module, thus forming a multi-layer winding with a wide frequency adaptability, adjustable from low to high frequencies. The interlayer spacing is adjustable, offering high flexibility and a simple process. Our existing encapsulation and electroplating processes can complete the production of the inductor layer, eliminating the need to purchase inductors externally. The package size is small, the cost is low, and the controllability is high. The electroplated inductor layer 2, viewed from the top view perpendicular to the surface of the flip chip 4 on the embedded capacitor substrate 5, is a square spiral shape (as shown in the attached image). Figure 3 It saves packaging space and has low impedance.

[0031] Please see Figure 1 In S5, the layers of inductor layer 2 are electrically connected to each other through electroplated metal pillars. The metal pillars can be electroplated together with inductor layer 2 on the same horizontal plane. The material of the metal pillars is the same as that of inductor layer 2. The other end of the metal pillars is connected to the line 3 to realize the electrical connection between inductor layer 2 and line 3.

[0032] Please see Figure 1 Between S6 and the electroplated inductor layer 2, a molding compound is used for final encapsulation to form package 1. Depending on the volume of the embedded capacitor substrate 5 or the number of mounted chips 4, the whole is cut into individual finished products.

[0033] All electroplating processes in this application involve first forming an electroplating protection layer on the surface using photolithography techniques such as exposure and development, and then forming a metal seed layer in the area to be electroplated by sputtering or copper deposition. The metal seed layer in this application is made of copper. The metal seed layer is used to ensure the bonding force between the metal to be electroplated and the molding compound, and at the same time to provide a surface for conductive ions to adhere to during electroplating, thus ensuring the electroplating effect.

[0034] All encapsulation processes in this application involve injection molding with molding compound to form the encapsulation. The encapsulating compound used in this application is epoxy resin encapsulating compound, which is low in cost and has good curing performance.

[0035] This application uses a buried capacitor substrate 5 connected to an electroplated inductor layer 2, with the chip 4 inside the package 1, i.e., below the inductor layer 2. The circuit 3 is located around the chip 4, making reasonable use of space and reducing the package size. It adopts a flip-chip process, resulting in low parasitic inductance. There are no externally purchased discrete inductor and capacitor components, and the package size is small, making it suitable for consumer terminals. The number of electroplated inductor layers and the interlayer spacing are adjustable, and the frequency adaptation range is wide, from low frequency to high frequency. The process is simple and the cost is low.

[0036] Example 2 The process steps are the same, the only difference being that the electroplated inductor layer 2, viewed from the top of the flip chip 4 perpendicular to the buried capacitor substrate 5, has a comb-like shape (as shown in the attached image). Figure 4 ).

[0037] It is understood that this invention application has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention application. Furthermore, under the teachings of this invention application, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention application. Therefore, this invention application is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this invention application are within the protection scope of this invention application.

Claims

1. A stacked structure for an RF chip module, comprising a package, a chip, and a buried capacitor substrate, wherein the package encapsulates the chip, which is flip-chip mounted on a chip carrier region of the buried capacitor substrate, characterized in that, The package body also encapsulates: An inductor layer is formed in the package and located directly above the chip by electroplating. Coil grooves are etched in the package and metal is electroplated in the coil grooves. The inductor layer is formed by layer-by-layer encapsulation, etching and electroplating. The layers of the inductor layer are electrically connected by electroplated metal pillars. The metal pillars are electroplated together with the inductor layers on the same horizontal plane. The other end of the metal pillar is connected to the circuit to realize the electrical connection between the inductor layer and the circuit. The circuit is formed by electroplating to achieve electrical connection between the inductor layer and the buried capacitor substrate, and the circuit is located around the chip; The capacitor is embedded inside the embedded capacitor substrate, and circuitry is plated inside the embedded capacitor substrate to achieve electrical connection between the inductor and the chip and the capacitor.

2. The stacked structure of the radio frequency chip module according to claim 1, characterized in that, The upper surface of the embedded capacitor substrate is provided with a line carrying area, which is located around the chip carrying area to realize electrical connection with the line.

3. The stacked structure of the radio frequency chip module according to claim 2, characterized in that, The lower surface of the embedded capacitor substrate is provided with exposed external leads to enable circuit lead-out of the package.

4. The stacked structure of the radio frequency chip module according to claim 3, characterized in that, The flip-chip mounting method involves connecting the chip pins to the chip carrier area using solder paste.

5. The stacked structure of the radio frequency chip module according to claim 4, characterized in that, The package is formed by multiple encapsulations through injection molding.

6. The stacked structure of the radio frequency chip module according to claim 1, characterized in that, The inductor layer is a square spiral shape in a top view perpendicular to the flip chip surface of the embedded capacitor substrate.

7. The stacked structure of the radio frequency chip module according to claim 1, characterized in that, The inductor layer has a comb-like shape in its top view perpendicular to the flip chip surface of the embedded capacitor substrate.

8. A packaging method for an RF chip module, characterized in that, Includes the following steps: Flip Chip Mounting Steps: A buried capacitor substrate is provided, with capacitors pre-embedded inside the buried capacitor substrate and circuits plated inside the buried capacitor substrate. Chip carrier area and circuit carrier area are formed on the buried capacitor substrate. Chips are flip-mounted in the chip carrier area on the buried capacitor substrate, and the circuit realizes the electrical connection between the chip and the capacitor. After flip-mount mounting, the first encapsulation is performed. Drill holes in the encapsulated material to expose the circuit-carrying area of ​​the embedded capacitor substrate, and electroplate the vias to form circuits. Electroplating inductor steps: Etching coil grooves inside the package and electroplating metal inside the coil grooves, forming an inductor layer through layer-by-layer encapsulation, etching and electroplating; An inductor layer is electroplated on the back of the chip to replace the inductor component. Electroplated metal pillars realize the electrical connection between the inductor layer and the circuit. The layers of the inductor layer are electrically connected through metal pillars. The metal pillars are formed together with the inductor layer on the same horizontal plane to realize the electrical connection between the inductor layer and the circuit. This circuit electrically connects the circuit carrying area of ​​the buried capacitor substrate and the inductor layer. Packaging steps: Re-encapsulate the chip, circuit, and inductor layer on the buried capacitor substrate into the package body, while the external pins of the buried capacitor substrate are exposed.

9. The packaging method for an RF chip module according to claim 8, characterized in that, In the flip-chip mounting step, solder paste is applied to the chip carrier area of ​​the buried capacitor substrate, the chip is mounted with its front side facing the buried capacitor substrate, and the chip pins are soldered to the chip carrier area.

10. The packaging method for the radio frequency chip module according to claim 9, characterized in that, The inductor layer is a square spiral shape in a top view perpendicular to the flip chip surface of the embedded capacitor substrate.

11. The packaging method for the radio frequency chip module according to claim 10, characterized in that, The inductor layer has a comb-like shape in its top view perpendicular to the flip chip surface of the embedded capacitor substrate.

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