A vertical structure semiconductor device with nanoscale line width and a method for manufacturing the same

Abstract

The application provides a vertical structure semiconductor device with nanometer line width and a preparation method thereof. The method provided by the application can realize the vertical structure semiconductor device with nanometer line width through a traditional thin film preparation process, can avoid the use of high-end photoetching machines, and provides a new idea for preparing the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication, and more specifically to a vertically structured semiconductor device with nanometer-scale linewidth and its fabrication method. Background Technology

[0002] Information technology is a core technology of the national economy, serving all sectors of the economy. Microelectronics technology is key to information technology, and integrated circuits are the most crucial of these. The development of Si integrated circuit technology has resulted in trillions of dollars of equipment and technology investment worldwide, creating a very strong industrial capability for Si-based processes. Simultaneously, long-term research investment has led to a very deep and thorough understanding of Si and its processes. Therefore, Si technology is the mainstream technology in the integrated circuit industry, and Si integrated circuit products are the mainstream products, accounting for over 90% of the integrated circuit industry.

[0003] In the field of integrated circuits, Fin-FET technology is a commonly used process for fabricating nanoscale patterns. When fabricated using EUV lithography, the size depends not only on the resolution of the lithography equipment but also on various influencing factors such as the type of photoresist, baking temperature, exposure dosage, development temperature, and time. It is costly, requires large-scale equipment, and is not easy to manufacture. Now that fabrication processes have extended below 7nm, the novel GAA-FET structure is beginning to dominate.

[0004] If technological advancements are achieved solely through equipment upgrades, resulting in a generation of equipment becoming obsolete every 18 months, this leads to a massive waste of resources and energy, causing increased production costs. Therefore, this situation severely restricts the development of the semiconductor industry. Currently, all devices are planar in structure; to sustain the continuous development of the semiconductor industry, new fabrication methods need to be developed. Summary of the Invention

[0005] Therefore, the purpose of this invention is to overcome the deficiencies in the prior art and provide a vertically structured semiconductor device with nanometer-scale linewidth and its fabrication method for nanogates. Specifically, addressing the shortcomings of the prior art, this invention proposes a method for fabricating nanogates by combining material oxidation and thin film deposition techniques, thereby improving the device fabrication process and reducing the device fabrication cost.

[0006] Before describing the content of this invention, the following terms are defined as follows:

[0007] The term "RIE" refers to reactive ion etching.

[0008] The term "ALD deposition" refers to the atomic layer deposition method.

[0009] The term "PECVD" refers to plasma-enhanced chemical vapor deposition.

[0010] The term "ICP-CVD" refers to inductively coupled plasma chemical vapor deposition.

[0011] The term "DUV lithography" refers to deep ultraviolet lithography.

[0012] The term "EUV lithography" refers to extreme ultraviolet lithography.

[0013] The term "ICP-RIE etching" refers to the inductively coupled plasma etching method.

[0014] The term "ALE etching" refers to the atomic layer etching method.

[0015] To achieve the above objectives, a first aspect of the present invention provides a vertically structured semiconductor device with nanometer-scale linewidth, characterized in that the vertically structured semiconductor device comprises, from bottom to top, the following components arranged sequentially:

[0016] Substrate;

[0017] A functional layer with a patterned structure located on a substrate, wherein the patterned structure is a separate regular pattern array, and the separate regular pattern array is preferably selected from one or more of the following: circular array, rectangular array, polygonal array; most preferably a circular array.

[0018] The source electrode is located on the substrate and is in contact with the functional layer;

[0019] A first dielectric isolation layer located on the source electrode and in contact with the functional layer;

[0020] A gate electrode located on the first dielectric isolation layer and in contact with the functional layer;

[0021] A second dielectric isolation layer located on the gate electrode and in contact with the functional layer;

[0022] The drain electrode is located on the second dielectric isolation layer and in contact with the functional layer; and

[0023] A third dielectric isolation layer located on the drain electrode and in contact with the functional layer;

[0024] Preferably, the following structures are stacked sequentially one or more times: source electrode, nth dielectric isolation layer, gate electrode, n+1th dielectric isolation layer, and drain electrode, where n is an integer ≥ 4.

[0025] According to the semiconductor device of the first aspect of the present invention, the functional regions corresponding to the third dielectric isolation layer have isolation properties, wherein the isolation properties are preferably electrical isolation or optical isolation;

[0026] The substrate material is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, germanium, epitaxial wafer with a multilayer structure, preferably silicon, gallium arsenide, silicon carbide, gallium nitride or gallium oxide, more preferably silicon, gallium arsenide or silicon carbide, more preferably silicon or silicon carbide, and most preferably silicon;

[0027] The source electrode, gate electrode, and drain electrode are made of one or more of the following materials: gold, silver, nickel, titanium, aluminum, copper, germanium, zinc, chromium, tin, preferably gold, silver, nickel, titanium, aluminum, copper, or germanium, more preferably gold, silver, nickel, titanium, aluminum, or copper, and even more preferably aluminum or copper; and / or

[0028] The dielectric isolation layer material is selected from one or more of the following: silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, and polyimide; preferably silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, or gallium oxide, more preferably silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, or aluminum nitride, and even more preferably silicon dioxide, silicon nitride, aluminum oxide, or titanium oxide;

[0029] Preferably, the first dielectric isolation layer, the second dielectric isolation layer, the third dielectric isolation layer, the nth dielectric isolation layer, and the (n+1)th dielectric isolation layer are made of the same material.

[0030] According to the semiconductor device of the first aspect of the present invention,

[0031] The contact method between the source electrode located on the substrate and the functional layer is either point contact or surround contact.

[0032] The gate electrode located on the first dielectric isolation layer contacts the functional layer in a circumferential contact manner;

[0033] The contact method between the drain electrode located on the second dielectric isolation layer and the functional layer is point contact or circumferential contact.

[0034] The first dielectric isolation layer located on the source electrode and the functional layer are in a circumferential contact manner;

[0035] The second dielectric isolation layer located on the gate electrode contacts the functional layer in a circumferential contact manner; and / or

[0036] The third dielectric isolation layer located on the drain electrode contacts the functional layer in a circumferential contact manner.

[0037] According to the semiconductor device of the first aspect of the present invention,

[0038] The source electrode, located on the substrate and in contact with the functional layer, has a patterned structure;

[0039] The gate electrode, located on the first dielectric isolation layer and in contact with the functional layer, has a patterned structure;

[0040] The drain electrode, located on the second dielectric isolation layer and in contact with the functional layer, has a patterned structure;

[0041] The first dielectric isolation layer, located on the source electrode and in contact with the functional layer, has a patterned structure;

[0042] The second dielectric isolation layer, located on the gate electrode and in contact with the functional layer, has a patterned structure; and / or

[0043] The third dielectric isolation layer, located on the drain electrode and in contact with the functional layer, has a patterned structure.

[0044] A second aspect of the present invention provides a method for fabricating a vertically structured semiconductor device with nanometer-scale linewidth as described in the first aspect, the method comprising the following steps:

[0045] (1) Prepare the substrate;

[0046] (2) Prepare a functional layer with a patterned structure on a substrate, wherein the patterned structure is a discrete regular patterned array;

[0047] (3) Fabricate a source electrode located on the substrate and in contact with the functional layer;

[0048] (4) Prepare a first dielectric isolation layer located on the source electrode and in contact with the functional layer;

[0049] (5) Fabricate a gate electrode located on the first dielectric isolation layer and in contact with the functional layer;

[0050] (6) Prepare a second dielectric isolation layer located on the gate electrode and in contact with the functional layer;

[0051] (7) Prepare a drain electrode located on the second dielectric isolation layer and in contact with the functional layer;

[0052] (8) Prepare a third dielectric isolation layer located on the drain electrode and in contact with the functional layer;

[0053] (9) Repeat steps (3) to (8) above sequentially, stacking the following structure once or multiple times: source electrode, nth dielectric isolation layer, gate electrode, n+1th dielectric isolation layer, drain electrode, where n is an integer ≥4;

[0054] Preferably, the method for preparing the isolation layer includes, but is not limited to, ion implantation, oxidation, and diffusion;

[0055] Preferably, the feature size of the fabricated device is consistent with the size of the regular pattern array separated in step (2); and / or

[0056] Preferably, the feature size of the fabricated device is selected from one or more of the following: 28nm, 14nm, 7nm, 5nm, 3nm.

[0057] According to the preparation method of the second aspect of the present invention,

[0058] In step (2), the method for fabricating the patterned functional layer on the substrate is selected from one or more of the following: photolithography, electron beam lithography, laser direct writing, wherein the photolithography is preferably selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography; and / or

[0059] Step (2) also includes the following steps:

[0060] When the subsequent device design size is consistent with the strip structure size, no further processing is performed; when the subsequent device design size is smaller than the strip structure size, the functional layer with patterned structure located on the substrate is transferred to the substrate of step (1), and when the structure size is reduced to the design size, the structure size is reduced by slow etching; and / or the patterned structure is oxidized, and then the oxide layer is removed, leaving the strip structure; wherein: the method of transferring the functional layer is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, wet etching, ALE etching; the method of slow etching is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, ALE etching; the method of oxidizing the patterned structure is preferably: thermal oxidation or wet oxidation; the method of removing the oxide layer is preferably: wet etching or dry etching.

[0061] According to the preparation method of the second aspect of the present invention,

[0062] When the substrate is a wafer and an isolation layer needs to be prepared first, step (2) may also include the following steps: prepare an isolation layer once or multiple times on the entire wafer to form an isolation layer;

[0063] When the substrate is a wafer and the preparation of an isolation layer is not required first, the following steps are included after step (2): spin-coating photoresist onto the substrate, then removing part of the photoresist from top to bottom until the wafer surface is exposed, preparing an isolation layer once or multiple times for a specific area to form an isolation layer, then removing the photoresist and cleaning thoroughly; wherein:

[0064] The method for removing a portion of the photoresist to expose the wafer surface is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, wet etching, and ALE etching; the method for preparing the isolation layer is preferably ion implantation; and / or the method for removing the photoresist is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, solution cleaning, and ALE etching;

[0065] Furthermore, when the wafer is a multilayer epitaxial layer, an isolation layer is epitaxially deposited between its multiple functional devices, and the isolation layer preparation step is not included after step (2).

[0066] According to the preparation method of the second aspect of the present invention,

[0067] In steps (3), (5), (7) and / or (9), the following steps are also included: depositing metal materials for the source electrode, gate electrode, and / or drain electrode; spin-coating photoresist to cover the structure surface; etching to remove the photoresist and etching to the structure surface; etching a portion of the metal material; removing the photoresist and cleaning; defining the pattern structure using photolithography; etching a portion of the metal material to the upper surface of the lower contact layer; and using the remaining metal material as the source electrode, gate electrode, and / or drain electrode; wherein when etching a portion of the metal material for the first time, a specific retention area can be set to connect to subsequent operations; and / or

[0068] The method for depositing metallic materials is thin film deposition, which is preferably selected from one or more of the following: magnetron sputtering, electron beam evaporation, atomic layer deposition, and chemical vapor deposition.

[0069] According to the preparation method of the second aspect of the present invention,

[0070] In steps (4), (6), (8) and / or (9), the following steps are also included: preferably using thin film deposition to deposit each dielectric isolation layer material, spin-coating photoresist to cover the structure surface, then etching to remove the photoresist and etching to the structure surface, etching part of each dielectric isolation layer material to the upper surface of the lower contact layer, removing the photoresist and cleaning it, and using the remaining dielectric isolation layer material as the dielectric isolation layer;

[0071] Preferably, the thin film deposition method is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating, and electron beam evaporation.

[0072] According to the preparation method of the second aspect of the present invention,

[0073] The method for etching the metallic material is selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, ALE etching; and / or

[0074] The method for etching the dielectric isolation layer material of each part is selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, and ALE etching;

[0075] Preferably, the thickness of each layer of metal material and dielectric material is not less than 5nm, more preferably not less than 4nm, further preferably not less than 3nm, even more preferably not less than 2nm, and most preferably not less than 1nm.

[0076] According to a specific embodiment of the present invention, the present invention provides a method for fabricating a vertically structured semiconductor device with nanometer-scale linewidth, the method comprising the following steps:

[0077] (1) Provide the required wafer substrate, prepare the patterned structure and transfer it onto the wafer substrate;

[0078] (2) Oxidize the pattern structure of step (1), then remove the oxide layer, leaving a separate regular pattern array;

[0079] (3) Spin coat photoresist onto the wafer substrate in step (1), and then remove part of the photoresist from top to bottom until the wafer surface is exposed;

[0080] (4) Prepare an isolation layer in a specific area once or multiple times to form an isolation layer, then remove the photoresist and clean it.

[0081] (5) Deposit the first metal material, spin-coat photoresist to cover the structure surface, then remove the photoresist and etch to the structure surface;

[0082] (6) Etch part of the first metal material, remove the photoresist, and clean it; then etch part of the metal material again, and use the remaining first metal material as the source electrode;

[0083] (7) Deposit the first dielectric isolation layer material, spin-coat photoresist to cover the structure surface, then remove the photoresist and etch to the structure surface;

[0084] (8) Etch part of the first dielectric isolation layer material, remove the photoresist, and clean it, and use the remaining first dielectric isolation layer material as the first dielectric isolation layer;

[0085] (9) Deposit a second metallic material to fabricate the gate electrode;

[0086] (10) Deposit the second dielectric isolation layer material to fabricate the second dielectric isolation layer;

[0087] (11) Deposit a third metal material to fabricate a drain electrode;

[0088] (12) Repeat steps (5) to (11) above sequentially, stacking the following structure once or multiple times: source electrode, nth dielectric isolation layer, gate electrode, n+1th dielectric isolation layer, drain electrode, where n is an integer ≥4;

[0089] Preferably, the feature size of the fabricated device is consistent with the size of the regular pattern array separated in step (2); and / or

[0090] Preferably, the feature size of the fabricated device is selected from one or more of the following: 28nm, 14nm, 7nm, 5nm, 3nm.

[0091] According to the method for fabricating a vertically structured semiconductor device with nanometer-scale linewidth of the present invention, in step (2), the method for fabricating a functional layer with a patterned structure on the substrate is selected from one or more of the following: photolithography, electron beam lithography, laser direct writing, wherein the photolithography is preferably selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography; and / or

[0092] Step (2) also includes the following steps:

[0093] When the subsequent device design size is consistent with the strip structure size, no further processing is performed; when the subsequent device design size is smaller than the strip structure size, the functional layer with patterned structure located on the substrate is transferred to the substrate of step (1), and when the structure size is reduced to the design size, the structure size is reduced by slow etching; and / or the patterned structure is oxidized, and then the oxide layer is removed, leaving the strip structure; wherein: the method of transferring the functional layer is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, wet etching, ALE etching; the method of slow etching is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, ALE etching; the method of oxidizing the patterned structure is preferably: thermal oxidation or wet oxidation; the method of removing the oxide layer is preferably: wet etching or dry etching; the solution used for wet etching is preferably HF solution or NH4F solution; the method used for dry etching is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, ALE etching.

[0094] The side length or diameter of the graphic structure is 30-80nm, preferably 40-80nm, more preferably 40-70nm, further preferably 40-60nm, and most preferably 50nm;

[0095] The period of the separated regular pattern array is 50-300nm, preferably 100-300nm, more preferably 100-250nm, more preferably 100-200nm, and most preferably 150nm;

[0096] Preferably, the etching depth of the separated regular pattern array is 500-800nm, more preferably 500-700nm, even more preferably 550-700nm, even more preferably 600-700nm, and most preferably 650nm.

[0097] Based on the aforementioned methods, the following further methods are included:

[0098] In steps (3), (5) to (12),

[0099] The method for removing photoresist and etching it to the structure surface is selected from one or more of the following: RIE etching, ICP-RIE etching, and Ar ion etching;

[0100] The cleaning solution is selected from one or more of the following: alcohol, deionized water, acetone, isopropanol; and / or

[0101] The solution for removing photoresist is selected from one or more of the following: acetone, photoresist remover;

[0102] Preferably, the thickness of each layer of metal material and dielectric material is not less than 5nm, more preferably not less than 4nm, further preferably not less than 3nm, even more preferably not less than 2nm, and most preferably not less than 1nm.

[0103] According to another specific embodiment of the present invention, the present invention provides a vertical structure semiconductor device with nanometer-scale linewidth, wherein the structure of the semiconductor device, from bottom to top, is as follows:

[0104] Substrate; source electrode; isolation layer material; gate electrode; isolation layer; drain electrode; isolation layer; the source electrode, isolation layer, gate electrode, isolation layer, and drain electrode can be stacked repeatedly upwards.

[0105] Preferably, the substrate is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, germanium; preferably a silicon wafer.

[0106] Preferably, the dielectric material is selected from one or more of the following: silicon nitride, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, and polyimide.

[0107] Preferably, the electrode metal material includes, but is not limited to, gold, silver, nickel, titanium, aluminum, copper, germanium, and zinc.

[0108] According to another specific embodiment of the present invention, the present invention provides a method for fabricating a vertically structured semiconductor device with nanometer-scale linewidth, characterized in that the method includes the following steps:

[0109] (1) Provide the wafer substrate required for the process fabrication;

[0110] (2) Prepare the required pattern array using pattern preparation methods;

[0111] (3) Using a pattern transfer method, the pattern prepared in step (2) is transferred to a wafer substrate;

[0112] (4) Using thermal oxidation to oxidize materials of a specific thickness;

[0113] (5) Use wet etching to remove the oxide layer and leave material of a specific size;

[0114] (6) Spin-coating photoresist;

[0115] (7) Remove part of the photoresist from top to bottom until the wafer surface is exposed;

[0116] (8) An isolation layer is prepared in a specific region by ion implantation;

[0117] (9) Remove the photoresist;

[0118] (10) Deposit a first metallic material of a specific thickness;

[0119] (11) Spin-coating photoresist;

[0120] (12) Remove part of the photoresist from top to bottom until the first metal surface is exposed;

[0121] (13) Using etching methods, part of the first metal material is removed;

[0122] (14) Remove the photoresist;

[0123] (15) Using overlay and etching methods, part of the first metal material is removed;

[0124] (16) Deposit a first medium material of a specific thickness;

[0125] (17) Spin-coating photoresist;

[0126] (18) Remove part of the photoresist from top to bottom until the surface of the first dielectric material is exposed;

[0127] (19) Using an etching method, part of the first dielectric material is removed;

[0128] (20) Remove photoresist;

[0129] (21) Deposit a second metallic material of a specific thickness;

[0130] (22) Spin-coating photoresist;

[0131] (23) Remove part of the photoresist from top to bottom until the surface of the second metal material is exposed;

[0132] (24) Using etching methods, part of the second metal material is removed;

[0133] (25) Remove photoresist;

[0134] (26) Part of the second metal material was removed by overlay and etching methods;

[0135] (27) Deposit a second medium material of a specific thickness;

[0136] (28) Spin-coating photoresist;

[0137] (29) Remove part of the photoresist from top to bottom until the surface of the second dielectric material is exposed;

[0138] (30) Use etching to remove part of the second dielectric material;

[0139] (31) Remove photoresist;

[0140] (32) Deposit a third metallic material of a specific thickness;

[0141] (33) Spin-coating photoresist;

[0142] (34) Remove part of the photoresist from top to bottom until the surface of the third metal material is exposed;

[0143] (35) Using etching methods, some of the third metal material is removed;

[0144] (36) Remove photoresist;

[0145] (37) Combine overlay and etching to remove part of the third metal material;

[0146] (38) Depositing a third medium material of a specific thickness;

[0147] (39) Spin-coating photoresist;

[0148] (40) Remove part of the photoresist from top to bottom until the surface of the third dielectric material is exposed;

[0149] (41) Using etching methods, part of the third medium material is removed;

[0150] (42) Steps (10) to (41) can be repeated as needed.

[0151] According to the method of this embodiment, the wafer material is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, germanium, and wafers with a certain epitaxial structure;

[0152] Silicon wafers are preferred;

[0153] The dielectric material is selected from one or more of the following: silicon nitride, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, and polyimide;

[0154] Preferably, the deposition medium material is uniform.

[0155] According to the method of this embodiment, the deposition method of the dielectric material is a thin film deposition method. Preferably, the thin film deposition method is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating, and electron beam evaporation.

[0156] According to the method of this embodiment, the deposition method of the metal material is a thin film deposition method. Preferably, the thin film deposition method is selected from one or more of the following: reactive ion magnetron sputtering, electron beam evaporation.

[0157] According to the method of this embodiment, the pattern preparation method in step (2) is selected from one or more of the following: photolithography, electron beam exposure, laser direct writing; preferably, the photolithography is selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography.

[0158] According to the method of this embodiment, the pattern transfer method in step (3) includes RIE etching, ICP-RIE etching, Ar ion etching, and wet etching.

[0159] According to the method of this embodiment, the feature size of the device prepared is consistent with the material structure size left in step (5);

[0160] Preferably, its feature size is 28nm, 14nm, 7nm, 5nm, or 3nm.

[0161] According to the method of this implementation scheme, the preparation of the isolation layer in step (8) can be a single isolation layer preparation or multiple isolation layer preparations, and the process can be carried out according to the subsequent requirements.

[0162] According to the method of this embodiment, the metallic material includes, but is not limited to, gold, silver, nickel, titanium, aluminum, copper, germanium, and zinc.

[0163] According to the method of this embodiment, the etching methods for metallic and dielectric materials include, but are not limited to, RIE etching, ICP-RIE etching, and Ar ion etching.

[0164] According to the method of this embodiment, the thickness of each layer of metal material and dielectric material is not less than 1 nm.

[0165] According to the method of this embodiment, the graphic structure prepared in step (2) can be a regular circular array, a rectangular array, or an irregular graphic array.

[0166] According to the method of this implementation scheme, in step (13), a portion of the first metal material is removed, and a specific retention area can be set to facilitate subsequent process connections.

[0167] According to the method of this implementation scheme, the number of repetitions in step (42) should be at least once.

[0168] The device fabricated according to the steps described in this embodiment has the following structure from bottom to top: source electrode, dielectric isolation layer, gate electrode, dielectric isolation layer, drain electrode, and dielectric isolation layer.

[0169] In summary, this invention provides a method for fabricating vertically structured semiconductor devices with nanometer-scale linewidths. This method can achieve nanometer-scale linewidth vertically structured semiconductor devices using traditional thin-film fabrication processes, not only avoiding the use of high-end lithography equipment but also providing a novel approach to device fabrication.

[0170] When planar device structures are transformed into vertical device structures, existing equipment and traditional processes can be used to fabricate devices with smaller linewidths. This not only avoids the pressure of equipment upgrades but also allows for the introduction of more device structure design ideas. Combined with current 3D integration processes, it can also meet the fabrication needs for a wide range of functions and structures.

[0171] The nanometer-scale linewidth vertical structure semiconductor device of the present invention can have, but is not limited to, the following beneficial effects:

[0172] 1. The method provided by this invention can realize semiconductor devices with vertical structures and nanometer-scale linewidths through traditional thin film preparation processes. This not only avoids the use of high-end lithography machines, but also provides a new approach to device preparation.

[0173] 2. This invention addresses the preparation and acquisition of nanogates by proposing a method that combines material oxidation and thin film deposition techniques to prepare nanogates, thereby improving the device fabrication process and reducing the device fabrication cost. Attached Figure Description

[0174] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings, wherein:

[0175] Figure 1 A flowchart of Embodiment 1 of the present invention is shown.

[0176] Figure 2 A flowchart of Embodiment 2 of the present invention is shown.

[0177] Figure 3 A schematic diagram of the wafer substrate described in Embodiment 2 of the present invention is shown.

[0178] Figure 4 A schematic diagram of the fabrication of the desired structure on a wafer is shown in Embodiment 2 of the present invention.

[0179] Figure 5 This diagram illustrates a partial material after thermal oxidation, as shown in Embodiment 2 of the present invention.

[0180] Figure 6 A schematic diagram of the oxide layer after removal is shown in Embodiment 2 of the present invention.

[0181] Figure 7 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0182] Figure 8 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0183] Figure 9 A schematic diagram of ion implantation to prepare an isolation layer is shown in Embodiment 2 of the present invention.

[0184] Figure 10 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0185] Figure 11 A schematic diagram of the deposition of a first metallic material is shown in Embodiment 2 of the present invention.

[0186] Figure 12 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0187] Figure 13 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0188] Figure 14 A schematic diagram of removing part of the first metal material is shown in Embodiment 2 of the present invention.

[0189] Figure 15 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0190] Figure 16 A top view of the removal of photoresist in Embodiment 2 of the present invention is shown.

[0191] Figure 17 A top view of Embodiment 2 of the present invention showing the removal of a portion of the first metal material is shown.

[0192] Figure 18 A schematic diagram of the deposition of the first dielectric isolation layer in Embodiment 2 of the present invention is shown.

[0193] Figure 19This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0194] Figure 20 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0195] Figure 21 A schematic diagram of removing part of the first dielectric isolation layer is shown in Embodiment 2 of the present invention.

[0196] Figure 22 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0197] Figure 23 A schematic diagram of the deposition of a second metallic material is shown in Embodiment 2 of the present invention.

[0198] Figure 24 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0199] Figure 25 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0200] Figure 26 A schematic diagram of removing part of the second metal material is shown in Embodiment 2 of the present invention.

[0201] Figure 27 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0202] Figure 28 A top view of the removal of photoresist in Embodiment 2 of the present invention is shown.

[0203] Figure 29 A top view of Embodiment 2 of the present invention showing the removal of a portion of the second metal material is shown.

[0204] Figure 30 A schematic diagram of the deposition of the second dielectric isolation layer in Embodiment 2 of the present invention is shown.

[0205] Figure 31 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0206] Figure 32 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0207] Figure 33 A schematic diagram of removing part of the second dielectric isolation layer is shown in Embodiment 2 of the present invention.

[0208] Figure 34 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0209] Figure 35A schematic diagram of the deposition of a third metallic material is shown in Embodiment 2 of the present invention.

[0210] Figure 36 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0211] Figure 37 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0212] Figure 38 A schematic diagram of removing part of the third metal material is shown in Embodiment 2 of the present invention.

[0213] Figure 39 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0214] Figure 40 A top view of the removal of photoresist in Embodiment 2 of the present invention is shown.

[0215] Figure 41 A top view of Embodiment 2 of the present invention showing the removal of a portion of the third metal material is shown.

[0216] Figure 42 A schematic diagram of the deposition of the third dielectric isolation layer in Embodiment 2 of the present invention is shown.

[0217] Figure 43 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0218] Figure 44 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0219] Figure 45 A schematic diagram of removing part of the third medium isolation layer is shown in Embodiment 2 of the present invention.

[0220] Figure 46 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0221] Figure 47 This diagram illustrates the preparation of a second device by repeating the above steps in Embodiment 2 of the present invention.

[0222] 1. Wafer substrate; 2. Patterned structure; 2'. Oxide layer; 4. Isolation layer; 5A, 5B, 5C. First metal material; 3, 6, 8, 10, 12, 14, 16. Photoresist; 7A, 7B, 7C. First dielectric isolation layer; 9A, 9B, 9C. Second metal material; 11A, 11B, 11C. Second dielectric isolation layer; 13A, 13B, 13C. Third metal material; 15A, 15B, 15C. Third dielectric isolation layer; 17. Fourth metal material; 18. Fourth dielectric isolation layer; 19. Fifth metal material; 20. Fifth dielectric isolation layer; 21. Sixth metal material. Detailed Implementation

[0223] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. However, it should be understood that these embodiments are merely for more detailed and specific explanation and should not be construed as limiting the present invention in any way.

[0224] The objects and functions of the present invention, as well as the methods for achieving these objects and functions, will be clarified by referring to exemplary embodiments. However, the present invention is not limited to the exemplary embodiments disclosed below: it can be implemented in various forms. The purpose of this specification is merely to help those skilled in the art to comprehensively understand the specific details of the invention.

[0225] Example 1

[0226] This embodiment illustrates a typical fabrication method for the nanoscale linewidth vertical structure semiconductor device described in this invention.

[0227] The specific process is as follows: Figure 1 As shown, it includes the following steps:

[0228] S100: Provide the required wafer substrate, fabricate the patterned structure and transfer it onto the wafer substrate;

[0229] S200: The graphic structure of oxidation step (1) is then removed, leaving a circular array;

[0230] S300: Spin-coat photoresist onto the wafer substrate in step (1), and then remove part of the photoresist from top to bottom until the wafer surface is exposed;

[0231] S400: An isolation layer is prepared for a specific area to form an isolation layer, and then the photoresist is removed and the area is cleaned.

[0232] S500: Deposit the first metal material, spin-coat photoresist, cover the structure surface, then remove the photoresist and etch to the structure surface;

[0233] S600: Etch part of the first metal material, remove the photoresist, and clean it; then etch part of the metal material again, and use the remaining first metal material as the source electrode;

[0234] S700: Deposit the first dielectric isolation layer material, spin-coat photoresist to cover the structure surface, then remove the photoresist and etch to the structure surface;

[0235] S800: Etch part of the first dielectric isolation layer material, remove the photoresist, and clean it thoroughly. Use the remaining first dielectric isolation layer material as the first dielectric isolation layer.

[0236] S900: Deposit a second metallic material to fabricate the gate electrode;

[0237] S1000: Deposit the second dielectric isolation layer material to fabricate the second dielectric isolation layer;

[0238] S1100: Deposit a third metal material to fabricate the drain electrode;

[0239] S1200: Repeat steps (5) to (11) above to continue fabricating a new device. The source electrode, fourth dielectric isolation layer, gate electrode, fifth dielectric isolation layer, and drain electrode can be stacked repeatedly.

[0240] Example 2

[0241] This embodiment combines Figure 2-47 This describes an optimized fabrication method for the nanoscale linewidth vertical structure semiconductor device described in this invention.

[0242] The specific process is as follows: Figure 2 As shown, it includes the following steps:

[0243] S100: Provides the wafer substrate 1 required for process fabrication;

[0244] S200: Fabricate patterned structures and transfer them to a wafer substrate;

[0245] S300: Oxidation pattern structure 2 using thermal oxidation method;

[0246] S400: Remove oxide layer 2';

[0247] S500: Spin-coated photoresist 3;

[0248] S600: Removes the photoresist 3 from the surface down to the structure surface;

[0249] S700: The isolation layer 4 was prepared by ion implantation;

[0250] S800: Remove photoresist 3;

[0251] S900: Deposition source electrodes 5A, 5B, 5C;

[0252] S1000: Spin-coated photoresist 6;

[0253] S1100: Removes the photoresist 6 from the surface down to the structure surface;

[0254] S1200: Remove part of the source electrodes 5B and 5C;

[0255] S1300: Remove photoresist 6;

[0256] S1400: Remove part of the source electrode 5A;

[0257] S1500: Deposition of first medium materials 7A, 7B, and 7C;

[0258] S1600: Spin-coated photoresist 8;

[0259] S1700: Removes the photoresist 8 from the surface down to the structure surface;

[0260] S1800: Remove part of the first dielectric material 9B and 9C;

[0261] S1900: Remove photoresist 8;

[0262] S2000: Deposited gate electrodes 9A, 9B, 9C;

[0263] S2100: Spin-coated photoresist 10;

[0264] S2200: Remove the photoresist 10 from the surface until the structure surface is reached;

[0265] S2300: Remove part of the gate electrodes 9B and 9C;

[0266] S2400: Remove photoresist 10;

[0267] S2500: Remove part of the gate electrode 9A;

[0268] S2600: Deposition of second medium materials 11A, 11B, and 11C;

[0269] S2700: Spin-coated photoresist 12;

[0270] S2800: Removes the photoresist 12 from the surface down to the structure surface;

[0271] S2900: Remove part of the second dielectric material 11B and 11C;

[0272] S3000: Remove photoresist 12;

[0273] S3100: Deposited drain electrodes 13A, 13B, 13C;

[0274] S3200: Spin-coated photoresist 14;

[0275] S3300: Remove some of the drain electrodes 13B and 13C;

[0276] S3400: Remove photoresist 14;

[0277] S3500: Remove part of the drain electrode 13A;

[0278] S3600: Deposition of third media materials 15A, 15B, and 15C;

[0279] S3700: Spin-coated photoresist 16;

[0280] S3800: Removes the photoresist 16 from the surface down to the structure surface;

[0281] S3900: Remove some of the third medium material 15B and 15C;

[0282] S4000: Remove photoresist 16;

[0283] S4100: Repeat S900~S3500 to prepare a new device.

[0284] In this embodiment, a silicon substrate is used as the wafer required for the process, such as Figure 3 As shown;

[0285] Next, using ultraviolet lithography, and in conjunction with a pre-designed photomask with a specific pattern, the pattern is fabricated on the photoresist. Then, using RIE etching with O2 and CF4 as etching gases at flow rates of 10 sccm and 30 sccm respectively, and an etching power of 150 W, the pattern is transferred onto a silicon wafer. The pattern used in this embodiment is as follows... Figure 3 As shown, it is a regular circular array with a diameter of 50nm, a period of 150nm, and an etching depth of 650nm; the structure after etching is as follows. Figure 4 As shown;

[0286] Next, a thermal oxidation method is used to oxidize part of the material. The silicon wafer is placed in a reaction tube made of quartz glass, and the reaction tube is heated to 1200°C using a resistance wire furnace. Water vapor passes through the reaction tube, oxidizing the 22.5nm thick silicon material. Figure 5 As shown;

[0287] The silicon wafer is then immersed in an HF solution to remove the oxide layer, leaving a circular array structure with a diameter of 5 nm, such as... Figure 6 As shown;

[0288] Then, photoresist is spin-coated onto the wafer surface to cover the structural surface, such as... Figure 7 As shown;

[0289] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 8 As shown;

[0290] Then, an isolation layer is created using ion implantation. Accelerated oxygen is used to form an isolation layer in a selected region, positioned from top to bottom at 320 nm to 330 nm. Figure 9 As shown.

[0291] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 10 As shown;

[0292] Next, a 100nm thick layer of metallic aluminum was deposited using a sputtering method, such as... Figure 11 As shown;

[0293] Then, photoresist is spin-coated to cover the surface of the structure, such as... Figure 12 As shown;

[0294] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 13 As shown;

[0295] Next, using the RIE etching method, with Ar as the etching gas at a flow rate of 100 sccm and an etching power of 200 W, part of the aluminum material was etched away, and the remaining aluminum was used as the source electrode. Figure 14 As shown;

[0296] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 15 As shown;

[0297] Next, using overlay and etching methods, some of the metallic aluminum is removed to prepare a source electrode with a specific shape, such as... Figure 17 As shown;

[0298] Next, using the ALD deposition method, a 10nm first dielectric isolation layer material, silicon dioxide, was deposited at a deposition temperature of 200℃. The precursor materials used were aminosilane and water vapor-coated surface pattern structures, such as... Figure 18 As shown;

[0299] Then, photoresist is spin-coated onto the wafer surface to cover the structural surface, such as... Figure 19 As shown;

[0300] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 20 As shown;

[0301] Next, using RIE etching with O2 and CF4 as etching gases at flow rates of 10 sccm and 30 sccm respectively, and an etching power of 150 W, part of the first dielectric isolation layer material was etched away. Figure 21 As shown;

[0302] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 22 As shown;

[0303] Next, a 100nm thick layer of metallic copper was deposited using a sputtering method, such as... Figure 23 As shown;

[0304] Then, photoresist is spin-coated onto the wafer surface to cover the structural surface, such as... Figure 24 As shown;

[0305] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 25 As shown;

[0306] Next, using the RIE etching method, with Ar as the etching gas at a flow rate of 100 sccm and an etching power of 200 W, part of the metallic copper material was etched away. Figure 26 As shown;

[0307] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 27 As shown;

[0308] Next, using overlay and etching methods, some of the metallic copper is removed to prepare a gate electrode with a specific shape, such as... Figure 29 As shown;

[0309] Next, a 10 nm second dielectric isolation layer of silicon dioxide was deposited using the ALD deposition method at a deposition temperature of 200 °C. The precursor materials used were aminosilane and water vapor-coated surface pattern structures, such as... Figure 30 As shown;

[0310] Then, photoresist is spin-coated onto the wafer surface to cover the structural surface, such as... Figure 31 As shown;

[0311] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 32 As shown;

[0312] Next, using RIE etching with O2 and CF4 as etching gases at flow rates of 10 sccm and 30 sccm respectively, and an etching power of 150 W, part of the second dielectric isolation layer material was etched away. Figure 33 As shown;

[0313] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 34 As shown;

[0314] Next, a 100nm thick layer of metallic aluminum was deposited using a sputtering method, such as... Figure 35 As shown;

[0315] Then, photoresist is spin-coated onto the wafer surface to cover the structural surface, such as... Figure 36 As shown;

[0316] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 37 As shown;

[0317] Next, using the RIE etching method, with Ar as the etching gas at a flow rate of 100 sccm and an etching power of 200 W, a portion of the metallic aluminum material was etched away, such as... Figure 38 As shown;

[0318] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 39 As shown;

[0319] Next, using overlay and etching methods, some of the metallic aluminum is removed to prepare a drain electrode with a specific shape, such as... Figure 41 As shown;

[0320] Next, a 10nm third dielectric isolation layer material, silicon dioxide, was deposited using the ALD deposition method at a deposition temperature of 200℃. The precursor materials used were aminosilane and water vapor-coated surface pattern structures, such as... Figure 42 As shown;

[0321] Then, photoresist is spin-coated onto the wafer surface to cover the structural surface, such as... Figure 43 As shown;

[0322] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 44 As shown;

[0323] Next, using RIE etching with O2 and CF4 as etching gases at flow rates of 10 sccm and 30 sccm respectively, and an etching power of 150 W, part of the third dielectric isolation layer material was etched away. Figure 45 As shown;

[0324] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 46 As shown;

[0325] Next, repeat the above steps to fabricate a new device with the source electrode, fourth dielectric isolation layer, gate electrode, fifth dielectric isolation layer, and drain electrode, as follows. Figure 47 As shown.

[0326] Although the invention has been described to a certain extent, it is apparent that appropriate variations can be made to the various conditions without departing from the spirit and scope of the invention. It is understood that the invention is not limited to the described embodiments, but falls within the scope of the claims, which include equivalent substitutions for each of the elements.

Claims

1. A vertically structured semiconductor device with nanometer-scale linewidth, characterized in that, The vertically structured semiconductor device comprises, from bottom to top, the following: Substrate; A functional layer with a patterned structure located on a substrate, wherein the patterned structure is a separate regular pattern array, and the separate regular pattern array is a circular array; The source electrode is located on the substrate and is in contact with the functional layer; A first dielectric isolation layer located on the source electrode and in contact with the functional layer; A gate electrode located on the first dielectric isolation layer and in contact with the functional layer; A second dielectric isolation layer located on the gate electrode and in contact with the functional layer; The drain electrode is located on the second dielectric isolation layer and is in contact with the functional layer; and A third dielectric isolation layer located on the drain electrode and in contact with the functional layer; The following structure is stacked sequentially one or more times: source electrode, nth dielectric isolation layer, gate electrode, n+1th dielectric isolation layer, drain electrode, where n is an integer ≥ 4; and: The contact method between the source electrode located on the substrate and the functional layer is either point contact or surround contact. The gate electrode located on the first dielectric isolation layer contacts the functional layer in a circumferential contact manner; The contact method between the drain electrode located on the second dielectric isolation layer and the functional layer is either point contact or circumferential contact. The first dielectric isolation layer located on the source electrode and the functional layer are in a circumferential contact manner; The second dielectric isolation layer located on the gate electrode contacts the functional layer in a circumferential contact manner; and / or The third dielectric isolation layer located on the drain electrode contacts the functional layer in a circumferential contact manner.

2. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 1, characterized in that: The functional layer corresponding to the third dielectric isolation layer has isolation properties; The substrate material is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, and germanium; The source electrode, gate electrode, and drain electrode are made of one or more of the following materials: gold, silver, nickel, titanium, aluminum, copper, germanium, zinc, chromium, tin; and / or The dielectric isolation layer material is selected from one or more of the following: silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, photoresist, and polyimide.

3. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 2, characterized in that, The first dielectric isolation layer, the second dielectric isolation layer, the third dielectric isolation layer, the nth dielectric isolation layer, and the (n+1)th dielectric isolation layer are made of the same material.

4. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 2, characterized in that: The isolation property is: electrical isolation or optical isolation; The substrate material is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, or gallium oxide; The source electrode, gate electrode, and drain electrode are made of one or more of the following materials: gold, silver, nickel, titanium, aluminum, copper, or germanium; and / or The dielectric isolation layer material is selected from one or more of the following: silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, or gallium oxide.

5. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 4, characterized in that: The substrate is made of one or more of the following materials: silicon, gallium arsenide, and silicon carbide; The source electrode, gate electrode, and drain electrode are made of one or more of the following materials: gold, silver, nickel, titanium, aluminum, copper; and / or The dielectric isolation layer material is selected from one or more of the following: silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, or aluminum nitride.

6. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 5, characterized in that: The substrate is made of silicon or silicon carbide. The source electrode, gate electrode, and drain electrode are made of aluminum or copper; and / or The dielectric isolation layer material is selected from one or more of the following: silicon dioxide, silicon nitride, aluminum oxide, or titanium oxide.

7. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 2, characterized in that: The substrate is an epitaxial wafer with a multilayer structure.

8. The vertical structure semiconductor device with nanometer-scale linewidth according to any one of claims 1 to 7, characterized in that: The source electrode, located on the substrate and in contact with the functional layer, has a patterned structure; The gate electrode, located on the first dielectric isolation layer and in contact with the functional layer, has a patterned structure; The drain electrode, located on the second dielectric isolation layer and in contact with the functional layer, has a patterned structure; The first dielectric isolation layer, located on the source electrode and in contact with the functional layer, has a patterned structure; The second dielectric isolation layer, located on the gate electrode and in contact with the functional layer, has a patterned structure; and / or The third dielectric isolation layer, located on the drain electrode and in contact with the functional layer, has a patterned structure.

9. A method for preparing a semiconductor device as described in any one of claims 1 to 8, characterized in that, The method includes the following steps: (1) Preparation of substrate; (2) Prepare a functional layer with a patterned structure on a substrate, wherein the patterned structure is a discrete array of regular patterns; (3) Fabricate a source electrode located on the substrate and in contact with the functional layer; (4) Prepare a first dielectric isolation layer located on the source electrode and in contact with the functional layer; (5) Fabricate a gate electrode located on the first dielectric isolation layer and in contact with the functional layer; (6) Prepare a second dielectric isolation layer located on the gate electrode and in contact with the functional layer; (7) Fabricate a drain electrode located on the second dielectric isolation layer and in contact with the functional layer; (8) Prepare a third dielectric isolation layer located on the drain electrode and in contact with the functional layer; (9) Repeat steps (3) to (8) above in sequence, stacking the following structures once or multiple times: source electrode, nth dielectric isolation layer, gate electrode, n+1th dielectric isolation layer, drain electrode, where n is an integer ≥4.

10. The preparation method according to claim 9, characterized in that: The method for preparing the dielectric isolation layer is selected from one or more of the following: ion implantation, oxidation, diffusion; The feature size of the fabricated device is consistent with the size of the regular pattern array separated in step (2); and / or The feature size of the fabricated device is selected from one or more of the following: 28nm, 14nm, 7nm, 5nm, 3nm.

11. The preparation method according to claim 9, characterized in that: In step (2), the method for preparing the patterned functional layer on the substrate is selected from one or more of the following: photolithography, electron beam lithography, laser direct writing; and / or Step (2) also includes the following steps: When the subsequent device design size is consistent with the strip structure size, no further processing is performed; when the subsequent device design size is smaller than the strip structure size, the functional layer with patterned structure located on the substrate is transferred to the substrate in step (1), and when the structure size is reduced to the design size, the structure size is reduced by slow etching; and / or the patterned structure is oxidized, and then the oxide layer is removed, leaving the strip structure.

12. The preparation method according to claim 11, characterized in that, In step (2): The photolithography is selected from one or more of the following: ultraviolet lithography, immersion lithography; and / or The method for transferring the functional layer is selected from one or more of the following: RIE etching, wet etching, ALE etching; the method for slow etching is selected from one or more of the following: RIE etching, ALE etching; the method for the oxide pattern structure is thermal oxidation; and / or the method for removing the oxide layer is wet etching or dry etching.

13. The preparation method according to claim 12, characterized in that, In step (2): The ultraviolet lithography is DUV lithography and / or EUV lithography; The RIE etching for the functional layer transfer is ICP-RIE etching; and / or The slow-speed RIE etching is ICP-RIE etching.

14. The preparation method according to claim 11, characterized in that, In step (2), the method for creating the oxidized pattern structure is wet oxidation.

15. The preparation method according to any one of claims 9 to 14, characterized in that: When the substrate is a wafer and an isolation layer needs to be prepared first, step (2) further includes the following steps: preparing an isolation layer once or multiple times on the entire wafer to form an isolation layer; When the substrate is a wafer and it is not necessary to prepare an isolation layer first, the following steps are included after step (2): spin-coating photoresist on the substrate, then removing part of the photoresist from top to bottom to expose the wafer surface, preparing an isolation layer once or multiple times for a specific area, forming an isolation layer, and then removing the photoresist and cleaning it.

16. The preparation method according to claim 15, characterized in that, When the substrate is a wafer and it is not necessary to prepare an isolation layer first, wherein: The method for removing a portion of the photoresist to expose the wafer surface is selected from one or more of the following: RIE etching, Ar ion etching, wet etching, ALE etching; the method for preparing the isolation layer is ion implantation; and / or the method for removing the photoresist is selected from one or more of the following: RIE etching, Ar ion etching, solution cleaning, ALE etching; Furthermore, when the wafer is a multilayer epitaxial layer, an isolation layer is epitaxially deposited between its multiple functional devices, and the isolation layer preparation step is not included after step (2).

17. The preparation method according to claim 16, characterized in that, The RIE etching that removes part of the photoresist to expose the wafer surface is ICP-RIE etching; and / or the RIE etching that removes the photoresist is ICP-RIE etching.

18. The preparation method according to any one of claims 9 to 14, characterized in that: In steps (3), (5), (7) and / or (9), the following steps are also included: depositing metal materials for the source electrode, gate electrode and / or drain electrode, spin-coating photoresist to cover the structure surface, then etching to remove the photoresist and etching to the structure surface, etching part of the metal material, removing the photoresist and cleaning it, defining the pattern structure using photolithography, then etching part of the metal material to the upper surface of the lower contact layer, and using the remaining metal material as the source electrode, gate electrode and / or drain electrode; wherein when etching part of the metal material for the first time, a specific retention area is set to connect to subsequent operations; The method for depositing metallic materials is thin film deposition.

19. The preparation method according to claim 18, characterized in that, The thin film deposition method is selected from one or more of the following: magnetron sputtering, electron beam evaporation, atomic layer deposition, and chemical vapor deposition.

20. The preparation method according to any one of claims 9 to 14, characterized in that: In steps (4), (6), (8) and / or (9), the following steps are also included: depositing each dielectric isolation layer material using thin film deposition, spin-coating photoresist to cover the structure surface, then etching to remove the photoresist and etching to the structure surface, etching part of each dielectric isolation layer material to the upper surface of the lower contact layer, removing the photoresist and cleaning it, and using the remaining dielectric isolation layer material as the dielectric isolation layer.

21. The preparation method according to claim 20, characterized in that, The thin film deposition method is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating, and electron beam evaporation.

22. The preparation method according to claim 18, characterized in that: The method for etching the metal material is selected from one or more of the following: RIE etching, Ar ion etching, and ALE etching.

23. The preparation method according to claim 22, characterized in that: The RIE etching of the etched portion of the metal material is ICP-RIE etching.

24. The preparation method according to claim 22, characterized in that: The thickness of each layer of metal material is no less than 1 nm.

25. The preparation method according to claim 24, characterized in that: The thickness of each layer of metal material is no less than 2nm.

26. The preparation method according to claim 25, characterized in that: The thickness of each layer of metal material is no less than 3nm.

27. The preparation method according to claim 26, characterized in that: The thickness of each layer of metal material is no less than 4nm.

28. The preparation method according to claim 27, characterized in that: The thickness of each layer of metal material is no less than 5nm.

29. The preparation method according to claim 20, characterized in that: The method for etching the dielectric isolation layer material of each part is selected from one or more of the following: RIE etching, Ar ion etching, and ALE etching.

30. The preparation method according to claim 29, characterized in that: The RIE etching of each dielectric isolation layer material in the etched portion is ICP-RIE etching.

31. The preparation method according to claim 29, characterized in that, The thickness of each dielectric isolation layer material is no less than 1 nm.

32. The preparation method according to claim 31, characterized in that, The thickness of each dielectric isolation layer material is no less than 2nm.

33. The preparation method according to claim 32, characterized in that, The thickness of each dielectric isolation layer material is no less than 3nm.

34. The preparation method according to claim 33, characterized in that, The thickness of each dielectric isolation layer material is no less than 4nm.

35. The preparation method according to claim 34, characterized in that, The thickness of each dielectric isolation layer material is no less than 5nm.

Images