A vertical structure semiconductor device with nanoscale line width and a method for manufacturing the same

Abstract

This invention provides a vertically structured semiconductor device with nanometer-scale linewidth and its fabrication method. The method provided by this invention can realize a vertically structured semiconductor device with nanometer-scale linewidth using traditional thin-film fabrication processes, not only avoiding the use of high-end lithography machines but also providing a new approach to device fabrication.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication, and more specifically to a vertically structured semiconductor device with nanometer-scale linewidth and its fabrication method. Background Technology

[0002] Information technology is a core technology of the national economy, serving all sectors of the economy. Microelectronics technology is key to information technology, and integrated circuits are the most crucial of these. The development of Si integrated circuit technology has resulted in trillions of dollars of equipment and technology investment worldwide, creating a very strong industrial capability for Si-based processes. Simultaneously, long-term research investment has led to a very deep and thorough understanding of Si and its processes. Therefore, Si technology is the mainstream technology in the integrated circuit industry, and Si integrated circuit products are the mainstream products, accounting for over 90% of the integrated circuit industry.

[0003] In the field of integrated circuits, Fin-FET technology is a commonly used process for fabricating nanopatterns. When fabricated using EUV lithography, the size depends not only on the resolution of the lithography equipment but also on various influencing factors such as the type of photoresist, baking temperature, exposure dosage, development temperature, and time. This process is costly, requires large-scale equipment, and is not easily mass-produced.

[0004] If technological advancements are achieved solely through equipment upgrades, resulting in a generation of equipment becoming obsolete every 18 months, this leads to a massive waste of resources and energy, causing increased production costs. Therefore, this situation severely restricts the development of the semiconductor industry. Currently, all devices are planar in structure; to sustain the continuous development of the semiconductor industry, new fabrication methods need to be developed. Summary of the Invention

[0005] Therefore, the purpose of this invention is to overcome the deficiencies in the prior art and provide a vertically structured semiconductor device with nanometer-scale linewidth and its fabrication method for nanogates. Specifically, addressing the shortcomings of the prior art, this invention proposes a method for fabricating nanogates by combining material oxidation and thin film deposition techniques, thereby improving the device fabrication process and reducing the device fabrication cost.

[0006] Before describing the content of this invention, the following terms are defined as follows:

[0007] The term "RIE" refers to reactive ion etching.

[0008] The term "ALD deposition" refers to atomic layer deposition.

[0009] The term "PECVD" refers to plasma-enhanced chemical vapor deposition.

[0010] The term "ICP-CVD" refers to inductively coupled plasma chemical vapor deposition.

[0011] The term "DUV lithography" refers to deep ultraviolet lithography technology.

[0012] The term "EUV lithography" refers to extreme ultraviolet lithography.

[0013] The term "ICP-RIE etching" refers to the inductively coupled plasma etching method.

[0014] The term "ALE etching" refers to atomic layer etching.

[0015] To achieve the above objectives, a first aspect of the present invention provides a vertically structured semiconductor device with nanometer-scale linewidth, characterized in that the vertically structured semiconductor device with nanometer-scale linewidth comprises, from bottom to top, the following components arranged sequentially:

[0016] Substrate;

[0017] A functional layer with a patterned structure is located on a substrate, wherein the patterned structure consists of multiple independent structures connected to the same supporting backplate; the multiple independent structures and the supporting backplate are fabricated in a single patterned structure; the structure in which the multiple independent structures are connected to the same supporting backplate is preferably a strip structure;

[0018] The source electrode is located on the substrate and is in contact with the functional layer;

[0019] A first dielectric isolation layer located on the source electrode and in contact with the functional layer;

[0020] A gate electrode located on the first dielectric isolation layer and in contact with the functional layer;

[0021] A second dielectric isolation layer located on the gate electrode and in contact with the functional layer;

[0022] The drain electrode is located on the second dielectric isolation layer and in contact with the functional layer; and

[0023] A third dielectric isolation layer located on the drain electrode and in contact with the functional layer;

[0024] Preferably, the following structures are stacked sequentially one or more times: source electrode, nth dielectric isolation layer, gate electrode, n+1th dielectric isolation layer, and drain electrode, where n is an integer ≥ 4.

[0025] According to the semiconductor device of the first aspect of the present invention,

[0026] The functional regions corresponding to the third dielectric isolation layer have isolation properties, preferably electrical or optical isolation; and / or

[0027] The substrate material is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, germanium, epitaxial wafer with a multilayer structure, preferably silicon, gallium arsenide, silicon carbide, gallium nitride or gallium oxide, more preferably silicon, gallium arsenide or silicon carbide, more preferably silicon or silicon carbide, and most preferably silicon;

[0028] The source electrode, gate electrode, and drain electrode are made of one or more of the following materials: gold, silver, nickel, titanium, aluminum, copper, germanium, zinc, chromium, tin, preferably gold, silver, nickel, titanium, aluminum, copper, or germanium, more preferably gold, silver, nickel, titanium, aluminum, or copper, and even more preferably aluminum or copper; and / or

[0029] The dielectric isolation layer material is selected from one or more of the following: silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, and polyimide; preferably silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, or gallium oxide, more preferably silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, or aluminum nitride, and even more preferably silicon dioxide, silicon nitride, aluminum oxide, or titanium oxide;

[0030] Preferably, the first dielectric isolation layer, the second dielectric isolation layer, the third dielectric isolation layer, the nth dielectric isolation layer, and the (n+1)th dielectric isolation layer are made of the same material.

[0031] According to the semiconductor device of the first aspect of the present invention,

[0032] The contact method between the source electrode located on the substrate and the functional layer is either point contact or surround contact.

[0033] The gate electrode located on the first dielectric isolation layer contacts the functional layer in a circumferential contact manner;

[0034] The contact method between the drain electrode located on the second dielectric isolation layer and the functional layer is point contact or circumferential contact.

[0035] The first dielectric isolation layer located on the source electrode and the functional layer are in a circumferential contact manner;

[0036] The second dielectric isolation layer located on the gate electrode contacts the functional layer in a circumferential contact manner; and / or

[0037] The third dielectric isolation layer located on the drain electrode contacts the functional layer in a circumferential contact manner.

[0038] According to the semiconductor device of the first aspect of the present invention,

[0039] The source electrode, located on the substrate and in contact with the functional layer, has a patterned structure;

[0040] The gate electrode, located on the first dielectric isolation layer and in contact with the functional layer, has a patterned structure;

[0041] The drain electrode, located on the second dielectric isolation layer and in contact with the functional layer, has a patterned structure;

[0042] The first dielectric isolation layer, located on the source electrode and in contact with the functional layer, has a patterned structure;

[0043] The second dielectric isolation layer, located on the gate electrode and in contact with the functional layer, has a patterned structure; and / or

[0044] The third dielectric isolation layer, located on the drain electrode and in contact with the functional layer, has a patterned structure.

[0045] A second aspect of the present invention provides a method for fabricating a vertically structured semiconductor device with nanometer-scale linewidth as described in the first aspect, the method comprising the following steps:

[0046] (1) Prepare the substrate;

[0047] (2) Prepare a functional layer and a support backplate with a patterned structure on a substrate, wherein the patterned structure consists of multiple independent structures connected to the same support backplate;

[0048] (3) Fabricate a source electrode located on the substrate and in contact with the functional layer;

[0049] (4) Prepare a first dielectric isolation layer located on the source electrode and in contact with the functional layer;

[0050] (5) Fabricate a gate electrode located on the first dielectric isolation layer and in contact with the functional layer;

[0051] (6) Prepare a second dielectric isolation layer located on the gate electrode and in contact with the functional layer;

[0052] (7) Prepare a drain electrode located on the second dielectric isolation layer and in contact with the functional layer;

[0053] (8) Prepare a third dielectric isolation layer located on the drain electrode and in contact with the functional layer;

[0054] (9) Repeat steps (3) to (8) above sequentially, stacking the following structure once or multiple times: source electrode, nth dielectric isolation layer, gate electrode, n+1th dielectric isolation layer, drain electrode, where n is an integer ≥4;

[0055] Preferably, the method for preparing the isolation layer includes, but is not limited to, ion implantation, oxidation, and diffusion;

[0056] Preferably, the feature size of the fabricated device is consistent with the size of the strip structure; and / or

[0057] Preferably, the feature size of the fabricated device is selected from one or more of the following: 28nm, 14nm, 7nm, 5nm, 3nm.

[0058] According to the preparation method of the second aspect of the present invention,

[0059] In step (2), the method for fabricating the patterned functional layer on the substrate is selected from one or more of the following: photolithography, electron beam lithography, laser direct writing, wherein the photolithography is preferably selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography; and / or

[0060] Step (2) also includes the following steps:

[0061] When the subsequent device design size is consistent with the strip structure size, no further processing is performed; when the subsequent device design size is smaller than the strip structure size, the functional layer with patterned structure located on the substrate is transferred to the substrate of step (1), and when the structure size is reduced to the design size, the structure size is reduced by slow etching; and / or the patterned structure is oxidized, and then the oxide layer is removed, leaving the strip structure; wherein: the method of transferring the functional layer is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, wet etching, ALE etching; the method of slow etching is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, ALE etching; the method of oxidizing the patterned structure is preferably: thermal oxidation or wet oxidation; the method of removing the oxide layer is preferably: wet etching or dry etching.

[0062] According to the preparation method of the second aspect of the present invention,

[0063] When the substrate is a wafer and an isolation layer needs to be prepared first, step (2) may also include the following steps: prepare an isolation layer once or multiple times on the entire wafer to form an isolation layer;

[0064] When the substrate is a wafer and the preparation of an isolation layer is not required beforehand, the following steps are included after step (2): spin-coating photoresist onto the substrate, then removing a portion of the photoresist from top to bottom until the wafer surface is exposed, preparing an isolation layer once or multiple times for a specific area to form an isolation layer, then removing the photoresist and cleaning thoroughly; wherein:

[0065] The method for removing a portion of the photoresist to expose the wafer surface is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, wet etching, and ALE etching; the method for preparing the isolation layer is preferably ion implantation; and / or the method for removing the photoresist is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, solution cleaning, and ALE etching;

[0066] Furthermore, when the wafer is a multilayer epitaxial layer, an isolation layer is epitaxially deposited between its multiple functional devices, and the step of preparing the isolation layer is not included after step (2).

[0067] According to the preparation method of the second aspect of the present invention, in steps (3), (5), (7) and / or (9), the method further includes the following steps:

[0068] (a) Deposit the metallic material of the source electrode, gate electrode and / or drain electrode, spin-coat photoresist to cover the surface of the structure;

[0069] (b) Etching removes the photoresist and etches it to the structure surface;

[0070] (c) Etch a portion of the metal material down to the upper surface of the lower contact layer, remove the photoresist, and clean it thoroughly;

[0071] (d) Define the pattern structure using photolithography, etch a portion of the metal material, and use the remaining metal material as the source electrode, gate electrode, and / or drain electrode; wherein, in step (c), when etching a portion of the first metal material, a reserved area is set to connect to subsequent operations;

[0072] The metallic material is selected from one or more of the following: a first metallic material, a second metallic material, a third metallic material, an nth metallic material, and an (n+1)th metallic material, where n is an integer ≥ 4; and / or

[0073] The method for depositing the metallic material is thin film deposition.

[0074] The thin film deposition method is preferably selected from one or more of the following: magnetron sputtering, electron beam evaporation, atomic layer deposition, and chemical vapor deposition.

[0075] According to the preparation method of the second aspect of the present invention, in steps (4), (6), (8) and / or (9), the method further includes the following steps:

[0076] (e) Deposit the dielectric isolation layer material, spin-coat it with photoresist, and cover the structure surface;

[0077] (f) Etching removes the photoresist and etches it to the structure surface;

[0078] (g) Define the patterned structure using photolithography, etch a portion of the dielectric isolation layer material down to the upper surface of the lower contact layer, remove the photoresist and clean it thoroughly, leaving the remaining dielectric isolation layer material as the dielectric isolation layer; wherein,

[0079] The dielectric isolation layer material is selected from one or more of the following: a first dielectric isolation layer material, a second dielectric isolation layer material, a third dielectric isolation layer material, an nth dielectric isolation layer material, and an (n+1)th dielectric isolation layer material, where n is an integer ≥ 4; and / or

[0080] The method for depositing the isolation layer material is thin film deposition.

[0081] Preferably, the thin film deposition method is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating, and electron beam evaporation.

[0082] According to the preparation method of the second aspect of the present invention,

[0083] The method for etching the metallic material is selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, ALE etching; and / or

[0084] The method for etching each dielectric isolation layer is selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, and ALE etching;

[0085] Preferably, the thickness of each layer of metal material and dielectric material is not less than 5nm, more preferably not less than 4nm, further preferably not less than 3nm, even more preferably not less than 2nm, and most preferably not less than 1nm.

[0086] According to a specific embodiment of the present invention, the present invention provides a method for fabricating a vertical semiconductor device with nanometer-scale linewidth, the method comprising the following steps:

[0087] (1) Provide the required wafer substrate;

[0088] (2) Prepare the patterned structure and transfer it onto the wafer substrate provided in step (1);

[0089] (3) Oxidize the graphic structure of step (2), then remove the oxide layer, leaving the strip structure;

[0090] (4) Spin coat photoresist onto the wafer substrate in step (1), and then remove part of the photoresist from top to bottom until the wafer surface is exposed;

[0091] (5) Prepare an isolation layer in a specific area once or multiple times to form an isolation layer, then remove the photoresist and clean it.

[0092] (6) Deposit the first metallic material to fabricate the source electrode;

[0093] (7) Deposit medium isolation layer material to fabricate the first medium isolation layer;

[0094] (8) Deposit a second metallic material to fabricate a gate electrode;

[0095] (9) Deposit the medium isolation layer material to fabricate the second medium isolation layer;

[0096] (10) Deposit a third metal material to fabricate a drain electrode;

[0097] (11) Repeat steps (6) to (10) above sequentially, stacking the following structure once or multiple times: source electrode, nth dielectric isolation layer, gate electrode, n+1th dielectric isolation layer, drain electrode, where n is an integer ≥4;

[0098] Preferably, the feature size of the fabricated device is consistent with the size of the strip structure left in step (3); and / or

[0099] Preferably, the feature size of the fabricated device is selected from one or more of the following: 28nm, 14nm, 7nm, 5nm, 3nm.

[0100] According to the method for fabricating a vertically structured semiconductor device with nanometer-scale linewidth of the present invention, in step (3), the method for fabricating a functional layer with a patterned structure on the substrate is selected from one or more of the following: photolithography, electron beam lithography, laser direct writing, wherein the photolithography is preferably selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography; and / or

[0101] Step (3) also includes the following steps:

[0102] When the subsequent device design size is consistent with the strip structure size, no further processing is performed; when the subsequent device design size is smaller than the strip structure size, the functional layer with patterned structure located on the substrate is transferred to the substrate of step (1), and when the structure size is reduced to the design size, the structure size is reduced by slow etching; and / or the patterned structure is oxidized, and then the oxide layer is removed, leaving the strip structure; wherein: the method of transferring the functional layer is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, wet etching, ALE etching; the method of slow etching is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, ALE etching; the method of oxidizing the patterned structure is preferably: thermal oxidation or wet oxidation; the method of removing the oxide layer is preferably: wet etching or dry etching; the solution used for wet etching is preferably HF solution or NH4F solution; the method used for dry etching is preferably selected from one or more of the following: RIE etching, ICP-RIE etching, ALE etching.

[0103] According to the method for fabricating a vertical semiconductor device with nanometer-scale linewidth according to the present invention, in step (3), the patterned structure is a strip structure with a common interconnect;

[0104] Preferably, the width of the strip structure is 30-80 nm, more preferably 40-80 nm, even more preferably 40-70 nm, even more preferably 40-60 nm, and most preferably 50 nm;

[0105] Preferably, the linewidth of the strip structure is 1-40 nm, more preferably 1-30 nm, even more preferably 1-20 nm, even more preferably 1-10 nm, and most preferably 5 nm; and / or

[0106] Preferably, the depth of the strip structure is 500-800nm, more preferably 500-700nm, even more preferably 550-700nm, even more preferably 600-700nm, and most preferably 650nm.

[0107] Based on the aforementioned method, it further includes: in steps (6) to (11),

[0108] The method for removing photoresist and etching it to the structure surface is selected from one or more of the following: RIE etching, ICP-RIE etching, and Ar ion etching;

[0109] The cleaning solution is selected from one or more of the following: acetone, alcohol, deionized water; and / or

[0110] The solution for removing photoresist is selected from one or more of the following: acetone, photoresist remover;

[0111] Preferably, the thickness of each layer of metal material and dielectric material is not less than 5nm, more preferably not less than 4nm, further preferably not less than 3nm, even more preferably not less than 2nm, and most preferably not less than 1nm.

[0112] According to another specific embodiment of the present invention, the present invention provides a vertical structure semiconductor device with nanometer-scale linewidth, the structure of which, from bottom to top, is as follows: substrate; source electrode; isolation layer material; gate electrode; isolation layer; drain electrode; isolation layer; and the source electrode, isolation layer, gate electrode, isolation layer, and drain electrode can be stacked repeatedly upwards.

[0113] Preferably, the substrate is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, germanium; preferably, it is a silicon wafer.

[0114] Preferably, the dielectric material is selected from one or more of the following: silicon nitride, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, and polyimide.

[0115] Preferably, the electrode metal material includes, but is not limited to, gold, silver, nickel, titanium, aluminum, copper, germanium, and zinc.

[0116] According to another specific embodiment of the present invention, the present invention provides a method for fabricating a vertically structured semiconductor device with nanometer-scale linewidth, the method comprising the following steps:

[0117] (1) Provide the wafer substrate required for the process fabrication;

[0118] (2) Use graphic preparation methods to prepare the required graphic;

[0119] (3) Using a pattern transfer method, the pattern prepared in step (2) is transferred to a wafer substrate;

[0120] (4) Using thermal oxidation to oxidize materials of a specific thickness;

[0121] (5) Use wet etching to remove the oxide layer and leave material of a specific size;

[0122] (6) Spin-coating photoresist;

[0123] (7) Remove part of the photoresist from top to bottom until the wafer surface is exposed;

[0124] (8) An isolation layer is prepared in a specific region by ion implantation;

[0125] (9) Remove the photoresist;

[0126] (10) Deposit a first metallic material of a specific thickness;

[0127] (11) Spin-coating photoresist;

[0128] (12) Remove part of the photoresist from top to bottom until the first metal surface is exposed;

[0129] (13) Using etching methods, part of the first metal material is removed;

[0130] (14) Remove the photoresist;

[0131] (15) Using photolithography and etching methods, a portion of the first metal material is removed to define the electrode positions;

[0132] (16) Deposit a first medium material of a specific thickness;

[0133] (17) Spin-coating photoresist;

[0134] (18) Remove part of the photoresist from top to bottom until the surface of the first dielectric material is exposed;

[0135] (19) Using an etching method, part of the first dielectric material is removed;

[0136] (20) Remove the photoresist;

[0137] (21) Etching removes part of the first dielectric material;

[0138] (22) Deposit a second metallic material of a specific thickness;

[0139] (23) Spin-coating photoresist;

[0140] (24) Remove part of the photoresist from top to bottom until the surface of the second metal material is exposed;

[0141] (25) Using etching methods, part of the second metal material is removed;

[0142] (26) Remove the photoresist;

[0143] (27) Using photolithography and etching methods, part of the second metal material is removed to define the electrode positions;

[0144] (28) Deposit a second medium material of a specific thickness;

[0145] (29) Spin-coating photoresist;

[0146] (30) Remove part of the photoresist from top to bottom until the surface of the second dielectric material is exposed;

[0147] (31) Using etching methods, part of the second dielectric material is removed;

[0148] (32) Remove photoresist;

[0149] (33) Etching removes part of the second dielectric material;

[0150] (34) Deposit a third metallic material of a specific thickness;

[0151] (35) Spin-coating photoresist;

[0152] (36) Remove part of the photoresist from top to bottom until the surface of the third metal material is exposed;

[0153] (37) Using etching methods, part of the third metal material is removed;

[0154] (38) Remove photoresist;

[0155] (39) Using photolithography and etching methods, part of the third metal material is removed to define the electrode positions;

[0156] (40) Depositing a third medium material of a specific thickness;

[0157] (41) Spin-coating photoresist;

[0158] (42) Remove part of the photoresist from top to bottom until the surface of the third dielectric material is exposed;

[0159] (43) Use etching to remove part of the third medium material;

[0160] (44) Remove photoresist;

[0161] (45) Etching removes part of the third dielectric material;

[0162] (46) Steps (10) to (45) can be repeated as needed.

[0163] According to the method of this embodiment, the wafer material is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, germanium, and wafers with a certain epitaxial structure;

[0164] Silicon wafers are preferred;

[0165] The dielectric material is selected from one or more of the following: silicon nitride, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, and polyimide;

[0166] Preferably, the deposition medium material is uniform.

[0167] According to the method of this embodiment, the deposition method of the dielectric material is a thin film deposition method. Preferably, the thin film deposition method is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating, and electron beam evaporation.

[0168] According to the method of this embodiment, the deposition method of the metal material is a thin film deposition method. Preferably, the thin film deposition method is selected from one or more of the following: reactive ion magnetron sputtering, electron beam evaporation.

[0169] According to the method of this embodiment, in step (2), the pattern preparation method is selected from one or more of the following: photolithography, electron beam exposure, laser direct writing; preferably, the photolithography is selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography.

[0170] According to the method of this embodiment, in step (3), the pattern transfer method includes RIE etching, ICP-RIE etching, Ar ion etching, and wet etching.

[0171] According to the method of this embodiment, the feature size of the device prepared is consistent with the material structure size left in step (5);

[0172] Preferably, its feature size is 28nm, 14nm, 7nm, 5nm, or 3nm.

[0173] According to the method of this embodiment, the isolation layer in step (8) can be prepared once or multiple times, and the process can be carried out according to the subsequent requirements.

[0174] According to the method of this embodiment, the metallic material includes, but is not limited to, gold, silver, nickel, titanium, aluminum, copper, germanium, and zinc.

[0175] According to the method of this embodiment, the etching methods for metallic and dielectric materials include, but are not limited to, RIE etching, ICP-RIE etching, and Ar ion etching.

[0176] According to the method of this embodiment, the thickness of each layer of metal material and dielectric material is not less than 1 nm.

[0177] According to the method of this embodiment, the graphic structure prepared in step (2) can be regular or irregular;

[0178] Preferably, its shape is a strip structure with common connecting elements.

[0179] According to the method of this embodiment, in step (13), a portion of the first metal material is removed, and a specific retention area can be set to facilitate subsequent process connections.

[0180] According to the method of this implementation scheme, the number of repetitions mentioned in step (46) should be at least once.

[0181] The device fabricated according to the steps described in this embodiment has the following structure from bottom to top: source electrode, dielectric isolation layer, gate electrode, dielectric isolation layer, drain electrode, and dielectric isolation layer.

[0182] In summary, this invention provides a method for fabricating vertically structured semiconductor devices with nanometer-scale linewidths. This method can achieve nanometer-scale linewidth vertically structured semiconductor devices using traditional thin-film fabrication processes, not only avoiding the use of high-end lithography equipment but also providing a novel approach to device fabrication.

[0183] When planar device structures are transformed into vertical device structures, existing equipment and traditional processes can be used to fabricate devices with smaller linewidths. This not only avoids the pressure of equipment upgrades but also allows for the introduction of more device structure design ideas. Combined with current 3D integration processes, it can also meet the fabrication needs for a wide range of functions and structures.

[0184] The nanometer-scale linewidth vertical structure semiconductor device of the present invention can have, but is not limited to, the following beneficial effects:

[0185] 1. The method provided by this invention can realize semiconductor devices with vertical structures and nanometer-scale linewidths through traditional thin film preparation processes. This not only avoids the use of high-end lithography machines, but also provides a new approach to device preparation.

[0186] 2. This invention addresses the preparation and acquisition of nanogates by proposing a method that combines material oxidation and thin film deposition techniques to prepare nanogates, thereby improving the device fabrication process and reducing the device fabrication cost. Attached Figure Description

[0187] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings, wherein:

[0188] Figure 1 A flowchart of Embodiment 1 of the present invention is shown.

[0189] Figure 2 A flowchart of Embodiment 2 of the present invention is shown.

[0190] Figure 3 A schematic diagram of the wafer substrate described in Embodiment 2 of the present invention is shown.

[0191] Figure 4 A schematic diagram of the fabrication of the desired structure on a wafer is shown in Embodiment 2 of the present invention.

[0192] Figure 5 A top view of the fabrication of the desired structure on a wafer is shown in Embodiment 2 of the present invention.

[0193] Figure 6The diagram shows a top view of a portion of the material after thermal oxidation, according to Embodiment 2 of the present invention.

[0194] Figure 7 The diagram shows a top view of Embodiment 2 of the present invention after the oxide layer has been removed.

[0195] Figure 8 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0196] Figure 9 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0197] Figure 10 A schematic diagram of ion implantation to prepare an isolation layer is shown in Embodiment 2 of the present invention.

[0198] Figure 11 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0199] Figure 12 A schematic diagram of the deposition of a first metallic material is shown in Embodiment 2 of the present invention.

[0200] Figure 13 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0201] Figure 14 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0202] Figure 15 A schematic diagram of removing part of the first metal material is shown in Embodiment 2 of the present invention.

[0203] Figure 16 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0204] Figure 17 A top view of the removal of photoresist in Embodiment 2 of the present invention is shown.

[0205] Figure 18 A top view of Embodiment 2 of the present invention showing the removal of a portion of the first metal material is shown.

[0206] Figure 19 A schematic diagram of the deposition of the first dielectric isolation layer in Embodiment 2 of the present invention is shown.

[0207] Figure 20 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0208] Figure 21 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0209] Figure 22A schematic diagram of removing part of the first dielectric isolation layer is shown in Embodiment 2 of the present invention.

[0210] Figure 23 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0211] Figure 24 A schematic diagram of the deposition of a second metallic material is shown in Embodiment 2 of the present invention.

[0212] Figure 25 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0213] Figure 26 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0214] Figure 27 A schematic diagram of removing part of the second metal material is shown in Embodiment 2 of the present invention.

[0215] Figure 28 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0216] Figure 29 A top view of the removal of photoresist in Embodiment 2 of the present invention is shown.

[0217] Figure 30 A top view of Embodiment 2 of the present invention showing the removal of a portion of the second metal material is shown.

[0218] Figure 31 A schematic diagram of the deposition of the second dielectric isolation layer in Embodiment 2 of the present invention is shown.

[0219] Figure 32 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0220] Figure 33 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0221] Figure 34 A schematic diagram of removing part of the second dielectric isolation layer is shown in Embodiment 2 of the present invention.

[0222] Figure 35 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0223] Figure 36 A schematic diagram of the deposition of a third metallic material is shown in Embodiment 2 of the present invention.

[0224] Figure 37 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0225] Figure 38A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0226] Figure 39 A schematic diagram of removing part of the third metal material is shown in Embodiment 2 of the present invention.

[0227] Figure 40 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0228] Figure 41 A top view of the removal of photoresist in Embodiment 2 of the present invention is shown.

[0229] Figure 42 A top view of Embodiment 2 of the present invention showing the removal of a portion of the third metal material is shown.

[0230] Figure 43 A schematic diagram of the deposition of the third dielectric isolation layer in Embodiment 2 of the present invention is shown.

[0231] Figure 44 This diagram shows a schematic of the photoresist after spin coating in Embodiment 2 of the present invention.

[0232] Figure 45 A schematic diagram of removing surface photoresist in Embodiment 2 of the present invention is shown.

[0233] Figure 46 A schematic diagram of removing part of the third medium isolation layer is shown in Embodiment 2 of the present invention.

[0234] Figure 47 A schematic diagram of photoresist removal in Embodiment 2 of the present invention is shown.

[0235] Figure 48 This diagram illustrates the preparation of a second device by repeating the above steps in Embodiment 2 of the present invention.

[0236] Explanation of reference numerals in the attached figures:

[0237] 1. Wafer substrate; 2, 3. Patterned structure; 3'. Oxide layer; 5. Isolation layer; 6A, 6B, 6C. First metal material; 4, 7, 9, 11, 13, 15, 17. Photoresist; 8A, 8B, 8C. First dielectric isolation layer; 10A, 10B, 10C. Second metal material; 12A, 12B, 12C. Second dielectric isolation layer; 14A, 14B, 14C. Third metal material; 16A, 16B, 16C. Third dielectric isolation layer; 18. Fourth metal material; 19. Fourth dielectric isolation layer; 20. Fifth metal material; 21. Fifth dielectric isolation layer; 22. Sixth metal material. Detailed Implementation

[0238] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. However, it should be understood that these embodiments are merely for more detailed and specific explanation and should not be construed as limiting the present invention in any way.

[0239] The objects and functions of the present invention, as well as the methods for achieving these objects and functions, will be clarified by referring to exemplary embodiments. However, the present invention is not limited to the exemplary embodiments disclosed below: it can be implemented in various forms. The purpose of this specification is merely to help those skilled in the art to comprehensively understand the specific details of the invention.

[0240] Example 1

[0241] This embodiment illustrates a typical fabrication method for the nanoscale linewidth vertical structure semiconductor device described in this invention.

[0242] The specific process is as follows: Figure 1 As shown, it includes the following steps:

[0243] S100: Provides the required wafer substrate;

[0244] S200: Prepare the patterned structure and transfer it onto the wafer substrate provided in step S100;

[0245] S300: The graphic structure of oxidation step S200, then the oxide layer is removed, leaving a strip structure;

[0246] S400: Photoresist is spin-coated onto the wafer substrate in step S100, and then a portion of the photoresist is removed from top to bottom until the wafer surface is exposed;

[0247] S500: An isolation layer is prepared for a specific area to form an isolation layer, and then the photoresist is removed and the area is cleaned.

[0248] S600: Deposit the first metallic material to fabricate the source electrode;

[0249] S700: Deposited medium isolation layer material, used to fabricate the first medium isolation layer;

[0250] S800: Deposit a second metallic material to fabricate the gate electrode;

[0251] S900: Deposited medium isolation layer material, used to fabricate a second medium isolation layer;

[0252] S1000: Deposit a third metal material to fabricate the drain electrode;

[0253] S1100: Repeat steps S600 to S1000 sequentially upwards to continue fabricating a new device. The source electrode, dielectric isolation layer, gate electrode, dielectric isolation layer, and drain electrode can be stacked repeatedly.

[0254] Example 2

[0255] This embodiment combines Figure 2-48 This describes an optimized fabrication method for the nanoscale linewidth vertical structure semiconductor device described in this invention.

[0256] The specific process is as follows: Figure 2 As shown, it includes the following steps:

[0257] S100: Provides the wafer substrate 1 required for process fabrication;

[0258] S200: Fabricate patterned structures and transfer them to a wafer substrate;

[0259] S300: Oxidation pattern structure 3 is achieved using thermal oxidation method;

[0260] S400: Removes oxide layer 3';

[0261] S500: Spin-coated photoresist 4;

[0262] S600: Removes the photoresist 4 from the surface until the structure surface is reached;

[0263] S700: The isolation layer 5 was prepared by ion implantation;

[0264] S800: Remove photoresist 4;

[0265] S900: Deposition source electrodes 6A, 6B, 6C;

[0266] S1000: Spin-coated photoresist 7;

[0267] S1100: Removes the photoresist 7 from the surface down to the structure surface;

[0268] S1200: Remove part of the source electrodes 6B and 6C;

[0269] S1300: Remove photoresist 7;

[0270] S1400: Remove part of the source electrode 6A according to the graphic definition;

[0271] S1500: Deposition of first medium materials 8A, 8B, and 8C;

[0272] S1600: Spin-coated photoresist 9;

[0273] S1700: Removes the photoresist 9 from the surface down to the structure surface;

[0274] S1800: Remove part of the first dielectric material 8B and 8C;

[0275] S1900: Remove photoresist 9;

[0276] S2000: Deposited gate electrodes 10A, 10B, 10C;

[0277] S2100: Spin-coated photoresist 11;

[0278] S2200: Remove the photoresist 11 from the surface down to the structure surface;

[0279] S2300: Remove part of the gate electrodes 10B and 10C;

[0280] S2400: Remove photoresist 11;

[0281] S2500: Remove part of the gate electrode 10A according to the graphic definition;

[0282] S2600: Deposition of secondary medium materials 12A, 12B, and 12C;

[0283] S2700: Spin-coated photoresist 13;

[0284] S2800: Remove the photoresist 13 from the surface down to the structure surface;

[0285] S2900: Remove part of the second dielectric material 12B and 12C;

[0286] S3000: Remove photoresist 13;

[0287] S3100: Deposited drain electrodes 14A, 14B, 14C;

[0288] S3200: Spin-coated photoresist 15;

[0289] S3300: Remove some of the drain electrodes 14B and 14C;

[0290] S3400: Remove photoresist 15;

[0291] S3500: Remove part of the drain electrode 14A according to the graphic definition;

[0292] S3600: Deposition of third media materials 16A, 16B, and 16C;

[0293] S3700: Spin-coated photoresist 17;

[0294] S3800: Removes the photoresist 17 from the surface down to the structure surface;

[0295] S3900: Remove some of the third medium material 16B and 16C;

[0296] S4000: Remove photoresist 17;

[0297] S4100: Repeat S900~S3500 to prepare a new device.

[0298] In this embodiment, a silicon substrate is used as the wafer required for the process, such as Figure 3 As shown;

[0299] Next, using ultraviolet lithography, and in conjunction with a pre-designed photomask with a specific pattern, the pattern is fabricated on the photoresist. Then, using RIE etching with O2 and CF4 as etching gases at flow rates of 10 sccm and 30 sccm respectively, and an etching power of 150 W, the pattern is transferred onto a silicon wafer. The pattern used in this embodiment is as follows... Figure 5 As shown, there are multiple strip-shaped structures on both sides, with a width of 50nm and an etching depth of 650nm; the structure after etching is as follows. Figure 4 As shown;

[0300] Next, a thermal oxidation method is used to oxidize part of the material. The silicon wafer is placed in a reaction tube made of quartz glass, and the reaction tube is heated to 1200°C using a resistance wire furnace. Water vapor passes through the reaction tube, oxidizing the 22.5nm thick silicon material. Figure 6 As shown;

[0301] The silicon wafer is then immersed in an HF solution to remove the oxide layer, leaving a strip structure with a linewidth of 5 nm, such as... Figure 7 As shown;

[0302] Then, photoresist is spin-coated onto the wafer surface to cover the structural surface, such as... Figure 8 As shown;

[0303] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 9 As shown;

[0304] Then, an isolation layer is created using ion implantation. Accelerated oxygen is used to form an isolation layer in a selected region, positioned from top to bottom at 320 nm to 330 nm. Figure 10 As shown.

[0305] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 11 As shown;

[0306] Next, a 100nm thick layer of metallic aluminum was deposited using a sputtering method, such as... Figure 12 As shown;

[0307] Then, photoresist is spin-coated to cover the surface of the structure, such as... Figure 13 As shown;

[0308] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 14 As shown;

[0309] Next, using the RIE etching method, with Ar as the etching gas at a flow rate of 100 sccm and an etching power of 200 W, a portion of the metallic aluminum material was etched away, such as... Figure 15 As shown;

[0310] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 16 As shown;

[0311] Next, photolithography was used in conjunction with RIE etching, using Ar as the etching gas at a flow rate of 100 sccm and an etching power of 200 W to etch away part of the aluminum material. The remaining aluminum was used as the source electrode. Figure 18 As shown;

[0312] Next, using the ALD deposition method, a 10nm first dielectric isolation layer material, silicon dioxide, was deposited at a deposition temperature of 200℃. The precursor materials used were aminosilane and water vapor-coated surface pattern structures, such as... Figure 19 As shown;

[0313] Then, photoresist is spin-coated onto the wafer surface to cover the structural surface, such as... Figure 20 As shown;

[0314] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 21 As shown;

[0315] Next, using RIE etching with O2 and CF4 as etching gases at flow rates of 10 sccm and 30 sccm respectively, and an etching power of 150 W, part of the first dielectric isolation layer material was etched away. Figure 22 As shown;

[0316] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 23 As shown;

[0317] Next, a 100nm thick layer of metallic copper was deposited using a sputtering method, such as... Figure 24 As shown;

[0318] Then, photoresist is spin-coated onto the wafer surface to cover the structural surface, such as... Figure 25As shown;

[0319] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 26 As shown;

[0320] Next, using the RIE etching method, with Ar as the etching gas at a flow rate of 100 sccm and an etching power of 200 W, part of the metallic copper material was etched away. Figure 27 As shown;

[0321] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 28 As shown;

[0322] Next, photolithography combined with RIE etching was used, with Ar as the etching gas at a flow rate of 100 sccm and an etching power of 200 W, to etch away part of the copper material. The remaining copper was used as the gate electrode. Figure 30 As shown;

[0323] Next, a 10 nm second dielectric isolation layer of silicon dioxide was deposited using the ALD deposition method at a deposition temperature of 200 °C. The precursor materials used were aminosilane and water vapor-coated surface pattern structures, such as... Figure 31 As shown;

[0324] Then, photoresist is spin-coated onto the wafer surface to cover the structural surface, such as... Figure 32 As shown;

[0325] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 33 As shown;

[0326] Next, using RIE etching with O2 and CF4 as etching gases at flow rates of 10 sccm and 30 sccm respectively, and an etching power of 150 W, part of the second dielectric isolation layer material was etched away. Figure 34 As shown;

[0327] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 35 As shown;

[0328] Next, a 100nm thick layer of metallic aluminum was deposited using a sputtering method, such as... Figure 36 As shown;

[0329] Then, photoresist is spin-coated onto the wafer surface to cover the structural surface, such as... Figure 37 As shown;

[0330] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 38 As shown;

[0331] Next, using the RIE etching method, with Ar as the etching gas at a flow rate of 100 sccm and an etching power of 200 W, a portion of the metallic aluminum material was etched away, such as... Figure 39 As shown;

[0332] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 40 As shown;

[0333] Next, combining photolithography with RIE etching, using Ar as the etching gas at a flow rate of 100 sccm and an etching power of 200 W, part of the copper material was etched away, and the remaining aluminum was used as the drain electrode. Figure 42 As shown;

[0334] Next, a 10nm third dielectric isolation layer material, silicon dioxide, was deposited using the ALD deposition method at a deposition temperature of 200℃. The precursor materials used were aminosilane and water vapor-coated surface pattern structures, such as... Figure 43 As shown;

[0335] Then, photoresist is spin-coated onto the wafer surface to cover the structural surface, such as... Figure 44 As shown;

[0336] Next, using the RIE etching method with O2 as the etching gas at a flow rate of 50 sccm and an etching power of 150 W, the photoresist on the surface was completely removed, and the etching proceeded to the structure surface, such as... Figure 45 As shown;

[0337] Next, using RIE etching with O2 and CF4 as etching gases at flow rates of 10 sccm and 30 sccm respectively, and an etching power of 150 W, part of the third dielectric isolation layer material was etched away. Figure 46 As shown;

[0338] Then, acetone is used to remove the photoresist, and the surface is cleaned with alcohol and deionized water. Figure 47 As shown;

[0339] Next, repeat the above steps to fabricate a new device with the source electrode, fourth dielectric isolation layer, gate electrode, fifth dielectric isolation layer, and drain electrode, as follows. Figure 48 As shown.

[0340] Although the invention has been described to a certain extent, it is apparent that appropriate variations can be made to the various conditions without departing from the spirit and scope of the invention. It is understood that the invention is not limited to the described embodiments, but falls within the scope of the claims, which include equivalent substitutions for each of the elements.

Claims

1. A vertical structure semiconductor device of nanometer scale line width, characterized by, The nanometer-scale linewidth vertical structure semiconductor device comprises, from bottom to top, the following: Substrate; A functional layer with a patterned structure located on a substrate, wherein the patterned structure consists of multiple independent structures connected to the same support backplate; the multiple independent structures and the support backplate are fabricated in a single patterned structure; the multiple independent structures are connected to the same support backplate. The source electrode is located on the substrate and is in contact with the functional layer; A first dielectric isolation layer located on the source electrode and in contact with the functional layer; A gate electrode located on the first dielectric isolation layer and in contact with the functional layer; A second dielectric isolation layer located on the gate electrode and in contact with the functional layer; The drain electrode is located on the second dielectric isolation layer and is in contact with the functional layer; and A third dielectric isolation layer located on the drain electrode and in contact with the functional layer.

2. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 1, characterized in that, The nanoscale linewidth vertical structure semiconductor device further includes: stacking the following structures sequentially one or more times: source electrode, nth dielectric isolation layer, gate electrode, n+1th dielectric isolation layer, and drain electrode, where n is an integer ≥ 4.

3. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 1 or 2, characterized in that, The supporting back plate has a strip-shaped structure.

4. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 1 or 2, characterized in that: The functional regions corresponding to the third dielectric isolation layer have isolation properties; and / or The substrate material is selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, germanium, and epitaxial wafers with multilayer structures; The source electrode, gate electrode, and drain electrode are made of one or more of the following materials: gold, silver, nickel, titanium, aluminum, copper, germanium, zinc, chromium, tin; and / or The dielectric isolation layer material is selected from one or more of the following: silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, and polyimide.

5. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 2, characterized in that, The first dielectric isolation layer, the second dielectric isolation layer, the third dielectric isolation layer, the nth dielectric isolation layer, and the (n+1)th dielectric isolation layer are made of the same material.

6. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 4, characterized in that: The isolation property is: electrical isolation or optical isolation; and / or The substrate is made of silicon, gallium arsenide, silicon carbide, gallium nitride, or gallium oxide. The source electrode, gate electrode, and drain electrode are made of gold, silver, nickel, titanium, aluminum, copper, or germanium; and / or The dielectric isolation layer material is silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, or gallium oxide.

7. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 6, characterized in that: The substrate is made of silicon, gallium arsenide, or silicon carbide. The source electrode, gate electrode, and drain electrode are made of gold, silver, nickel, titanium, aluminum, or copper; and / or The dielectric isolation layer material is silicon dioxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, or aluminum nitride.

8. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 7, characterized in that: The substrate is made of silicon or silicon carbide. The source electrode, gate electrode, and drain electrode are made of aluminum or copper; and / or The dielectric isolation layer material is silicon dioxide, silicon nitride, aluminum oxide, or titanium oxide.

9. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 8, characterized in that, The substrate is made of silicon.

10. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 1 or 2, characterized in that: The contact method between the source electrode located on the substrate and the functional layer is either point contact or surround contact. The gate electrode located on the first dielectric isolation layer contacts the functional layer in a circumferential contact manner; The contact method between the drain electrode located on the second dielectric isolation layer and the functional layer is either point contact or circumferential contact. The first dielectric isolation layer located on the source electrode and the functional layer are in a circumferential contact manner; The second dielectric isolation layer located on the gate electrode contacts the functional layer in a circumferential contact manner; and / or The third dielectric isolation layer located on the drain electrode contacts the functional layer in a circumferential contact manner.

11. The vertical structure semiconductor device with nanometer-scale linewidth according to claim 1 or 2, characterized in that: The source electrode, located on the substrate and in contact with the functional layer, has a patterned structure; The gate electrode, located on the first dielectric isolation layer and in contact with the functional layer, has a patterned structure; The drain electrode, located on the second dielectric isolation layer and in contact with the functional layer, has a patterned structure; The first dielectric isolation layer, located on the source electrode and in contact with the functional layer, has a patterned structure; The second dielectric isolation layer, located on the gate electrode and in contact with the functional layer, has a patterned structure; and / or The third dielectric isolation layer, located on the drain electrode and in contact with the functional layer, has a patterned structure.

12. A method for preparing a semiconductor device as described in any one of claims 1 to 11, characterized in that, The method includes the following steps: (1) Preparation of substrate; (2) Prepare a functional layer and a support backplate with a patterned structure on a substrate, wherein the patterned structure consists of multiple independent structures connected to the same support backplate; (3) Fabricate a source electrode located on the substrate and in contact with the functional layer; (4) Prepare a first dielectric isolation layer located on the source electrode and in contact with the functional layer; (5) Fabricate a gate electrode located on the first dielectric isolation layer and in contact with the functional layer; (6) Prepare a second dielectric isolation layer located on the gate electrode and in contact with the functional layer; (7) Fabricate a drain electrode located on the second dielectric isolation layer and in contact with the functional layer; (8) Prepare a third dielectric isolation layer located on the drain electrode and in contact with the functional layer; (9) Repeat steps (3) to (8) above in sequence, stacking the following structures once or multiple times: source electrode, nth dielectric isolation layer, gate electrode, n+1th dielectric isolation layer, drain electrode, where n is an integer ≥4.

13. A method for preparing the semiconductor device as described in claim 3, characterized in that, The method includes the following steps: (1) Preparation of substrate; (2) Prepare a functional layer and a support backplate with a patterned structure on a substrate, wherein the patterned structure consists of multiple independent structures connected to the same support backplate; (3) Fabricate a source electrode located on the substrate and in contact with the functional layer; (4) Prepare a first dielectric isolation layer located on the source electrode and in contact with the functional layer; (5) Fabricate a gate electrode located on the first dielectric isolation layer and in contact with the functional layer; (6) Prepare a second dielectric isolation layer located on the gate electrode and in contact with the functional layer; (7) Fabricate a drain electrode located on the second dielectric isolation layer and in contact with the functional layer; (8) Prepare a third dielectric isolation layer located on the drain electrode and in contact with the functional layer; (9) Repeat steps (3) to (8) above in sequence, stacking the following structure once or multiple times: source electrode, nth dielectric isolation layer, gate electrode, n+1th dielectric isolation layer, drain electrode, where n is an integer ≥4; The feature dimensions of the fabricated device are consistent with the dimensions of the strip structure.

14. The method according to claim 12 or 13, characterized in that: Methods for preparing the isolation layer include, but are not limited to, epitaxial growth, ion implantation, oxidation, diffusion; and / or The feature size of the fabricated device is selected from one or more of the following: 28nm, 14nm, 7nm, 5nm, 3nm.

15. The preparation method according to claim 12 or 13, characterized in that: In step (2), the method for preparing the patterned functional layer on the substrate is selected from one or more of the following: photolithography, electron beam lithography, laser direct writing; and / or Step (2) also includes the following steps: When the subsequent device design size is consistent with the strip structure size, no further processing is performed; when the subsequent device design size is smaller than the strip structure size, the functional layer with the patterned structure located on the substrate is transferred to the substrate in step (1), and when the structure size is reduced to the design size, the structure size is reduced by slow etching; and / or The oxide pattern is then removed, leaving a strip-shaped structure.

16. The preparation method according to claim 15, characterized in that, In step (2): The photolithography is selected from one or more of the following: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography; and / or The method for transferring the functional layer is selected from one or more of the following: RIE etching, ICP-RIE etching, wet etching, and ALE etching; the method for slow etching is selected from one or more of the following: RIE etching, ICP-RIE etching, and ALE etching; the method for creating the oxide pattern structure is thermal oxidation or wet oxidation; the method for removing the oxide layer is wet etching or dry etching.

17. The preparation method according to claim 12 or 13, characterized in that: When the substrate is a wafer and an isolation layer needs to be prepared first, step (2) may also include the following steps: prepare an isolation layer once or multiple times on the entire wafer to form an isolation layer; When the substrate is a wafer and it is not necessary to prepare an isolation layer first, the following steps are included after step (2): spin-coating photoresist on the substrate, then removing part of the photoresist from top to bottom to expose the wafer surface, preparing an isolation layer once or multiple times for a specific area to form an isolation layer, and then removing the photoresist and cleaning it. Furthermore, when the wafer is a multilayer epitaxial layer, an isolation layer is epitaxially deposited between its multiple functional devices, and the isolation layer preparation step is not included after step (2).

18. The preparation method according to claim 17, characterized in that: The method for removing part of the photoresist to expose the wafer surface is selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, wet etching, and ALE etching; The isolation layer is prepared by ion implantation; and / or The method for removing photoresist is selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, solution cleaning, and ALE etching.

19. The preparation method according to claim 12 or 13, characterized in that: In steps (3), (5), (7) and / or (9), the method further includes the following steps: (a) Deposit the metallic material of the source electrode, gate electrode and / or drain electrode, spin-coat photoresist to cover the surface of the structure; (b) Etching removes the photoresist and etches it to the structure surface; (c) Etch part of the metal material down to the upper surface of the lower contact layer, remove the photoresist, and clean it thoroughly; (d) Define the pattern structure using photolithography, etch a portion of the metal material, and use the remaining metal material as the source electrode, gate electrode, and / or drain electrode; wherein, in step (c), when etching a portion of the first metal material, a reserved area is set to connect to subsequent operations; The metallic material is selected from one or more of the following: a first metallic material, a second metallic material, a third metallic material, an nth metallic material, and an (n+1)th metallic material, where n is an integer ≥ 4; and / or The method for depositing metallic materials is thin film deposition.

20. The preparation method according to claim 19, characterized in that, The thin film deposition method is selected from one or more of the following: magnetron sputtering, electron beam evaporation, atomic layer deposition, and chemical vapor deposition.

21. The preparation method according to claim 12 or 13, characterized in that: In steps (4), (6), (8) and / or (9), the method further includes the following steps: (e) Deposit the dielectric isolation layer material, spin-coat it with photoresist, and cover the structure surface; (f) Etching removes the photoresist and etches it to the structure surface; (g) Define the patterned structure using photolithography, etch a portion of the dielectric isolation layer material down to the upper surface of the lower contact layer, remove the photoresist and clean it thoroughly, leaving the remaining dielectric isolation layer material as the dielectric isolation layer; wherein, The dielectric isolation layer material is selected from one or more of the following: a first dielectric isolation layer material, a second dielectric isolation layer material, a third dielectric isolation layer material, an nth dielectric isolation layer material, and an (n+1)th dielectric isolation layer material, where n is an integer ≥ 4; and / or The method for depositing the isolation layer material is thin film deposition.

22. The preparation method according to claim 21, characterized in that, Thin film deposition methods are selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating, and electron beam evaporation.

23. The preparation method according to claim 19, characterized in that: The method for etching the metallic material is selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, ALE etching; and / or The method for etching each dielectric isolation layer is selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, and ALE etching.

24. The preparation method according to claim 23, characterized in that, The thickness of each layer of metal and dielectric material is no less than 5 nm.

25. The preparation method according to claim 24, characterized in that, The thickness of each layer of metal and dielectric material is no less than 4 nm.

26. The preparation method according to claim 25, characterized in that, The thickness of each layer of metal and dielectric material is no less than 3 nm.

27. The preparation method according to claim 26, characterized in that, The thickness of each layer of metal and dielectric material is no less than 2nm.

28. The preparation method according to claim 27, characterized in that, The thickness of each layer of metal and dielectric material is no less than 1 nm.

29. The preparation method according to claim 21, characterized in that, The method for etching the metallic material is selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, ALE etching; and / or The method for etching each dielectric isolation layer is selected from one or more of the following: RIE etching, ICP-RIE etching, Ar ion etching, and ALE etching.

30. The preparation method according to claim 29, characterized in that, The thickness of each layer of metal and dielectric material is no less than 5 nm.

31. The preparation method according to claim 30, characterized in that, The thickness of each layer of metal and dielectric material is no less than 4 nm.

32. The preparation method according to claim 31, characterized in that, The thickness of each layer of metal and dielectric material is no less than 3 nm.

33. The preparation method according to claim 32, characterized in that, The thickness of each layer of metal and dielectric material is no less than 2nm.

34. The preparation method according to claim 33, characterized in that, The thickness of each layer of metal and dielectric material is no less than 1 nm.

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