Transistor with controllable source / drain structure

Abstract

A transistor structure includes a substrate, a gate conductive region, a gate dielectric layer, and a first conductive region. At least a portion of the gate conductive region is disposed below a surface of the substrate. The gate dielectric layer surrounds a bottom wall and sidewalls of the gate conductive region. A bottom wall of the first conductive region is aligned or substantially aligned with the sidewalls of the gate conductive region.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device, and more particularly to a U-groove transistor or a buried gate transistor in which the source / drain regions are aligned or substantially aligned with the gate region. [Background Technology]

[0002] Figure 1 This is a cross-sectional view illustrating the structure of the transistor 100 used in a conventional buried wordline DRAM cell 10. For example... Figure 1 As illustrated, the gate region 101 is partially or entirely located below the initial surface 110a of the P-type doped substrate 110. The gate region 101 includes a gate conductive region, a dielectric gate cap 101b disposed above the gate conductive region, and a gate oxide layer 105 surrounding or surrounding the gate conductive region. The gate conductive region may include a metallic material 101a, such as tungsten (W) and titanium nitride (TiN) 101c, or a polycrystalline silicon material (not shown). A drain terminal 102 having an N+ doped region 102a and a source terminal 103 having an N+ doped region 103a are located on the left and right sides of the gate 101, respectively. The drain terminal 102 and the source terminal 103 may also include n-type lightly doped drain (n-LDD) regions 102b and 103b, respectively. One of the drain terminal 102 and the source terminal 103 is connected to a capacitor of a dynamic random access memory cell, and the other is connected to a bit line BL. Furthermore, the channel region of the access transistor (e.g., an NMOS transistor) 100 connected between the drain terminal 102 and the source terminal 103 surrounds the gate oxide layer 105.

[0003] Since the drain terminal 102 and source terminal 103 are formed using ion implantation technology, the N+ doped regions and n-type lightly doped drain regions 102b / 103b (especially the N+ doped regions) of the drain terminal 102 and source terminal 103 may partially overlap with the gate region 101, generating a higher electric field and thus increasing the gate-induced drain leakage (GIDL). On the other hand, ion implantation may generate multiple lattice defects in the drain terminal 102 and source terminal 103. Since these lattice defects may be difficult to completely repair through subsequent heat treatment, they may increase the source or drain resistance and further induce a higher gate-induced drain leakage current, resulting in the access transistor 100 having more severe storage node charges and a lower turn-on current (I-on).

[0004] Furthermore, the critical voltage of the access transistor 100 depends on the uniformity of the ion implantation distribution of the p-type well 106 formed in the substrate 110. However, conventional fabrication methods employ multiple ion implantation steps followed by an annealing process to form the drain terminal 102 and source terminal 103 in the p-type well 106. This may result in an uneven doping profile of the p-type well 106, inevitably increasing the threshold voltage variation and channel resistance.

[0005] Therefore, there is a need to provide an advanced transistor structure that addresses the problems faced by known technologies. [Summary of the Invention]

[0006] An embodiment of the present invention provides a transistor structure including a substrate, a gate conductive region, a gate dielectric layer, and a first conductive region. At least a portion of the gate conductive region is disposed below the surface of the substrate. The gate dielectric layer surrounds the bottom wall and sidewalls of the gate conductive region. The bottom wall of the first conductive region is aligned or substantially aligned with the sidewalls of the gate conductive region.

[0007] In some embodiments of this specification, the top wall of the first conductive region is aligned or substantially aligned with the top wall of the shallow trench isolation structure (STI) near the first conductive region, but is lower than the top wall of the gate cap located above the gate conductive region.

[0008] In some embodiments of this specification, the doping concentration between the bottom wall and the top wall of the first conductive region is adjustable.

[0009] In some embodiments of this specification, the first conductive region having an adjustable doping concentration is independent of the substrate.

[0010] In some embodiments of this specification, the substrate is a silicon substrate, and the first conductive region having an adjustable doping concentration is formed by a selective epitaxy process.

[0011] In some embodiments of this specification, the transistor structure further includes a channel layer surrounding the gate dielectric layer, wherein the channel layer is independent of the substrate.

[0012] In some embodiments of this specification, the channel layer may be a doped silicon layer.

[0013] In some embodiments of this specification, the channel layer may be a doped silicon-germanium (SiGe) layer.

[0014] In some embodiments of this specification, the substrate is a silicon substrate, and the channel layer is formed by a selective epitaxial growth process.

[0015] In some embodiments of this specification, the gate dielectric layer includes a horizontally extending portion covering the top surface of the first conductive region.

[0016] In some embodiments of this specification, the top surface of one end of the channel layer is aligned or substantially aligned with the surface of the substrate.

[0017] In some embodiments of this specification, the gate conductive region includes a tungsten plug and a titanium nitride (TiN) layer surrounding the tungsten plug.

[0018] In some embodiments of this specification, the transistor structure further includes a channel layer surrounding the gate dielectric layer, wherein the channel layer is a doped layer located in the substrate.

[0019] Another embodiment of the present invention provides a transistor structure including a substrate, a gate conductive region, a gate dielectric layer, and a first conductive region. At least a portion of the gate conductive region is disposed below the initial surface of the substrate. The gate dielectric layer surrounds the bottom wall and sidewalls of the gate conductive region. The first conductive region is adjacent to the gate conductive region and is independent of the substrate. The vertical gap or vertical overlap distance between the bottom wall of the first conductive region and the top wall of the gate conductive region is less than 5 nm.

[0020] In some embodiments of this specification, the doping concentration from the bottom wall to the top wall of the first conductive region is adjustable in the vertical direction.

[0021] In some embodiments of this specification, the substrate is a silicon substrate, and the first conductive region having an adjustable doping concentration is formed by a selective epitaxial process.

[0022] Another embodiment of the present invention provides a transistor structure including a substrate, a gate conductive region, a gate dielectric layer, a channel layer, and a first conductive region. At least a portion of the gate conductive region is disposed below the initial surface of the substrate. The gate dielectric layer surrounds the bottom and sidewalls of the gate conductive region. The channel layer surrounds the gate dielectric layer. The first conductive region is in contact with the channel layer, wherein the channel layer is a composite layer and is independent of the substrate.

[0023] In some embodiments of this specification, the composite layer includes a high-mobility sublayer and a silicon sublayer located above the high-mobility sublayer. The high-mobility sublayer may be doped silicon-germanium (Si). 1-x Ge x ) layer, silicon carbide (Si) 1-x C x ) layer, gallium arsenide (Ga) 1-x As x ) layer or indium antimony arsenide (In 1-x As x Sb) layer.

[0024] Another embodiment of the present invention provides a transistor structure including a substrate, a gate conductive region, a gate dielectric layer, a channel layer, and a first conductive region. At least a portion of the gate conductive region is disposed below the initial surface of the substrate. The gate dielectric layer surrounds the bottom and sidewalls of the gate conductive region, wherein the top wall of the first conductive region is lower than the top wall of the shallow trench isolation (STI) structure adjacent to the first conductive region, and lower than the top wall of the gate cap located above the gate conductive region. [Attached Image Description]

[0025] The technical advantages and spirit of this invention can be understood through the following description and in conjunction with the accompanying drawings. After reading the various drawings and the detailed description of the preferred embodiments shown in the drawings, those skilled in the art will gain a better understanding of the above and other aspects of this specification.

[0026] Figure 1 It is a cross-sectional view of the structure of a transistor used in a traditional embedded word line dynamic random access memory cell.

[0027] Figure 2A(1) is a top view of a portion of the structure of a semiconductor substrate for forming an NMOS transistor for a buried word line dynamic random access memory cell according to an embodiment of the present invention.

[0028] Figure 2A(2) is a structural cross-section view taken along the tangent C2A of Figure 2A(1).

[0029] Figure 2B(1) is a top view of a partial structure after multiple gate grooves are formed in a semiconductor substrate.

[0030] Figure 2B(2) is a structural cross-section drawn along the tangent C2B of Figure 2B(1).

[0031] Figure 2C(1) is a top view showing the partial structure after the channel regions are formed in the gate recess.

[0032] Figure 2C(2) is a cross-sectional view of the structure drawn along the tangent C2C of Figure 2C(1).

[0033] Figure 2D(1) is a top view of a partial structure after the gate dielectric layer is formed in the gate recess.

[0034] Figure 2D(2) is a cross-sectional view of the structure drawn along the tangent C2D of Figure 2D(1).

[0035] Figure 2E(1) is a top view showing the partial structure after the gate conductive region is formed in the gate groove.

[0036] Figure 2E(2) is a structural cross-section drawn along the tangent C2E of Figure 2E(1).

[0037] Figure 2F(1) is a partial top view showing the structure after the dielectric material is filled on the top of the gate groove.

[0038] Figure 2F(2) is a cross-sectional view of the structure drawn along the tangent C2F of Figure 2F(1).

[0039] Figure 2G(1) is a partial top view of the structure after the removal of the silicon nitride hard mask layer and the formation of a dielectric gate cover over the gate conductive region.

[0040] Figure 2G(2) is a structural cross-section drawn along the tangent C2G of Figure 2G(1).

[0041] Figure 2H(1) is a top view of a partial structure after the formation of the first, second, and third grooves in the semiconductor substrate.

[0042] Figure 2H(2) is a cross-sectional view of the structure drawn along the tangent C2H in Figure 2H(1).

[0043] Figure 2I(1) is a top view of the partial structure after the first conductive region, the second conductive region and the third conductive region are formed in the first groove, the second groove and the third groove, respectively.

[0044] Figure 2I(2) is a structural cross-section drawn along the tangent C2I of Figure 2I(1).

[0045] Figure 2J(1) is a partial structural cross-sectional view similar to Figure 2H(2) according to another embodiment of the present invention.

[0046] Figure 2J(2) is a partial structural cross-sectional view similar to Figure 2I(2) according to another embodiment of the present invention.

[0047] Figure 2K(1) is a top view of the local structure corresponding to Figure 2J(1) when the same process is applied to the dynamic random access memory array structure.

[0048] Figure 2K(2) is a top view of the local structure corresponding to Figure 2J(2) when the same process is applied to the dynamic random access memory array structure.

[0049] Figure 3A(1) is a top view of a partial structure of a semiconductor substrate for forming an NMOS transistor for a buried word line dynamic random access memory cell, according to another embodiment of the present invention.

[0050] Figure 3A(2) is a structural cross-section view taken along the tangent C3A of Figure 3A(1).

[0051] Figure 3B(1) is a top view of a partial structure after multiple gate grooves are formed in a semiconductor substrate.

[0052] Figure 3B(2) is a structural cross-section drawn along the tangent C3B of Figure 3B(1).

[0053] Figure 3C(1) is a top view showing the partial structure after the channel regions are formed in the gate recess.

[0054] Figure 3C(2) is a cross-sectional view of the structure drawn along the tangent C3C of Figure 3C(1).

[0055] Figure 3D(1) is a top view of a partial structure after the gate dielectric layer is formed in the gate recess.

[0056] Figure 3D(2) is a structural cross-section drawn along the tangent C3D of Figure 3D(1).

[0057] Figure 3E(1) is a top view showing the partial structure after the gate conductive region is formed in the gate groove.

[0058] Figure 3E(2) is a structural cross-section drawn along the tangent C3E of Figure 3E(1).

[0059] Figure 3F(1) is a partial top view illustrating the structure after the dielectric material is formed to fill the top of the gate recess.

[0060] Figure 3F(2) is a cross-sectional view of the structure drawn along the tangent C3F of Figure 3F(1).

[0061] Figure 3G(1) is a partial top view of the structure after the removal of the silicon nitride hard mask layer and the formation of a dielectric gate cover over the gate conductive region.

[0062] Figure 3G(2) is a structural cross-section drawn along the tangent C3G of Figure 3G(1).

[0063] Figure 3H(1) is a top view of a partial structure after the formation of the first, second, and third grooves in the semiconductor substrate.

[0064] Figure 3H(2) is a cross-sectional view of the structure drawn along the tangent C3H of Figure 3H(1).

[0065] Figure 3I(1) is a top view of the partial structure after the first conductive region, the second conductive region and the third conductive region are formed in the first groove, the second groove and the third groove, respectively.

[0066] Figure 3I(2) is a structural cross-section drawn along the tangent C3I of Figure 3I(1).

[0067] [Symbol Explanation]

[0068] 1: Storage Node

[0069] 2: Storage Node

[0070] 10: Embedded character line dynamic random access memory unit

[0071] 20: Embedded character line dynamic random access memory unit

[0072] 21: Transistor

[0073] 22: Transistor

[0074] 30: Embedded character line dynamic random access memory unit

[0075] 31: Transistor

[0076] 32: Transistor

[0077] 100: Transistor

[0078] 101: Gate region

[0079] 101a: Metallic Materials

[0080] 101b: Dielectric gate cover

[0081] 101c: Titanium Nitride

[0082] 102:Terminal

[0083] 102a: N+ type doped region

[0084] 102b: Lightly doped drain region

[0085] 103:Terminal

[0086] 103a: N+ type doped region

[0087] 103b: Lightly doped drain region

[0088] 105: Gate oxide layer

[0089] 106: p-type trap

[0090] 110: Substrate

[0091] 110a: Initial surface of the substrate

[0092] 201: Semiconductor substrate

[0093] 201a: Initial Surface

[0094] 202: Shallow trench isolation structure

[0095] 203: Pad oxide layer

[0096] 204: p-type trap

[0097] 206: Silicon nitride hard mask layer

[0098] 207A: Gate recess

[0099] 207As: Sidewall of the gate trench

[0100] 207Ao: Bottom wall of the gate trench

[0101] 207B: Gate Groove

[0102] 207Bs: Sidewalls of the gate trench

[0103] 207Bs: Bottom wall of the gate trench

[0104] 208A: Passage Area

[0105] 208B: Passage Area

[0106] 209: Gate dielectric layer

[0107] 210A: Gate Conductive Region

[0108] 210B: Gate Conductive Region

[0109] 211: Thin layer of titanium nitride

[0110] 212: Tungsten

[0111] 213A: First Conductive Region

[0112] 213B: Second conductive region

[0113] 213C: Third Conductive Region

[0114] 214: Gate cover material

[0115] 214A: Gate cover

[0116] 214B: Gate cover

[0117] 216A: First Groove

[0118] 216Ao: Bottom surface of the first groove

[0119] 216B: Second groove

[0120] 216Bo: Bottom surface of the second groove

[0121] 216C: Third Groove

[0122] 216Co: Bottom surface of the third groove

[0123] 217A: n-type lightly doped drain region

[0124] 217B: n-type lightly doped drain region

[0125] 217C: n-type lightly doped drain region

[0126] 218A: (N+) heavily doped region

[0127] 218B: (N+) heavily doped region

[0128] 218C: (N+) heavily doped region

[0129] 301: Semiconductor substrate

[0130] 301a: Initial surface

[0131] 302: Shallow trench isolation structure

[0132] 303: Pad oxide layer

[0133] 304: p-type trap

[0134] 306: Silicon nitride hard mask layer

[0135] 307A: Gate Groove

[0136] 307As: Sidewall of the gate trench

[0137] 307Ao: Bottom wall of the gate trench

[0138] 307B: Gate Groove

[0139] 307Bs: Sidewalls of the gate recess

[0140] 307Bs: Bottom wall of the gate trench

[0141] 308A: Passage Area

[0142] 308B: Passage Area

[0143] 309: Gate dielectric layer

[0144] 310A: Gate Conductive Region

[0145] 310B: Gate Conductive Region

[0146] 311: Thin layer of titanium nitride

[0147] 312: Tungsten

[0148] 313A: First Conductive Region

[0149] 313B: Second Conductive Region

[0150] 313C: Third Conductive Region

[0151] 314: Gate cover material

[0152] 314A: Gate cover

[0153] 314B: Gate cover

[0154] 316A: First Groove

[0155] 316Ao: Bottom surface of the first groove

[0156] 316B: Second Groove

[0157] 316Bo: Bottom surface of the second groove

[0158] 316C: Third Groove

[0159] 316Co: Bottom surface of the third groove

[0160] 317A: n-type lightly doped drain region

[0161] 317B: n-type lightly doped drain region

[0162] 317C: n-type lightly doped drain region

[0163] 318A: (N+) heavily doped region

[0164] 318B: (N+) heavily doped region

[0165] 318C: (N+) heavily doped region

[0166] BL: Bitline

[0167] C2A: Tangent

[0168] C2B: Tangent

[0169] C2C: Tangent

[0170] C2D: Tangent

[0171] C2E: Tangent

[0172] C2F: Tangent

[0173] C2G: Tangent

[0174] C2H: Tangent

[0175] C2I: Tangent

[0176] C3A: Tangent

[0177] C3B: Tangent

[0178] C3C: Tangent

[0179] C3D: Tangent

[0180] C3E: Tangent

[0181] C3F: Tangent

[0182] C3G: Tangent

[0183] C3H: Tangent

[0184] C3I: Tangent

[0185] H2: Groove depth

[0186] H3: Groove depth

Detailed Implementation Methods

[0187] The embodiments shown below provide a transistor structure that reduces gate-induced drain leakage current (GIDL), minimizes threshold voltage variation, and lowers channel resistance. The claimed invention will be described in more detail below with reference to the structures and arrangements described in the specification, using specific embodiments.

[0188] It should be noted that the preferred embodiments presented in this specification are merely for illustrating and describing the invention, and are not intended to disclose or limit the invention in a precise and exhaustive manner. Furthermore, it should be pointed out that the embodiments disclosed herein can still be implemented using other features, elements, steps, and parameters not specifically described in the following specification. Therefore, the description and drawings in this specification are merely illustrative and not intended to limit the invention. Those skilled in the art can provide various modifications and similar configurations without departing from the spirit of this specification. Additionally, the drawings are not necessarily drawn to scale, and the same elements in different embodiments may be represented by the same element reference numerals.

[0189] The following embodiments describe the formation of transistor structures for semiconductor devices. In some embodiments of the invention, NMOS transistors (but not limited to) used in dynamic random access memory cells are used as examples; in other embodiments, PMOS transistors (not shown) may have similar structures except for having doping properties or forming materials opposite to those of NMOS transistors.

[0190] Example 1

[0191] According to one embodiment of the present invention, a method for forming a transistor structure includes the following steps:

[0192] Step S21: Prepare a semiconductor substrate with an initial surface;

[0193] Step S22: Form a gate conductive region below the initial surface of the semiconductor substrate.

[0194] The steps for forming the gate conductive region include the following sub-steps S221-S225:

[0195] Sub-step S221: Form at least one gate groove in the semiconductor substrate using a patterned silicon nitride hard mask layer;

[0196] Sub-step S222: Forming a channel region in the gate trench, wherein the channel region is a doped layer in the semiconductor substrate (optional);

[0197] Sub-step S223: Form a gate dielectric layer in the gate trench;

[0198] Sub-step S224: forming a gate conductive region surrounded by a gate dielectric layer in the gate recess; and sub-step S225: forming a gate cap.

[0199] Step S23: Form a first conductive region, aligning or substantially aligning the bottom wall of the first conductive region with the top wall of the gate conductive region. The formation of the first conductive region includes sub-steps S231-S233:

[0200] Sub-step S231: Expose the initial surface of the substrate;

[0201] Sub-step S232: Etching the exposed semiconductor substrate to form a groove for forming the first conductive region; and

[0202] Sub-step S233: Form the first conductive region by a selective growth method (e.g., selective epitaxy growth (SEG) or atomic layer deposition (ALD)).

[0203] Please refer to step S21: Prepare a semiconductor substrate 201 having an initial surface 201a. Figure 2A(1) is a top view of a partial structure of the semiconductor substrate 201 for forming an NMOS transistor, as illustrated in an embodiment of the present invention. Figure 2A(2) is a cross-sectional view of the structure taken along the tangent C2A of Figure 2A(1).

[0204] In this embodiment, the semiconductor substrate 201 may include a silicon layer, such as a monocrystalline silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer. Then, as illustrated in Figures 2A(1) and 2A(2), at least one shallow trench isolation structure (STI) 202 is formed in the semiconductor substrate 201 to define the active areas for forming NMOS transistors 21 and 22; a pad oxide layer 203 is formed over the shallow trench isolation structure 202 and the initial surface 201a of the semiconductor substrate 201. The pad oxide layer 203 may include silicon oxide, silicon oxynitride, or a combination thereof. Subsequently, deep n-well implantation, p-well implantation, threshold implantation, and thermal annealing processes are used to form the doped well region profiles of the state random access memory array cells (including the p-well 204 located in the semiconductor substrate 201).

[0205] Please refer to step S22: A gate conductive region 210A is formed below the initial surface 201a of the semiconductor substrate 201. The formation step of the gate conductive region 210A includes the following sub-steps S221-S225:

[0206] Please refer to sub-step S221: pattern the silicon nitride hard mask layer 206 and remove unwanted material to form a plurality of gate recesses (e.g., gate recesses 207A and 207B) in the semiconductor substrate 201. Figure 2B(1) is a partial top view of the structure after the gate recesses 207A and 207B are formed in the semiconductor substrate. Figure 2B(2) is a cross-sectional view of the structure drawn along the tangent C2B of Figure 2B(1).

[0207] The formation of gate recesses 207A and 207B includes the following steps: First, a patterned silicon nitride hard mask layer 206 with at least one opening is formed on the pad oxide layer 203, and at least one etching process is performed using the patterned silicon nitride hard mask layer 206 to remove a portion of the pad oxide layer 203 and a portion of the semiconductor substrate 201, thereby forming gate recesses 207A and 207B in the active region.

[0208] Alternatively, a photoresist patterning (etching) process can be performed directly to remove a portion of the silicon nitride hard mask layer 206, a portion of the pad oxide layer 203, and a portion of the semiconductor substrate 201, thereby defining gate recesses 207A and 207B in the active region.

[0209] Please refer to sub-step S222 to form a channel region (e.g., channel region 208A) in a gate recess (e.g., gate recess 210A), wherein the channel region 208A is a doped layer (optional) formed in the semiconductor substrate 201. In this embodiment, the formation of channel regions 208A and 208B includes the following steps: First, as shown in FIG2C(1), FIG2C(2) is a cross-sectional view of the structure drawn along the tangent C2C of FIG2C(1). A p-type doped polysilicon plug 208P is formed to fill gate recesses 207A and 207B; then a thermal annealing process is performed to drive the p-type dopant (e.g., boron) previously doped in the p-type doped polysilicon plug 208P through the bottom walls 207Ao and 207Bo and the side walls 207As and 207Bs of the gate recesses 207A and 207B, thereby forming doped channel regions 208A and 208B in the semiconductor substrate 201.

[0210] Please refer to sub-step S223: A gate dielectric layer (also referred to as the first gate dielectric layer) 209 is formed in gate recesses 207A and 207B. Figure 2D(1) is a partial top view of the structure after the gate dielectric layer 209 is formed in gate recesses 207A and 207B. Figure 2D(2) is a cross-sectional view of the structure drawn along the tangent C2D of Figure 2D(1). In this embodiment, the formation of the gate dielectric layer 209 includes the following steps: First, the p-type doped polysilicon plugs 208P filled in the gate recesses 207A and 207B are removed by an etching process. Then, a thermal oxidation process is performed to grow a hot gate dielectric material on the bottom walls 207Ao and 207Bo and their sidewalls 207As and 207Bs of the gate recesses 207A and 207B. In this way, the gate dielectric layer 209, made of a hot gate dielectric material, can protect the p-type doped silicon channel layer from exposure to the external environment or contamination.

[0211] In other embodiments, the gate dielectric layer 209 may be a dielectric layer (e.g., including silicon dioxide or a high-k dielectric material) formed by a deposition process (e.g., low-pressure chemical vapor deposition (LPCVD)) on the bottom walls 207Ao and 207Bo and their sidewalls 207As and 207Bs of the gate recesses 207A and 207B.

[0212] Please refer to step S224: Gate conductive regions 210A and 210B, surrounded by the gate dielectric layer 209, are formed in the gate recesses (e.g., gate recesses 207A and 207B). FIG2E(1) is a partial top view of the structure after the gate conductive regions 210A and 210B are formed in the gate recesses 207A and 207B, respectively. FIG2E(2) is a cross-sectional view of the structure drawn along the tangent C2E of FIG2E(1). In this embodiment, the formation of the gate conductive regions 210A and 210B includes the following steps: First, a deposition process (e.g., low-pressure chemical vapor deposition process) is performed to form a titanium nitride (TiN) thin layer 211 above the gate dielectric layer 209; and the remaining unfilled portions of the gate recesses 207A and 207B are filled with tungsten 212. Next, an etch-back process is performed to remove a portion of the titanium nitride thin layer 211 and tungsten 212 located in the gate recesses 207A and 207B, so that the top of the remaining titanium nitride thin layer 211 and tungsten 212 is below the initial surface 201a of the semiconductor substrate 201.

[0213] Thus, the initial surface 201a located in the gate recesses 207A and 207B, below the semiconductor substrate 201, can be formed. The remaining portions of the titanium nitride layer 211 and tungsten 212, which are surrounded by the gate dielectric layer 209, together form the gate conductive regions 210A and 210B.

[0214] Please refer to sub-step S225: Forming the gate cap. Please refer to step S225. Gate cap material 214 (e.g., silicon nitride) is filled into the gate recesses 207A and 207B respectively to protect the gate conductive regions 210A and 210B. In this embodiment, the tops of the gate recesses 207A and 207B can be filled by depositing silicon nitride, and the deposited gate cap material 214 is planarized using (e.g., chemical mechanical polishing (CMP) technology) with silicon nitride hard mask layer 206 as a stop layer to form the gate caps 214A and 214B. FIG2F(1) is a partial top view of the structure after the gate cap material 214 is formed to fill the tops of the gate recesses 207A and 207B. FIG2F(2) is a cross-sectional view of the structure drawn along the tangent C2F of FIG2F(1).

[0215] Please refer to step S23: Forming a conductive region, aligning or substantially aligning the bottom wall of the conductive region with the top wall of the gate conductive region. The steps for forming the conductive region include sub-steps S231-S233:

[0216] Please refer to sub-step S231: expose the initial surface 201a of the substrate 201; etch or remove the silicon nitride hard mask layer 206, a portion of the gate cover material 214 and the pad oxide layer 203 to expose the shallow trench isolation structure 202 and the active region (or the initial surface 201a of the semiconductor substrate 201), leaving the dielectric gate cover 214A and 214B still located on top of the gate conductive regions 210A and 210B to protect the gate conductive regions 210A and 210B from being exposed. Figure 2G(1) is a partial top view of the structure after the dielectric gate cover is formed above the gate conductive region and the initial surface 201a of the substrate 201 is exposed after the removal of the silicon nitride hard mask layer 206. Figure 2G(2) is a cross-sectional view of the structure drawn along the tangent C2G of Figure 2G(1).

[0217] Please refer to sub-step S232: Etch the exposed semiconductor substrate 201 to form a plurality of grooves (including the first groove 216A) for forming conductive regions. Figure 2H(1) is a partial top view of the structure after the first groove 216A, the second groove 216B and the third groove 216C are formed in the semiconductor substrate 201. Figure 2H(2) is a cross-sectional view of the structure drawn along the tangent C2H of Figure 2H(1).

[0218] In this embodiment, a combination of a shallow trench isolation structure 202, a gate dielectric layer 209, and dielectric gate caps 214A and 214B is used as an etching mask to perform the etching process, thereby removing a portion of the semiconductor substrate 201 exposed in the active region (including the top of the channel regions 208A and 208B), thus forming a first groove 216A, a second groove 216B, and a third groove 216C. The first groove 216A and the second groove 216B are formed on opposite sides of the dielectric gate cap 214A. The second groove 216B and the third groove 216C are formed on opposite sides of the dielectric gate cap 214B.

[0219] It is worth noting that the etching process forming the first groove 216A, the second groove 216B, and the third groove 216C should stop at an appropriate groove depth H2 so that the bottom surfaces 216Ao and 216Bo of the first groove 216A and the second groove 216B are aligned or substantially aligned with the top wall 210At of the gate conductive region 210A, and the bottom surfaces 216Bo and 216Co of the second groove 216B and the third groove 216C are aligned or substantially aligned with the top wall 210Bt of the gate conductive region 210B.

[0220] For example, an appropriate trench depth H2 can be controlled by considering the different etch rates of the silicon semiconductor substrate 201, the shallow trench isolation structure 202 made of silicon oxide, and the dielectric gate caps 214A and 214B made of silicon nitride. In some embodiments of the present invention, an appropriate trench depth H2 can be approximately 50 nanometers (nm); and the bottom surfaces 216Ao, 216Bo, and 216Co of the first trench 216A, the second trench 216B, and the third trench 216C can be aligned with the bottom edges of the dielectric gate caps 214A and 214B. Furthermore, as shown in FIG2H(2), the top surface of one end of the channel layer 208A or 208B is aligned or substantially aligned with the surface of the substrate 201 (e.g., the bottom surfaces 216Ao, 216Bo, and 216Co of the first trench 216A, the second trench 216B, and the third trench 216C).

[0221] Please refer to sub-step S233: The conductive region is formed by a selective growth method (e.g., selective epitaxial growth or atomic layer deposition). Figure 2I(1) is a partial top view of the structure after the first conductive region 213A, the second conductive region 213B, and the third conductive region 213C are formed in the first groove 216A, the second groove 216B, and the third groove 216C, respectively. Figure 2I(2) is a cross-sectional view of the structure drawn along the tangent C2I of Figure 2I(1).

[0222] The formation of the first conductive region 213A, the second conductive region 213B, and the third conductive region 213C includes the following steps: First, a silicon selective growth process (e.g., selective epitaxial growth process or atomic layer deposition process) is performed to form n-type lightly doped drain regions 217A, 217B, and 217C, respectively, on the portions of the semiconductor substrate 201 exposed via the first groove 216A, the second groove 216B, and the third groove 216C. Then, another silicon selective growth process (e.g., selective epitaxial growth process or atomic layer deposition process) is performed to form (N+) heavily doped regions 218A, 218B, and 218C, respectively, on the n-type lightly doped drain regions 217A, 217B, and 217C. Subsequently, an optional Rapid Thermal Annealing (RTA) process is performed to improve the activity of the doping concentration of the lightly doped n-type drain regions 217A, 217B, and 217C and the (N+) heavily doped regions 218A, 218B, and 218C. In one embodiment, each of the (N+) heavily doped regions 218A, 218B, and 218C has a top surface aligned or substantially aligned with the top of the shallow trench isolation structure 202. As shown in FIG2I(2), the top wall of the first conductive region 213A is aligned or substantially aligned with the top wall of the shallow trench isolation structure 202 adjacent to the first conductive region 213A, but lower than the top wall of the gate cap 214A located above the gate conductive region 210A.

[0223] In another embodiment, through an etching process, the vertical gap distance (when the bottom wall of the first conductive region 213A is higher than the top wall of the gate conductive region 210A) or the vertical overlap distance (when the bottom wall of the first conductive region 213A is lower than the top wall of the gate conductive region 210A) between the bottom wall of the first conductive region 213A and the top wall of the gate conductive region 210A can be controlled within a predetermined range, for example, less than 3 nanometers to 5 nanometers.

[0224] The (N+) heavily doped region 218A and the n-type lightly doped drain region 217A together form the first conductive region 213A; the (N+) heavily doped region 218B and the n-type lightly doped drain region 217B together form the second conductive region 213B; and the (N+) heavily doped region 218C and the n-type lightly doped drain region 217C together form the third conductive region 213C. By using silicon selective growth technology to form the first conductive region 213A, the doping concentration distribution from the bottom wall to the top wall of the first conductive region 213A can be adjusted. Similarly, the doping concentration distribution of the second conductive region 213B and the third conductive region 213C can also be adjusted using this method.

[0225] The first conductive region 213A, the second conductive region 213B, the channel region 208A, the gate conductive region 210A, and the gate dielectric layer 209 together constitute NMOS transistor 21. The third conductive region 213C, the second conductive region 213B, the channel region 208B, the gate conductive region 210B, and the gate dielectric layer 209 together constitute NMOS transistor 22. The first conductive region 213A and the second conductive region 213B serve as the source and drain of NMOS transistor 21, respectively. The third conductive region 213C and the second conductive region 213B can serve as the source and drain of NMOS transistor 22, respectively.

[0226] After performing the first back-end process steps, the embedded word line dynamic random access memory cell 20 can be fabricated. The first conductive region 213A, the second conductive region 213B and the third conductive region 213C can be connected to the storage node 1, the bit line BL and the storage node 2 of the embedded word line dynamic random access memory cell 20, respectively (as shown in Figure 2I(2)).

[0227] In summary, by evaluating different etch selectivity ratios for silicon, silicon oxide, and silicon nitride (as illustrated in Figures 2H(1) and 2H(2)), the etching process for forming silicon trenches (e.g., first trench 216A, second trench 216B, and third trench 216C) can be more accurately controlled. This allows for the alignment or approximate alignment of the bottom of the source / drain with the bottom of the dielectric gate cap (or the top wall of the gate conductive region) during the formation of the source or drain of NMOS transistors 21 and 22 by controlling the etching depth. This reduces the gate-induced drain leakage current caused by gate-source / drain overlap.

[0228] Furthermore, since the (N+) heavily doped region of the source or drain and the n-type lightly doped drain region of the newly designed source or drain are formed by silicon selective epitaxial growth technology (as shown in Figures 2I(1) and 2I(2)), lattice defects can be avoided during the ion implantation process for forming the source or drain. Compared with conventional designs, the new design of this invention has higher doping concentration activity and lower resistance on the storage node side because it uses silicon selective growth technology to form the N+ doped region. Therefore, the NMOS transistors 21 and 22 designed in this invention have higher on-current than conventional cell access transistors. The channels of NMOS transistors 21 and 22 are formed using p-type doped polysilicon heating drive technology (as shown in Figures 2C(1) and 2C(2)), which can improve the uniformity of channel doping and reduce the critical voltage variation of NMOS transistors 21 and 22.

[0229] Furthermore, during the formation of the first conductive region 213A, the second conductive region 213B, and the third conductive region 213C, a rapid thermal annealing (RTA) process can be selected to drive in the dopants, thereby causing the lightly doped n-type drain regions 217A, 217B, and 217C to overlap with the gate, further reducing the source or drain resistance of the NMOS transistors 21 and 22.

[0230] To avoid short circuits between the storage nodes (first conductive region 213A or third conductive region 213C) and the bit line BL (second conductive region 213B), in another embodiment illustrated in FIG2J(1) (similar to the structure illustrated in FIG2H(2)), a suitable etchant is used to allow the top surface of the remaining shallow trench isolation structure 202 to be slightly lower than the top surfaces of the remaining dielectric gate caps 214A and 214B. FIG2K(1) is a top view of the structure corresponding to FIG2J(1) when the same process is applied to the random access memory array structure. Several structures in FIG2J(1) can be repeated in the random access memory array structure of FIG2K(1).

[0231] Then refer to Figure 2J(2), whose structure is similar to that of Figure 2I(2). Based on the silicon exposed in the active region, selective growth is performed in the first trench 216A, the second trench 216B, and the third trench 216C to form the first conductive region 213A, the second conductive region 213B, and the third conductive region 213C. The top surfaces of the first conductive region 213A, the second conductive region 213B, and the third conductive region 213C are lower than the top surfaces of the remaining shallow trench isolation structure 202 and the remaining dielectric gate caps 214A and 214B, so that storage node 1 and storage node 2 will not be short-circuited with the bit line BL. Figure 2K(2) is a top view corresponding to Figure 2J(2) when the same process is applied to the random access memory array structure. Several structures in Figure 2J(2) can be repeated in the random access memory array structure of Figure 2K(1). As shown in Figure 2J(2), the top wall of the first conductive region 213A is lower than the top wall of the shallow trench isolation structure 202 adjacent to the first conductive region 213A, and is also lower than the top wall of the gate cover 214A located above the gate conductive region.

[0232] Example 2

[0233] According to another embodiment of the present invention, a method for forming a transistor structure includes the following steps:

[0234] Step S31: Prepare a semiconductor substrate with an initial surface;

[0235] Step S32: Form a gate conductive region below the initial surface of the semiconductor substrate.

[0236] The steps for forming the gate conductive region include the following sub-steps S321-S325:

[0237] Sub-step S321: Form at least one gate groove in the semiconductor substrate using a patterned silicon nitride hard mask layer;

[0238] Sub-step S322: Forming a channel region in the gate recess, wherein the channel layer in the channel region is independent of the substrate (optional);

[0239] Sub-step S323: Form a gate dielectric layer in the gate recess;

[0240] Sub-step S324: Forming a gate conductive region surrounded by a gate dielectric layer in the gate recess; and sub-step S325: Forming a gate cap.

[0241] Step S33: Form a first conductive region, aligning or substantially aligning the bottom wall of the first conductive region with the top wall of the gate conductive region. The formation of the first conductive region includes sub-steps S331-S333:

[0242] Step S331: Expose the initial surface of the substrate;

[0243] Step S332: Etching the exposed semiconductor substrate to form a groove for forming the first conductive region; and

[0244] Step S333: Form a first conductive region by means of a selective growth method (e.g., selective epitaxial growth) or atomic layer deposition.

[0245] Please refer to step S31: Prepare a semiconductor substrate 301 having an initial surface 301a. Figure 3A(1) is a top view of a partial structure of the semiconductor substrate 301 for forming an NMOS transistor, as illustrated in an embodiment of the present invention. Figure 3A(2) is a cross-sectional view of the structure taken along tangent C3A of Figure 3A(1). The semiconductor substrate 301 may include a silicon layer, such as a monocrystalline silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer. At least one shallow trench isolation structure (STI) 302 is formed in the semiconductor substrate 301 to define the active regions for forming NMOS transistors 31 and 32; a pad oxide layer 303 is formed over the shallow trench isolation structure 302 and the initial surface 301a of the semiconductor substrate 301. The pad oxide layer 303 may include silicon oxide, silicon oxynitride, or a combination thereof. Subsequently, deep n-type well ion implantation process, p-type well ion implantation process, critical ion implantation process and thermal annealing process are used to form the doped well region profile of the state random access memory array cell (including p-type well 304 located in semiconductor substrate 301).

[0246] Please refer to step S32: A gate conductive region 310A is formed below the initial surface 301a of the semiconductor substrate 301. The formation step of the gate conductive region 310A includes the following sub-steps S321-S325:

[0247] Please refer to sub-step S321: pattern the silicon nitride hard mask layer 306 and remove unwanted material to form a plurality of gate recesses (e.g., gate recesses 307A and 307B) in the semiconductor substrate 301. Figure 3B(1) is a partial top view of the structure after the gate recesses 307A and 307B are formed in the semiconductor substrate. Figure 3B(2) is a cross-sectional view of the structure drawn along the tangent C3B of Figure 3B(1).

[0248] The formation of gate recesses 307A and 307B includes the following steps: First, a patterned silicon nitride hard mask layer 306 with at least one opening is formed on the pad oxide layer 303, and at least one etching process is performed using the patterned silicon nitride hard mask layer 306 to remove a portion of the pad oxide layer 303 and a portion of the semiconductor substrate 301, thereby forming gate recesses 307A and 307B in the active region.

[0249] Alternatively, a photoresist patterning (etching) process can be performed directly to remove a portion of the silicon nitride hard mask layer 306, a portion of the pad oxide layer 303, and a portion of the semiconductor substrate 301, thereby defining gate recesses 307A and 307B in the active region.

[0250] Referring to sub-step S322, a channel region (e.g., channel region 308A) is formed in a gate recess (e.g., gate recess 310A), wherein the channel region 311A ​​is independent of the semiconductor substrate 301 (optional). Figure 3C(1) is a partial top view showing the structure after the channel regions 308A and 308B are formed in gate recesses 307A and 307B, respectively. Figure 3C(2) is a cross-sectional view of the structure drawn along the tangent C3C of Figure 3C(1).

[0251] In this embodiment, the formation of channel regions 308A and 308B includes performing a selective growth process (e.g., selective epitaxial growth or atomic layer deposition) to form p-type doped polycrystalline silicon layers and silicon-germanium layers on the bottom walls 307Ao and 307Bo and the sidewalls 307As and 307Bs of the gate recesses 307A and 307B, respectively. Each of channel regions 308A and 308B can be a deposited layer that extends independently from the surface of the semiconductor substrate 301 towards the center of the gate recess 307A or 307B. Furthermore, this selectively grown channel layer can improve the uniformity of channel doping. Forming a p-type doped silicon-germanium channel layer through selective epitaxial growth, or a selectively grown channel layer formed from other high-mobility materials, helps to reduce channel resistance and increase conduction current. In another embodiment, the channel region may include a composite selective growth layer, which may include a high-mobility sublayer (e.g., a silicon-germanium layer, a silicon carbide layer, a gallium arsenide layer, or an indium antimony arsenide layer) formed on the bottom walls 307Ao and 307Bo and the sidewalls 307As and 307Bs of the gate recesses 307A and 307Bs, and a silicon proton layer located on the high-mobility sublayer. The selectively grown silicon proton layer is a capping layer between the high-mobility sublayer and the gate oxide to reduce interface traps.

[0252] Please refer to sub-step S323: A gate dielectric layer 309 is formed in gate recesses 307A and 307B. Figure 3D(1) is a partial top view showing the structure after the gate dielectric layer 309 is formed in gate recesses 307A and 307B. Figure 3D(2) is a cross-sectional view of the structure drawn along the tangent C3D of Figure 3D(1). In this embodiment, the formation of the gate dielectric layer 309 includes the following steps: First, a thermal oxidation process is performed to grow a hot gate dielectric material on the channel regions 308A and 308B in the gate recesses 307A and 307B. Thereby, the gate dielectric layer 309 made of the hot gate dielectric material can protect the p-type doped silicon or silicon-germanium channel layer from exposure to the external environment or contamination.

[0253] In other embodiments, the gate dielectric layer 309 may be a dielectric layer (e.g., including silicon dioxide or a high dielectric constant dielectric material) formed on the channel regions 308A and 308B by a deposition process (e.g., low-pressure chemical vapor deposition (LPCVD)).

[0254] It is worth noting that the gate dielectric layer 309 may include a horizontally extending portion 309a covering the top surface 308t of the channel regions 308A and 308B.

[0255] Please refer to step S324: Gate conductive regions 310A and 310B, surrounded by the gate dielectric layer 309, are formed in the gate recesses (e.g., gate recesses 307A and 307B). FIG3E(1) is a partial top view of the structure after the gate conductive regions 310A and 310B are formed in the gate recesses 307A and 307B, respectively. FIG3E(2) is a cross-sectional view of the structure drawn along the tangent C3E of FIG3E(1). In this embodiment, the formation of the gate conductive regions 310A and 310B includes the following steps: First, a deposition process (e.g., low-pressure chemical vapor deposition process) is performed to form a titanium nitride thin layer 311 above the gate dielectric layer 309; and the remaining unfilled portions of the gate recesses 307A and 307B are filled with tungsten 312. Next, an etch-back process is performed to remove a portion of the titanium nitride thin layer 311 and tungsten 312 located in the gate recesses 307A and 307B, so that the top of the remaining titanium nitride thin layer 311 and tungsten 312 is below the initial surface 301a of the semiconductor substrate 301.

[0256] Thus, the initial surface 301a located in the gate recesses 307A and 307B, below the semiconductor substrate 301, can be formed. The remaining portions of the titanium nitride thin layer 311 and tungsten 312, which are surrounded by the gate dielectric layer 309, together form the gate conductive regions 310A and 310B.

[0257] Please refer to sub-step S325: Forming the gate cap. Please refer to step S325. Gate cap material 314 (e.g., silicon nitride) is filled into the gate recesses 307A and 307B respectively to protect the gate conductive regions 310A and 310B. In this embodiment, the tops of the gate recesses 307A and 307B can be filled by depositing silicon nitride, and a silicon nitride hard mask layer 306 is used as a stop layer. The deposited gate cap material 314 is planarized using (e.g., chemical mechanical polishing) to form the gate caps 314A and 314B. FIG3F(1) is a partial top view of the structure after the gate cap material 314 is formed to fill the tops of the gate recesses 307A and 307B. FIG3F(2) is a cross-sectional view of the structure drawn along the tangent C3F of FIG3F(1).

[0258] Please refer to step S33: Forming a conductive region, aligning or substantially aligning the bottom wall of the conductive region with the top wall of the gate conductive region. The steps for forming the conductive region include sub-steps S331-S333:

[0259] Please refer to sub-step S331: expose the initial surface 301a of the substrate 301; etch or remove the silicon nitride hard mask layer 306, a portion of the gate cover material 314 and the pad oxide layer 303 to expose the shallow trench isolation structure 302 and the active region (or the initial surface 301a of the semiconductor substrate 301), leaving the dielectric gate cover 314A and 314B still located on top of the gate conductive regions 310A and 310B to protect the gate conductive regions 310A and 310B from exposure. Figure 3G(1) is a partial top view of the structure after the removal of the silicon nitride hard mask layer 306, the formation of the dielectric gate cover above the gate conductive region, and the exposure of the initial surface 301a of the substrate 301. Figure 3G(2) is a cross-sectional view of the structure drawn along the tangent C3G of Figure 3G(1).

[0260] Please refer to sub-step S332: Etch the exposed semiconductor substrate 301 to form a plurality of grooves (including the first groove 316A) for forming conductive regions. Figure 3H(1) is a partial top view of the structure after the first groove 316A, the second groove 316B and the third groove 316C are formed in the semiconductor substrate 301. Figure 3H(2) is a cross-sectional view of the structure drawn along the tangent C3H of Figure 3H(1).

[0261] In this embodiment, a combination of a shallow trench isolation structure 302, a gate dielectric layer 309, and dielectric gate caps 314A and 314B is used as an etching mask to perform the etching process, thereby removing a portion of the semiconductor substrate 301 exposed in the active region (including the top of the channel regions 308A and 308B), thus forming a first groove 316A, a second groove 316B, and a third groove 316C. The first groove 316A and the second groove 316B are formed on opposite sides of the dielectric gate cap 314A. The second groove 316B and the third groove 316C are formed on opposite sides of the dielectric gate cap 314B.

[0262] It is worth noting that the etching process forming the first groove 316A, the second groove 316B, and the third groove 316C should stop at an appropriate groove depth H3 so that the bottom surfaces 316Ao and 316Bo of the first groove 316A and the second groove 316B are aligned or substantially aligned with the top wall 310At of the gate conductive region 310A, and the bottom surfaces 316Bo and 316Co of the second groove 316B and the third groove 316C are aligned or substantially aligned with the top wall 310Bt of the gate conductive region 310B.

[0263] For example, an appropriate trench depth H3 can be controlled by considering the different etch rates of the silicon semiconductor substrate 301, the shallow trench isolation structure 302 made of silicon oxide, and the dielectric gate caps 314A and 314B made of silicon nitride. In some embodiments of the present invention, an appropriate trench depth H3 can be approximately 50 nanometers; and the bottom surfaces 316Ao, 316Bo, and 316Co of the first trench 316A, the second trench 316B, and the third trench 316C can be aligned with the bottom edges of the dielectric gate caps 314A and 314B. Furthermore, as shown in FIG3H(2), the top surface of one end of the channel layer 308A or 308B is aligned or substantially aligned with the surface of the substrate 301 (e.g., the bottom surfaces 316Ao, 316Bo, and 316Co of the first trench 316A, the second trench 316B, and the third trench 316C).

[0264] Please refer to sub-step S333: The conductive region is formed by a selective growth method (e.g., selective epitaxial growth or atomic layer deposition). Figure 3I(1) is a partial top view of the structure after the first conductive region 313A, the second conductive region 313B, and the third conductive region 313C are formed in the first groove 316A, the second groove 316B, and the third groove 316C, respectively. Figure 3I(2) is a cross-sectional view of the structure drawn along the tangent C3I of Figure 3I(1).

[0265] The formation of the first conductive region 313A, the second conductive region 313B, and the third conductive region 313C includes the following steps: First, a silicon selective growth process (e.g., selective epitaxial growth process or atomic layer deposition process) is performed to form n-type lightly doped drain regions 317A, 317B, and 317C, respectively, on the portions of the semiconductor substrate 301 exposed via the first groove 316A, the second groove 316B, and the third groove 316C. Then, another silicon selective growth process (e.g., selective epitaxial growth process or atomic layer deposition process) is performed to form (N+) heavily doped regions 318A, 318B, and 318C, respectively, on the n-type lightly doped drain regions 317A, 317B, and 317C. Subsequently, an optional rapid thermal annealing process is performed to improve the activity of the doping concentration of the n-type lightly doped drain regions 317A, 317B, and 317C and the (N+) heavily doped regions 318A, 318B, and 318C. In one embodiment, each of the (N+) heavily doped regions 318A, 318B, and 318C has a top surface that is aligned or substantially aligned with the top of the shallow trench isolation structure 302. As shown in FIG3I(2), the top wall of the first conductive region 313A is aligned or substantially aligned with the top wall of the shallow trench isolation structure 302 adjacent to the first conductive region 313A.

[0266] The first conductive region 313A is formed by the (N+) heavily doped region 318A and the n-type lightly doped drain region 317A; the second conductive region 313B is formed by the (N+) heavily doped region 318B and the n-type lightly doped drain region 317B; and the third conductive region 313C is formed by the (N+) heavily doped region 318C and the n-type lightly doped drain region 317C. By using silicon selective growth technology to form the first conductive region 313A, the doping concentration distribution from the bottom to the top wall of the first conductive region 313A can be adjusted. Similarly, the doping concentration distribution of the second conductive region 313B and the third conductive region 313C can also be adjusted using this method.

[0267] The first conductive region 313A, the second conductive region 313B, the channel region 308A, the gate conductive region 310A, and the gate dielectric layer 309 together constitute the NMOS transistor 31. The third conductive region 313C, the second conductive region 313B, the channel region 308B, the gate conductive region 310B, and the gate dielectric layer 309 together constitute the NMOS transistor 32. The first conductive region 313A and the second conductive region 313B serve as the source and drain of the NMOS transistor 31, respectively. The third conductive region 313C and the second conductive region 313B can serve as the source and drain of the NMOS transistor 32, respectively.

[0268] After performing the first back-end process steps, the embedded word line dynamic random access memory cell 30 can be fabricated. Among them, the first conductive region 313A, the second conductive region 313B and the third conductive region 313C can be connected to the storage node 1, the bit line BL and the storage node 2 of the embedded word line dynamic random access memory cell 30, respectively (as shown in Figure 3I(2)).

[0269] In summary, by evaluating different etch selectivity ratios for silicon, silicon oxide, and silicon nitride (as illustrated in Figures 3H(1) and 3H(2)), the etching process of silicon trenches (e.g., the first trench 316A, the second trench 316B, and the third trench 316C) can be more accurately controlled. During the formation of the source or drain of NMOS transistors 31 and 32, the bottom of the source / drain can be aligned or approximately aligned with the bottom of the dielectric gate cover (or the top wall of the gate conductive region) by controlling the etching depth, thereby reducing the gate-induced drain leakage current caused by gate-source / drain overlap.

[0270] Furthermore, since the (N+) heavily doped region of the newly designed source or drain and the n-type lightly doped drain region are formed by silicon selective epitaxial growth technology (as shown in Figures 3I(1) and 3I(2)), lattice defects can be avoided during the ion implantation process for forming the source or drain. Compared with conventional designs, the new design of this invention has higher doping concentration activity and lower resistance on the storage node side because it uses silicon selective growth technology to form the N+ doped region. Therefore, the NMOS transistors 31 and 32 designed in this invention have higher on-current than conventional cell access transistors. The channels of NMOS transistors 31 and 32 are formed using p-type doped polysilicon heating drive technology (as shown in Figures 3C(1) and 3C(2)), which can improve the uniformity of channel doping and reduce the critical voltage variation of NMOS transistors 31 and 32.

[0271] As shown in Figure 3I(2), the gate dielectric layer 309 (thermal oxide layer) includes a horizontally extended portion 309a covering the top surface of the drain / source region, which can separate the drain / source region from the dielectric gate cover 314A and 314B made of silicon nitride, further reducing the generation of gate-induced drain leakage problems.

[0272] In addition, during the formation of the first conductive region 313A, the second conductive region 213B and the third conductive region 313C, a rapid thermal annealing process can be selected to drive in the dopants, so that the lightly doped n-type drain regions 317A, 317B and 317C overlap with the gate, further reducing the source or drain resistance of NMOS transistors 31 and 32.

[0273] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A transistor structure, characterized in that, include: One substrate; A gate conductive region, at least a portion of which is disposed below a surface of the substrate; A gate dielectric layer, surrounding a bottom wall and a side wall of the gate conductive region; A channel layer surrounds the gate dielectric layer, wherein the channel layer is independent of the substrate; as well as A first conductive region having a bottom wall aligned or substantially aligned with a top wall of the gate conductive region.

2. The transistor structure as described in claim 1, characterized in that, A top wall of the first conductive region is aligned or substantially aligned with a top wall of a shallow trench isolation structure (STI) adjacent to the first conductive region, but is lower than a top wall of a gate cap located above the gate conductive region.

3. The transistor structure as described in claim 1, characterized in that, The doping concentration between the bottom wall and the top wall of the first conductive region is adjustable.

4. The transistor structure as described in claim 3, characterized in that, The first conductive region, which has an adjustable doping concentration, is independent of the substrate.

5. The transistor structure as described in claim 4, characterized in that, The substrate is a silicon substrate, and the first conductive region with adjustable doping concentration is formed by a selective epitaxy process.

6. The transistor structure as described in claim 1, characterized in that, The channel layer is a doped silicon layer.

7. The transistor structure as described in claim 1, characterized in that, The channel layer is a doped silicon-germanium (Si) layer. 1-x Ge x )layer.

8. The transistor structure as described in claim 1, characterized in that, The substrate is a silicon substrate, and the channel layer is formed by a selective epitaxial process.

9. The transistor structure as claimed in claim 1, characterized in that, The gate dielectric layer includes a horizontal extension covering a top surface of the first conductive region.

10. The transistor structure as described in claim 9, characterized in that, One top surface of the channel layer is aligned or substantially aligned with the surface of the substrate.

11. The transistor structure as described in claim 9, characterized in that, The gate conductive region includes a tungsten plug and a titanium nitride (TiN) layer surrounding the tungsten plug.

12. The transistor structure as claimed in claim 1, characterized in that, The channel layer is an epitaxial doped layer.

13. A transistor structure, characterized in that, include: One substrate; A gate conductive region, at least a portion of which is disposed below a surface of the substrate; A gate dielectric layer, surrounding a bottom wall and a side wall of the gate conductive region; A channel layer surrounds the gate dielectric layer, wherein the channel layer is independent of the substrate; as well as A first conductive region, adjacent to the gate conductive region and independent of the substrate; Wherein, the vertical gap or vertical overlap distance between a bottom wall of the first conductive region and a top wall of the gate conductive region is less than 5 nanometers (nm).

14. The transistor structure as described in claim 13, characterized in that, The doping concentration between the bottom wall and the top wall of the first conductive region is adjustable.

15. The transistor structure as described in claim 14, characterized in that, The substrate is a silicon substrate, and the first conductive region with adjustable doping concentration is formed by a selective epitaxial process.

16. A transistor structure, characterized in that, include: One substrate; A gate conductive region, at least a portion of which is disposed below a surface of the substrate; A gate dielectric layer, surrounding a bottom wall and a side wall of the gate conductive region; A channel layer surrounds the gate dielectric layer; as well as A first conductive region is in contact with the channel layer; The channel layer is a composite layer and is independent of the substrate.

17. The transistor structure as claimed in claim 16, characterized in that, The composite layer includes a high mobility sublayer and a silicon proton layer located above the high mobility sublayer.

18. The transistor structure as claimed in claim 17, characterized in that, This high-mobility sublayer is a doped silicon-germanium layer or a silicon carbide (Si) layer. 1-x C x ) layer, gallium arsenide (Ga) 1-x As x ) layer or indium antimony arsenide (In 1-x As x Sb) layer.

19. A transistor structure, characterized in that, include: One substrate; A gate conductive region, at least a portion of which is disposed below a surface of the substrate; A gate dielectric layer, surrounding a bottom wall and a side wall of the gate conductive region; A channel layer surrounds the gate dielectric layer, wherein the channel layer is independent of the substrate; as well as First conductive region; In this configuration, a top wall of the first conductive region is aligned or substantially aligned with a top wall of a shallow trench isolation structure adjacent to the first conductive region, but is lower than a top wall of a gate cap located above the gate conductive region.

20. The transistor structure as claimed in claim 19, characterized in that, A bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

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