Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, including: a substrate, the substrate having a plurality of channel layers thereon, the channel layers extending along a first direction; an inner sidewall between two ends of adjacent channel layers, a side of the inner sidewall being coplanar with an end surface of the channel layers; a gate trench between adjacent channel layers; a gate structure on the substrate and in the gate trench, the gate structure surrounding the plurality of channel layers along a second direction, the first direction being perpendicular to the second direction; a first sidewall and a second sidewall on a side wall of the gate structure, the first sidewall being on the second sidewall; a source / drain opening on two sides of the gate structure, the source / drain opening exposing the inner sidewall; a source / drain doped layer in the source / drain opening. A bottom dummy gate material layer covers a side wall of a fin structure. The generation of byproducts after forming the source / drain opening is reduced, the source / drain doped layer has a good growth environment, the morphology of the source / drain doped layer is improved, and thus the performance of the finally formed semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] A FinFET is an emerging multi-gate device that typically includes fins protruding from the surface of a semiconductor substrate, a gate structure covering part of the top surface and sidewalls of the fins, and source / drain doped regions located in the fins on both sides of the gate structure. Compared to planar metal-oxide-semiconductor field-effect transistors, FinFETs have stronger short-channel rejection and higher operating current.

[0003] With the further development of semiconductor technology, the size of integrated circuit devices is getting smaller and smaller, and the manufacturing process of traditional fin field-effect transistors is also being challenged.

[0004] Therefore, the performance of fin field-effect transistors in the existing technology needs to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which effectively improves the performance of the final semiconductor structure.

[0006] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate having a plurality of channel layers stacked along the normal direction of the substrate surface, the channel layers extending along a first direction; an inner sidewall located between the two ends of adjacent channel layers, the side surface of the inner sidewall being perpendicular to the end face of the channel layer; a gate trench located between adjacent channel layers; a gate structure located on the substrate and within the gate trench, the gate structure surrounding the plurality of channel layers along a second direction, the first direction being perpendicular to the second direction; a first sidewall and a second sidewall located on the sidewall of the gate structure, the first sidewall being located on the second sidewall; source / drain openings located on both sides of the gate structure, the source / drain openings exposing the inner sidewalls, the bottom surface of the source / drain openings being lower than the top surface of the substrate; and a source / drain doped layer located within the source / drain openings.

[0007] Optionally, the material of the inner sidewall is the same as the material of the second sidewall.

[0008] Optionally, the material of the inner sidewall includes silicon nitride; the material of the second sidewall includes silicon nitride.

[0009] Optionally, it may also include: an isolation layer located on the substrate, wherein the top surface of the isolation layer is not higher than the top surface of the channel layer located at the bottom layer.

[0010] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate having a plurality of initial channel layers and a plurality of initial sacrificial layers, wherein the plurality of initial channel layers and the plurality of initial sacrificial layers are stacked at intervals along the normal direction of the substrate surface, and the plurality of initial channel layers and the plurality of initial sacrificial layers extend along a first direction; forming a dummy gate material layer on the substrate, the dummy gate material layer covering the sidewalls and top surface of the plurality of initial channel layers and the plurality of initial sacrificial layers; and patterning the dummy gate material layer to form a dummy gate structure, the dummy gate structure including a bottom dummy gate material layer and a top dummy gate structure located on the bottom dummy gate material layer, the bottom dummy gate material layer covering the plurality of initial channel layers and the plurality of initial sacrificial layers. The initial sacrificial layer has sidewalls that expose the top surface of the initial channel layer at the top layer. The top pseudo-gate structure covers a portion of the top surface of the initial channel layer at the top layer along a second direction, the first direction being perpendicular to the second direction. A first sidewall is formed on the sidewall of the top pseudo-gate structure. Using the top pseudo-gate structure and the first sidewall as a mask, several initial channel layers, several initial sacrificial layers, and the bottom pseudo-gate material layer are etched to form source / drain openings, several channel layers, several sacrificial layers, and the initial bottom pseudo-gate structure. A portion of the sacrificial layer exposed by the sidewalls of the source / drain openings is etched to form an isolation groove between adjacent channel layers. An inner sidewall is formed within the isolation groove. A source / drain doped layer is formed within the source / drain openings.

[0011] Optionally, the method of patterning the pseudo-gate material layer to form a pseudo-gate structure includes: forming a patterned layer on the pseudo-gate material layer, the patterned layer exposing a portion of the top surface of the pseudo-gate material layer; etching the pseudo-gate material layer using the patterned layer as a mask until the top surface of the initial channel layer located at the top layer is exposed, thereby forming the pseudo-gate structure.

[0012] Optionally, the pseudo-gate structure includes a pseudo-gate layer.

[0013] Optionally, the material of the sacrificial layer is different from the material of the channel layer, and the material of the sacrificial layer is the same as the material of the pseudo gate layer.

[0014] Optionally, the materials of the sacrificial layer and the pseudo-gate layer include silicon and germanium; the material of the channel layer includes silicon.

[0015] Optionally, the process of forming the isolation groove further includes: thinning the initial bottom pseudo-gate structure to form a bottom pseudo-gate structure, wherein the dimension of the bottom pseudo-gate structure parallel to the first direction and the second direction is smaller than the dimension of the initial bottom pseudo-gate structure parallel to the first direction and the second direction.

[0016] Optionally, the process of forming the inner sidewall also includes forming a second sidewall on the sidewall of the bottom pseudo-grid structure.

[0017] Optionally, the method for forming the second sidewall and the inner sidewall includes: forming a first initial inner sidewall within the isolation groove, the sidewall and bottom surface of the source / drain opening, the sidewalls of the bottom pseudo-gate structure and the top pseudo-gate structure, and the top surface of the top pseudo-gate structure; etching back the first initial inner sidewall until the bottom surface of the source / drain opening and the top surface of the top pseudo-gate structure are exposed, thereby forming a second initial inner sidewall; etching back the second initial inner sidewall until the sidewalls of the top pseudo-gate structure, the bottom pseudo-gate structure, and the channel layer are exposed, thereby forming the second sidewall and the inner sidewall.

[0018] Optionally, the material of the inner sidewall includes silicon nitride; the material of the second sidewall includes silicon nitride.

[0019] Optionally, after forming the source / drain doped layers, the method further includes: forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the top dummy gate structure and the bottom dummy gate structure; removing the top dummy gate structure and the bottom dummy gate structure to form a gate opening within the dielectric layer; removing the sacrificial layer to form a gate trench between adjacent channel layers; and forming a gate structure within the gate opening and the gate trench, the gate structure surrounding the channel layer.

[0020] Optionally, before forming the gate structure, the method further includes forming an isolation layer on the substrate, wherein the top surface of the isolation layer is not higher than the top surface of the channel layer located at the bottom layer.

[0021] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0022] In the method for forming the technical solution of the present invention, by covering the sidewalls of the fin structure with the bottom dummy gate material layer, the first sidewall is avoided from being formed on the sidewalls of the fin structure during the formation of the first sidewall on the sidewall of the top dummy gate structure. This reduces the generation of byproducts after the formation of the source / drain openings, provides a good growth environment for the source / drain doped layer, improves the morphology of the source / drain doped layer, and thereby improves the performance of the final semiconductor structure.

[0023] On the other hand, since the sidewalls of some initial channel layers and some initial sacrificial layers do not form the first sidewall, it is not necessary to perform back etching on the first sidewall, thereby avoiding making the height of the top pseudo gate structure very high, which can effectively reduce the process difficulty and improve the morphology of the source and drain openings.

[0024] Furthermore, the material of the sacrificial layer is the same as the material of the dummy gate layer; the process of forming the isolation groove also includes thinning the initial bottom dummy gate layer. This effectively reduces process steps and improves production efficiency.

[0025] Furthermore, the process of forming the inner sidewall within the isolation groove also includes forming the second sidewall. This effectively reduces process steps and improves production efficiency. Attached Figure Description

[0026] Figure 1 and Figure 2 This is a schematic diagram of the steps involved in the formation of a semiconductor structure.

[0027] Figures 3 to 5 This is a schematic diagram of the steps involved in the formation of another semiconductor structure;

[0028] Figures 6 to 21 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0029] As described in the background section, the performance of existing fin field-effect transistors needs improvement. This will be explained in detail below with reference to the accompanying drawings.

[0030] Figure 1 and Figure 2 This is a schematic diagram of the steps involved in the formation of a semiconductor structure.

[0031] Please refer to Figure 1 A substrate 100 is provided, on which a fin structure 101 is provided; a dummy gate structure 102 is formed on the substrate 100, the dummy gate structure 102 spans across the fin structure 101, and the dummy gate structure 102 covers part of the sidewalls and top surface of the fin structure 101; a sidewall material layer is formed on the sidewalls and top surface of the dummy gate structure 102, exposing the sidewalls and top surface of the fin structure 101; the sidewall material layer is etched back until the gate structure 102 and the top surface of the fin structure 101 are exposed, forming a sidewall 103.

[0032] Please refer to Figure 2 After the sidewall 103 is formed, the fin structure 101 is etched using the pseudo-gate structure 102 and the sidewall 103 as a mask, and a source / drain opening 104 is formed in the fin structure 101.

[0033] In this embodiment, since the sidewall material layer is also formed on the exposed sidewalls of the fin structure 101, the sidewall 103 will remain on the sidewalls of the fin structure 101 after the sidewall material layer is etched back. After the source / drain opening 104 is formed, the sidewall 103 located on the sidewalls of the fin structure 101 is no longer supported by the fin structure 101 and is prone to collapse into byproducts. These byproducts will affect the growth of the subsequently formed source / drain doped layer, thereby deteriorating the morphology of the source / drain doped layer and reducing the performance of the final semiconductor structure.

[0034] To address the aforementioned problems, a method for forming a semiconductor structure has been proposed in the prior art. This will be described in detail below with reference to the accompanying drawings.

[0035] Figures 3 to 5 This is a schematic diagram of the steps involved in the formation of another semiconductor structure.

[0036] Please refer to Figure 3 A substrate 200 is provided, on which a fin structure 201 is provided; an initial dummy gate structure 202 is formed on the substrate 200, the initial dummy gate structure 202 spans across the fin structure 201, and the initial dummy gate structure 202 covers part of the sidewalls and top surface of the fin structure 201; a sidewall material layer is formed on the sidewalls and top surface of the initial dummy gate structure 202, and on the sidewalls and top surface of the fin structure 201; the sidewall material layer is etched back until the initial gate structure 202 and the top surface of the fin structure 201 are exposed, forming an initial sidewall 203.

[0037] Please refer to Figure 4 After forming the initial sidewall 203, the fin structure 201 is etched using the initial pseudo-gate structure 202 and the initial sidewall 203 as a mask, and a source / drain opening 204 is formed in the fin structure 201.

[0038] Please refer to Figure 5 After forming the source / drain opening 204, the initial sidewall 203 is etched back until the top surface of the substrate 200 is exposed, forming the sidewall 206.

[0039] In this embodiment, although the initial sidewalls retained on the sidewalls of the fin structure 201 can be removed by etching back the initial sidewalls 203, the initial pseudo-gate structure 202 will also be etched away during the etching back process, thus ultimately forming the pseudo-gate structure 205. Therefore, in order to ensure that the final pseudo-gate structure 205 has a preset height, the initial pseudo-gate structure 202 needs to be made very high along the normal line of the substrate 200 surface.

[0040] However, if the required height of the initial pseudo-gate structure 202 is too high, it increases the manufacturing difficulty of the initial pseudo-gate structure 202, resulting in poor sidewall verticality and affecting the morphology of the source / drain opening 204 formed by the initial pseudo-gate structure 202 as a mask. Poor morphology of the source / drain opening 204 will cause significant difficulties in subsequent manufacturing processes.

[0041] Based on this, the present invention provides a semiconductor structure and its formation method. By covering the sidewalls of several initial channel layers and several initial sacrificial layers with the bottom dummy gate material layer, the first sidewall is avoided from being formed on the sidewalls of the several initial channel layers and several initial sacrificial layers during the formation of the first sidewall on the sidewall of the top dummy gate structure. This reduces the generation of byproducts after the formation of the source / drain openings, provides a good growth environment for the source / drain doped layers, improves the morphology of the source / drain doped layers, and thus improves the performance of the finally formed semiconductor structure.

[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] Figures 6 to 21 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0044] Please refer to Figure 6 A substrate 300 is provided, wherein the substrate 300 has a plurality of initial channel layers 301 and a plurality of initial sacrificial layers 302, the plurality of initial channel layers 301 and the plurality of initial sacrificial layers 302 are stacked at intervals along the normal direction of the surface of the substrate 300, and the plurality of initial channel layers 301 and the plurality of initial sacrificial layers 302 extend along a first direction X.

[0045] In this embodiment, the substrate 300 is made of silicon.

[0046] In this embodiment, the method for the substrate 300 and a plurality of initial channel layers 301 and a plurality of initial sacrificial layers 302 includes: providing an initial substrate (not shown); forming a plurality of channel material films overlapping along the normal direction of the surface of the initial substrate and a sacrificial material film located in two adjacent channel material films on the initial substrate; forming a patterned layer (not shown) on the top channel material film; and etching the initial substrate, the plurality of channel material films and the plurality of sacrificial material films using the patterned layer as a mask to form the substrate 300 and the plurality of initial channel layers 301 and the plurality of initial sacrificial layers 302.

[0047] The initial sacrificial layer 302 is made of a different material than the initial channel layer 301. This is because the sacrificial layer needs to be removed during the subsequent formation of the gate structure. Therefore, by using different materials, the initial sacrificial layer 302 and the initial channel layer 301 have a larger etch selectivity, reducing damage to the channel layer during the removal of the sacrificial layer.

[0048] In this embodiment, the initial sacrificial layer 302 is made of silicon-germanium; the initial channel layer 301 is made of silicon. In other embodiments, the initial sacrificial layer may also be made of germanium; the initial channel layer may be made of silicon-germanium.

[0049] Please refer to Figure 7 An isolation layer 303 is formed on the substrate 300.

[0050] In this embodiment, the method for forming the isolation layer 303 includes: forming an isolation material layer (not shown) on the substrate 300, the isolation material layer covering the sidewalls of a plurality of initial channel layers and a plurality of initial sacrificial layers; etching back the isolation material layer to form the isolation layer 303, wherein the top surface of the isolation layer 303 is not higher than the top surface of the initial channel layer 301 located at the bottom layer.

[0051] The material of the isolation layer 303 includes silicon oxide or silicon nitride. In this embodiment, the material of the isolation layer 203 is silicon nitride.

[0052] Please refer to Figure 8 After the isolation layer 303 is formed, a pseudo gate material layer 304 is formed on the substrate 300, the pseudo gate material layer 304 covering the sidewalls and top surface of a plurality of initial channel layers 301 and a plurality of initial sacrificial layers 302.

[0053] In this embodiment, the method for forming the pseudo-gate material layer 304 includes: forming a pseudo-gate material film (not shown) on the substrate; and performing planarization treatment on the pseudo-gate material film to form the pseudo-gate material layer 304.

[0054] In this embodiment, the pseudo-gate material film is formed using a furnace deposition process.

[0055] In this embodiment, the planarization process employs a chemical mechanical polishing process.

[0056] Please refer to Figure 9 and Figure 10 , Figure 9 It is a 3D diagram of a semiconductor structure. Figure 10 yes Figure 9A schematic diagram of a cross-section along line AA shows that the pseudo-gate material 304 is graphically processed to form a pseudo-gate structure. The pseudo-gate structure includes a bottom pseudo-gate material layer 305 and a top pseudo-gate structure 306 located on the bottom pseudo-gate material layer 305. The bottom pseudo-gate material layer 305 covers the sidewalls of several initial channel layers 301 and several initial sacrificial layers 302, and exposes the top surface of the initial channel layer 301 located at the top layer. The top pseudo-gate structure 306 covers part of the top surface of the initial channel layer 301 located at the top layer along the second direction Y. The first direction X is perpendicular to the second direction Y.

[0057] In this embodiment, by covering the sidewalls of the initial channel layers 301 and initial sacrificial layers 302 with the bottom dummy gate material layer 305, the formation of the first sidewalls on the sidewalls of the initial channel layers 301 and initial sacrificial layers 302 during the subsequent formation of the first sidewalls on the sidewalls of the top dummy gate structure 306 is avoided. This reduces the generation of byproducts after the subsequent formation of source / drain openings, providing a favorable growth environment for the subsequently formed source / drain doped layers, improving the morphology of the source / drain doped layers, and thereby enhancing the performance of the final semiconductor structure.

[0058] On the other hand, since the sidewalls of the initial channel layers 301 and the initial sacrificial layers 302 do not form the first sidewall, it is not necessary to perform back etching on the first sidewall, thereby avoiding making the height of the top pseudo gate structure 304 very high, which can effectively reduce the process difficulty and improve the morphology of the source and drain openings formed subsequently.

[0059] In this embodiment, the method for patterning the pseudo-gate material layer 304 to form a pseudo-gate structure includes: forming a patterned layer (not shown) on the pseudo-gate material layer 304, wherein the patterned layer exposes a portion of the top surface of the pseudo-gate material layer 304; etching the pseudo-gate material layer 304 using the patterned layer as a mask until the top surface of the top surface of the initial channel layer 301 located at the top layer is exposed, thereby forming the pseudo-gate structure.

[0060] In this embodiment, the gate structure includes a dummy gate layer, and the material of the dummy gate layer is the same as the material of the initial sacrificial layer 302.

[0061] Please refer to Figure 11 , Figure 11 and Figure 10 With the view orientation consistent, a first sidewall 307 is formed on the sidewall of the top pseudo-grid structure 306.

[0062] In this embodiment, the method for forming the first sidewall 307 includes: forming a first sidewall material layer (not shown) on the top surface of the bottom pseudo-gate material layer 305, the top surface of the top pseudo-gate structure 306, and the sidewall of the top pseudo-gate structure 306; and etching the first sidewall material layer back until the top surfaces of the top pseudo-gate structure 306 and the bottom pseudo-gate material layer 305 are exposed, thereby forming the first sidewall 307.

[0063] In this embodiment, the first sidewall material layer is formed using atomic layer deposition.

[0064] In this embodiment, the first sidewall 307 is made of silicon nitride.

[0065] Please refer to Figures 12 to 14 , Figure 12 This is a top view of the semiconductor structure. Figure 13 yes Figure 12 Schematic diagram of the cross section along line BB. Figure 14 yes Figure 12 A schematic diagram of the cross-section along the CC line shows that, using the top pseudo-gate structure 306 and the first sidewall 307 as masks, several initial channel layers 301, several initial sacrificial layers 302, and the bottom pseudo-gate material layer 305 are etched to form source / drain openings 308, several channel layers 317, several sacrificial layers 318, and the initial bottom pseudo-gate structure 309.

[0066] In this embodiment, the source / drain opening 308 serves to provide space for the subsequently formed source / drain doped layer.

[0067] Please refer to Figure 15 and Figure 16 , Figure 15 and Figure 13 The view orientation is consistent. Figure 16 and Figure 14 With the view orientation consistent, after forming the source / drain opening 308, the portion of the sacrificial layer 318 exposed on the sidewall of the source / drain opening 308 is etched to form an isolation groove 310 between adjacent channel layers 317.

[0068] In this embodiment, the isolation groove 310 serves to provide space for the subsequently formed inner sidewalls. These inner sidewalls ensure electrical isolation between the subsequently formed gate structure and the source / drain doped layers.

[0069] In this embodiment, the process of forming the isolation groove 310 further includes: thinning the initial bottom dummy gate structure 309 to form a bottom dummy gate structure 311. The dimension of the bottom dummy gate structure 311 parallel to the first direction X and the second direction Y is smaller than the dimension of the initial bottom dummy gate structure 309 parallel to the first direction X and the second direction Y. Since the material of the initial sacrificial layer 302 is the same as the material of the gate layer, the material of the sacrificial layer 318 formed by the initial sacrificial layer 302 is also the same as that of the gate layer. Therefore, during the etching of the sacrificial layer 318 to form the isolation groove 310, the initial bottom dummy gate structure 309 can be thinned using the same etching process, which can effectively reduce process steps and improve production efficiency.

[0070] In this embodiment, the purpose of thinning the initial bottom pseudo-gate structure 309 is to provide space for the subsequent formation of a second sidewall on the sidewall of the bottom pseudo-gate structure 311.

[0071] Please refer to Figure 17 and Figure 18 After the isolation groove 310 is formed, an inner sidewall 312 is formed within the isolation groove 310.

[0072] In this embodiment, the process of forming the inner sidewall 312 further includes forming a second sidewall 313 on the sidewall of the bottom pseudo-gate structure 311. This effectively reduces process steps and improves production efficiency.

[0073] In this embodiment, the method for forming the second sidewall 313 and the inner sidewall 312 includes: forming a first initial inner sidewall (not shown) within the isolation groove 310, the sidewall and bottom surface of the source / drain opening 308, the sidewalls of the bottom pseudo-gate structure 311 and the top pseudo-gate structure 306, and the top surface of the top pseudo-gate structure 306; etching back the first initial inner sidewall until the bottom surface of the source / drain opening 308 and the top surface of the top pseudo-gate structure 306 are exposed, forming a second initial inner sidewall (not shown); etching back the second initial inner sidewall until the sidewalls of the top pseudo-gate structure 306, the bottom pseudo-gate structure 311, and the channel layer 317 are exposed, forming the second sidewall 313 and the inner sidewall 312.

[0074] In this embodiment, the inner sidewall 312 is made of silicon nitride; the second sidewall 313 is made of silicon nitride.

[0075] Please refer to Figure 19 , Figure 19 and Figure 17With the view orientation consistent, after the inner sidewall 312 is formed, a source / drain doped layer 314 is formed within the source / drain opening 308.

[0076] In this embodiment, the source / drain doped layer 314 contains source / drain ions.

[0077] When the semiconductor structure is a P-type device, the material of the source / drain doped layer 314 includes silicon, germanium, or silicon-germanium; the source / drain ions are P-type ions, including boron ions and BF ions. 2- The source / drain doped layer 314 is made of silicon, gallium arsenide, or indium gallium arsenide when the semiconductor structure is an N-type device; the source / drain ions are N-type ions, including phosphorus ions or arsenic ions.

[0078] In this embodiment, the semiconductor structure is an N-type device, the source / drain doped layer 314 is made of silicon, and the source / drain ions are phosphorus ions.

[0079] Please refer to Figure 20 After forming the source / drain doped layer 314, a dielectric layer 315 is formed on the substrate 300, the dielectric layer 315 covering the sidewalls of the top pseudo-gate structure 306 and the bottom pseudo-gate structure 311.

[0080] In this embodiment, the method for forming the dielectric layer 315 includes: forming an initial dielectric layer (not shown) on the source / drain doped layer 314 and the dummy gate structure, the initial dielectric layer covering the top surface and sidewall surface of the dummy gate structure; planarizing the initial dielectric layer until the protective layer surface at the top of the dummy gate structure is exposed, thereby forming the dielectric layer 315.

[0081] In this embodiment, the dielectric layer 315 is made of silicon oxide.

[0082] Please refer to Figure 21 After forming the dielectric layer 315, the top pseudo-gate structure 306 and the bottom pseudo-gate structure 311 are removed, and a gate opening is formed in the dielectric layer 315; the sacrificial layer 302 is removed, and a gate trench is formed between adjacent channel layers 317; a gate structure 316 is formed in the gate opening and the gate trench, and the gate structure 316 surrounds the channel layer 317.

[0083] In this embodiment, the gate structure 316 includes a gate layer.

[0084] The gate layer is made of metal, including one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum. In this embodiment, the gate layer is made of tungsten.

[0085] Accordingly, an embodiment of the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 21 The system includes: a substrate 300 having a plurality of channel layers 317 stacked along the normal direction of the surface of the substrate 300, the channel layers 317 extending along a first direction X; an inner sidewall 312 located between the two ends of adjacent channel layers 317, the side of the inner sidewall 312 being perpendicular to the end face of the channel layer 317; a gate trench located between adjacent channel layers 317 or between the channel layer 317 and the substrate 300; and a gate structure 316 located on the substrate 300 and within the gate trench. The gate structure 316 surrounds a plurality of channel layers 317 along a second direction Y, wherein the first direction X is perpendicular to the second direction Y; a first sidewall 307 and a second sidewall 313 are located on the sidewalls of the gate structure 316, wherein the first sidewall 307 is located on the second sidewall 313; source / drain openings 308 are located on both sides of the gate structure 316, wherein the source / drain openings 308 expose the inner sidewalls 312, and the bottom surface of the source / drain openings 308 is lower than the top surface of the substrate 300; and a source / drain doped layer 314 is located within the source / drain openings 308.

[0086] In this embodiment, the material of the inner sidewall 312 is the same as the material of the second sidewall 313.

[0087] In this embodiment, the inner sidewall 312 is made of silicon nitride; the second sidewall 313 is made of silicon nitride.

[0088] In this embodiment, it further includes an isolation layer 303 located on the substrate 300, wherein the top surface of the isolation layer 303 is not higher than the top surface of the channel layer 317 located at the bottom layer.

[0089] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a plurality of channel layers, the plurality of channel layers being stacked along the normal direction of the substrate surface, the channel layers extending along a first direction; An inner wall located between the two ends of an adjacent channel layer, wherein the side of the inner wall is perpendicular to the end face of the channel layer; Gate trench located between adjacent channel layers; A gate structure located on the substrate and within the gate trench, the gate structure surrounding a plurality of the channel layers along a second direction, the first direction being perpendicular to the second direction; A first sidewall and a second sidewall are located on the sidewall of the gate structure, with the first sidewall located on the second sidewall; Source and drain openings are located on both sides of the gate structure, the source and drain openings expose the inner sidewalls, and the bottom surface of the source and drain openings is lower than the top surface of the substrate; The source / drain doped layer located within the source / drain opening.

2. The semiconductor structure as described in claim 1, characterized in that, The material of the inner side wall is the same as that of the second side wall.

3. The semiconductor structure as described in claim 1, characterized in that, The material of the inner sidewall includes silicon nitride; the material of the second sidewall includes silicon nitride.

4. The semiconductor structure as described in claim 1, characterized in that, Also includes: An isolation layer located on the substrate, wherein the top surface of the isolation layer is not higher than the top surface of the channel layer located at the bottom layer.

5. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a plurality of initial channel layers and a plurality of initial sacrificial layers, wherein the plurality of initial channel layers and the plurality of initial sacrificial layers are stacked at intervals along the normal direction of the substrate surface, and the plurality of initial channel layers and the plurality of initial sacrificial layers extend along a first direction, respectively. A pseudo-gate material layer is formed on the substrate, the pseudo-gate material layer covering the sidewalls and top surface of a plurality of initial channel layers and a plurality of initial sacrificial layers; The pseudo-gate material layer is patterned to form a pseudo-gate structure, which includes a bottom pseudo-gate material layer and a top pseudo-gate structure located on the bottom pseudo-gate material layer. The bottom pseudo-gate material layer covers the sidewalls of several initial channel layers and several initial sacrificial layers, and exposes the top surface of the initial channel layer located at the top layer. The top pseudo-gate structure covers part of the top surface of the initial channel layer located at the top layer along a second direction, wherein the first direction is perpendicular to the second direction. A first sidewall is formed on the sidewall of the top pseudo-grid structure; Using the top pseudo-gate structure and the first sidewall as a mask, several initial channel layers, several initial sacrificial layers, and the bottom pseudo-gate material layer are etched to form source / drain openings, several channel layers, several sacrificial layers, and the initial bottom pseudo-gate structure. Etching the portion of the sacrificial layer exposed on the sidewall of the source / drain opening forms an isolation groove between adjacent channel layers; An inner wall is formed within the isolation groove; A source / drain doped layer is formed within the source / drain opening.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method for patterning the pseudo-gate material layer to form a pseudo-gate structure includes: forming a patterned layer on the pseudo-gate material layer, the patterned layer exposing a portion of the top surface of the pseudo-gate material layer; etching the pseudo-gate material layer using the patterned layer as a mask until the top surface of the initial channel layer located at the top layer is exposed, thereby forming the pseudo-gate structure.

7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The pseudo-gate structure includes a pseudo-gate layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The material of the sacrificial layer is different from that of the channel layer, and the material of the sacrificial layer is the same as that of the pseudo-gate layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The materials of the sacrificial layer and the pseudo-gate layer include silicon and germanium; the material of the channel layer includes silicon.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process of forming the isolation groove also includes: thinning the initial bottom pseudo-gate structure to form a bottom pseudo-gate structure, wherein the dimension of the bottom pseudo-gate structure parallel to the first direction and the second direction is smaller than the dimension of the initial bottom pseudo-gate structure parallel to the first direction and the second direction.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process of forming the inner sidewall also includes forming a second sidewall on the sidewall of the bottom pseudo-grid structure.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the second sidewall and the inner sidewall includes: forming a first initial inner sidewall within the isolation groove, the sidewall and bottom surface of the source / drain opening, the sidewalls of the bottom pseudo-gate structure and the top pseudo-gate structure, and the top surface of the top pseudo-gate structure; etching back the first initial inner sidewall until the bottom surface of the source / drain opening and the top surface of the top pseudo-gate structure are exposed, thereby forming a second initial inner sidewall; etching back the second initial inner sidewall until the sidewalls of the top pseudo-gate structure, the bottom pseudo-gate structure, and the channel layer are exposed, thereby forming the second sidewall and the inner sidewall.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The material of the inner sidewall includes silicon nitride; the material of the second sidewall includes silicon nitride.

14. The method for forming a semiconductor structure as described in claim 10, characterized in that, After forming the source / drain doped layers, the method further includes: forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the top dummy gate structure and the bottom dummy gate structure; removing the top dummy gate structure and the bottom dummy gate structure to form a gate opening within the dielectric layer; removing the sacrificial layer to form a gate trench between adjacent channel layers; and forming a gate structure within the gate opening and the gate trench, the gate structure surrounding the channel layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, Prior to forming the gate structure, the method further includes forming an isolation layer on the substrate, wherein the top surface of the isolation layer is not higher than the top surface of the channel layer located at the bottom layer.

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