Bidirectional bipolar device for esd protection

Abstract

The present invention relates to a bidirectional bipolar device for ESD protection. An electrostatic discharge (ESD) protection device, comprising: a substrate comprising: first, second and third doped regions, the second doped region disposed between the first and third doped regions, the second doped region having a first conductivity type and a first doping concentration, and the first and third doped regions having a second conductivity type and a second doping concentration; first and second doped terminal regions disposed within the first and second doped regions, respectively; a doped island region disposed within the second doped region, the first and second doped terminal regions and the doped island region having the second conductivity type and a third doping concentration, the third doping concentration being higher than the first and second doping concentrations; and conductive terminals coupled to the doped terminal regions, respectively; and an insulating layer disposed on the substrate between the conductive terminals and covering at least the second doped region.

Description

Technical Field

[0001] This disclosure generally relates to electrostatic discharge (ESD) protection devices and methods for forming ESD protection devices. Background Technology

[0002] ESD voltages higher than the normal voltage supplied to electronic devices can damage them. Therefore, electronic devices are often coupled to ESD protection devices to protect them from such damage. When the ESD voltage is below a predetermined level, negligible current flows through these ESD protection devices. However, when the ESD voltage exceeds the predetermined level, the ESD protection devices may turn on to divert current away from the devices, thus protecting them from damage.

[0003] Conventional NPN (or PNP) based ESD protection devices are unidirectional and cannot be directly used for bidirectional ESD protection. That is, conventional bipolar ESD protection devices can only support unipolar high-voltage bias, meaning they can only withstand high-voltage bias in one direction. For example, for a typical NPN transistor-based ESD protection device, a high-voltage bias can only be applied in the direction from the collector terminal of the NPN transistor to the emitter / base terminal (or from the emitter / base terminal of the PNP transistor to the collector terminal) to function as an effective ESD protection device. Otherwise, if the voltage at the emitter / base terminal is significantly higher than the voltage at the collector terminal (e.g., more than 0.7V higher), the NPN transistor is forward biased and may turn on, discharging current away from the device, even when the voltage bias between the terminals is below a predetermined level. Summary of the Invention

[0004] According to various embodiments, a semiconductor device providing ESD protection is provided. The ESD protection device may include a substrate comprising a bipolar junction transistor disposed therein, including: a first doped region, a second doped region, and a third doped region, the second doped region being disposed between the first and third doped regions, wherein the second doped region has a first conductivity type and a first doping concentration, and the first and third doped regions have a second conductivity type and a second doping concentration; a first doped terminal region disposed within the first doped region; a second doped terminal region disposed within the third doped region; and a doped island region disposed within the second doped region, wherein the first, second, and third doped terminal regions have a second conductivity type and a third doping concentration, the third doping concentration being higher than the first and second doping concentrations; a first conductive terminal coupled to the first doped terminal region; a second conductive terminal coupled to the second doped terminal region; and an insulating layer disposed on the substrate between the first and second conductive terminals, the insulating layer at least covering the second doped region.

[0005] According to various embodiments, a method for forming an ESD protection device is provided. The method may include: providing a substrate including a bipolar junction transistor disposed in the substrate, the provision of the substrate including: providing a first doped region, a second doped region, and a third doped region, the second doped region being disposed between the first doped region and the third doped region, wherein the second doped region has a first conductivity type and a first doping concentration, and the first doped region and the third doped region have a second conductivity type and a second doping concentration; providing a first doped terminal region disposed within the first doped region; providing a second doped terminal region disposed within the third doped region; and providing a doped island region disposed within the second doped region, wherein the first doped terminal region, the second doped terminal region, and the doped island region have the second conductivity type and a third doping concentration, the third doping concentration being higher than the first doping concentration and the second doping concentration; providing a first conductive terminal coupled to the first doped terminal region; providing a second conductive terminal coupled to the second doped terminal region; and providing an insulating layer disposed on the substrate between the first conductive terminal and the second conductive terminal, the insulating layer at least covering the second doped region.

[0006] Other features of the advantageous embodiments are provided in the dependent claims. Attached Figure Description

[0007] In the accompanying drawings, the same reference numerals generally indicate the same parts in all different views. The drawings are not necessarily drawn to scale, but generally emphasize the principles of the invention. In the following description, various embodiments are described with reference to the following drawings, wherein:

[0008] Figure 1 A simplified cross-sectional view of a bidirectional ESD device according to various non-limiting embodiments is shown.

[0009] Figure 2 Various non-limiting embodiments are shown. Figure 1 A simplified schematic diagram of a bidirectional ESD device.

[0010] Figure 3 This illustrates different base lengths obtained by simulating ESD protection devices using Technology Computer-Aided Design (TCAD). Figure 1 Performance charts for ESD protection devices.

[0011] Figure 4A and 4B The diagram shows the different currents obtained for simulating ESD protection devices using TCAD. Figure 1 A current density diagram of a portion of the ESD protection device.

[0012] Figure 5 A simplified cross-sectional view of an ESD protection device according to an alternative, non-limiting embodiment is shown.

[0013] Figure 6 A simplified cross-sectional view of an ESD protection device according to another alternative, non-limiting embodiment is shown.

[0014] Figure 7 A simplified cross-sectional view of an ESD protection device according to another alternative, non-limiting embodiment is shown.

[0015] Figure 8 A simplified cross-sectional view of an ESD protection device according to another alternative, non-limiting embodiment is shown.

[0016] Figure 9A A simplified cross-sectional view of an ESD protection device according to another alternative, non-limiting embodiment is shown.

[0017] Figure 9B It shows Figure 9A A simplified schematic diagram of an ESD protection device.

[0018] Figure 10A and 10B A flowchart of a method for forming an ESD protection device according to various non-limiting embodiments is shown. Detailed Implementation

[0019] Embodiments of this disclosure generally relate to semiconductor devices. More specifically, embodiments relate to providing ESD protection devices in semiconductor devices. For example, such ESD protection devices may be incorporated into integrated circuits (ICs). Semiconductor devices or ICs may be used with devices such as, but not limited to, consumer electronics products. Existing methods for integrating ESD protection devices into semiconductor devices require multiple etch masks and a large footprint. Some embodiments relate to ESD protection devices with a smaller footprint that can be integrated into the semiconductor device during manufacturing with a reduced number of etch masks.

[0020] The invention, including its various aspects, features, advantages, and details, is explained more fully below with reference to the non-limiting examples shown in the accompanying drawings. Descriptions of well-known materials, manufacturing tools, processing techniques, etc., are omitted to avoid unnecessarily obscuring the invention with unnecessary detail. However, it should be understood that while the detailed descriptions and specific examples indicate aspects of the invention, they are given by way of illustration only and not by way of limitation. Various substitutions, modifications, additions, and / or arrangements within the spirit and / or scope of the basic inventive concept will be apparent to those skilled in the art from this disclosure.

[0021] As used throughout the specification and claims, approximate language may be used to modify any quantitative expression that is permissible to vary without causing a change in the underlying function. Therefore, values ​​modified by one or more terms such as “approximate” or “about” are not limited to the specified exact values. In some cases, approximate language may correspond to the precision of the instrument used to measure the value. Furthermore, the modification of direction by one or more terms such as “substantially” means that the direction applies within the normal tolerance range of the semiconductor industry. For example, “substantially parallel” means extending in approximately the same direction within the normal tolerance range of the semiconductor industry, while “substantially perpendicular” means an angle of ninety degrees plus or minus the normal tolerance range of the semiconductor industry.

[0022] The terminology used herein is for the purpose of describing specific examples only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprise” (and any form of “comprise,” such as “comprises” and “comprising”), “have” (and any form of “have,” such as “has” and “having”), “include” (and any form of “include,” such as “includes” and “including”), and “contain” (and any form of “contain,” such as “contains” and “containing”) are open-ended linking verbs. Thus, a method or apparatus that “comprises,” “has,” “includes,” or “contains” one or more steps or elements has, but is not limited to, having only, these steps or elements. Similarly, a method step or apparatus element that “comprises,” “has,” “includes,” or “contains” one or more features has, but is not limited to, these features. Furthermore, apparatus or structures configured in a certain way are configured at least in this manner, but may also be configured in ways not listed.

[0023] As used herein, when referring to two physical elements, the term "connection" indicates a direct connection between the two physical elements. However, the term "coupled" can indicate a direct connection or a connection through one or more intermediate elements.

[0024] As used herein, the terms “may” and “may” indicate: a possibility of occurring within a set of circumstances; possessing a specified property, characteristic, or function; and / or qualifying one verb by expressing one or more of the capabilities, functions, or possibilities associated with the qualifying verb. Thus, the use of “may” and “may” indicates that the modified term is clearly suitable, permissible, or appropriate for the specified capability, function, or use, while taking into account that in some cases the modified term may not be suitable, permissible, or appropriate. For example, in some cases an event or capability may be expected, while in others it may not occur—this distinction is captured by the terms “may” and “may”.

[0025] Figure 1 A simplified cross-sectional view of a bidirectional bipolar ESD device according to various non-limiting embodiments is shown.

[0026] Figure 2 Various non-limiting embodiments are shown. Figure 1 A simplified schematic diagram of a bidirectional bipolar ESD device.

[0027] refer to Figure 1 ESD devices according to various non-limiting embodiments of the present disclosure may include a symmetrical bipolar transistor structure having two emitter / collector portions. Each emitter / collector portion may each include a heavily doped terminal region 130, 134 (e.g., an N+ or P+ region) of a second conductivity type located within a medium-voltage well region 108, 110 (e.g., an MV N-Well or an MV P-Well). The heavily doped terminal regions 130, 134 are connected to conductive terminals 160, 162 (e.g., formed in a metal layer above a substrate). At the center between the emitter / collector portions, a heavily doped floating region 132 (e.g., an N+ or P+ region, not connected to any terminals) of a second conductivity type is located within and surrounded by a low-voltage well region 120 (e.g., an LV P-Well or an LV N-Well) of a first conductivity type and a drift region 122 (e.g., a P-Drift or N-Drift) of a first conductivity type. The heavily doped floating central island region 132 is isolated from the two heavily doped terminal regions by a barrier or insulating layer 159 formed on the substrate surface. The insulating layer 159 may be formed between the conductive terminals and at least on the surface of the low-voltage well region having drift regions 120, 122, which within the substrate separate the two emitter / collector portions, including emitter / collector terminals, from the floating central island region. The insulating layer 159 may be a silicide barrier layer 150 (e.g., SAB) or polysilicon barrier layers 151a, 151b, but not a shallow trench isolation (STI) structure. A bidirectional bipolar transistor structure is arranged within a high-voltage well 106 (e.g., HV PWell or HV NWell) having a first conductivity type, which is isolated from the bulk substrate region 102 (e.g., P-Sub or N-Sub) having a first conductivity type. The substrate isolation region 103 separates the high-voltage well 106 (e.g., HV PWell or HV NWell) having a first conductivity type from the bulk substrate region 102 (e.g., P-Sub or N-Sub) having a first conductivity type. The substrate isolation region 103 may be an epitaxial doped region (e.g., N-epi or P-epi) or a buried oxide region having a second conductivity type.

[0028] The low-voltage well and drift regions 120, 122 (e.g., P-type or N-type regions) having a first conductivity type can also compensate a portion of the intermediate-voltage well 108 (e.g., MV N-Well or MV P-Well) having a second conductivity type located at the top (e.g., towards the surface of the substrate 101 opposite the bulk substrate layer 102), so that the top of the intermediate-voltage well becomes a region having the first conductivity type. That is, the low-voltage well having drift regions 120, 122 (e.g., P-type or N-type regions) compensates a portion of the intermediate-voltage well (e.g., MV N-Well) located at the top, serving as the base of the bipolar transistor structure (NPN or PNP). Specifically, in this region, the total doping concentration of the low-voltage wells (e.g., LV PWell and P-Drift or LV NWell and N-Drift) with drift regions 120, 122 is higher than the doping concentration of the medium-voltage well regions 108, 110 (e.g., MV NWell or MV PWell), causing the net doping concentration in a portion of the medium-voltage well regions 108, 110 near terminals 160, 162 to become a first conductivity type (e.g., P-type or N-type).

[0029] refer to Figure 1 In some non-limiting embodiments, in the multiple doped regions of the first conductivity type (102, 106, 120, 122) and the second conductivity type (103, 108, 110, 130, 132, 134), the first conductivity type is P-type and the second conductivity type is N-type. Alternatively, in other non-limiting embodiments, in the multiple doped regions of the first conductivity type (102, 106, 120, 122) and the second conductivity type (103, 108, 110, 130, 132, 134), the first conductivity type is N-type and the second conductivity type is P-type.

[0030] ESD protection device 100 may include substrate 101. In various non-limiting embodiments, substrate 101 may include any silicon-containing substrate, including but not limited to silicon (Si), single-crystal silicon, polycrystalline Si, amorphous Si, silicon-on-sapphire (SOS), silicon-on-insulator (SOI) or alternative silicon-on-insulator (SRI) or silicon-germanium substrates. Substrate 102 may also include various isolation, doping and / or device features. Substrate 102 may include: other suitable elemental semiconductors, such as germanium (Ge) in crystal; compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb) or combinations thereof; alloy semiconductors, including GaAsP, AlInAs, GalnAs, GaInP, GaInAsP or combinations thereof.

[0031] In various non-limiting embodiments, substrate 101 may have a body or substrate region 102 disposed within substrate 101. Substrate region 102 may have a first conductivity type. For example, substrate region 102 may have a first conductivity type of P-type. In this case, substrate region 102 may contain a P-type dopant. The doping concentration of substrate region 102 may range from about 1E15 cm⁻¹. -3 up to 5E15cm -3 Therefore, substrate region 102 may include a P-type substrate region (e.g., P-Sub). However, in an alternative, non-limiting embodiment, substrate 101 may have a substrate region 102 of a first conductivity type of N-type. Therefore, substrate region 102 may include an N-type substrate region (e.g., N-Sub). In this case, substrate region 102 may contain an N-type dopant with a doping concentration similar to that of a P-type dopant.

[0032] The substrate 101 of the ESD protection device 100 may further include a substrate isolation region 103, which is disposed within the substrate 101 and at least partially located above the substrate region 102. The substrate isolation region 103 may be an epitaxial region 104. The epitaxial region 104 may have a second conductivity type different from the first conductivity type of the substrate region 102. The epitaxial region 104 may have a higher doping concentration than the substrate region 102. For example, the epitaxial region 104 may have a doping concentration of approximately 5E15 cm⁻¹. -3 up to 1E16 cm -3 The doping concentration range. In some exemplary non-limiting embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type. In this case, the epitaxial region 104 can include an N-type dopant. Therefore, the epitaxial region 104 can include an N-epi region. However, in alternative non-limiting embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type. In this case, the epitaxial region 104 can include a P-type dopant. Therefore, the epitaxial region 104 can include a P-epi region (e.g., P-Epi). Alternatively, the substrate isolation region 103 can include a deep well region instead of an epitaxial region. For example, in some embodiments, a deep N-Well (or a deep P-Well) can be used instead of an N-epi region (or a P-epi region).

[0033] The substrate 101 of the ESD protection device 100 may further include a first conductive region 106 disposed within the substrate 101 and at least partially located above both the substrate isolation region 103 (e.g., epitaxial region 104) and the substrate region 102. The first conductive region 106 may have a first conductivity type similar to that of the substrate region 102. The first conductive region 106 may have a higher doping concentration than the substrate region 102 and the substrate isolation region 103. The first conductive region 106 may be a high-voltage well region. For example, the first conductive region 106 may have a doping concentration of approximately 1E16 cm⁻¹.-3 up to 5E16cm -3 The doping concentration. In some exemplary non-limiting embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type. In this case, the first conductive region 106 may include a P-type dopant. Therefore, the first conductive region 106 may include a high-voltage P-type well (e.g., HV P-Well). However, in alternative non-limiting embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type. In this case, the first conductive region 106 may include an N-type dopant. Therefore, the first conductive region 106 may include a high-voltage N-type well (e.g., HV N-Well).

[0034] The substrate 101 of the ESD protection device 100 may further include a first terminal portion and a second terminal portion. The first terminal portion includes a second conductive region 108, and the second terminal portion includes a third conductive region 110. The first and second terminal portions are disposed within the substrate 101 and are at least partially located above the first conductive region 106. The second and third conductive regions 108 and 110 may be arranged spaced apart from each other. At least a portion of the second conductive region 108 and the third conductive region 110 may each be disposed immediately below the top surface of the substrate 101. The top surface of the substrate 101 is opposite to the substrate region 102. The second conductive region 108 and the third conductive region 110 may each be a medium-voltage well. The second and third conductive regions 108 and 110 may have the same second conductivity type as the deep well region of the epitaxial region 104 or the substrate isolation region 103. In some exemplary non-limiting embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the second conductive region 108 and the third conductive region 110 may include an N-type dopant. Therefore, the second and third conductive regions 108 and 110 can each include a medium-voltage N-type well region (e.g., MV N-Well). However, in an alternative, non-limiting embodiment, the first conductivity type can be N-type and the second conductivity type can be P-type. In this case, the second and third conductive regions 108 and 110 can include P-type dopants. Therefore, the second and third conductive regions 108 and 110 can each include a medium-voltage P-type well region (e.g., MV P-Well). The second and third conductive regions (medium-voltage well regions) can have a higher doping concentration than the first conductive region 106. For example, the second and third conductive regions can have a doping concentration of approximately 1E17 cm⁻¹. -3 up to 5E17cm -3 The range of doping concentrations.

[0035] The first and second terminal portions may each include a corresponding terminal area. The first terminal area 130 may be at least partially disposed within the second conductive area 108. The first terminal area 130 may be configured to be connected to a first external voltage. The second terminal area 134 may be at least partially disposed within the third conductive area 110. The second terminal area 134 may be configured to be connected to a second external voltage.

[0036] The first and second terminal regions 130 and 134 may have the same second conductivity type as the second and third conductive regions 108 and 110. The first terminal region 130 and the second terminal region 134 may each include a heavily doped region. That is, the doping concentration of the first and second terminal regions 130 and 134 is higher than the doping concentration of the second and third conductive regions 108 and 110. In some exemplary non-limiting embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the first and second terminal regions 130 and 134 may include N-type dopants. Therefore, the first and second terminal regions 130 and 134 may each be N+ regions. However, in alternative non-limiting embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type. In this case, the first and second terminal regions 130 and 134 may include P-type dopants. Therefore, the first and second terminal regions 130 and 134 may each be P+ regions.

[0037] refer to Figure 1 In the exemplary, non-limiting embodiment shown, the first terminal region 130 and the second terminal region 134 may be disposed immediately below the top surface of the substrate 101. The first terminal region 130 may be connected to a first external terminal 160 to which a first external voltage can be applied, and the second terminal region 134 may be connected to a second external terminal 162 to which a second external voltage can be applied. Furthermore, the first and second terminal regions 130, 134 and the second and third conductive regions 108, 110 may be isolated from the substrate region 102 by the first conductive region 106 and the substrate isolation region 103 (e.g., the epitaxial region 104).

[0038] The substrate 101 of the ESD protection device 100 may further include a fourth conductive region 120 disposed within the substrate 101 and at least partially located above the first conductive region 106. At least a portion of the fourth conductive region 120 may be disposed immediately below the top surface of the substrate 101. At least a portion of the fourth conductive region 120 may further abut (i.e., directly contact) a portion of the first conductive region 106. The fourth conductive region 120 may be further centrally (e.g., equidistantly) disposed between the second conductive region 108 and the third conductive region 110 of the first and second terminal portions. The fourth conductive region 120 may also abut (i.e., directly contact) the second and third conductive regions 108, 110. A first sidewall 111 of the fourth conductive region 120 may abut the second conductive region 108, and a second sidewall 113 of the fourth conductive region 120 (opposite to the first sidewall) may abut the third conductive region 110. The fourth conductive region 120 is separated from the first and second terminal regions 130, 134 by at least a portion of the second and third conductive regions. Furthermore, in some embodiments, a portion of the fourth conductive region 120 may further overlap with a portion of the second conductive region 108, and another portion of the fourth conductive region 120 may further overlap with a portion of the third conductive region 110. This overlap can provide better performance for the ESD protection device.

[0039] The fourth conductive region 120 may be a low-voltage well region having a first conductivity type. In some exemplary non-limiting embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the fourth conductive region 120 may include a P-type dopant. Therefore, the fourth conductive region 120 may include a low-voltage P-type well (e.g., LV P-Well). However, in alternative non-limiting embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type. In this case, the fourth conductive region 120 may include an N-type dopant. Therefore, the fourth conductive region 120 may include a low-voltage N-type well (e.g., LV N-Well).

[0040] refer to Figure 1 In the exemplary, non-limiting embodiment shown, the fourth conductive region may be disposed immediately below the top surface of the substrate 101. Furthermore, the fourth conductive region 120 may be separated from the substrate region 102 by the first conductive region 106 and the substrate isolation region 103 (e.g., epitaxial region 104).

[0041] The fourth conductive region 120 may further include a floating (or unconnected) central island region 132. The floating region 132 may be a heavily doped region disposed within the fourth conductive region 120. The floating region 132 may be disposed in the center of the fourth conductive region 120 such that the floating region 132 is equidistant from the first sidewall 111 and the second sidewall 113 of the fourth conductive region 120. The floating region 132 may be arranged to be a distance L from the first and second sidewalls 111 and 113 of the fourth conductive region 120. The distance L adjusts the bidirectional bipolar ESD protection device for different voltage applications. The breakdown voltage and holding voltage may be varied based on the distance L. For example, a bidirectional NPN (or PNP) device with a longer distance L between the floating region and the sidewalls has a higher breakdown voltage and holding voltage than a bidirectional NPN (or PNP) device with a shorter distance L. A bidirectional NPN (or PNP) device with a shorter distance L between the floating region and the sidewall has a lower breakdown voltage and holding voltage than a bidirectional NPN (or PNP) device with a longer distance L. The floating region 132 has the same second conductivity type as the first and second terminal regions 130, 134. However, the floating region 132 is not configured to be connected to an external voltage. In some exemplary non-limiting embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type. In this case, the floating region 132 may include an N-type dopant. Therefore, the floating region 132 may include an N+ region. However, in alternative non-limiting embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type. In this case, the floating region 132 may include a P-type dopant. Therefore, the floating region 132 may include a P+ region.

[0042] refer to Figure 1 In the exemplary, non-limiting embodiment shown, the floating region 132 may be centrally disposed immediately below the top surface of the substrate 101 within the fourth conductive region 120. Furthermore, the floating region 132 may be isolated from the substrate region 102 by the first conductive region 106 and the substrate isolation region 103 (e.g., the epitaxial region 104).

[0043] The depth of the fourth conductive region 120 can be less than or substantially equal to the depths of the second conductive region 108 and the third conductive region 110. (Reference) Figure 1 In the exemplary, non-limiting embodiment shown, the depth of the fourth conductive region 120 may be less than the depths of the second conductive region 108 and the third conductive region 110. However, in an alternative, non-limiting embodiment, the depths of the second conductive region 108, the third conductive region 110, and the fourth conductive region 120 may be substantially the same.

[0044] The second conductive region 108 and the third conductive region 110 may have approximately equal doping concentrations. Furthermore, the doping concentrations of the second and third conductive regions 108 and 110 may be higher than the doping concentration of the first conductive region 106. The first terminal region 130 and the second terminal region 134 may each have higher doping concentrations than the second and third conductive regions 108 and 110. For example, the second conductive region 108 may have a doping concentration of approximately 1E17 cm⁻¹. -3 up to 5E17cm -3 The doping concentration range; the third conductive region 110 can also have approximately 1E17cm. -3 up to 5E17cm -3 The doping concentration range; the first terminal region 130 can have approximately 5E19 cm⁻¹ -3 up to 5E20cm -3 The doping concentration range, and the second terminal region 134 can have approximately 5E19 cm⁻¹ -3 up to 5E20cm -3 The doping concentration range. The second and third conductive regions 108, 110 and the first and second terminal regions 130, 134 can have the same conductivity type as the epitaxial region 104. That is, they can have a second conductivity type. In an exemplary non-limiting embodiment where the first conductivity type can be P-type and the second conductivity type can be N-type, the second and third conductive regions 108, 110 can be N-type wells and the first and second terminal regions 130, 134 can be N+ regions.

[0045] The fourth conductive region 120 can have approximately 5E17cm -3 Up to 1E18cm -3 The doping concentration range is specified. Furthermore, the doping concentration of the fourth conductive region 120 can be higher than that of the epitaxial region 104. The fourth conductive region 120 can have a higher doping concentration than the first conductive region 106. The fourth conductive region 120 can have a higher doping concentration than the second and third conductive regions 108 and 110. Providing a fourth conductive region 120 with a higher doping concentration than the second and third conductive regions 108 and 110 can help achieve a sufficiently high holding voltage to provide latch-up immunity.

[0046] The heavily doped floating region 132 can have the same doping concentration as the heavily doped first terminal region 130 and second terminal region 134.

[0047] Among the multiple doped regions, substrate region 102 has the lowest doping concentration. When substrate isolation region 104 is an epitaxial region 103 or a deep well region, it has a higher doping concentration than substrate region 102. First conductive region 106 has a higher doping concentration than substrate isolation region 104 and / or substrate region 102. Second and third conductive regions 108 and 110 have the same doping concentration and are higher than the doping concentration of first conductive region 106. Fourth conductive region 120 has a higher doping concentration than second and third conductive regions 108 and 110. First terminal region 130, floating region 132, and second terminal region 134 have the same doping concentration and are also the highest doping concentration relative to other regions.

[0048] In some exemplary, non-limiting embodiments, the fourth conductive region 120 may further include a drift region 122 (e.g., a P-drift for an LV P-Well or an N-drift for an LV N-Well) along the boundaries of the second and third conductive regions 108, 110 (e.g., along the sidewalls 111 and 113 of the fourth conductive region 120). The drift region 122 may have approximately 5E16 cm. -3 Up to 1E17cm -3 The doping concentration range. Drift regions can help increase the breakdown voltage of ESD protection devices 100.

[0049] The ESD protection device 100 may also include a barrier or insulating layer 159 disposed above the top surface of the substrate 101. For example... Figure 1 As shown, the insulating layer 159 may be a silicide barrier layer 150 arranged extending between the second conductive region 108 and the third conductive region 110, overlapping at least a portion of these conductive regions 108, 110 and the fourth conductive region 120. In various non-limiting embodiments, the silicide barrier layer 150 may prevent silicides on the first terminal region 130, the second terminal region 134 and the floating region 132 from interacting or being processed (or in other words, prevent silicides deposited during the manufacture of the ESD protection device 100 from interacting with the first terminal region 130, the second terminal region 134 and the floating region 132). The insulating layer 159 serves to electrically insulate the floating region 132 from the terminal regions 130, 134. The silicide barrier layer 150 may be formed of any silicide barrier material known to those skilled in the art, such as, but not limited to, nitrides. The insulating layer 159 is needed because silicide material may be formed in any exposed or uncovered area on the surface of the substrate 101. Electrically, silicides function similarly to metals, and they short-circuit the floating region 132 and the terminal regions 130, 134 together. Silicide blocking materials (e.g., nitrides) prevent silicide formation in the covered areas, thus preventing short circuits.

[0050] The ESD protection device 100 may further include a first isolation element 140 and a second isolation element 142. The first isolation element 140 may be configured to isolate the second conductive region 108 and the first terminal region 130. The second isolation element 142 may be configured to isolate the third conductive region 110 and the second terminal region 134. The first isolation element 140 is disposed immediately below the top surface of the substrate 101, on the side of the first terminal region 130 and the second conductive region 108 opposite to the floating terminal region 132 and the fourth conductive region 120. The second isolation element 142 is disposed immediately below the top surface of the substrate 101, on the side of the second terminal region 134 and the third conductive region 110 opposite to the floating terminal region 132 and the fourth conductive region 120. That is, the first and second isolation elements 140 and 142 are disposed at the ends of the ESD protection device 100. For example, the first and second isolation elements 140 and 142 may be shallow trench isolation (STI) blocks.

[0051] When the ESD protection device 100 is in use, the ESD protection device 100 can also be configured to connect to a device ( Figure 1 (Not shown in the image), such as, but not limited to, consumer electronics products, i.e., devices to be protected by ESD protection device 100. In use, the device to be protected is connected to the first and second terminals 160, 162 of ESD protection device 100. The voltage between these terminals 160, 162 can be referred to as the ESD voltage. Depending on the ESD voltage, the first and second terminals 160, 162 can be emitters or collectors. That is, one of the first and second terminals 160, 162 can be an emitter, while the other of the first and second terminals 160, 162 can be a collector, depending on the direction of the voltage difference of the ESD voltage. When the ESD voltage is below a predetermined level, a negligible current flows through ESD protection device 100. However, when the ESD voltage exceeds the predetermined level, ESD protection device 100 turns on to divert the current away from the device, thereby protecting the device from damage.

[0052] In particular, in order to protect the device from damage due to excessive ESD voltage between terminals 160 and 162, the ESD protection device 100 can be configured such that when the difference between the first external voltage and the second external voltage exceeds a predetermined threshold, at least one discharge current can pass through the ESD protection device 100.

[0053] refer to Figure 1 and Figure 2The device can be configured, for example, to be connected to the first terminal region 130 and the second terminal region 134 via terminals 160 and 162. When the first external voltage is higher than the second external voltage, the pn (or np) junction at the first sidewall 111 between the fourth conductive region 220 and the second conductive region 108 can be reverse biased. Therefore, when the difference between the first external voltage and the second external voltage exceeds a first predetermined threshold, the pn junction at the first sidewall 111 may break down, and a first npn (or pnp) transistor can be turned on, which may include the second conductive region 108 as the collector, the fourth conductive region 120 as the base, and the third conductive region 110 as the emitter. Then, a first discharge current can flow from the emitter of the first npn transistor through the base to the collector. In other words, the first discharge current can flow through the fourth conductive region 120 between the second conductive region 108 and the third conductive region 110. Then, the first discharge current can turn on a second NPN (or PNP) transistor, which may include a third conductive region 110 as the emitter, a first conductive region 106 as the base, and an epitaxial region 104 as the collector. Then, a second discharge current can flow from the emitter of this second NPN (or PNP) transistor through the base to the collector. In other words, the first discharge current allows the second discharge current to flow through the first conductive region 106 between the epitaxial region 104 and the third conductive region 110.

[0054] When the second external voltage is higher than the first external voltage, the pn junction at the second sidewall 113 between the fourth conductive region 120 and the third conductive region 110 can also be reverse biased. Therefore, when the difference between the first and second external voltages exceeds a first predetermined threshold, the pn (or np) junction at the second sidewall 113 may break down and the first npn (or pnp) transistor can be turned on. This transistor may include the third conductive region 110 as the collector, the fourth conductive region 120 as the base, and the second conductive region 108 as the emitter. Then, a first discharge current can flow from the emitter of the first npn (or pnp) transistor through the base to the collector. In other words, the first discharge current can flow through the fourth conductive region 120 between the second conductive region 108 and the third conductive region 110. Then, the first discharge current can turn on the second npn (or pnp) transistor, which may include the second conductive region 108 as the emitter, the first conductive region 106 as the base, and the epitaxial region 104 as the collector. Then, the second discharge current can flow from the emitter of the second npn transistor through the base to the collector. In other words, the first discharge current allows the second discharge current to flow through the first conductive region 106 between the epitaxial region 104 and the second conductive region 108.

[0055] Therefore, as Figure 2As shown, in various non-limiting embodiments, the equivalent circuit of the ESD protection device 100 may include a transistor having a second conductive region 108 as an emitter (when the second external voltage is higher than the first external voltage) and a third conductive region 110 as an emitter (when the first external voltage is higher than the second external voltage). The first conductive region 106 can serve as the base regardless of the direction of the current flowing through the ESD protection device. It will be understood that if Figure 2 If the conductivity type is reversed in the illustrated embodiment, the direction of the current can be reversed.

[0056] Providing a substrate isolation region 103 (e.g., epitaxial region 104) and a first conductive region 106, and configuring these regions 103, 106 to be floating, allows the substrate isolation region 103 to act as the collector of the second NPN (or PNP) transistor, and allows the first conductive region 106 to act as the base of the first and second NPN (or PNP) transistors, regardless of the voltage polarity between the first and second terminal portions 108 / 130, 110 / 134 (in other words, regardless of which of the first and second external voltages is higher). Therefore, the ESD protection device 100 is capable of supporting bidirectional high-voltage bias and providing bidirectional ESD current conduction. In various non-limiting embodiments where the first external voltage can be higher than the second external voltage, the first external voltage can be a general supply voltage (e.g., VDD) and the second external voltage can be ground (e.g., GND), or the first external voltage can be positive and the second external voltage can be negative. In alternative non-limiting embodiments where the first external voltage can be lower than the second external voltage, the second external voltage can be a general supply voltage (e.g., VDD) and the first external voltage can be ground. Alternatively, the first external voltage can be negative, and the second external voltage can be positive.

[0057] Furthermore, in various non-limiting embodiments, as described above, both the first discharge current and the second discharge current of the ESD protection device 100 can help conduct current away from the device. This allows the ESD protection device 100 to have improved ESD current conduction capability.

[0058] In various non-limiting embodiments, the ESD protection device 100 may be compact and may have good clamping capability (i.e., minimize the variation in on-resistance) and high holding voltage to provide latch-up resistance. Figure 3 The TCAD simulation-like TLP IV curves of the Bi-NPN structures with different base lengths of the present invention are shown. Figure 3The performance of the ESD protection device 100 is shown when the base length of the ESD protection device 100 is set to 0.8 μm (301) and 1.2 μm (311) and the first external voltage is greater than the second external voltage. However, due to the symmetry of the structure of the ESD protection device 100, the results obtained when the second external voltage is greater than the first external voltage are different from those obtained when the base length of the ESD protection device 100 is greater than that ... Figure 3 The results shown are essentially the same. Specifically, Figure 300 is a plot of the relationship between transmission line pulse (TLP) current and transmission line pulse (TLP) voltage. Figure 300 shows the results obtained by simulating device 100 using Technology Computer-Aided Design (TCAD). Referring to Figure 300, the results show that device 100 with a base length of 0.8 μm can have a holding voltage (Vh) of approximately 12.0 V (at 303), a trigger voltage (Vt1) of approximately 13.0 V (at 305), a second breakdown voltage (Vt2) of approximately 23.5 V (at 307), and a second breakdown current (It2) of approximately 3.5 mA / μm (at 307). Furthermore, the results show that a device 100 with a base length of 1.2 μm can have a holding voltage (Vh) of approximately 14.0 V (at 313), a trigger voltage (Vt1) of approximately 16.0 V (at 315), a second breakdown voltage (Vt2) of approximately 27.5 V (at 317), and a second breakdown current (It2) of approximately 3.4 mA / μm (at 317). Figure 3 As shown, each of plots 301 and 311 illustrates a high holding voltage and a small snapback to provide latch-up-resistant ESD protection. For example, the holding voltage must be greater than the supply voltage (e.g., VDD) to avoid latch-up, and the holding voltage should be high to minimize the difference between the trigger voltage and the holding voltage (i.e., small snapback). These plots do not show the bending behavior common in unidirectional NPN devices. Bending behavior does not occur because the current flows more uniformly. Bending behavior is undesirable because it would mean a significant increase in on-resistance.

[0059] Figures 4A-4B A current density plot of a portion of the ESD protection device 100 is shown, obtained by simulating the ESD protection device 100 using TCAD. Figure 4A The current density plot for a discharge current of approximately 0.2 mA / µm is shown. Figure 4B A current density plot for a discharge current of approximately 2 mA / µm is shown. In the simulation, the first voltage (left terminal) is higher than the second voltage (right terminal). Figure 4A As shown, at a lower discharge current, a higher current density flows from the second conductive region 108 through the first conductive region 106 compared to reaching the third conductive region 110 through the fourth conductive region 120. Figure 4BAs shown, at higher discharge currents, a higher current density flows from the second conductive region 108 through the fourth conductive region 120 to the third conductive region 110 compared to the first conductive region 208. In other words, the current density plot indicates that for high discharge currents, the first discharge current can be higher than the second discharge current. This suggests that the ESD device 100 is initially triggered at the bottom. However, as the discharge current increases, the floating region 132 assists in collecting a large amount of higher current level current.

[0060] In various non-limiting embodiments, the implantation material used for substrate region 102, epitaxial region 104, first to fourth conductive regions 106, 108, 110, 120, terminal regions 130, 134, and floating region 132 can be the same implantation material, such as epitaxial silicon in a non-limiting embodiment. The P-type material can be, or is not limited to, epitaxial silicon-germanium, and / or the N-type material can be, or is not limited to, doped silicon containing N-type dopants. P-type dopants can include, for example, boron (B), aluminum (Al), indium (In), or combinations thereof, while N-type dopants can include carbon (C), phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof. Other types of implantation materials and dopants known to those skilled in the art can also be used to form regions 102, 104, 106, 108, 110, 120; terminal regions 130, 134; and floating region 132.

[0061] Figure 5 A simplified cross-sectional view of an ESD protection device 500 according to an alternative, non-limiting embodiment is shown. The ESD protection device 500 is similar to the ESD protection device 100; therefore, common features are labeled with the same reference numerals and need not be discussed further. Figure 5 As shown, the fourth conductive region 120' is similar to the fourth conductive region 120 of the ESD protection device 100, but the fourth conductive region 120' of the ESD protection device 500 does not overlap with the second and third conductive regions 108, 110. Furthermore, the substrate portion of the ESD protection device 500 can be further isolated from other devices in the substrate by vertical isolation elements (e.g., trenches) 170, 172. The vertical isolation elements 170, 172 can be deep trench isolation (e.g., DTI) structures that extend from the top surface of the substrate 101 into the substrate region 102 (i.e., the bulk substrate) of the substrate 101. For example, the vertical isolation elements 170, 172 can be arranged at the ends of the ESD protection device 500 adjacent to the first and second isolation elements 140, 142, respectively.

[0062] Figure 6A simplified cross-sectional view of an ESD protection device 600 according to an alternative, non-limiting embodiment is shown. The ESD protection device 600 is a bidirectional bipolar ESD protection device with a polybounded junction. The ESD protection device 600 is similar to the ESD protection device 100; therefore, common features are labeled with the same reference numerals and need not be discussed further. Figure 6 As shown, the barrier or insulating layer 159 of the ESD protection device 600 may include two multi-junction (e.g., polyblocks) 151a and 151b, instead of the silicide barrier layer 150. The polyblocks 151a and 151b may include: gate oxide regions 156a and 156b; polysilicon 158a and 158b; and spacers 154a and 154b for the polysilicon. The first polyblock 151a may insulate the floating region 132 from the first terminal region 130. The second polyblock 151b may insulate the floating region 132 from the second terminal region 134.

[0063] Figure 7 A simplified cross-sectional view of an ESD protection device 700 according to an alternative, non-limiting embodiment is shown. The ESD protection device 700 is a bidirectional bipolar ESD protection device formed using a silicon-on-insulator (SOI) structure. The ESD protection device 700 is similar to the ESD protection device 100; therefore, common features are labeled with the same reference numerals and need not be discussed further. Figure 7 As shown, the substrate isolation region 103 may include a buried oxide region 105 instead of an epitaxial region 103. The buried oxide region 105 may be disposed between the substrate region 102 and the first conductive region 106 (instead of an epitaxial region or deep well region) of the ESD protection device 100. The buried oxide region 105 can facilitate a thinner substrate. Oxide material is an insulating material that conducts almost no electrical current. Oxide material can be used to completely isolate bipolar devices from the substrate. The buried oxide layer 105 can provide better isolation performance.

[0064] Figure 8 A simplified cross-sectional view of an ESD protection device 800 according to an alternative, non-limiting embodiment is shown. Figure 8 ESD protection devices arranged in a stack are shown for use in higher voltage applications. ESD protection device 800 may include stacked two or more ESD protection devices 100 to facilitate greater current conduction. For example, as... Figure 8 As shown, the ESD protection device 800 may include a first ESD protection device 100a and a second ESD protection device 100b arranged adjacent to each other in the substrate 101. The first and second ESD protection devices 100a and 100b may each be... Figure 1ESD protection devices. Common features are marked with the same reference numerals and do not need to be discussed. Reference Figure 8 The substrate portions of the first and second ESD protection devices 100a and 100b can be isolated from each other by vertical isolation elements (e.g., trenches) 170, 172, and 174. The vertical isolation elements 170, 172, and 174 can be deep trench isolation (e.g., DTI) structures extending from the top surface of substrate 101 into substrate region 102 (i.e., the bulk substrate) of substrate 101. The vertical isolation elements can be arranged between each of two or more adjacent ESD protection devices (e.g., between the first and second ESD protection devices 100a and 100b) and at the ends of ESD protection devices configured as terminal ends (e.g., at the ends of the first and second ESD protection devices 100a and 100b).

[0065] refer to Figure 8 The first terminal region 130a of the first ESD protection device 100a can be configured to be connected to a first external voltage via a first external terminal 160', and the second terminal region 134b of the second ESD protection device 100b can be configured to be connected to a second external voltage via a second external terminal 162'. The second terminal region 134a of the first ESD protection device 100a can be connected to the first terminal region 130b of the second ESD protection device 100b via a terminal connector 165. The terminal connector 165 can be formed in the same layer as the external terminals 160' and 162' (e.g., a metal layer above the substrate).

[0066] For higher voltage ESD protection, additional ESD protection devices 100 can be arranged adjacent to each other in the substrate with their terminals connected in series. For example, the first terminal area of ​​the first ESD protection device can be configured to be connected to a first external voltage via a first external terminal, and the second terminal area of ​​the last ESD protection device can be configured to be connected to a second external voltage via a second external terminal. Each intermediate ESD protection device can be daisy-chained. For example, the first terminal area of ​​an intermediate ESD protection device can be connected to the second terminal area of ​​the preceding ESD protection device, and the second terminal area of ​​an intermediate ESD protection device can be connected to the first terminal area of ​​the following ESD protection device.

[0067] Alternatively, ESD protection devices 100a and 100b may also be one of ESD protection devices 500, 600, or 700.

[0068] Figure 9A A simplified cross-sectional view of an ESD protection device 900 according to an alternative, non-limiting embodiment is shown. Figure 9AAn ESD protection device configured for multi-terminal protection is shown. Specifically, Figure 9A An ESD protection device 900 for a three-terminal configuration is shown, wherein each terminal (160, 162, 164) is isolated from the other two terminals. For example, these three terminals could be a power supply terminal (e.g., VDD), an input / output terminal (e.g., IO), and a ground terminal (e.g., GND). The ESD protection device 900 can simultaneously provide bipolar ESD current conduction for both the VDD-to-I / O path and the I / O-to-ground path within a single configuration. Some parts of the ESD protection device 900 are similar to those of the ESD protection device 100; therefore, common features are labeled with the same reference numerals and need not be discussed further. Figure 9B A simplified schematic diagram of an ESD protection device 900 according to various aspects of this disclosure is shown. Figure 9B As shown, the ESD protection device 900 can be connected to another semiconductor device 901 (e.g., a consumer electronic device) and / or integrated with another semiconductor device 901 (e.g., a consumer electronic device) to provide ESD protection to the semiconductor device 901.

[0069] like Figure 9A As shown, the ESD protection device 900 may further include a third terminal portion. The third terminal portion may include a fifth conductive region 112, a third terminal region 138, and a third external terminal 164. The fifth conductive region 112 may be disposed within the substrate 101 and at least partially located above the first conductive region 106. The fifth conductive region 112 is similar to the second and third conductive regions 108 and 110. That is, the doping concentration is similar to that of the second and third conductive regions 108 and 110, and the conductivity type is the same as that of the second and third conductive regions 108 and 110. Furthermore, the second, third, and fifth conductive regions 108, 110, and 112 may be arranged to be spaced apart from each other within the first conductive region 106. At least a portion of the fifth conductive region 112 may also be disposed immediately below the top surface of the substrate 101. The fifth conductive region 112 may also be a medium-voltage well. The fifth conductive region 112 may also have the same second conductivity type as the second and third conductive regions 108 and 110. In some exemplary, non-limiting embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type. In this case, the fifth conductivity region 112 can also include an N-type dopant. Therefore, the fifth conductivity region 112 can also include a medium-voltage N-type well region (e.g., MV N-Well). However, in alternative, non-limiting embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type. In this case, the fifth conductivity region 111 can include a P-type dopant. Therefore, the fifth conductivity region 112 can include a medium-voltage P-type well region (e.g., MV P-Well).

[0070] Similarly, the fifth conductive region 112 may further include a corresponding terminal region. A third terminal region 138 may be at least partially disposed within the fifth conductive region 112. The third terminal region 138 may be configured to be connected to a third external voltage. For example, a first terminal region 130 may be configured to be connected to a power supply line (e.g., VDD), a second terminal region 134 may be configured to be connected to an input / output line, and the third terminal region 138 may be configured to be connected to ground.

[0071] The third terminal region 138 may also have the same second conductivity type as the fifth conductive region 112. The third terminal region 138 may be similar to the first and second terminal regions 130 and 134. That is, the doping concentration is similar and the conductivity type is the same. The third terminal region 138 may also include a heavily doped region. In some exemplary non-limiting embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the third terminal region 138 may also include an N-type dopant. Therefore, the third terminal region 138 may also be an N+ region like the first and second terminal regions. However, in alternative non-limiting embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type. In this case, the third terminal region 138 may include a P-type dopant. Therefore, the third terminal region 138 may also be a P+ region like the first and second terminal regions.

[0072] refer to Figure 9A In the exemplary, non-limiting embodiment shown, the third terminal region 138 may also be disposed immediately below the top surface of the substrate 101. The third terminal region 138 may be connected to a third external terminal 164 to which a third external voltage may be applied. Furthermore, the third terminal region 138 and the fifth conductive region 112 may be isolated from the substrate region 102 by the first conductive region 106 and the substrate isolation region 103 (e.g., epitaxial region 104).

[0073] The substrate 101 of the ESD protection device 900 may further include a sixth conductive region 124 disposed within the substrate 101 and at least partially located above the first conductive region 106. At least a portion of the sixth conductive region 124 may be adjacent to (i.e., in direct contact with) a portion of the first conductive region 106. The sixth conductive region 124 may be further centrally (e.g., equidistantly) disposed between the third conductive region 110 and the fifth conductive region 112. The sixth conductive region 124 may be adjacent to (i.e., in direct contact with) the third and fifth conductive regions 110, 112. A first sidewall 115 of the sixth conductive region 124 may be adjacent to the third conductive region 110, and a second sidewall 117 of the sixth conductive region 124 (opposite to the first sidewall) may be adjacent to the fifth conductive region 112. The sixth conductive region 124 is separated from the second and third terminal regions 134, 138 by at least a portion of the third and fifth conductive regions. Furthermore, in some embodiments, a portion of the sixth conductive region 124 may further overlap with a portion of the third conductive region 110, and another portion of the sixth conductive region 124 may further overlap with a portion of the fifth conductive region 112. This overlap can provide better performance for the ESD protection device.

[0074] The sixth conductive region 124 is similar to the fourth conductive region 120. That is, the doping concentration is similar and the conductivity type is the same. The sixth conductive region 124 can also be a low-voltage well region having a first conductivity type. In some exemplary non-limiting embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type. In this case, the sixth conductive region 124 can include a P-type dopant. Therefore, the sixth conductive region 124 can include a low-voltage P-type well (e.g., LV PWell). However, in alternative non-limiting embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type. In this case, the sixth conductive region 124 can include an N-type dopant. Therefore, the sixth conductive region 124 can include a low-voltage N-type well (e.g., LV NWell).

[0075] refer to Figure 9A In the exemplary, non-limiting embodiment shown, the sixth conductive region 124 may be disposed immediately below the top surface of the substrate 101. Furthermore, the sixth conductive region 124 may be separated from the substrate region 102 by the first conductive region 106 and the substrate isolation region 103 (e.g., the epitaxial region 104).

[0076] The sixth conductive region 124 may further include a second heavily doped floating (or unconnected) region 136. The second floating region 136 may be disposed within the sixth conductive region 124. The second floating region 136 may be disposed at the center of the sixth conductive region 124, such that the second floating region 136 is equidistant from the first sidewall 115 and the second sidewall 117 of the sixth conductive region 124. The second floating region 136 is similar to the floating region 132. In some exemplary non-limiting embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the first and second floating regions 132, 136 may include N-type dopant. Therefore, the first and second floating regions 132, 136 may also include N+ regions. However, in alternative non-limiting embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type. In this case, the first and second floating regions 132, 136 may include P-type dopant. Therefore, the first and second floating regions 132, 136 may include P+ regions.

[0077] refer to Figure 9A In the exemplary, non-limiting embodiment shown, the second floating region 136 may be disposed immediately below the top surface of the substrate 101. Furthermore, the second floating region 136 may be isolated from the substrate region 102 by the first conductive region 106 and the substrate isolation region 103 (e.g., epitaxial region 104).

[0078] In some exemplary, non-limiting embodiments, the sixth conductive region 124 may further include a drift region 126 (e.g., a P-drift for an LV P-Well or an N-drift for an LV N-Well) along the boundaries of the third and fifth conductive regions 110, 112 (e.g., along the sidewalls 115 and 117 of the sixth conductive region 124). The drift region helps to increase the breakdown voltage of the ESD protection device 900.

[0079] The ESD protection device 900 may also include a second barrier or insulating layer 159' disposed above the top surface of the substrate 101. For example... Figure 9A As shown, the second insulating layer 159' may be a second silicide barrier layer 152 arranged to extend between the third conductive region 110 and the fifth conductive region 112, overlapping at least a portion of these conductive regions 110, 112 and the sixth conductive region 124. Like the insulating layer 159, the second insulating layer 159' prevents the silicides on the second terminal region 134, the third terminal region 138, and the second floating region 136 from interacting or being processed (or in other words, prevents the silicides deposited during the manufacture of the ESD protection device 900 from interacting with the second terminal region 134, the third terminal region 138, and the second floating region 136). The insulating layer 159' serves to electrically insulate the second floating region 136 from the terminal regions 134, 138.

[0080] The ESD protection device 900 may further include a first isolation element 140' and a second isolation element 142'. The first isolation element 140' may be configured to isolate the second conductive region 108 and the first terminal region 130. The second isolation element 142' may be configured to isolate the fifth conductive region 112 and the third terminal region 138. The first isolation element 140' is disposed immediately below the top surface of the substrate 101, on the side of the first terminal region 130 and the second conductive region 108 opposite to the floating terminal region 132 and the fourth conductive region 120. The second isolation element 142' is disposed immediately below the top surface of the substrate 101, on the side of the third terminal region 138 and the fifth conductive region 112 opposite to the second floating terminal region 136 and the sixth conductive region 124. That is, the first and second isolation elements 140' and 142' are disposed at the ends of the ESD protection device 900. For example, the first and second isolation elements 140' and 142' may be shallow trench isolation (STI) blocks. Furthermore, the substrate portion of the ESD protection device 900 can be further isolated from other devices in the substrate by vertical isolation elements (e.g., trenches) 170', 172'.

[0081] Figure 10A and 10B A flowchart of a method 1000 for forming an ESD protection device according to various non-limiting embodiments is shown. Figure 10A As shown, method 1000 can begin by providing a substrate 101 (at 1002). Method 1000 may include forming (at 1004) a substrate region 102 of a first conductivity type within the substrate 101. Method 1000 may include forming (at 1006) a substrate isolation region 103 (e.g., an epitaxial region 104 or a buried oxide layer 105 having a second conductivity type) within the substrate 101 and at least partially over the substrate region 102. Method 1000 may include forming (at 1008) a first conductive region 106 of the first conductivity type within the substrate 101 and at least partially over the epitaxial region 104. Method 1000 may include forming (at 1010) second and third conductive regions 108, 110 of the second conductivity type within the substrate 101 and at least partially over the first conductive region 106. The second and third conductive regions 108, 110 are spaced apart from each other. Method 1000 may include forming a fourth conductive region 120 within substrate 101 and at least partially over the first conductive region 106 between the second and third conductive regions 108, 110 (at 1012). In some alternative, non-limiting embodiments, the fourth conductive region 120 may also be formed partially over portions of the second and third conductive regions 108, 110.

[0082] The substrate region 102, epitaxial region 104, buried oxide region 105, and first, second, third, and fourth conductive regions 106, 108, 110, and 120 can be formed using any method known to those skilled in the art. In a non-limiting example, each of these regions 102, 104, 106, 108, 110, and 120 can be formed by using a mask to expose a portion of the substrate 101 intended for the respective region 102, 104, 106, 108, 110, and 120, and doping the exposed portion with a suitable dopant (e.g., a P-type or N-type dopant). In a non-limiting example, the buried oxide region 105 can be formed by using a mask to expose a portion of the substrate 101 intended for the respective regions 102, 104, 106, 108, 110, and 120 and injecting oxygen into the exposed portion.

[0083] Next, method 1000 may include forming and configuring (at 1016) terminal regions 130, 134 and floating region 132. For example, at 1016, method 1000 may include forming a first terminal region 130 at least partially within a second conductive region 108, a second terminal region 134 at least partially within a third conductive region 110, and a floating region 132 at least partially within a fourth conductive region 120, and configuring the first terminal region 130 and the second terminal region 134 to be connected to a first external voltage and a second external voltage, respectively. In various non-limiting embodiments, terminal regions 130, 134 and floating region 120 may be formed by implanting dopant into corresponding portions of substrate 101. Dopant implantation may be performed by any method known to those skilled in the art, such as, but not limited to, ion implantation.

[0084] Method 1000 may further include forming (at 1018) a barrier or insulating layer 159 (e.g., a silicide barrier layer 150 or polysilicon blocks 151a, 151b) over substrate 101 to at least cover the fourth conductive region 120 and at least partially cover the second conductive region 108 and the third conductive region 110. The silicide barrier layer 150 may further completely cover the floating region 132 and the fourth conductive region 120 and at least partially cover the first terminal region 130, the second conductive region 108, the second terminal region 134, and the third conductive region 110. The silicide barrier layer 150 and the polysilicon blocks 151a, 151b may be formed using any method known to those skilled in the art. For example, in a non-limiting example, the silicide barrier layer 150 may be formed by depositing a silicide barrier material over the top surface of substrate 101 and etching the silicide barrier material.

[0085] Method 1000 may then include forming (at 1020) isolation elements 140, 142 (e.g., shallow trench isolation (STI) blocks). In various non-limiting embodiments, isolation elements 140, 142 may be formed by any method known to those skilled in the art. For example, a mask may be disposed over substrate 101 to expose portions of substrate 101 intended for isolation elements 140, 142, and the exposed portions may then be etched to form trenches, which may be filled with an isolation material.

[0086] Next, method 1000 may include forming deep isolation elements 170, 172, 174 (e.g., deep trench isolation (DTI) blocks) prior to forming the substrate region (at 1003). In various non-limiting embodiments, the deep isolation elements 170, 172 may be formed by any method known to those skilled in the art. For example, a mask may be disposed over substrate 101 to expose portions of substrate 101 intended for the deep isolation elements 170, 172, and the exposed portions may then be etched to form deep trenches, which may be filled with an isolation material.

[0087] The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Therefore, the foregoing embodiments are to be considered exemplary in all respects and not to limit the invention described herein. Accordingly, the scope of the invention is indicated by the appended claims rather than by the foregoing description, and all changes falling within the meaning and scope of equivalents of the claims are intended to be included therein.

Claims

1. An electrostatic discharge (ESD) protection device, comprising: A substrate, comprising a bipolar junction transistor disposed therein, including: A first doped region, a second doped region, and a third doped region, wherein the second doped region is disposed between the first doped region and the third doped region, wherein the second doped region has a first conductivity type and a first doping concentration, and the first doped region and the third doped region have a second conductivity type and a second doping concentration, and wherein the second doped region includes a first well region and a drift region; A first doped terminal region is disposed within the first doped region; A second doped terminal region is disposed within the third doped region; and A doped island region is disposed within the second doped region, wherein the first doped terminal region, the second doped terminal region, and the doped island region have a second conductivity type and a third doping concentration, the third doping concentration being higher than the first doping concentration and the second doping concentration; and A first conductive terminal is coupled to the first doped terminal region; A second conductive terminal, coupled to the second doped terminal region; and An insulating layer is disposed on the substrate between the first conductive terminal and the second conductive terminal, the insulating layer at least covering the second doped region.

2. The ESD protection device according to claim 1, wherein the doped island region is disposed along the top surface of the second doped region at the center of the second doped region, so as to be surrounded by the second doped region.

3. The ESD protection device according to claim 2, wherein the first doped region and the third doped region are spaced apart from each other, and the second doped region is symmetrically arranged between the first doped region and the third doped region.

4. The ESD protection device according to claim 1, wherein the first doped region and the third doped region each include a second well region.

5. The ESD protection device according to claim 4, further comprising: A fourth doped region is disposed within the substrate, wherein the first doped region, the second doped region, and the third doped region are disposed above the fourth doped region, the fourth doped region having the first conductivity type and the fourth doping concentration, and the fourth doped region including a third well region.

6. The ESD protection device according to claim 5, wherein the third doping concentration is higher than the first doping concentration, the first doping concentration is higher than the second doping concentration, and the fourth doping concentration is lower than the third doping concentration.

7. The ESD protection device according to claim 6 further includes: A fifth doped region is disposed within the substrate, wherein the first doped region, the second doped region, the third doped region, and the fourth doped region are disposed above the fifth doped region, the fifth doped region having the second conductivity type and including an epitaxial region or a buried oxide region.

8. The ESD protection device according to claim 7 further includes: A sixth doped region is disposed within the substrate, wherein the first doped region, the second doped region, the third doped region, the fourth doped region, and the fifth doped region are disposed above the sixth doped region, the sixth doped region having the first conductivity type and being a bulk substrate region isolated from the fourth doped region by the fifth doped region.

9. The ESD protection device according to claim 5, wherein the insulating layer is one of a silicide barrier layer or a polysilicon barrier layer.

10. The ESD protection device according to claim 5, wherein the depth of the first doped region is substantially the same as the depth of the third doped region, and the depth of the second doped region is substantially equal to or less than the depths of the first doped region and the third doped region.

11. The ESD protection device of claim 10, wherein the first sidewall of the second doped region is adjacent to the first doped region, and the second sidewall of the second doped region is adjacent to the third doped region.

12. The ESD protection device of claim 11, wherein the second doped region overlaps with at least a portion of the first doped region and at least a portion of the third doped region.

13. The ESD protection device of claim 12, wherein the first doped terminal region has a higher doping concentration than the first doped region, the second doped terminal region has a higher doping concentration than the third doped region, and the doped island region has a higher doping concentration than the second doped region.

14. The ESD protection device of claim 13, wherein the second doped region has a higher doping concentration than the first doped region or the third doped region.

15. The ESD protection device according to claim 5, further comprising: Another bipolar junction transistor, disposed in the substrate, includes another first doped region, another second doped region, and another third doped region, the second doped region being disposed between the first doped region and the third doped region, wherein the other second doped region has the first conductivity type and the first doping concentration, and the other first doped region and the other third doped region have the second conductivity type and the second doping concentration; Another first doped terminal region is disposed within the other first doped region; Another second doped terminal region is disposed within the other third doped region; Another doped island region is disposed within the other second doped region, wherein the other first doped terminal region, the other second doped terminal region, and the other doped island region have the second conductivity type and the third doping concentration; as well as Another first conductive terminal is coupled to the other first doped terminal region; Another second conductive terminal is coupled to the other second doped terminal region; as well as Another insulating layer is disposed on the substrate between the other first conductive terminal and the other second conductive terminal, the other insulating layer at least covering the other second doped region. The second conductive terminal is connected to the other first conductive terminal.

16. The ESD protection device according to claim 15, further comprising: A deep trench isolation element is disposed between the bipolar junction transistor and the other bipolar junction transistor, the deep trench isolation element extending from the top surface of the substrate to a body substrate region in the substrate.

17. The ESD protection device according to claim 8, further comprising: A seventh doped region is disposed within the substrate and spaced apart from the third doped region, the seventh doped region having the second conductivity type and the second doping concentration; A third doped terminal region is disposed within the seventh doped region, the third doped terminal region having the second conductivity type and the third doping concentration; The third conductive terminal is coupled to the third doped terminal region; An eighth doped region is disposed within the substrate between the third and seventh doped regions, the eighth doped region having the first conductivity type and the first doping concentration; A second doped island region is disposed within the eighth doped region, the second doped island region having the second conductivity type and the third doping concentration; as well as A second insulating layer is disposed on the substrate between the second conductive terminal and the third conductive terminal, the second insulating layer at least covering the eighth doped region.

18. The ESD protection device of claim 17 further includes a shallow trench isolation element disposed within the substrate and located only in the first doped terminal region and the third doped terminal region.

19. A method for forming an electrostatic discharge (ESD) protection device, comprising: A substrate is provided, the substrate including a bipolar junction transistor disposed therein, the substrate comprising: A first doped region, a second doped region, and a third doped region are provided, the second doped region being disposed between the first doped region and the third doped region, wherein the second doped region has a first conductivity type and a first doping concentration, and the first doped region and the third doped region have a second conductivity type and a second doping concentration, and wherein the second doped region includes a first well region and a drift region; A first doped terminal region is provided within the first doped region; Provides a second doped terminal region disposed within the third doped region; and Provides a doped island region disposed within a second doped region, wherein the first doped terminal region, the second doped terminal region, and the doped island region have a second conductivity type and a third doping concentration, the third doping concentration being higher than the first doping concentration and the second doping concentration; and Provide a first conductive terminal coupled to the first doped terminal region; Provides a second conductive terminal coupled to the second doped terminal region; and An insulating layer is provided on the substrate disposed between the first conductive terminal and the second conductive terminal, the insulating layer at least covering the second doped region.

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