A chip and battery system

Abstract

The application relates to a chip and battery system. The chip comprises a chip body and a balance discharge circuit arranged on the chip body, and the balance discharge circuit comprises: at least two switching devices, each of which is used for being coupled to the two ends of one of the at least two electric cores in series with a resistance outside the chip body; and a control circuit coupled to the two ends of each switching device and used for collecting the voltage of the electric core coupled to the disconnected switching device when the switching device is disconnected, and then determining whether to control at least one switching device to be turned on to balance discharge the coupled electric core according to the collected voltage of the electric core. The chip and battery system of the application can accurately collect the voltage of the electric core, facilitate heat dissipation, help to improve the upper limit of the balance discharge current, and facilitate user adjustment of the balance discharge current.

Description

Technical Field

[0001] This invention relates to the field of battery management technology, and more particularly to a chip and battery system. Background Technology

[0002] For battery packs that use multiple cells connected in series to achieve a higher battery output voltage, the voltage difference between cells increases over time due to capacity mismatch and varying degrees of aging. This voltage difference reduces the effective battery capacity. For example, during charging, the cell with the highest voltage triggers the overvoltage protection first, preventing the entire string from charging and the other cells from fully charging. Similarly, during discharging, the cell with the lowest voltage triggers the overvoltage protection first, preventing the entire string from discharging.

[0003] The worst-case scenario is a significant voltage difference between the battery cells, causing one cell's voltage to drop to near discharge overvoltage protection, while another cell's voltage rises to near charging overvoltage protection. Such a battery pack cannot be effectively charged or discharged, and must be prematurely decommissioned. Therefore, to better utilize the battery pack, it's necessary to manage the charge level of each cell. For example, a charge balancing design can be implemented for cells connected in series within the battery protection chip. However, this generates heat, making heat dissipation within the chip a bottleneck that limits the upper limit of the balanced discharge current. Summary of the Invention

[0004] The purpose of this invention is to overcome the above-mentioned technical problems and provide a chip and battery system that can accurately acquire the voltage of the battery cell, facilitate heat dissipation, improve the upper limit of the balanced discharge current, and make it convenient for users to adjust the balanced discharge current.

[0005] To achieve the above objectives, the present invention provides a chip comprising a chip body and a balanced discharge circuit disposed on the chip body. The balanced discharge circuit includes: at least two switching devices, each switching device being connected in series with a resistor outside the chip body and then coupled to the two ends of one of at least two series-connected battery cells; and a control circuit coupled to the two ends of each of the switching devices and configured to acquire the voltage of the battery cell coupled to the disconnected switching device when the switching device is disconnected, and then determine whether to control at least one switching device to conduct based on the acquired voltage of the battery cell, so as to perform balanced discharge on the coupled battery cell.

[0006] Optionally, the at least two switching devices are connected in series, with one end of the at least two connected switching devices used to couple to and ground the first end of the at least two connected cells, and the other end of the at least two connected switching devices used to couple to the second end of the at least two connected cells; the end of each switching device away from ground is used to couple to the resistor; in two adjacent switching devices, the resistor of the upper-level switching device coupled to the resistor of the lower-level switching device is connected in series and then coupled to the two ends of the cell corresponding to the upper-level switching device; and when the control circuit acquires the voltage of at least one cell, the control circuit controls the at least two switching devices to be turned off.

[0007] Optionally, the control circuit further includes a first inverter, wherein the lowest-level switching device is grounded and is an NMOS transistor, the control terminal of which is coupled to the input terminal of the first inverter, the output terminal of the first inverter is used to receive the control signal sent by the control circuit, the highest-level switching device is a PMOS transistor, and the switching device located between the at least two series-connected switching devices is one of the following: an NMOS transistor, a PMOS transistor, or a combination of an NMOS transistor and a PMOS transistor.

[0008] Optionally, the control circuit includes: at least two acquisition circuits or at least two comparison circuits, each acquisition circuit or each comparison circuit being coupled to both ends of one of the at least two switching devices; each acquisition circuit being used to acquire the voltage of the cell coupled to the switching device when the switching device is open; each comparison circuit being used to acquire the voltage of the cell coupled to the switching device when the switching device is open, and to compare the voltage of the cell with a set value and output a comparison result; control logic being used to output at least two first control signals, each first control signal being used to characterize whether the corresponding switching device needs to be opened to acquire the voltage of the cell coupled to the corresponding switching device; and the control logic being coupled to the output terminals of the at least two acquisition circuits or the at least two comparison circuits, and being used to output at least two second control signals according to the output results of the at least two acquisition circuits or the at least two comparison circuits, each second control signal being used to characterize whether the voltage of the cell coupled to the corresponding switching device is greater than the balance discharge threshold voltage; and a logic operation circuit being used to perform logic operations on at least one first control signal and at least one second control signal to output at least one control signal, each control signal being used to control the corresponding switching device to be turned off or on.

[0009] Optionally, the logic operation circuit includes: a first OR gate, including at least two input terminals, wherein the at least two input terminals of the first OR gate correspondingly receive the at least two first control signals, and the output terminal of the first OR gate is used to output a third control signal, wherein the third control signal is used to characterize whether all switching devices are turned off; and at least two second OR gates, wherein the first input terminal of each second OR gate is used to receive the first control signal corresponding to the coupled switching device, the second input terminal of each second OR gate is used to receive the third control signal, and the output terminal of each second OR gate is used to output the control signal and is coupled to the control terminal of one of the at least two switching devices.

[0010] Optionally, the second OR gate further includes a third input terminal, which is used to receive a fourth control signal. The fourth control signal is used to characterize whether all cells coupled to all switching devices need to undergo balanced discharge. When all cells coupled to all switching devices need balanced discharge, the fourth control signal is at a logic high level; when at least one cell coupled to a switching device does not need balanced discharge, the fourth control signal is at a logic low level. The control circuit further includes a third OR gate and a second inverter. The third OR gate includes at least two input terminals, each of which receives at least two second control signals. The output terminal of the third OR gate is coupled to the input terminal of the second inverter, and the output terminal of the second inverter is used to output the fourth control signal.

[0011] Optionally, each of the acquisition circuits or each of the comparison circuits further receives the first control signal, which is used to control whether the corresponding acquisition circuit or comparison circuit operates; wherein: the first control signal is a first logic level, which indicates that the corresponding switching device needs to be disconnected to acquire the voltage of the cell coupled to the corresponding switching device, and the first logic level also controls the corresponding acquisition circuit or comparison circuit to operate; the first control signal is a second logic level, which indicates that the corresponding switching device does not need to be disconnected to acquire the voltage of the cell coupled to the corresponding switching device, and the second logic level also controls the corresponding acquisition circuit or comparison circuit to stop operating.

[0012] Optionally, the chip further includes peripheral circuitry, which includes at least two resistors connected in series with the at least two switching devices.

[0013] Optionally, the chip is a battery protection chip, which integrates a battery protection circuit for protecting the at least two cells connected in series.

[0014] A second aspect of the present invention provides a battery system comprising: at least two cells connected in series; and a chip provided in the first aspect, wherein each switching device on the chip is connected in series with a resistor outside the chip body and then coupled to both ends of one of the at least two cells connected in series.

[0015] In the above scheme, each switching device is connected in series with a resistor outside the chip body and then coupled to the two ends of one of the at least two cells connected in series. The control circuit is coupled to the two ends of each switching device and collects the voltage of the cell coupled to the disconnected switching device when the switching device is disconnected. This can accurately collect the voltage of the cell. The resistor is set outside the chip body, which facilitates heat dissipation and helps to increase the upper limit of the balanced discharge current. At the same time, it is convenient for users to adjust the balanced discharge current by adjusting the size of the resistor.

[0016] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a passive equalization circuit.

[0019] Figure 2A This is a schematic diagram of the chip structure provided in the first embodiment of this application;

[0020] Figure 2B for Figure 2A The diagram shows a structural schematic of a variant of the chip.

[0021] Figure 3A This is a schematic diagram of the chip structure provided in the second embodiment of this application;

[0022] Figure 3B for Figure 3A The diagram shows a structural schematic of a variant of the chip.

[0023] Figure 4 This is a schematic diagram of the battery system provided in the first embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the battery system provided in the second embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Figure 1 This is a schematic diagram of a passive equalization circuit. Figure 1 As shown, the passive equalization circuit includes multiple batteries 110 connected in series and multiple equalization units 120, with each battery 110 connected to a corresponding equalization unit 120. Each equalization unit 120 includes a comparator 121, an equalization start voltage source 122, an equalization resistor 123, and a switching element 124.

[0027] One input of comparator 121 is electrically connected to the corresponding battery 110 to acquire the voltage of the corresponding battery 110, while its other input is electrically connected to the equalization start voltage source 122, thereby comparing the voltage of the corresponding battery 110 with the equalization start voltage provided by the equalization start voltage source 122 to generate a corresponding control signal.

[0028] The equalizing resistor 123 and the switching element 124 are connected in parallel to the positive and negative terminals of the corresponding battery 110, thereby forming an equalizing circuit. The switching element 124 is further connected to the output terminal of the comparator 121 to receive the control signal generated by the comparator 121. The control signal determines whether the switching element 124 is turned on. That is, the control signal determines whether the equalizing circuit formed by the equalizing resistor 123 and the switching element 124 performs an equalizing operation on the corresponding battery 110.

[0029] During charging, the comparator 121 in the equalization unit 120 collects the voltage of the corresponding battery 110 and compares it with the equalization start-up voltage provided by the equalization start-up voltage source 122. If the collected voltage of the corresponding battery 110 is higher than the equalization start-up voltage, the control signal issued by the comparator 121 controls the switch element 124 to close, and the equalization circuit formed by the equalization resistor 123 and the switch element 124 is opened, so that the equalization resistor 123 can discharge the corresponding battery 110 to consume the power of the corresponding battery 110. That is to say, during the charging process, the battery 110 with a higher state of charge reaches the equalization start-up voltage earlier, and its corresponding equalization circuit is open for a longer time, consuming more power, thereby achieving the purpose of equalizing the power of the batteries 110 in the battery pack.

[0030] The above solution has the following problems:

[0031] 1) In this passive balancing circuit, excess charge in each battery 110 is consumed by the corresponding balancing resistor 123. Therefore, the passive balancing circuit generates a significant amount of heat during operation. This is especially true when a significant number of batteries 110 have voltages higher than the balancing start-up voltage provided by the balancing start-up voltage source 122, requiring balancing operations. The heat generation then increases accordingly, making heat dissipation a serious problem. Therefore, the balancing current of this passive balancing circuit cannot be too large, limiting its balancing capability.

[0032] 2) The equalizing resistor 123 and the switching element 124 are connected in series and coupled to the two ends of the battery 110. The two input terminals of the comparator 121 are connected in parallel with the series equalizing resistor 123 and the switching element 124. Only the control signal output from the output terminal of the comparator 121 controls the conduction and cutoff of one switching element 124. That is, the conduction and cutoff of the switching element 124 in different equalizing units are independently controlled, which leads to inaccurate battery voltage detection results. In addition, if the voltage of all batteries is higher than the equalizing start voltage, all switching elements 124 are turned on, and all batteries undergo equalizing discharge, resulting in energy waste and large heat generation.

[0033] In view of this, this application provides a chip and battery system. In this chip and battery system, an external balancing discharge current-limiting resistor is used, and the balancing discharge switch is integrated only on the chip. This facilitates heat dissipation, helps to increase the upper limit of the balancing discharge current, and allows the user to easily adjust the balancing discharge current by adjusting the resistance value. Furthermore, the control circuit only samples the voltage drop across the balancing discharge switch, that is, directly samples the voltage from the drain and source of the balancing discharge switch transistor. When detecting the cell voltage, the balancing discharge switch, which might affect the detection result, can be prevented from conducting, thus ensuring accurate detection of the cell voltage.

[0034] Figure 2A This is a schematic diagram of the chip structure provided in the first embodiment of this application. Figure 2A As shown, the chip includes a chip body (not shown in the figure) and a balancing discharge circuit (circuit to the right of the dashed line in the figure) disposed on the chip body. The balancing discharge circuit includes a control circuit and at least two switching devices. Figure 2A The example shows at least two switching devices including MN(1), MP(2)...MP(n), each of which is connected in series with a resistor outside the chip body and then coupled to the two ends of one of the at least two cells connected in series.

[0035] The control circuit may include, for example, control logic, logic operation circuitry, at least two acquisition circuits, or at least two comparison circuits. The logic operation circuitry may include a first OR gate OR1 and at least two second OR gates such as OR21, OR22…OR2n. Furthermore, the control circuitry is coupled to both ends of each switching device; for example, each switching device may have an acquisition circuit or comparison circuit coupled to both ends. The control circuitry is used to acquire the voltage of the cell coupled to the disconnected switching device when the switching device is open, and then, based on the acquired cell voltage, determines whether to control at least one switching device to conduct, so as to perform balanced discharge on the coupled cell.

[0036] In the above scheme, each switching device is connected in series with a resistor outside the chip body and then coupled to the two ends of one of the at least two cells connected in series. The control circuit is coupled to the two ends of each switching device, and when the cell voltage is collected, the switching device that affects the cell voltage detection result can be disconnected. This can accurately collect the cell voltage. The resistor is placed outside the chip body, which facilitates heat dissipation and helps to increase the upper limit of the balanced discharge current. At the same time, it is convenient for users to adjust the balanced discharge current by adjusting the size of the resistor.

[0037] The control circuit may also include a first inverter INV1, the lowest level switching device (coupled to the negative terminal of the battery) is grounded and may be an NMOS transistor, the control terminal of which is coupled to the input terminal of the first inverter INV1, the output terminal of the first inverter INV1 is used to receive the control signal BAL_CTRL(1) sent by the control circuit, the highest level switching device (coupled to the positive terminal of the battery) may be a PMOS transistor, and the switching device located between at least two series-connected switching devices may be one of the following: an NMOS transistor, a PMOS transistor, or a combination of an NMOS transistor and a PMOS transistor.

[0038] In other words, the selection of the switching device type for the balanced discharge circuit on the chip can be as follows:

[0039] 1) When the discharge switch corresponding to the top-level cell is a PMOS, the control circuit is relatively simple. This is because if a charge pump is not used to pump the voltage above VDD, the highest voltage of the control signal inside the chip is the VDD potential. However, if the top-level switch is an NMOS, since its conduction requirement is VGS > Vth, there will inevitably be a voltage drop greater than Vth on the top-level switch. This voltage drop multiplied by the balancing discharge current will cause a large amount of on-chip heat generation. Therefore, the discharge switch corresponding to the top-level cell is a PMOS with its gate connected to a low potential for conduction.

[0040] 2) The discharge switch for the lowest-level cell is an NMOS. This is because unless an internal charge pump is used to generate a negative potential below ground, using a PMOS as a balance discharge switch at the lowest level would cause the PMOS switch to experience a voltage drop greater than Vth when it is turned on, resulting in a large amount of on-chip heat generation. Therefore, the discharge switch for the lowest-level cell is an NMOS, and a high potential can be output to its gate through logic conversion, such as the first inverter INV1, when the NMOS switch is turned on.

[0041] 3) The balance discharge switch corresponding to the intermediate stage cell can be PMOS and / or NMOS. It can be PMOS alone, NMOS alone, or a combination of PMOS and NMOS. At the same time, the corresponding control logic needs to be selected according to the type of switch.

[0042] Figure 2B for Figure 2A The diagram shows a structural schematic of a variant of the chip. Figure 2A The difference in the chip shown is that, Figure 2B The chip shown may also include peripheral circuitry, i.e. the circuitry to the left of the dashed line. The peripheral circuitry includes at least two resistors such as R(1), R(2) ... R(n-1), R(n), and the at least two resistors are connected in series with at least two switching devices such as MN(1), MP(2) ... MP(n).

[0043] Furthermore, in Figure 2A and Figure 2B In the chip shown, to reduce the number of pins (i.e., the number of wires extending from the right side of the dashed line to the left side), at least two switching devices such as MN(1), MP(2)...MP(n) can be connected in series. One end of the at least two connected switching devices is used to couple to the first end of the at least two connected cells, such as the negative terminal of a battery, and grounded. The other end of the at least two connected switching devices is used to couple to the second end of the at least two connected cells, such as the positive terminal of a battery. The end of each switching device away from ground is used to couple to a resistor. For example, one end of switching device MN(1) is grounded, and the other end is coupled to resistor R(1). The other end of switching device MP(2) away from switching device MN(1) is coupled to resistor R(2). In two adjacent switching devices, the resistors such as R(2) used for coupling the upper-level switching device such as MP(2) to the upper-level switching device and the resistors such as R(1) used for coupling the lower-level switching device such as MN(1) are connected in series and then connected in parallel to the two ends of the battery cell corresponding to the upper-level switching device such as MP(2); and when the control circuit collects the voltage of the battery cell, the control circuit controls at least two switching devices to be turned off.

[0044] For example, R(1) is connected in series with MN(1) and can be coupled between the two ends of cell (1), MP(2) is connected in series with R(2) and R(1) and can be coupled between the two ends of cell (2), MP(n) is connected in series with R(n) and R(n-1) and can be coupled between the two ends of cell (n), and cell (1), cell (2) ... cell (n) are connected in series in sequence.

[0045] Since the control circuit, such as the acquisition circuit or the comparison circuit, is coupled to both ends of each switching device, and at least two switching devices, such as MN(1), MP(2)...MP(n), are connected in series, the voltage detection result of the battery cell will be affected when the switching device is closed. Therefore, in order to ensure the accuracy of the voltage detection result of the battery cell, the switching device needs to be disconnected when the voltage is detected.

[0046] In other words, at least two switching devices can exist in, but are not limited to, the following two situations:

[0047] The first scenario involves at least two switching devices not connected in series. The upper-level switching device, such as MP(2), is connected in series with the resistor R(2) that is coupled to the upper-level switching device, but not with the resistor R(1) that is coupled to the lower-level switching device, such as MN(1). For example, R1 is connected in series with MN1 and can be coupled between the two ends of the cell (1); R2 is connected in series with MP2 and can be coupled between the two ends of the cell (2). R1 ​​is not connected in series with R2 and MP2, so when collecting the voltage of the cell, only the switching device corresponding to the cell whose voltage needs to be collected needs to be disconnected.

[0048] The second case involves at least two switching devices connected in series. The upper-level switching device, such as MP(2), is coupled to a resistor, such as R(2), and the lower-level switching device, such as MN(1), is coupled to a resistor, such as R(1), in series. For example, in… Figure 2B In the circuit, MP2 (upper stage) is connected in series with R2 (upper stage) and R1 (lower stage), and can be coupled between the two ends of the cell (2). Since the closing of other switching devices will also affect the detection result of the cell that needs to be detected, all switching devices will be turned off as long as one cell needs to be detected.

[0049] Furthermore, such as Figure 2B As shown, to filter power supply noise, the peripheral circuit may also include at least two capacitors, each corresponding to at least two resistors. One end of each capacitor is coupled to a resistor, and the other end is grounded. Figure 2BThe diagram exemplarily illustrates at least two capacitors including C(1), C(2), ..., C(n-1), C(n). For example, one end of C(1) is coupled to one end of R(1), and the other end is grounded; one end of C(2) is coupled to one end of R(2), and the other end is grounded; one end of C(n-1) is coupled to one end of R(n-1), and the other end is grounded; one end of C(n) is coupled to one end of R(n), and the other end is grounded.

[0050] in addition, Figure 2A and Figure 2B The chip can be a battery protection chip, which integrates battery protection circuitry to protect at least two cells connected in series. This "battery protection circuitry" can include overcharge protection, overcurrent / short circuit protection, and over-discharge protection. Furthermore, the battery protection circuitry can include separate control logic or share control logic with a balancing discharge circuit.

[0051] Continue to refer to Figure 2A and Figure 2B The acquisition circuit or comparison circuit can be coupled one-to-one with the switching device. The control logic is used to output at least two first control signals CELL_SCAN(n), which indicate whether it is necessary to disconnect the corresponding switching device to acquire the voltage of the cell coupled to the corresponding switching device; and the control logic is coupled to the output terminals of at least two acquisition circuits or at least two comparison circuits, and is used to output at least two second control signals BAL_DET(n) according to the output results of at least two acquisition circuits or at least two comparison circuits, which indicate whether the voltage of the cell coupled to the corresponding switching device is greater than the balance discharge threshold voltage.

[0052] The acquisition circuit acquires the voltage of the cell coupled to the switching device when the switching device is open. Then, the control logic compares the cell voltage acquired by the acquisition circuit with a set value and outputs at least two second control signals BAL_DET(n). The comparison circuit acquires the voltage of the cell coupled to the switching device when the switching device is open, compares the cell voltage with a set value, and outputs the comparison result. The control logic outputs at least two second control signals BAL_DET(n) based on the output results of at least two comparison circuits.

[0053] In addition, each acquisition circuit or each comparison circuit can also receive a first control signal CELL_SCAN(n), which is used to control whether the corresponding acquisition circuit or comparison circuit operates. Specifically: the first control signal CELL_SCAN(n) is a first logic level, such as a logic high level, indicating that the corresponding switching device needs to be disconnected to acquire the voltage of the cell coupled to the corresponding switching device, and the first logic level can also control the corresponding acquisition circuit or comparison circuit to operate; the first control signal CELL_SCAN(n) is a second logic level, such as a logic low level, indicating that the corresponding switching device does not need to be disconnected to acquire the voltage of the cell coupled to the corresponding switching device, and the second logic level can also control the corresponding acquisition circuit or comparison circuit to stop operating.

[0054] In one example, the comparison circuit may include a comparator, with a first output terminal of the comparator coupled to one end of a switching device, a second input terminal of the comparator coupled to the other end of a switching device, and a third output terminal of the comparator capable of receiving a first control signal CELL_SCAN(n). The comparator is used to compare the difference between the voltages input to the first and second input terminals with a preset value stored internally, and outputs the comparison result to the control circuit through its output terminal.

[0055] Furthermore, when the second control signal BAL_DET(n) is at a logic low level, it indicates that the voltage of the cell coupled to the corresponding switching device is greater than the balance discharge threshold voltage. When the second control signal BAL_DET(n) is at a logic high level, it indicates that the voltage of the cell coupled to the corresponding switching device is not greater than the balance discharge threshold voltage. Moreover, when the cell voltage is greater than the balance discharge threshold and cell voltage acquisition is not required, the corresponding switching device can be turned on for balance discharge (all switching devices can be turned off when all cell voltages are greater than the balance discharge threshold). When the cell voltage is less than the balance discharge threshold or cell voltage acquisition is required, the corresponding switching device is turned off.

[0056] The logic operation circuit may include, for example, a first OR gate OR1 and at least two second OR gates such as OR21, OR22, ..., OR(2n). The logic operation circuit can be used to perform logical operations on at least one first control signal (such as at least one of CELL_SCAN(1), CELL_SCAN(2), ..., CELL_SCAN(n)) and at least one second control signal (such as at least one of BAL_DET(1), BAL_DET(2), ..., BAL_DET(n)) to output at least one control signal (such as at least one of BAL_CTRL(1), ..., BAL_CTRL(n)). Each control signal (such as one of BAL_CTRL(1), ..., BAL_CTRL(n)) is used to control the corresponding switching device to be turned off or on.

[0057] The first OR gate OR1 may include at least two input terminals, which respectively receive at least two first control signals CELL_SCAN(n). The output terminal of the first OR gate OR1 is used to output a third control signal CELL_SCAN, which is used to characterize whether all switching devices are turned off. The first input terminal of each second OR gate, such as OR21, OR22...OR(2n), is used to receive the first control signal CELL_SCAN(n) corresponding to the switching device. The second input terminal of each second OR gate is used to receive the third control signal CELL_SCAN. The output terminal of each second OR gate is used to output a control signal BAL_CTRL(n) and is coupled to the control terminal of one of the at least two switching devices.

[0058] Figure 3A This is a schematic diagram of the chip structure provided in the second embodiment of this application. Figure 2A The difference in the chip shown is that, Figure 3A Each of the second OR gates of the chip shown also includes a third input terminal, which is used to receive a fourth control signal STOP_BAL. The fourth control signal STOP_BAL is used to characterize whether all the cells coupled to the switching devices need to be balanced discharged.

[0059] In this circuit, all cells coupled to the switching devices require balancing discharge, and the fourth control signal STOP_BAL is at a logic high level. If at least one cell coupled to a switching device does not require balancing discharge, the fourth control signal STOP_BAL is at a logic low level. The control circuit also includes a third OR gate and a second inverter INV2. The third OR gate OR3 has at least two inputs, each receiving at least two second control signals BAL_DET(n). The output of the third OR gate OR3 is coupled to the input of the second inverter INV2, which outputs the fourth control signal STOP_BAL. Therefore, the function of the third OR gate OR3 and the second inverter INV2 is as follows: if the voltage of all cells is higher than the balancing threshold voltage, then all cells no longer require balancing discharge, and all switching devices are turned off.

[0060] In other words, when the cell voltage is higher than the equilibrium discharge threshold voltage, the switching devices need to be turned on to discharge; however, when the voltage of all cells is higher than the equilibrium threshold voltage, all cells can stop balancing discharge, and all switching devices are turned off.

[0061] Figure 3B for Figure 3A The diagram shows a structural schematic of a variant of the chip. Figure 3A The difference in the chip shown is that, Figure 3B The chip shown also includes peripheral circuitry; for details on peripheral circuitry, please refer to [link / reference needed]. Figure 2B Information about the location.

[0062] Figure 4 This is a schematic diagram of the battery system provided in the first embodiment of this application. Figure 4 As shown, the battery system includes at least two cells connected in series, such as Cell(1), Cell(2), ..., Cell(n), and the chip described in the first embodiment above. Each switching device on the chip is connected in series with at least one resistor outside the chip body and then coupled to the two ends of one of the at least two cells connected in series. Wherein, if the chip is... Figure 2A The chip shown also includes peripheral circuits such as resistors R(1), R(2)...R(n-1), R(n) and capacitors such as C(1), C(2)...C(n-1), C(n).

[0063] Continue to refer to Figure 4 One end of at least two series-connected switching devices such as MN(1), MP(2)...MP(n) is coupled to the first end of at least two series-connected cells such as Cell(1), Cell(2)...Cell(n) as the negative terminal of the battery and grounded. The other end of at least two series-connected switching devices such as MN(1), MP(2)...MP(n) is coupled to the second end of at least two series-connected cells such as Cell(1), Cell(2)...Cell(n) as the positive terminal of the battery.

[0064] The acquisition circuit or comparison circuit is coupled to both ends of each switching device and is used to acquire the voltage of the cell coupled to the disconnected switching device when the switching device is disconnected. Then, the control logic determines whether to control at least one switching device to conduct based on the acquired cell voltage in order to perform balanced discharge on the coupled cell.

[0065] Figure 5 This is a schematic diagram of the battery system provided in the second embodiment of this application. Figure 5 As shown, the battery system includes at least two cells (Cell(1), Cell(2)...Cell(n)) connected in series and the chip of the second embodiment described above. Each switching device on the chip is connected in series with at least one resistor outside the chip body and then coupled to the two ends of one of the at least two cells connected in series. Wherein, if the chip is... Figure 3A The chip shown also includes peripheral circuits such as resistors R(1), R(2)...R(n-1), R(n) and capacitors such as C(1), C(2)...C(n-1), C(n).

[0066] exist Figure 4 and Figure 5 The diagram illustrates a battery system comprising n series-connected cells. The left side of the dashed line represents the circuit diagram outside the chip, and the right side of the dashed line represents the circuit diagram inside the chip body. MN(1) is the balance discharge switch for the first cell Cell(1), MP(2) is the balance discharge switch for the second cell Cell(2), and MP(n) is the balance discharge switch for the topmost cell Cell(n).

[0067] like Figure 4 As shown, the voltage sampling and detection module, i.e., the acquisition circuit or comparison circuit, takes voltages from the source and drain terminals of the balancing discharge switch transistor, respectively. CELL_SCAN(n) acts as an enable signal (high enable) to control the operation of the voltage sampling and detection module. The control logic determines when to perform cell voltage detection through the output signal CELL_SCAN(n), and based on the judgment result of the voltage sampling and detection module on the voltage of the nth cell, the output signal BAL_DET(n) determines whether to perform balancing discharge on the nth cell. For example, when the BAL_DET(n) output is low, it indicates that the control logic determines that balancing discharge can be performed. CELL_SCAN is a logical OR of all CELL_SCAN(n) signals; that is, as long as the chip detects the cell voltage of any cell, CELL_SCAN is high, and the switching device can be turned off.

[0068] BAL_CTRL(n) is a signal that controls the balancing discharge switch. A high logic value disables balancing discharge, while a low logic value enables it. This signal is the result of a logical OR operation between BAL_DEL(n) and CELL_SCAN. Therefore, as long as CELL_SCAN is high, even if BAL_DEL(n) is low, BAL_CTRL(n) will still be high, disabling balancing discharge. This is because when only balancing discharge switches are built-in and at least two switches are connected in series, balancing discharge in a cell will not only distort the voltage detection of that cell but also cause distortion in the voltage detection of adjacent cells. Therefore, when voltage detection is performed on any cell, all balancing discharge switches within the chip must be turned off to ensure that the true cell voltage is detected.

[0069] like Figure 5 As shown, when all BAL_DET(1) to BAL_DET(n) are low, the third OR gate OR3 outputs low, which is then inverted by the second inverter INV2, making STOP_BAL high and forcing all balance discharge switches to turn off.

[0070] In summary, due to the current-limiting resistor and switch being built into the chip, and the comparator detecting the voltage drop across the resistor and switch, heat dissipation within the chip becomes a bottleneck limiting the upper limit of the balancing discharge current. The chip and battery system of this application externalizes the balancing discharge current-limiting resistor, integrating only the balancing discharge switch on the chip body. The comparator is coupled across the two ends of the balancing discharge switch. When detecting the cell voltage, the balancing discharge switch is disabled to ensure accurate cell voltage detection. Simultaneously, during balancing discharge, the heat source in the balancing discharge path, such as the resistor, is placed outside the chip, increasing the allowable upper limit of the balancing discharge current. Furthermore, it allows users to easily adjust the balancing discharge current by adjusting the resistor value.

[0071] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0072] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip, characterized in that, The chip includes a chip body and a balancing discharge circuit disposed on the chip body, the balancing discharge circuit comprising: At least two switching devices, each of which is connected in series with a resistor outside the chip body and then coupled to the two ends of one of the at least two cells connected in series; A control circuit is coupled to both ends of each of the switching devices and is used to acquire the voltage of the cell coupled to the disconnected switching device when the switching device is disconnected, and then determine whether to control at least one switching device to conduct based on the acquired cell voltage, so as to perform balanced discharge on the coupled cell. The control circuit includes: At least two acquisition circuits or at least two comparison circuits are provided, each of the acquisition circuits or each of the comparison circuits being coupled to both ends of one of the at least two switching devices. Each acquisition circuit is used to acquire the voltage of the cell coupled to the switching device when the switching device is open, and each comparison circuit is used to acquire the voltage of the cell coupled to the switching device when the switching device is open, and compare the voltage of the cell with a set value and output a comparison result. The control logic is configured to output at least two first control signals, each first control signal being configured to characterize whether the corresponding switching device needs to be disconnected to acquire the voltage of the cell coupled to the corresponding switching device; and the control logic is coupled to the output terminals of the at least two acquisition circuits or the at least two comparison circuits, and is configured to output at least two second control signals based on the output results of the at least two acquisition circuits or the at least two comparison circuits, each second control signal being configured to characterize whether the voltage of the cell coupled to the corresponding switching device is greater than the balance discharge threshold voltage; A logic operation circuit is used to perform logical operations on at least one first control signal and at least one second control signal to output at least one control signal, each of the control signals being used to control the corresponding switching device to be turned off or on.

2. The chip according to claim 1, characterized in that, The at least two switching devices are connected in series, one end of the at least two switching devices connected in series is used to be coupled to and grounded to the first end of the at least two battery cells connected in series, and the other end of the at least two switching devices connected in series is used to be coupled to the second end of the at least two battery cells connected in series. The end of each switching device away from ground is used to be coupled to the resistor. In two adjacent switching devices, the resistor used by the upper-level switching device to be coupled to the resistor used by the lower-level switching device is connected in series and then coupled to the two ends of the corresponding cell of the upper-level switching device. Furthermore, when the control circuit acquires the voltage of at least one battery cell, the control circuit controls both of the at least two switching devices to turn off.

3. The chip according to claim 1 or 2, characterized in that, The control circuit further includes a first inverter, wherein the lowest-level switching device is grounded and is an NMOS transistor, the control terminal of which is coupled to the input terminal of the first inverter, the output terminal of the first inverter is used to receive the control signal sent by the control circuit, the highest-level switching device is a PMOS transistor, and the switching device located between the at least two series-connected switching devices is one of the following: an NMOS transistor, a PMOS transistor, or a combination of an NMOS transistor and a PMOS transistor.

4. The chip according to claim 1, characterized in that, The logic operation circuit includes: The first OR gate includes at least two input terminals, which respectively receive the at least two first control signals. The output terminal of the first OR gate is used to output a third control signal, which is used to characterize whether all switching devices are turned off. At least two second OR gates, each second OR gate having a first input terminal for receiving a first control signal corresponding to a coupled switching device, a second input terminal for receiving the third control signal, and an output terminal for outputting the control signal and being coupled to the control terminal of one of the at least two switching devices.

5. The chip according to claim 4, characterized in that: The second OR gate further includes a third input terminal, which is used to receive a fourth control signal. The fourth control signal is used to characterize whether all cells coupled to all switching devices need to undergo balanced discharge. Wherein, when all cells coupled to all switching devices need to undergo balanced discharge, the fourth control signal is at a logic high level; when at least one cell coupled to at least one switching device does not need to undergo balanced discharge, the fourth control signal is at a logic low level. The control circuit further includes a third OR gate and a second inverter. The third OR gate includes at least two input terminals, which respectively receive at least two second control signals. The output terminal of the third OR gate is coupled to the input terminal of the second inverter, and the output terminal of the second inverter is used to output the fourth control signal.

6. The chip according to any one of claims 1, 4, or 5, characterized in that, Each of the acquisition circuits or each of the comparison circuits further receives the first control signal, which is used to control whether the corresponding acquisition circuit or comparison circuit operates; wherein: The first control signal is a first logic level, which indicates that the corresponding switching device needs to be disconnected in order to acquire the voltage of the cell coupled to the corresponding switching device. Furthermore, the first logic level also controls the corresponding acquisition circuit or comparison circuit to operate. The first control signal is a second logic level, which indicates that it is not necessary to disconnect the corresponding switching device to acquire the voltage of the cell coupled to the corresponding switching device. Furthermore, the second logic level also controls the corresponding acquisition circuit or comparison circuit to stop working.

7. The chip according to any one of claims 1, 2, 4, and 5, characterized in that, The chip also includes peripheral circuitry, which includes at least two resistors connected in series with the at least two switching devices.

8. The chip according to any one of claims 1, 2, 4, and 5, characterized in that, The chip is a battery protection chip, which integrates a battery protection circuit. The battery protection circuit is used to protect the at least two cells connected in series.

9. A battery system, characterized in that, include: At least two battery cells connected in series; The chip according to any one of claims 1-8, wherein each switching device on the chip is connected in series with a resistor outside the chip body and then coupled to both ends of one of the at least two cells connected in series.

Images