Method and apparatus for adaptive output sampling for power converters

Abstract

The present disclosure relates to methods and apparatus for adaptive output sampling of power converters. A method of operating a DC-DC power converter in a low power burst mode, the method comprising: sampling an output voltage of the DC-DC power converter at a sampling frequency to determine when to initiate a burst for the low power burst mode; and adapting the sampling frequency based on the output voltage.

Description

Technical Field

[0001] The present invention generally relates to systems and methods for adapting the sampling frequency of a power converter output in a low-power burst operation mode. Background Technology

[0002] Power converters can operate in low-power burst mode to conserve power resources. When burst mode is enabled, the power converter is turned on and off as needed to maintain a minimum voltage level, using less power than continuous operation. Bursts are used as needed to maintain the converter's output. In discrete-time burst mode, the voltage level is monitored by sampling the power converter's output to determine if a burst is needed. The monitoring circuitry and its auxiliary equipment are turned on at the sampling frequency. If the sampling frequency is too low, transient fluctuations in the output load may be missed. If the sampling frequency is too high, resources may be wasted by unnecessarily turning the monitoring equipment on and off. Therefore, the efficiency and effectiveness of burst mode are affected by the sampling frequency. Summary of the Invention

[0003] According to one embodiment, a method for operating a DC-DC power converter in a low-power burst mode includes: sampling the output voltage of the DC-DC power converter at a sampling frequency to determine when to initiate a burst for the low-power burst mode; and adapting the sampling frequency based on the output voltage.

[0004] According to one embodiment, a system for setting the sampling frequency of the output voltage of a DC-DC power converter during a low-power burst mode of the DC-DC power converter includes: a frequency adaptation circuit configured to receive a clock signal having a first frequency and output an adapted clock signal having an adapted frequency depending on the output voltage of the DC-DC power converter; and a voltage monitoring circuit enabled by the adapted clock signal to sample the output voltage of the DC-DC power converter using the adapted frequency.

[0005] According to one embodiment, a system providing an adaptive sampling frequency for sampling the output voltage of a DC-DC power converter in a low-power burst mode includes: an oscillator configured to generate a clock signal; a frequency adaptation circuit configured to receive the clock signal and output an adapted clock signal including an adapted sampling frequency determined by a frequency selection signal; and a tracking circuit configured to receive data indicating when a burst for the low-power burst mode is initiated, and output data depending on the frequency selection signal. Attached Figure Description

[0006] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0007] Figure 1 A system for operating a DC-DC power converter in low-power burst mode is shown;

[0008] Figure 2 A system is described in which the sampling frequency of the voltage of the electrical load is adaptively set during a low-power burst mode in one embodiment;

[0009] Figure 3 A system for setting the sampling frequency of a voltage for regulating an electrical load during a low-power burst mode, according to one embodiment, is described.

[0010] Figure 4 A flowchart depicting a method 400 for operating a power converter in a low-power burst mode with adaptive sampling in one embodiment is shown;

[0011] Figure 5 A flowchart is shown illustrating a method for depicting an observation window of a low-power burst mode implementing an embodiment of adaptive sampling;

[0012] Figure 6 One embodiment of a system for adapting the sampling frequency of a power converter output in low-power burst mode is described; and

[0013] Figure 7 A flowchart depicts a step-by-step method for operating a power converter in low-power burst mode according to one embodiment. Detailed Implementation

[0014] DC-DC power converters have many known applications, such as providing regulated, controlled output voltages from unregulated input voltages. Unfortunately, when a DC-DC converter has low output power (low current or voltage), its efficiency decreases due to the increased ratio of switching losses to output power. DC-DC converters can be configured to operate in low-power burst modes to improve converter efficiency during low-power operation of the device.

[0015] Figure 1 A system 100 for operating a DC-DC power converter in discrete-time low-power burst mode is described.

[0016] System 100 includes a power supply 102 to provide an unregulated input voltage (VIN) to a DC-DC converter bridge 104. During normal operation, the DC-DC converter bridge 104 provides a regulated output voltage (VOUT) to the output 106 based on a drive signal 108A.

[0017] During low-power operation, the DC-DC converter bridge 104 is driven only in intermittent bursts when the output needs to return to the appropriate level for low-power operation. When the DC-DC converter bridge 104 is driven continuously to provide some power efficiency, the system 100 uses less power between bursts compared to normal operation. However, these efficiencies are limited by the sampling frequency used to monitor power demand.

[0018] In system 100, the sampling frequency is determined by clock signal 114A. Clock signal 114A is received by control logic circuitry 110. Control logic circuitry 110 periodically enables sampling of the output of DC-DC converter bridge 104 according to the frequency of clock signal 114A by providing enable signal 110B to voltage monitor 116 and auxiliary analog block 118. Auxiliary analog block 118 may include components for further sampling the output voltage to support the operation of voltage monitor 116 and initiating bursts. Voltage monitor 116 senses the voltage at output 106 and communicates with control logic circuitry 110. When needed, control logic circuitry 110 triggers command signal 110A to bridge driver 108 to initiate a burst. Bridge driver 108a responds to drive DC-DC converter bridge 104 according to the command signal, which raises the voltage level at output 106.

[0019] A burst is determined by the level of the output voltage sensed by voltage monitor 116. If the sampled voltage drops below a threshold, a burst is initiated. Otherwise, voltage monitor 116 and auxiliary circuitry are de-energized to await the next sample. Voltage monitor 116 and auxiliary analog block 118 consume power each time the output voltage is sampled. Therefore, more samples equal more power consumption. As a result, the higher the sampling frequency of the output voltage, the less efficient the burst mode becomes. However, if the sampling frequency is too low, transient fluctuations in the output voltage may be missed, creating complexity in system 100 or other devices receiving regulated power at output 106. A static sampling frequency limits the system's efficiency because the sampling remains the same regardless of load changes.

[0020] The efficiency of a DC-DC converter can be improved by using an adapted clock signal to determine the sampling frequency used to monitor the output voltage. The adapted clock signal can be adjusted with load changes, so unwanted sampling is cut off when the output load decreases. Furthermore, the sampling rate can be increased as the load increases, so transient fluctuations are not missed. In various embodiments, adaptive sampling frequencies can also produce more predictable power efficiency benefits. With a static sampling frequency, the system efficiency changes because the burst-to-sample ratio will vary with load. However, an adapted frequency allows for a more consistent maintenance of the burst-to-sample ratio, or even pinning the burst-to-sample ratio to each other. Therefore, the efficiency of such devices and methods can be more predictable. In various embodiments, it may be advantageous to keep the sampling frequency at least twice the burst frequency, according to the general Shannon theorem for sampling, which states that the sampling frequency must be at least the signal frequency in order to reconstruct the signal.

[0021] Figure 2 A system is described that adaptively sets the sampling frequency of the regulated voltage of an electrical load during a low-power burst mode 200 in one embodiment.

[0022] System 200, which adaptively sets the sampling frequency of the regulated voltage of an electrical load during low-power burst modes, may include frequency adaptation circuitry 215. In various embodiments, frequency adaptation circuitry 215 may be digital. Frequency adaptation circuitry 215 may receive clock signal 214A. Frequency adaptation circuitry 215 may also communicate (directly or indirectly) with voltage monitor 216. It will be understood that voltage monitors may be implemented in different ways in various embodiments. For example, a comparator may compare the output voltage with a reference voltage, or the output voltage may be converted to an equivalent current and then compared with a reference current. In various embodiments, output signal 216A from voltage monitor 216 may be provided to frequency adaptation circuitry 215. Voltage monitor 216, when enabled, may sense the voltage at the output 206 of a power converter (such as a DC-DC power converter).

[0023] Frequency adaptation circuit 215 can output an adapted clock signal 215A, which depends on clock signal 214A and the voltage at output 206 sensed by voltage monitor 216. In various embodiments, the frequency of clock signal 214A can be constant. The adapted clock signal 215A can be adapted to account for variations in the load coupled to the DC-DC converter to improve system power efficiency, thereby setting the sampling frequency of the regulated output voltage of the electrical load during low-power burst mode 200.

[0024] For example, the frequency of the adapted clock signal 215A can increase with increasing load and decrease with decreasing load. The adapted clock signal 215A can then be used to enable and disable the voltage monitor 216 and the auxiliary analog block 218 to sample the output voltage using the frequency determined by the adapted clock signal 215A. A burst may or may not be initiated depending on the voltage at output 206. In various embodiments, the frequency adaptation circuit 215 may include a programmable divider that divides the frequency of the clock signal 214A to generate the adapted clock signal 215A. The divisor used for the programmable divider may be determined based on sampling of the voltage level sensed by the voltage monitor 216. In various embodiments, a programmable multiplier may be used to generate the adapted clock signal 215A, which is the product of the clock signal 214A. The multiplier used for the programmable multiplier may be determined based on the voltage level sensed by the voltage monitor 216.

[0025] Figure 3 A system 200, according to one embodiment, is described for setting the sampling frequency of an regulated output of an electrical load during a low-power burst mode.

[0026] In various embodiments, system 200 for setting the sampling frequency of the regulated output voltage of the electrical load during low-power burst modes may include a DC-DC converter bridge 204. DC-DC converter bridge 204 may receive a voltage supply (VIN) 202. DC-DC converter bridge 204 provides a regulated output voltage to output 206 based on drive signal 208A.

[0027] During low-power burst mode operation, when more power is needed, the DC-DC converter bridge 204 can be driven in intermittent bursts, which can be determined by the voltage level sensed at output 206 by voltage monitor 216. Voltage monitor 216 can monitor the voltage at output 206 using a frequency determined by an adapted clock signal 215A.

[0028] System 200 for setting the sampling frequency of the regulated output voltage of an electrical load during low-power burst modes may include an oscillator 214 to provide a clock signal 214A to frequency adaptation circuitry 215. In various embodiments, oscillator 214 may include a low-frequency oscillator. Utilizing a low-frequency oscillator may be advantageous for limiting the power requirements of oscillator 214.

[0029] In various embodiments, the operation of oscillator 214 may be triggered by a burst mode enable signal. The burst mode enable signal 217 may include a flag indicating when the system is in a low-power mode (such as standby mode). It should also be understood that the burst mode enable signal 217 may also be triggered by operating conditions such as current drawn by the load. In various embodiments, other conditions may trigger a change to the burst operating mode.

[0030] When in a low-power burst mode (e.g., when enabled by burst mode enable signal 217), oscillator 214 can output clock signal 214A. In various embodiments, oscillator 214 may operate only when enabled by burst mode enable signal 217.

[0031] Clock signal 214A can be received by frequency adaptation circuit 215, which can adapt the signal based on the output load measured by sampling the regulated output voltage. Frequency adaptation circuit 215 can output the adapted clock signal 215A to control logic circuit 210. Then, control logic circuit 210 can enable sampling of the output of DC-DC converter bridge 204 according to the frequency of the adapted clock signal 215A by providing enable signal 210B to voltage monitor 216 and auxiliary analog block 218.

[0032] The auxiliary analog block 218 may include: a reference voltage generator for the voltage monitor 216, a bias circuit for the voltage monitor 216, an oscillator for timing output bursts, and other circuitry supporting the operation of the voltage monitor 216 or the converter. The adapted clock signal 215A may have initial or default settings. In various embodiments, the initial frequency of the adapted clock signal 215A may be equal to the frequency of the clock signal 214A.

[0033] Voltage monitor 216 can sense the voltage at output 206 and communicate with control logic circuitry 210 when enabled. Output signal 216A from voltage monitor 216 can be provided to control logic circuitry 210. Control logic circuitry 210 can trigger command signal 210A to bridge driver 208 to initiate a burst based on the sampled voltage when needed. The burst can increase the voltage level at output 206.

[0034] The need for a burst can be determined based on the output voltage sensed by voltage monitor 216. If the sampled voltage drops below a threshold, control logic circuit 210 can initiate a burst. Command signal 210A can be provided to bridge driver 208. Furthermore, the bridge driver can provide switching signals for the operation of DC-DC converter bridge 204. If the output voltage sampled by voltage monitor 216 is higher than the threshold, voltage monitor 216 and auxiliary circuitry can be de-energized to await the next sample.

[0035] In various embodiments, voltage monitor 216 can transmit the voltage sampled at output 206 to control logic circuitry 210 via output signal 216A. Control logic circuitry 210 can provide frequency command or frequency selection signal 210C to frequency adaptation circuitry 215. In various embodiments, output signal 216A can be provided directly to frequency adaptation circuitry 215.

[0036] The frequency selection signal 210C can be adjusted based on the voltage sampled at output 206. Furthermore, the frequency adaptation circuit 215 can change the frequency of the adapted clock signal 215A based on the frequency selection signal 210C. For example, the frequency adaptation circuit 215 may include a frequency divider, wherein the frequency of the clock signal 215A is the quotient of the frequency of the clock signal 214A and a divisor. The divisor can be selected based on the frequency selection signal 210C.

[0037] Figure 4 A flowchart is shown depicting a method 400 for operating a power converter in a low-power burst mode with adaptive sampling in one embodiment.

[0038] In step 402, burst mode is enabled. In various embodiments, burst mode may be enabled by burst mode enable signal 217. In step 404, oscillator 214 may be enabled. Oscillator 214 may be enabled by burst mode enable signal 217. In step 406, the system may wait to enable sampling of the output voltage of the power converter. In various embodiments, sampling may be triggered by the rising edge of an adapted clock signal. However, it is understood that the falling edge of the adapted clock signal or other times derived from the adapted clock signal may be used. In various embodiments, the adapted clock signal may have a default or initial setting, the frequency of which is determined before the voltage at the output is sampled.

[0039] Once triggered by the adapted clock signal, in step 408, the monitoring circuitry can enter observation cycle 407, where voltage monitor 216 and auxiliary analog block 218 are enabled. If necessary, a burst can be initiated and executed in step 410. And, if necessary, the adapted clock signal can be adjusted in step 412. The observation window can be closed in step 414, and voltage monitor 216 and auxiliary analog block 218 can be disabled.

[0040] In step 416, it can be determined whether burst mode is still enabled. This can be determined by the state of burst mode enable signal 217. If burst mode is still enabled after the watch window is closed, the method may include returning to step 406 to wait for an adapted clock signal to trigger another watch window. As will be understood, in various embodiments, this may occur at the next rising edge of the adapted clock signal 215A. In various embodiments, it may also be triggered by the falling edge of the adapted clock signal 215A, or at other times derived from the adapted clock signal 215A.

[0041] In various embodiments, step 416 can be performed sequentially or simultaneously with other steps. For example, the burst mode enable signal 217 can be continuously monitored. This can allow for a faster response if the operating mode changes. This can be advantageous in various embodiments because auxiliary circuitry can be activated to switch out of burst mode. By continuously monitoring the operating mode (or simultaneously with other steps), any activation required to switch the mode can be initiated once a mode change is detected. This can reduce or eliminate the waiting time associated with switching modes.

[0042] If burst mode is no longer enabled in step 416, the method can proceed to step 418. This can be determined by the state of the burst mode enable signal 217. In step 418, oscillator 214 can be disabled. And, in step 420, burst mode can be exited. Furthermore, the power converter can start or resume standard operation.

[0043] Figure 5 A flowchart is shown illustrating a method 500 for an observation window that implements an embodiment of adaptive sampling for low-power burst modes.

[0044] In various embodiments, method 500 may include opening an observation window in step 502. This may include enabling voltage monitor 216 and auxiliary analog block 218. This step may correspond to reference [reference]. Figure 4 Step 408 is discussed.

[0045] Method 500 may include evaluating the voltage at the output of the power converter (e.g., output 206) in step 504. This may include sensing the output voltage of the power converter using known techniques and devices. After evaluating the output voltage, the method may include determining in step 506 whether to initiate a burst. In various embodiments, the output voltage detected by a voltage monitor may be compared to a minimum level or threshold of the output voltage. If the output voltage detected in step 504 is below the minimum level or threshold, a burst may be generated in step 508.

[0046] After the burst is generated at step 508, the voltage at the output can be detected again. The output voltage can be compared again with a minimum level or threshold to determine if it is correct. In various embodiments, the voltage monitor can continuously detect the voltage at the converter's output while the observation window is open. In various embodiments, bursts can be continuously generated until the output voltage reaches a minimum level. The minimum value or threshold used for comparison in step 510 can be the same minimum value or threshold used for comparing the output voltage in step 506. In various embodiments, the minimum value or threshold used for comparison in step 510 can be a different minimum value or threshold used for comparison with the output voltage in step 506. For example, the voltage level that triggers the burst can be the same as (in various embodiments) or different (in various embodiments) the voltage level used to determine whether an additional burst is needed.

[0047] If the output voltage at step 510 does not exceed the threshold, the method can loop back to step 508 and generate additional bursts. This loop can continue until the output voltage rises to a sufficient voltage level.

[0048] Once it has been determined that the voltage at the output has risen sufficiently, it can be determined at step 512 whether to increase the frequency of the output voltage sampling. In various embodiments, this may include increasing the frequency of an adapted clock signal.

[0049] It is understood that the considerations for determining whether to increase the sampling frequency may differ in different embodiments. There are several different ways to measure whether the frequency of the adapted clock signal needs to be changed. Some examples are provided below. However, these examples are for illustrative purposes only. Other methods can be used to adapt the sampling frequency of the modulated output voltage. In various embodiments, adaptive sampling can be used to maintain a stable state between the burst and sample ratio. For example, the sample-to-burst ratio can be maintained by adaptive sampling within a range of 2:1, 4:1, or between 2:1 and 4:1. In various embodiments with adaptive sampling of the output, any other ratio or range can be maintained.

[0050] In various embodiments, the number of clock cycles (or observation windows) between bursts can be tracked. If the number of clock cycles between bursts is lower than desired, this can indicate that the voltage output is not being sampled frequently enough, and the frequency used to sample the output can be increased. In various embodiments, if a burst occurs within a continuous observation window, the frequency used to sample the output voltage can be increased. In various embodiments, the number of cycles in which bursts occur and the number of cycles in which no bursts occur can be tracked and compared to determine whether the frequency used for sampling should be increased. For example, if the number of cycles in which bursts are needed is higher than desired relative to the number of cycles in which bursts are needed, the frequency used for sampling can be increased.

[0051] In various embodiments, the determination of whether to increase the sampling frequency may depend on a voltage threshold used to adapt the sampling frequency. The voltage detected by a voltage monitor at the converter's output can be compared to this threshold to adapt the sampling frequency. The voltage threshold for adapting the sampling frequency may be lower than a level or threshold used to determine whether a burst has occurred. If the output level drops below this lower threshold, the frequency can be increased.

[0052] In various embodiments, the determination of whether to increase the sampling frequency may depend on the number of bursts required to increase the voltage level. For example, in various embodiments, a count may be performed for each cycle through step 508. If the number of bursts (or cycles through step 508) is greater than a threshold, the frequency used for sampling the output may be increased. In various embodiments, the number of bursts provided in each cycle may also be counted directly.

[0053] In various embodiments, a rolling average of the number of observation windows opened between bursts can be tracked. If this number is less than desired (below a threshold), the frequency can be increased.

[0054] If it is determined in step 512 that the frequency used for sampling the output voltage needs to be increased, then the frequency can be increased in step 514. If it is determined in step 512 that the frequency used for sampling the output voltage does not need to be increased, then step 514 can be skipped. Furthermore, the observation window can be closed in step 516. Closing the observation window may require disabling voltage monitor 216 and auxiliary analog block 218.

[0055] Returning to step 506, if it is determined that a burst is not required, it can be determined in step 515 whether to reduce the frequency of the sampled output voltage. If it is determined in step 515 that the frequency will be adjusted, the method can proceed to step 514. If it is determined that the frequency will not be adjusted, the method can proceed to step 516. It is understood that the process for determining whether to reduce the frequency may differ in different embodiments. There are many different methods for measuring whether the frequency of the adapted clock signal needs to be reduced. Some examples are provided below. However, these examples are for illustrative purposes only. Other methods may be used.

[0056] For example, the number of clock cycles (or observation windows) between bursts can be tracked. If the number of clock cycles is higher than expected, this may indicate that the converter's output is being oversampled. The frequency used to sample the output can be reduced.

[0057] In various embodiments, the number of cycles in which bursts occur and the number of cycles in which bursts do not occur can be tracked and compared to determine whether the frequency used for sampling should be reduced. For example, if the number of cycles in which bursts are not needed is higher than the desired number relative to the number of cycles in which bursts are needed, the frequency used for sampling can be reduced.

[0058] In various embodiments, the voltage output can be compared to another voltage threshold higher than a minimum level or threshold used to determine whether a burst has occurred. If the output level remains above that threshold, this can indicate that more output is being sampled than desired, and the sampling rate can be reduced. For example, if the voltage level drops below a higher threshold and remains above the threshold used to determine whether a burst has occurred, the sampling frequency can be reduced. In various embodiments, a rolling average of the number of observation windows between bursts can be tracked, and if this number is higher than a desired number, the frequency can be reduced. In various embodiments, reducing the sampling frequency can include adjusting the adapted clock signal.

[0059] After determining in step 515 whether to reduce the output sampling frequency, the observation window can be closed in step 516. This may include disabling the voltage monitor. Auxiliary circuitry may also be disabled.

[0060] Figure 6 A system 600 is described in one embodiment of a low-power burst mode that adapts the sampling frequency for the output of a power converter.

[0061] System 600 may include an oscillator 214. In various embodiments, oscillator 214 may include a low-speed clock. System 600 may also include a clock divider 602 and a multiplexer MUX 604. A voltage monitor 216 may be used in system 600 to detect the voltage at the output 206 of the DC-DC power converter. System 600 may also include a bridge driver 208 and a voltage detection circuit 606. System 600 may also include a ramp counter 608 and a ramp / buck counter 610. Ramp / buck counter 610 may include a saturated ramp / buck counter.

[0062] In various embodiments, the oscillator 214 may be enabled by a burst mode enable signal 217 ( Figure 6(Not shown) Enable. When enabled, oscillator 214 can provide clock signal 214A to clock divider 602. Clock divider 602 can then output multiple signals. Each signal can have a frequency equal to the quotient of the frequency of clock signal 214A and the divisor. For example, the first signal 602A can have the same frequency as clock signal 214A. The second signal 602B can have a frequency equal to the frequency of clock signal 214A divided by 2. The third signal 602C can have a frequency equal to the frequency of clock signal 214A divided by 4. The nth output 602N can have a frequency equal to the frequency of clock signal 214A divided by the frequency of the digit X. The value of the digit X can be derived from the number of outputs. For example, X can be equal to 2. N or 2 (N－1) In various embodiments, clock divider 602 may have eight outputs, and X may be equal to 128. It is understood that the number of signals output from clock divider 602 may differ between embodiments. Furthermore, it should be understood that the divisor may vary in different embodiments.

[0063] The signal output from clock divider 602 can be provided to MUX 604. MUX can output one of the signals according to frequency selection signal 603. In various embodiments, frequency selection signal 603 may include three bits. The number of bits in the frequency selection signal may vary in different embodiments.

[0064] The MUX 604 may include a first input 604A, a second input 604B, and an Nth input 604N. Various embodiments of the MUX 604 may have different numbers of inputs. The number of inputs to the MUX 604 may correspond to the number of output signals generated by the clock divider 602. Inputs may correspond to bit values. The number of bits in the frequency selection signal may be at least large enough to select each potential input of the MUX. For example, an 8-input MUX may have a 3-bit frequency selection signal. When the frequency selection signal 603 sends a bit value corresponding to the input, the MUX 604 may output the corresponding input. For example, if the first input 604A corresponds to the bit value "000", then when the frequency selection signal sends "000", the MUX will output the signal provided to the first input 604A. The output of the MUX 604 may include an adapted clock signal 215A.

[0065] In various embodiments, the voltage monitor 216 can be enabled by an adapted clock signal 215A. For example, the voltage monitor 216 can be enabled when the adapted clock signal 215A is high. The adapted clock signal 215A can also enable... Figure 6 Auxiliary simulation block 218 not shown in the text.

[0066] When enabled, voltage monitor 216 can detect the voltage at the converter's output 206. An output signal 216A from voltage monitor 216 can be transmitted to voltage checking circuit 606, where the voltage detected by voltage monitor 216 determines whether a burst is needed to increase the output voltage at output 206. If the voltage at output 206 is normal (no burst is needed), it can be asserted that there is no burst signal 606A. If the voltage at output 206 is abnormal (a burst is needed), it can be asserted that there is a burst signal 606B. Voltage checking circuit 606 can check the voltage using the frequency of a matched clock signal 215A. The matched clock signal 215A can be provided to voltage checking circuit 606.

[0067] In various embodiments, a no-burst signal can be provided to voltage monitor 216. A no-burst signal 606A can disable voltage monitor 216. This saves power by turning off voltage monitor 216 when not needed. The no-burst signal 606A can also disable auxiliary analog block 218 (…). Figure 6 (Not shown in the image). A burst signal 606B can be provided to the bridge driver 208. When asserted, the burst signal 606B can cause the bridge driver 208 to initiate a burst.

[0068] In various embodiments, a no-burst signal 606A and a burst signal 606B are provided to an up-counter 608. The up-counter 608 can be used to track the frequency at which a period converter that does not require bursts needs to generate a burst. When asserted, the no-burst signal 606A can increment the up-counter 608. When the up-counter 608 overflows, an overflow signal 608A can be provided to an up / down counter 610. For a two-bit counter, the up-counter 608 overflows when the number of samples without bursts exceeds four times the number of samples with bursts; however, in various embodiments, the up-counter may include a different number of bits.

[0069] When the overflow signal 608A is asserted, it increments the ramp / decrement counter 610, which in turn changes the value of the frequency selection signal 603. The MUX 604 can be configured such that it selects a slower signal as the frequency selection signal increments, thereby adjusting the frequency of the adapted clock signal 215A based on the voltage at output 206. This slows down the adapted clock signal because fewer bursts are needed to maintain the voltage at output 206 at the desired level. It is understood that the number of bits in the ramp counter 608 can vary in different embodiments. In various embodiments, the size of the ramp counter can affect when the overflow signal 608A is asserted, and therefore when the ramp / decrement counter is incremented and the frequency of the adapted clock signal 215A is changed.

[0070] The up-counter 608 can also be configured to assert the down-signal 608B after consecutive resets. In different embodiments, the number of resets required to trigger the assertion of the down-signal 608B may vary. In some embodiments, two consecutive resets of the up-counter 608 may trigger the assertion of the down-signal 608B. In some embodiments, three consecutive resets of the up-counter 608 may trigger the assertion of the down-signal 608B. In various embodiments, the down-signal 608B may be triggered by more than three consecutive resets.

[0071] When asserted, the decrement signal 608B decrements the ramp / buck counter 610, thereby altering the outputs of the frequency selection signal 603 and the MUX 604. The MUX can be configured to select a faster signal when the frequency selection signal is decremented, thus adapting the frequency of the adapted clock signal 215A based on the voltage at output 206. This causes the adapted clock signal to be accelerated because more bursts are needed to maintain the voltage at output 206 at the desired level.

[0072] It is understood that the components of system 600 may differ in different embodiments. For example, the sizes of ramp / buck counter 610 and ramp counter 608 may differ in different embodiments. Different sizes of ramp counters can be used, so the adapted clock signal 215A will vary more or less frequently. The size of ramp / buck counter 610 may correspond to the number of different input signals provided to MUX 604. In various embodiments, frequency adaptation circuitry 215 may include MUX 604 and clock divider 602.

[0073] Figure 7 A flowchart is depicted of a method 700 for operating a power converter in a low-power burst mode in one embodiment.

[0074] In various embodiments, the method 700 for operating a DC-DC power converter in a low-power burst mode may include step 702 sampling the output voltage of the DC-DC power converter at a sampling frequency to determine when to initiate a true low-power burst mode burst; and step 704 adapting the sampling frequency based on the output voltage.

[0075] In various embodiments, method 700 may further include initiating a burst when the output voltage drops below a voltage threshold.

[0076] In various embodiments, method 700 may further include increasing the sampling frequency when the output voltage drops below a lower voltage threshold.

[0077] In various embodiments, method 700 may further include, wherein adapting the sampling frequency includes increasing the sampling frequency in response to an increase in the electrical load powered by the output voltage.

[0078] In various embodiments, method 700 may further include, wherein adapting the sampling frequency includes reducing the sampling frequency in response to a decrease in the electrical load powered by the output voltage.

[0079] In various embodiments, method 700 may further include: counting the number of consecutive samples of the output voltage that do not trigger a burst; determining that the number exceeds an upper threshold; and wherein adapting the sampling frequency includes reducing the sampling frequency.

[0080] In various embodiments, method 700 may further include an upper threshold equal to 3.

[0081] In various embodiments, method 700 may further include tracking the ratio of sampling to burst of the output voltage; determining that the ratio is too high; and wherein adapting the sampling frequency includes reducing the sampling frequency.

[0082] In various embodiments, method 700 may further include: tracking the ratio of the sampling to the burst of the output voltage; determining that the ratio is too low; and wherein adapting the sampling frequency includes increasing the sampling frequency.

[0083] In various embodiments, method 700 may further include determining that the number of samples of the output voltage occurring between the first burst and the second burst is less than a lower threshold; and wherein adapting the sampling frequency includes increasing the sampling frequency.

[0084] In various embodiments, method 700 may further include: determining that a burst has been initiated for two consecutive samples of the output voltage; and wherein adapting the sampling frequency includes increasing the sampling frequency.

[0085] In various embodiments, systems other than power converters operating in burst or other forms of discrete correction can be adaptively sampled according to this disclosure by monitoring the system's output variables and adapting the sampling frequency of the output variables based on measurements of those output variables. For example, temperature control implemented by an actuator (e.g., a heater) operating in a burst can be monitored by sampling the temperature and adapting the sampling rate. In another example, a linear voltage regulator where the gate signal of the output MOS is driven by a capacitor can have circuitry that provides "boost" or "drop" pulses based on an output voltage monitor, which can be turned on according to an adaptive sampling frequency.

[0086] Example 1. A method for operating a DC-DC power converter in a low-power burst mode, the method comprising: sampling the output voltage of the DC-DC power converter at a sampling frequency to determine when to initiate a burst for the low-power burst mode; and adapting the sampling frequency based on the output voltage.

[0087] Example 2. Based on the method of Example 1, it further includes initiating a burst when the output voltage drops below a voltage threshold.

[0088] Example 3. Based on the methods of Examples 1 and 2, it further includes increasing the sampling frequency when the output voltage drops below a low voltage threshold.

[0089] Example 4. According to the method of Examples 1 to 3, wherein adapting the sampling frequency includes increasing the sampling frequency in response to an increase in the electrical load powered by the output voltage.

[0090] Example 5. According to the methods of Examples 1 to 4, the adaptive sampling frequency includes reducing the sampling frequency in response to a reduction in the electrical load powered by the output voltage.

[0091] Example 6. The method according to Examples 1 to 5 further includes: counting the number of consecutive samples of the output voltage that do not trigger a burst; determining that the number exceeds an upper threshold; and wherein adapting the sampling frequency includes reducing the sampling frequency.

[0092] Example 7. Following the method of Examples 1 to 6, where the upper threshold is equal to 3.

[0093] Example 8. The method according to Examples 1 to 7 further includes: tracking the ratio of the output voltage sampling to the burst; determining that the ratio is too high; and wherein adapting the sampling frequency includes reducing the sampling frequency.

[0094] Example 9. The method according to Examples 1 to 8 further includes: tracking the ratio of the output voltage sampling to the burst; determining that the ratio is too low; and wherein adapting the sampling frequency includes increasing the sampling frequency.

[0095] Example 10. The method according to Examples 1 to 9 further includes: determining that the number of samples of the output voltage occurring between the first burst and the second burst is less than a lower threshold; and wherein adapting the sampling frequency includes increasing the sampling frequency.

[0096] Example 11. The method according to Examples 1 to 10 further includes: determining that a burst has been initiated based on two consecutive samples of the output voltage; and wherein adapting the sampling frequency includes increasing the sampling frequency.

[0097] Example 12. A system for setting a sampling frequency of the output voltage of a DC-DC power converter during a low-power burst mode of the DC-DC power converter, the system comprising: a frequency adaptation circuit configured to receive a clock signal having a first frequency and output an adapted clock signal having an adapted frequency, the adapted frequency depending on the output voltage of the DC-DC power converter; and a voltage monitoring circuit enabled by the adapted clock signal to sample the output voltage of the DC-DC power converter using the adapted frequency.

[0098] Example 13. The system according to Example 12 further includes control logic circuitry configured to receive an output voltage sampled by a voltage monitoring circuitry and to transmit a frequency selection signal to a frequency adaptation circuitry configured to adjust the frequency of the adaptation based on changes in the frequency selection signal, wherein the frequency selection signal is determined from the output voltage sampled by the voltage monitoring circuitry.

[0099] Example 14. A system based on Examples 12 to 13, wherein the control logic circuit is configured to output a burst command signal when the output voltage drops below a voltage threshold.

[0100] Example 15. A system according to Examples 12 to 14, wherein the frequency adaptation circuit includes: a clock divider configured to receive a clock signal at a clock signal input and configured to output a plurality of signals having frequencies that are quotients of the clock signal; and a multiplexer configured to receive the plurality of signals and select one of the plurality of signals as the adapted clock signal output based on a frequency selection signal determined from an output voltage sampled by a voltage monitoring circuit.

[0101] Example 16. A system based on Examples 12 to 15, wherein the number of signals is equal to 8, and the frequency selection signal is a 3-bit signal.

[0102] Example 17. A system for providing an adapted sampling frequency for sampling the output voltage of a DC-DC power converter in a low-power burst mode, the system comprising: an oscillator configured to generate a clock signal; a frequency adaptation circuit configured to receive the clock signal and output an adapted clock signal including the adapted sampling frequency, the adapted sampling frequency being determined by a frequency selection signal; and a tracking circuit configured to receive data indicating when a burst is initiated for the low-power burst mode and configured to output a data-dependent frequency selection signal.

[0103] Example 18. The system according to Example 17, wherein the frequency adaptation circuit includes: a clock divider configured to receive a clock signal at a clock signal input and configured to output a plurality of signals having frequencies that are quotients of the clock signal; and a multiplexer configured to receive the plurality of signals and a frequency selection signal, the multiplexer being configured to select one of the plurality of signals as the adapted clock signal output based on the frequency selection signal.

[0104] Example 19. A system according to Examples 17 to 18, wherein the tracking circuitry includes an up-counter in communication, the up-counter being configured to increment when a burst is initiated and reset when a burst is not initiated; and a saturation up-down counter, the saturation up-down counter being configured to receive an overflow signal from the up-counter and increment the count each time the up-counter overflows, and being configured to decrement the count when the up-counter is reset twice consecutively, the count being provided to the multiplexer as a frequency selection signal.

[0105] Example 20. A system based on Examples 17 to 19, wherein the frequency selection signal is a 3-bit signal, the up-counter is a 2-bit counter, and the saturation up-down counter is a 3-bit counter.

[0106] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of exemplary embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art based on the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for operating a DC-DC power converter in low-power burst mode, the method comprising: In response to the received clock signal, the observation window is opened by activating the voltage monitoring circuit and the auxiliary analog module; The voltage monitoring circuit samples the output voltage of the DC-DC power converter at a sampling frequency to determine when to initiate a burst for the low-power burst mode. By controlling the logic circuit, when the output voltage of the DC-DC power converter is lower than the voltage threshold, a burst is initiated, wherein the burst is timed by the oscillator in the auxiliary analog module, and the oscillator has the oscillator frequency of the auxiliary analog module. The sampling frequency is adapted based on the output voltage. The sampling frequency adaptation includes: A clock signal with a first low frequency is received from a low-frequency oscillator through a frequency adaptation circuit; Receive the output signal from the voltage monitoring circuit; The adapted sampling frequency depends on the clock signal and the output signal sampled by the voltage monitoring circuit; And when the output voltage of the DC-DC power converter sampled by the voltage monitoring circuit is higher than a threshold, the observation window is closed by powering off the voltage monitoring circuit and the auxiliary analog module through the control logic circuit, in order to wait for the next sampling.

2. The method of claim 1, further comprising increasing the sampling frequency when the output voltage drops below a low voltage threshold.

3. The method of claim 1, wherein adapting the sampling frequency includes increasing the sampling frequency in response to an increase in the electrical load powered by the output voltage.

4. The method of claim 1, wherein adapting the sampling frequency includes reducing the sampling frequency in response to a decrease in the electrical load powered by the output voltage.

5. The method according to claim 1, further comprising: When a burst mode enable signal is received, burst mode is enabled; The low-frequency oscillator is enabled by the burst mode enable signal; Waiting to enable sampling of the output voltage of the DC-DC power converter; By enabling the voltage monitoring circuit and the auxiliary simulation module, the observation period can be entered. Determine whether the burst mode is still enabled; If the burst mode is still enabled, return to the waiting state; If the burst mode is not enabled, the low-frequency oscillator is disabled.

6. The method of claim 1, further comprising: The number of consecutive samples of the output voltage that do not trigger a burst between bursts is counted; It is determined that the number exceeds the upper threshold; as well as Adapting the sampling frequency includes reducing the sampling frequency.

7. The method of claim 6, wherein the upper threshold is equal to 3.

8. The method of claim 1, further comprising: Track the ratio of the sampling to the burst of the output voltage; Determining that the ratio is too high; and Adapting the sampling frequency includes reducing the sampling frequency.

9. The method of claim 1, further comprising: Track the ratio of the sampling to the burst of the output voltage; Determining that the ratio is too low; and Adapting the sampling frequency includes increasing the sampling frequency.

10. The method of claim 1, further comprising: The number of samples of the output voltage occurring between the first burst and the second burst is determined to be less than a lower threshold. as well as Adapting the sampling frequency includes increasing the sampling frequency.

11. The method of claim 1, further comprising: Two consecutive samples of the output voltage determine that a burst has been initiated; and Adapting the sampling frequency includes increasing the sampling frequency.

12. A system for setting the sampling frequency of the output voltage of a DC-DC power converter during a low-power burst mode, the system comprising: An auxiliary simulation module includes an oscillator having an auxiliary simulation module oscillator frequency. A frequency adaptation circuit is configured to receive a clock signal having a first low frequency from a low-frequency oscillator and output an adapted clock signal having an adapted frequency that depends on the output voltage of the DC-DC power converter. A voltage monitoring circuit, enabled by the adapted clock signal, to sample the output voltage of the DC-DC power converter using the adapted frequency; as well as The control logic circuit is configured to receive the adapted clock signal from the frequency adaptation circuit and, in response to receiving the adapted clock signal, open an observation window by enabling the voltage monitoring circuit and the auxiliary analog module. The control logic circuit is also configured to initiate a burst when the output voltage is lower than a voltage threshold, the burst being timed by the oscillator in the auxiliary analog module. The control logic circuit is further configured to power off the voltage monitoring circuit and the auxiliary analog module to wait for the next sampling when the output voltage of the DC-DC power converter sampled by the voltage monitoring circuit is higher than the threshold.

13. The system of claim 12, wherein the control logic circuit is configured to receive the output voltage sampled by the voltage monitoring circuit and transmit a frequency selection signal to the frequency adaptation circuit, the frequency adaptation circuit being configured to adjust the adapted frequency according to a change in the frequency selection signal, and the frequency selection signal being determined from the output voltage sampled by the voltage monitoring circuit.

14. The system of claim 13, wherein the control logic circuit is configured to output a burst command signal when the output voltage drops below a voltage threshold.

15. The system of claim 12, wherein the frequency adaptation circuit comprises: A clock divider, configured to receive the clock signal at a clock signal input and configured to output a plurality of signals having frequencies that are quotients of the clock signal; as well as A multiplexer configured to receive the plurality of signals and select one of the plurality of signals as the adapted clock signal output based on a frequency selection signal determined from the output voltage sampled by the voltage monitoring circuit.

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