Drive circuit and bridge circuit drive method

Abstract

The application discloses a driving circuit and a bridge circuit driving method. The driving circuit works in a high voltage domain and / or a low voltage domain to drive upper bridge transistors in a bridge circuit. The driving circuit comprises a current mirror unit, a first signal generating unit, a first control unit, a second control unit and a driving unit. According to the driving circuit and the bridge circuit driving method, the driving circuit has a simple structure, can be realized by using miniaturized discrete devices or integrated by an integrated circuit process, and can realize the effects of reducing the volume and area. Meanwhile, no logic gate is used in the high voltage domain, so that the risk that the gate voltage of a device exceeds the withstand voltage is avoided. Through timing control, a control signal representing the turn-off of the upper bridge transistors can be generated to control the turn-on of lower bridge transistors, so that the upper and lower bridge transistors are prevented from being turned on simultaneously and passing through.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a driving circuit and a bridge circuit driving method. Background Technology

[0002] In the field of power electronics, one application scenario for half-bridge or H-bridge circuits is that their supply voltage is typically higher than the input control signal voltage. Furthermore, half-bridge or H-bridge circuits use N-type transistors as the power devices for both the upper and lower bridges, with the drain of the N-type transistor connected to the supply terminal. For an N-type transistor to turn on, its gate voltage needs to be higher than its drain voltage. Therefore, half-bridge or H-bridge circuits typically have a charge pump that provides a higher supply voltage VCP than the supply terminal VM to turn on the N-type transistor. Consequently, the upper bridge's drive circuit needs a level shifting function to convert the input low-voltage control signal into a high-voltage control signal.

[0003] Common bridge drivers use optocouplers or transformer isolation to convert control signals from low-voltage domains to high-voltage domains. However, these methods are bulky, complex, and difficult to miniaturize or integrate. Another type of bridge driver uses digital logic gates to generate the required high-level N-type transistors. However, logic gates are generally low-voltage devices with limited gate withstand voltage. When there is a significant difference between the voltages of the power supply, the control signal, and the voltage generated by the internal charge pump, the control signal cannot be directly input into the logic gate. Otherwise, there is a risk of overvoltage at the gate of the bridge transistor.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a driving circuit and a bridge circuit driving method, which can realize the conversion of the low voltage domain of the control signal into the high voltage domain and drive the upper bridge transistor.

[0006] To achieve the above objectives, embodiments of the present invention provide a driving circuit that operates in a high voltage domain and / or a low voltage domain to drive the upper bridge transistor in a bridge circuit. The driving circuit includes: a current mirror unit, a first signal generation unit, a first control unit, a second control unit, and a driving unit.

[0007] The current mirror unit is used to generate a drive current by replicating the input current;

[0008] The first signal generation unit is used to receive the input signal for controlling the upper bridge transistor, so as to generate a control signal for controlling the state of the upper bridge transistor. The control signal includes a first control signal and a second control signal.

[0009] The first control unit is used to receive the first control signal and the drive current, and to generate the first control voltage;

[0010] The second control unit is used to receive the second control signal and drive current, and to generate the second control voltage;

[0011] The driving unit is used to generate a driving voltage at the control terminal of the upper bridge transistor under the action of the first control voltage and the second control voltage to control the upper bridge transistor to turn on or off.

[0012] In one or more embodiments of the present invention, the current mirror unit includes a first MOS transistor and a plurality of second MOS transistors. The first MOS transistor and the plurality of second MOS transistors are connected in a common gate configuration. The drain and gate of the first MOS transistor are connected to receive an input current. The sources of the first MOS transistor and the plurality of second MOS transistors are connected to ground. The plurality of second MOS transistors are used to replicate the input current to generate a corresponding drive current at the drain of the plurality of second MOS transistors.

[0013] In one or more embodiments of the present invention, the current mirror unit further includes a plurality of matching resistors, the number of which is the same as the number of MOS transistors in the current mirror unit, and are connected one-to-one between the source of the MOS transistor and the ground voltage.

[0014] In one or more embodiments of the present invention, the first signal generating unit includes: a first inverter and a second inverter, wherein the input terminal of the first inverter is used to receive the input signal, the output terminal of the first inverter is used to output the second control signal, the input terminal of the second inverter is used to receive the second control signal, and the output terminal of the second inverter is used to output the first control signal.

[0015] In one or more embodiments of the present invention, the first control unit includes a third MOS transistor and a bias unit. The source of the third MOS transistor is connected to a current mirror unit, and the gate of the third MOS transistor is used to receive a first control signal. One end of the bias unit is connected to a power supply voltage, and the other end of the bias unit is connected to the drain of the third MOS transistor and a driving unit to generate a first control voltage.

[0016] In one or more embodiments of the present invention, the biasing unit is one or more of a MOS transistor, a bias resistor, and a diode.

[0017] In one or more embodiments of the present invention, the second control unit includes a seventh MOS transistor, the drain of which is connected to a driving unit, the source of which is connected to a current mirror unit, and the gate of which is used to receive a second control signal.

[0018] In one or more embodiments of the present invention, the driving unit includes a fifth MOS transistor and a differential voltage unit. The gate of the fifth MOS transistor is connected to a first control unit to receive a first control voltage. The source of the fifth MOS transistor is connected to a power supply voltage. The drain of the fifth MOS transistor is connected to a second control unit, a first terminal of the differential voltage unit, and a control terminal of the upper bridge transistor. The second terminal of the differential voltage unit is connected to the source of the upper bridge transistor.

[0019] In one or more embodiments of the present invention, the differential pressure unit is one or more of a driving resistor, a MOSFET, and a diode.

[0020] In one or more embodiments of the present invention, the first signal generating unit further includes a first pulse generating unit and a second pulse generating unit, wherein the input terminal of the first pulse generating unit is used to receive a second control signal, the output terminal of the first pulse generating unit is used to output a third control signal, the input terminal of the second pulse generating unit is used to receive the second control signal, and the output terminal of the second pulse generating unit is used to output a fourth control signal.

[0021] In one or more embodiments of the present invention, the first pulse generating unit includes a first delay unit, a third inverter, and a first AND gate; the second pulse generating unit includes a second delay unit, a fourth inverter, and a second AND gate; the input terminal of the first delay unit is connected to the input terminal of the third inverter to receive a second control signal, the output terminal of the first delay unit and the output terminal of the third inverter are respectively connected to the first input terminal and the second input terminal of the first AND gate, the output terminal of the first AND gate is used to output a third control signal, the input terminal of the second delay unit is connected to the input terminal of the fourth inverter to receive the second control signal, the output terminal of the second delay unit and the output terminal of the fourth inverter are respectively connected to the first input terminal and the second input terminal of the second AND gate, the output terminal of the second AND gate is used to output a fourth control signal.

[0022] The drive circuit also includes a third control unit and a fourth control unit;

[0023] The third control unit is used to receive the third control signal and drive current, and generate a third control voltage to increase the rise rate of the first control voltage.

[0024] The fourth control unit is used to receive the third control signal and drive current and generate the fourth control voltage. At the same time, the second control unit receives the fourth control signal to generate an updated second control voltage. The first control voltage and the fourth control voltage work together to accelerate the turn-off of the upper bridge transistor.

[0025] In one or more embodiments of the present invention, the third control unit includes an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, and a second resistor. The source of the eighth MOS transistor is connected to a current mirror unit, the gate of the eighth MOS transistor is used to receive a third control signal, the drain of the eighth MOS transistor is connected to the drain and gate of the ninth MOS transistor, the source of the ninth MOS transistor is connected to a first terminal of the second resistor, the second terminal of the second resistor is connected to a power supply voltage, the gate of the ninth MOS transistor is connected to the gate of the tenth MOS transistor, the source of the tenth MOS transistor is connected to a power supply voltage, and the drain of the tenth MOS transistor is connected to the first control unit to improve the rise rate of the first control voltage.

[0026] In one or more embodiments of the present invention, the fourth control unit includes an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a first voltage divider resistor, and a second voltage divider resistor. The source of the eleventh MOS transistor is connected to a current mirror unit, the gate of the eleventh MOS transistor is used to receive a third control signal, the drain of the eleventh MOS transistor is connected to the gate of the twelfth MOS transistor, the source of the twelfth MOS transistor is connected to the control terminal of the upper bridge transistor, the drain of the twelfth MOS transistor is connected to the source of the upper bridge transistor, the source of the thirteenth MOS transistor is connected to a power supply voltage, the gate of the thirteenth MOS transistor is connected to a first control unit to receive a first control voltage, the drain of the thirteenth MOS transistor is connected to a first terminal of the first voltage divider resistor, the second terminal of the first voltage divider resistor is connected to the gate of the twelfth MOS transistor and a first terminal of the second voltage divider resistor, and the second terminal of the second voltage divider resistor is connected to the drain of the twelfth MOS transistor.

[0027] In one or more embodiments of the present invention, the fourth control unit further includes a third diode and a fourth diode, wherein the cathode of the third diode is connected to the source of the twelfth MOS transistor, the anode of the third diode is connected to the gate of the twelfth MOS transistor, the cathode of the fourth diode is connected to the source of the twelfth MOS transistor, and the anode of the fourth diode is connected to the drain of the twelfth MOS transistor.

[0028] In one or more embodiments of the present invention, the driving circuit further includes a Zener diode, the cathode of which is connected to the gate of the upper bridge transistor, and the anode of which is connected to the source of the upper bridge transistor.

[0029] In one or more embodiments of the present invention, the first signal generating unit further includes a judgment circuit, the judgment circuit being used to generate an identification signal characterizing whether the upper bridge transistor is turned off based on a first control signal and a fourth control signal.

[0030] In one or more embodiments of the present invention, the determination circuit includes a NAND gate, the first input terminal of the NAND gate is used to receive a first control signal, the second input terminal of the NAND gate is used to receive a fourth control signal, and the output terminal of the NAND gate is used to output an identification signal.

[0031] This invention also discloses a bridge circuit driving method, comprising:

[0032] The input current is copied to generate the drive current;

[0033] Under the control of the first control signal, the first control unit is turned on to receive the first drive current and the first control voltage is generated through the first control unit;

[0034] Under the control of the second control signal, the second control unit is turned on to receive the second drive current and the second control voltage is generated through the second control unit;

[0035] Under the control of the first control voltage and the second control voltage, the upper bridge transistor is turned on and off.

[0036] In one or more embodiments of the present invention, the bridge circuit driving method further includes:

[0037] Under the control of the fourth control signal, the second control unit is turned on to receive the second drive current and generate the updated second control voltage.

[0038] Under the control of the third control signal, the third control unit is turned on to receive the third drive current and generate the third control voltage. The rise rate of the first control voltage is increased through the third control unit.

[0039] Under the control of the first to fourth control signals, a drive voltage is generated at the control terminal of the upper bridge transistor, which, in conjunction with the rise of the first control voltage, accelerates the turn-off of the upper bridge transistor.

[0040] Compared with the prior art, according to the driving circuit and bridge circuit driving method of the present invention, the driving circuit generates a driving current by replicating the input current through a current mirror unit; receives an input signal controlling the upper bridge transistor through a first signal generation unit to generate a control signal controlling the state of the upper bridge transistor, the control signal including a first control signal and a second control signal; receives the first control signal and the driving current through a first control unit and generates a first control voltage; receives the second control signal and the driving current through a second control unit and generates a second control voltage; and generates a driving voltage at the control terminal of the upper bridge transistor under the action of the first control voltage and the second control voltage to control the upper bridge transistor to turn on or off, thereby enabling the driving circuit to operate in a high voltage domain and / or a low voltage domain to drive the upper bridge transistor in the bridge circuit.

[0041] The driving circuit structure of this invention is simple and can be implemented using miniaturized discrete devices or integrated through integrated circuit technology to reduce size and area. At the same time, no logic gates are used in the high voltage domain, thereby avoiding the risk of the device's gate voltage exceeding the withstand voltage. Through timing control, a control signal representing the turn-off of the upper bridge transistor can be generated to control the turn-on of the lower bridge transistor, avoiding simultaneous turn-on and punch-through of the upper and lower bridge transistors. Attached Figure Description

[0042] Figure 1 This is a circuit schematic diagram of the driving circuit according to Embodiment 1 of the present invention.

[0043] Figure 2 This is a circuit schematic diagram of the first signal generation unit according to Embodiment 1 of the present invention.

[0044] Figure 3 This is a logic diagram of the control signals and voltages according to Embodiment 1 of the present invention.

[0045] Figure 4 This is a flowchart of a bridge circuit driving method according to Embodiment 1 of the present invention.

[0046] Figure 5 This is a circuit diagram of the driving circuit according to Embodiment 2 of the present invention.

[0047] Figure 6 This is a circuit diagram of the second signal generation circuit according to Embodiment 2 of the present invention.

[0048] Figure 7 This is a circuit diagram of the judgment circuit according to Embodiment 2 of the present invention.

[0049] Figure 8 This is a logic diagram of the control signals and voltages according to Embodiment 2 of the present invention.

[0050] Figure 9 This is a flowchart of a bridge circuit driving method according to Embodiment 2 of the present invention. Detailed Implementation

[0051] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0052] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0053] Example 1

[0054] like Figure 1 As shown, a driving circuit is provided. This driving circuit can operate in a high voltage domain or a low voltage domain, or achieve a level shift function to drive the upper bridge transistor MNH in a bridge circuit. The bridge circuit is an H-bridge (full bridge) or a half bridge circuit, and the upper bridge transistor MNH is selected as an N-type transistor. The drain of the upper bridge transistor MNH in the bridge circuit is connected to the power supply VM, and the gate of the upper bridge transistor MNH is used to receive the driving voltage HS_GT generated by the driving circuit. The source of the upper bridge transistor MNH is connected to the drain of the lower bridge transistor MNL in the bridge circuit to form the output terminal OUT. The source of the lower bridge transistor MNL is connected to the ground voltage, and the gate of the lower bridge transistor MNL is used to receive the driving voltage LS_GT.

[0055] like Figure 1 and Figure 2 As shown, the driving circuit includes: a current mirror unit 10, a first signal generation unit 20, a first control unit 30, a second control unit 40, and a driving unit 50.

[0056] The current mirror unit 10 is used to generate a drive current by replicating the input current Ibias. The input current Ibias is generated by a current source connected to the current mirror unit 10. The current source can be a regular current source or a current mirror.

[0057] like Figure 1As shown, the current mirror unit 10 includes a first MOSFET MN01 and multiple second MOSFETs. In this embodiment, two second MOSFETs are provided, namely second MOSFET MN02 and second MOSFET MN03. The first MOSFET MN01, second MOSFET MN02, and second MOSFET MN03 are connected via a common gate. The drain and gate of the first MOSFET MN01 are connected, and the drain of the first MOSFET MN01 is connected to a current source to receive the input current Ibias. The sources of the first MOSFET MN01, second MOSFET MN02, and second MOSFET MN03 are all connected to ground. The second MOSFETs MN02 and MN03 are used to replicate the input current Ibias and generate drive currents respectively.

[0058] To mitigate the impact of mismatch in the current mirror unit 10 caused by the manufacturing process, multiple matching resistors can be added to the current mirror unit 10. The number of matching resistors is the same as the number of MOSFETs in the current mirror unit 10, and they are connected one-to-one between the source of the MOSFET and ground to reduce the impact of mismatch. In this embodiment, three matching resistors are provided: a first matching resistor RD1, a second matching resistor RD2, and a third matching resistor RD3. The first terminal of the first matching resistor RD1 is connected to the source of the first MOSFET MN01, and the second terminal of the first matching resistor RD1 is connected to ground. The first terminal of the second matching resistor RD2 is connected to the source of the second MOSFET MN02, and the second terminal of the third matching resistor RD3 is connected to the source of the second MOSFET MN03, and the second terminal of the third matching resistor RD3 is connected to ground. In other embodiments, matching resistors may not be provided.

[0059] like Figure 2 As shown, the first signal generation unit 20 is used to receive the input signal IN_HS that controls the upper bridge transistor MNH, so as to generate control signals for controlling the state of the upper bridge transistor MNH. The control signals include a first control signal ON and a second control signal OFF. In this embodiment, when the upper bridge transistor MNH is turned on or off, the levels of the first control signal ON and the second control signal OFF are opposite to each other.

[0060] The first signal generation unit 20 includes a first inverter INV1 and a second inverter INV2, both powered by a low-voltage power supply PVDD. The input terminal of the first inverter INV1 receives the input signal IN_HS, and its output terminal outputs a second control signal OFF. The input terminal of the second inverter INV2 receives the second control signal OFF, and its output terminal outputs a first control signal ON.

[0061] like Figure 3 As shown, when the upper bridge transistor MNH needs to be turned on, the first control signal ON toggles to a high level signal and the second control signal OFF toggles to a low level signal; when the upper bridge transistor MNH needs to be turned off, the first control signal ON toggles to a low level signal and the second control signal OFF toggles to a high level signal.

[0062] like Figure 1 As shown, the first control unit 30 is connected to the current mirror unit 10 and the drive unit 50. The first control unit 30 is used to receive the first control signal ON and the drive current, and to generate the first control voltage PGT. When it is necessary to turn on the upper bridge transistor MNH, the first control unit 30 is turned on under the control of the first control signal ON to receive the drive current transmitted from the current mirror unit 10.

[0063] Specifically, the first control unit 30 includes a third MOSFET MNA and a bias unit 31. The source of the third MOSFET MNA is connected to the drain of the second MOSFET MN02 in the current mirror unit 10, and the gate of the third MOSFET MNA is used to receive a first control signal ON. The first control signal ON controls the turning on and off of the third MOSFET MNA. When the third MOSFET MNA is turned on under the control of the first control signal ON, it receives the drive current transmitted from the drain of the second MOSFET MN02. In this embodiment, the third MOSFET MNA is an N-channel MOSFET, and the third MOSFET MNA is turned on when the first control signal ON is a high-level signal. In other embodiments, the third MOSFET MNA can be a P-channel MOSFET or other devices or structures, so that the third MOSFET MNA can be turned on when the first control signal ON is a low-level signal.

[0064] One end of the bias unit 31 is connected to the power supply voltage VCP, and the other end of the bias unit 31 is connected to the drain of the third MOSFET MNA and the drive unit 50. If the power supply voltage VCP is in the high voltage domain and the first control signal ON is in the low voltage domain, that is, the drive circuit needs to realize the conversion from the low voltage domain to the high voltage domain, the third MOSFET MNA can be replaced with a high voltage-resistant device, so that the drive circuit can operate not only in the low voltage domain but also in the high voltage domain. If the power supply voltage VCP is in the low voltage domain and the first control signal ON is in the low voltage domain, the third MOSFET MNA is a low voltage device.

[0065] The bias unit 31 is one or more of a MOSFET, a bias resistor, and a diode. In this embodiment, the bias unit 31 includes a first resistor RD0 and a fourth MOSFET MP0. The source of the fourth MOSFET MP0 is connected to the first terminal of the first resistor RD0, and the second terminal of the first resistor RD0 is connected to the power supply voltage VCP. The gate of the fourth MOSFET MP0 is connected to the drain and simultaneously connected to the drain of the third MOSFET MNA and the driving unit 50. The third MOSFET MNA is turned on by the first control signal ON, making the first resistor RD0, the fourth MOSFET MP0, the third MOSFET MNA, and the second MOSFET MN02 conduct, thereby generating a control voltage PGT at the drain of the fourth MOSFET MP0.

[0066] In this embodiment, the fourth MOSFET MP0 is connected in a diode configuration, thereby creating a voltage difference between the power supply voltage VCP and the control voltage PGT to turn on the drive unit 50. By adding a first resistor RD0, when the third MOSFET MNA is turned on, the control voltage PGT drops more, resulting in a larger voltage difference between the power supply voltage VCP and the control voltage PGT to turn on the drive unit 50.

[0067] In other embodiments, the positions of the first resistor RD0 and the fourth MOS transistor MP0 can be interchanged, or the first resistor RD0 can be omitted.

[0068] In other embodiments, the fourth MOSFET MP0 can be replaced by a bias resistor or a first diode. If a first diode is used, the anode of the first diode is connected to the first terminal of the first resistor RD0, and the cathode of the first diode is connected to the drain of the third MOSFET MNA and the driving unit 50. If a bias resistor is used, the first terminal of the bias resistor is connected to the first terminal of the first resistor RD0, and the second terminal of the bias resistor is connected to the drain of the third MOSFET MNA and the driving unit 50.

[0069] like Figure 1 As shown, the second control unit 40 is used to receive the second control signal OFF and the drive current, and to generate the second control voltage. When the upper bridge transistor MNH needs to be turned off, the second control unit 40 is turned on under the control of the second control signal OFF to receive the drive current transmitted from the current mirror unit 10.

[0070] The second control unit 40 includes a seventh MOSFET MNB. The drain of the seventh MOSFET MNB is connected to the gate of the driving unit 50 and the upper bridge transistor MNH. The source of the seventh MOSFET MNB is connected to the drain of the second MOSFET MN03 of the current mirror unit 10. The gate of the seventh MOSFET MNB is used to receive the second control signal OFF, which controls the turning on and off of the seventh MOSFET MNB. In this embodiment, the seventh MOSFET MNB is an N-channel MOSFET, and it is turned on when the second control signal OFF is high. In other embodiments, the seventh MOSFET MNB can be a P-channel MOSFET or other devices or structures, so that it can be turned on when the second control signal OFF is low.

[0071] The seventh MOSFET MNB receives the drive current from the drain of the second MOSFET MN03 by turning on the seventh MOSFET MNB. This pulls down the drain voltage of the seventh MOSFET MNB, generating a second control voltage at the control terminal of the upper-bridge transistor MNH, thus turning off the upper-bridge transistor MNH. When the power supply voltage VCP is in the high-voltage domain and the second control signal OFF is in the low-voltage domain, i.e., the drive circuit needs to achieve a transition from the low-voltage domain to the high-voltage domain, the seventh MOSFET MNB can be replaced with a high-voltage resistant device. If the power supply voltage VCP is in the low-voltage domain and the second control signal OFF is in the low-voltage domain, the seventh MOSFET MNB becomes a low-voltage device.

[0072] like Figure 1 As shown, the driving unit 50 is used to generate a driving voltage HS_GT at the control terminal of the upper bridge transistor MNH under the action of a first control voltage PGT and a second control voltage to control the upper bridge transistor MNH to turn on or off. If the driving unit 50 is turned on under the control of the first control voltage PGT and the second control unit 40 is turned off, a driving voltage HS_GT is generated at the control terminal (gate) of the upper bridge transistor MNH, and the upper bridge transistor is turned on by increasing the voltage difference between the driving voltage HS_GT and the voltage at the output terminal OUT. If the driving unit 50 is turned off under the control of the first control voltage PGT and the second control unit 40 is turned on, the second control voltage generated at the control terminal (gate) of the upper bridge transistor MNH is turned off.

[0073] Specifically, the driving unit 50 includes a fifth MOSFET MP1 and a differential voltage unit 51. The gate of the fifth MOSFET MP1 is connected to the drain of the third MOSFET MNA of the first control unit 30 to receive the first control voltage PGT. The source of the fifth MOSFET MP1 is connected to the power supply voltage VCP, and the drain of the fifth MOSFET MP1 is connected to the second control unit 40, the first terminal of the differential voltage unit 51, and the control terminal of the upper bridge transistor MNH. The second terminal of the differential voltage unit 51 is connected to the source of the upper bridge transistor MNH. The differential voltage unit 51 creates a voltage difference between the gate and source of the upper bridge transistor MNH, thereby turning on the upper bridge transistor MNH. When the power supply voltage VCP is in the high voltage domain and the first control signal ON is in the low voltage domain, i.e., the driving circuit needs to realize the conversion from the low voltage domain to the high voltage domain, the fifth MOSFET MP1 can be replaced with a high voltage-resistant device. If the power supply voltage VCP is in the low voltage domain and the first control signal ON is in the low voltage domain, the fifth MOSFET MP1 is a low voltage device.

[0074] The differential pressure unit 51 is one or more of a driving resistor, a MOSFET, and a diode. In this embodiment, for example... Figure 1 As shown, a driving resistor is selected as the voltage differential unit 51. Alternatively, the voltage differential unit 51 can be selected from either a sixth MOSFET or a second diode. If the driving resistor R0 is selected as the voltage differential unit 51, its first terminal is connected to the control terminal of the upper-bridge transistor MNH, and its second terminal is connected to the source of the upper-bridge transistor MNH. If the sixth MOSFET is selected as the voltage differential unit 51, its gate and drain are connected and simultaneously connected to the source of the upper-bridge transistor MNH, and the source of the sixth MOSFET is connected to the control terminal of the upper-bridge transistor MNH. If the second diode is selected as the voltage differential unit 51, its anode is connected to the control terminal of the upper-bridge transistor MNH, and its cathode is connected to the source of the upper-bridge transistor MNH.

[0075] In this embodiment, the driving circuit further includes a Zener diode Z0. The cathode of Zener diode Z0 is connected to the gate of the upper-bridge transistor MNH, and the anode of Zener diode Z0 is connected to the source of the upper-bridge transistor MNH. When the load driven by the output terminal OUT is heavy, and the difference between the first driving voltage HS_GT and the voltage at the output terminal OUT is too large, Zener diode Z0 will break down. Zener diode Z0 stabilizes the difference between the first driving voltage HS_GT and the voltage at the output terminal OUT at a fixed value, thereby protecting the upper-bridge transistor MNH. In other embodiments, Zener diode Z0 can be replaced with any device with voltage regulation function.

[0076] The turn-on process of the upper-bridge transistor MNH:

[0077] like Figure 1 , Figure 2 and Figure 3 As shown, the input current Ibias in the low-voltage domain flows into the first MOSFET MN01. It is mirrored by the current mirror unit 10, replicating the input current Ibias to the second MOSFETs MN02 and MN03, respectively generating drive currents. The first control signal ON flips to a high level to turn on the third MOSFET MNA, and the second control signal OFF flips to a low level to turn off the seventh MOSFET MNB. The drive current is then transmitted through the third MOSFET MNA to the fourth MOSFET MP0 and the first resistor RD0, generating a voltage drop. The first control voltage PGT decreases, thereby turning on the fifth MOSFET MP1.

[0078] The current generated by turning on the fifth MOSFET MP1 flows through the drive resistor R0, creating a voltage drop across R0. This raises the drive voltage HS_GT relative to the output terminal OUT, increasing the difference between the first drive voltage HS_GT and the output terminal OUT. This provides a turn-on voltage between the gate and source of the upper bridge transistor MNH, at which point the upper bridge transistor MNH turns on and provides a large current to the output terminal OUT. During this process, the input current Ibias, the input signal IN_HS, or the first control signal ON in the low-voltage domain are transferred to the control voltage PGT and the first drive voltage HS_GT in the high-voltage domain through the current mirror unit 10, the fifth MOSFET MP1, and the drive resistor R0, thereby turning on the upper bridge transistor MNH.

[0079] The second control signal OFF is a low-level signal during the turn-on process of the upper bridge transistor MNH, and the seventh MOSFET MNB is in the off state, so there will be no voltage extraction at the output terminal OUT that would interfere with the turn-on of the upper bridge transistor MNH.

[0080] The turn-off process of the upper-bridge transistor MNH:

[0081] like Figure 1 , Figure 2 and Figure 3 As shown, when the input signal IN_HS goes low, the first control signal ON toggles to a low level, and the second control signal OFF toggles to a high level.

[0082] The third MOSFET MNA is turned off because the first control signal ON is a low level signal. The fourth MOSFET MP0 is also turned off. The control voltage PGT is raised to be equal to or close to the power supply voltage VCP, thereby turning off the fifth MOSFET MP1.

[0083] On the other hand, the seventh MOSFET MNB is turned on because the second control signal OFF is a high-level signal. The second MOSFET MN03 replicates the input current Ibias to generate a drive current, thereby removing the charge from the parasitic capacitance between the gate and source of the upper bridge transistor MNH. This generates a second control voltage at the gate of the upper bridge transistor MNH, thereby reducing the voltage between the gate and source of the upper bridge transistor MNH. As a result, the voltage between the gate and source of the upper bridge transistor MNH gradually decreases to 0, thus turning off the upper bridge transistor MNH.

[0084] The present invention also discloses a bridge circuit, including the above-described driving circuit.

[0085] The present invention also discloses a chip including a bridge circuit.

[0086] like Figure 4 As shown, the present invention also discloses a bridge circuit driving method, comprising:

[0087] The input current Ibias is replicated by the current mirror unit 10 to generate the drive current.

[0088] Under the control of the first control signal ON, the first control unit 30 is turned on to receive the first drive current and the first control voltage PGT is generated through the first control unit 30.

[0089] Under the control of the second control signal OFF, the second control unit 40 is turned on to receive the second drive current and generate the second control voltage.

[0090] Under the control of the first control voltage PGT and the second control voltage, the upper bridge transistor MNH is turned on and off.

[0091] The drive unit 50 is turned on under the control of the first control voltage PGT, and the second control unit 40 is turned off under the control of the second control voltage. The drive unit 50 generates a drive voltage HS_GT at the control terminal of the upper bridge transistor MNH to turn on the upper bridge transistor MNH. The drive unit 50 is turned off under the control of the first control voltage PGT, and the second control unit 40 is turned on under the control of the second control voltage. The second control unit 40 generates a second control voltage at the control terminal of the upper bridge transistor MNH to turn off the upper bridge transistor MNH.

[0092] Example 2

[0093] like Figure 5 and Figure 6 As shown, the difference between this embodiment and Embodiment 1 is that the driving circuit further includes a third control unit 60 and a fourth control unit 70. The first signal generation unit 20 also includes a first pulse generation unit 21 and a second pulse generation unit 22.

[0094] In addition, four second MOSFETs are provided: MN02, MN03, MN04, and MN05, all connected in a common-gate configuration. MOSFETs MN02, MN03, MN04, and MN05 are used to replicate the input current Ibias to generate drive currents respectively. Five matching resistors are provided: RD1, RD2, RD3, RD4, and RD5. RD1 is connected in series between the source of MOSFET MN01 and ground; RD2 is connected in series between the source of MOSFET MN02 and ground; RD3 is connected in series between the source of MOSFET MN03 and ground; RD4 is connected in series between the source of MOSFET MN04 and ground; and RD5 is connected in series between the source of MOSFET MN05 and ground.

[0095] like Figure 6 As shown, the input terminal of the first pulse generation unit 21 is used to receive the second control signal OFF, and the output terminal of the first pulse generation unit 21 is used to output the third control signal OFFpls. The input terminal of the second pulse generation unit 22 is used to receive the second control signal OFF, and the output terminal of the second pulse generation unit 22 is used to output the fourth control signal OFF1.

[0096] The first pulse generation unit 21 includes a first delay unit Delay1, a third inverter INV3, and a first AND gate U1. The second pulse generation unit 22 includes a second delay unit Delay2, a fourth inverter INV4, and a second AND gate U2. The delay time of the first delay unit Delay1 is shorter than the delay time of the second delay unit Delay2.

[0097] The input terminal of the first delay unit Delay1 is connected to the input terminal of the third inverter INV3 to receive the second control signal OFF. The output terminal of the first delay unit Delay1 and the output terminal of the third inverter INV3 are respectively connected to the first input terminal and the second input terminal of the first AND gate U1. The output terminal of the first AND gate U1 is used to output the third control signal OFFpls.

[0098] The input of the second delay unit Delay2 is connected to the input of the fourth inverter INV4 to receive the second control signal OFF. The output of the second delay unit Delay2 and the output of the fourth inverter INV4 are respectively connected to the first and second inputs of the second AND gate U2. The output of the second AND gate U2 is used to output the fourth control signal OFF1.

[0099] like Figure 5 As shown, the third control unit 60 receives the third control signal OFFpls and the drive current, and generates a third control voltage to increase the rise rate of the first control voltage PGT. The fourth control unit 70 receives the third control signal OFFpls and the drive current and generates a fourth control voltage. At the same time, the second control unit 40 receives the fourth control signal OFF1 to generate an updated second control voltage. The first and fourth control voltages work together to accelerate the turn-off of the upper bridge transistor MNH.

[0100] Specifically, the third control unit 60 includes an eighth MOSFET MND, a ninth MOSFET MP3, a tenth MOSFET MP4, and a second resistor R2.

[0101] The source of the eighth MOSFET MND is connected to the drain of the second MOSFET MN04 in the current mirror unit 10. The gate of the eighth MOSFET MND is used to receive the third control signal OFFpls, which controls the turning on and off of the eighth MOSFET MND. In this embodiment, when the third control signal OFFpls is a high-level signal, the eighth MOSFET MND is turned on to receive the drive current. In other embodiments, the eighth MOSFET MND can be a P-channel MOSFET or other devices or structures, so that when the third control signal OFFpls is a low-level signal, the eighth MOSFET MND can be turned on.

[0102] The drain of the eighth MOSFET MND is connected to the drain and gate of the ninth MOSFET MP3. The source of the ninth MOSFET MP3 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is connected to the power supply voltage VCP. The gate of the ninth MOSFET MP3 is connected to the gate of the tenth MOSFET MP4. The source of the tenth MOSFET MP4 is connected to the power supply voltage VCP, and the drain of the tenth MOSFET MP4 is connected to the drain of the fourth MOSFET MP0 of the first control unit 30.

[0103] Under the control of the third control signal OFFpls, when the eighth MOSFET MND is turned on, the voltage PGT_OFF at the drain of the ninth MOSFET MP3 decreases, and the tenth MOSFET MP4 is turned on. This generates a third control voltage at the drain of the tenth MOSFET MP4 to increase the rise rate of the first control voltage PGT, so that the first control voltage PGT rises quickly to be equal to or close to the power supply voltage VCP.

[0104] In this embodiment, the ninth MOSFET MP3 is connected in a diode configuration, thereby creating a voltage difference between the power supply voltage VCP and the voltage PGT_OFF at the drain of the ninth MOSFET MP3 to turn on the tenth MOSFET MP4. By adding a second resistor R2, when the eighth MOSFET MND is turned on, the voltage PGT_OFF drops more, resulting in a larger voltage difference between the power supply voltage VCP and the voltage PGT_OFF to turn on the tenth MOSFET MP4.

[0105] In other embodiments, the positions of the second resistor R2 and the ninth MOS transistor MP3 can be interchanged, or the second resistor R2 can be omitted.

[0106] In other embodiments, the ninth MOSFET MP3 can be replaced by a bias resistor or a diode. If a diode is used, the anode of the diode is connected to the first terminal of the second resistor R2, and the cathode of the diode is connected to the drain of the eighth MOSFET MND and the gate of the tenth MOSFET MP4. If a bias resistor is used, the first terminal of the bias resistor is connected to the first terminal of the second resistor R2, and the second terminal of the bias resistor is connected to the drain of the eighth MOSFET MND and the gate of the tenth MOSFET MP4.

[0107] like Figure 5 As shown, the fourth control unit 70 includes an eleventh MOSFET MNC, a twelfth MOSFET MP5, a thirteenth MOSFET MP2, a first voltage divider resistor R3, and a second voltage divider resistor R4.

[0108] The source of the eleventh MOSFET MNC is connected to the drain of the second MOSFET MN05 in the current mirror unit 10, and the drain of the eleventh MOSFET MNC is connected to the gate of the twelfth MOSFET MP5. The gate of the eleventh MOSFET MNC is used to receive the third control signal OFFpls, which controls the turning on and off of the eleventh MOSFET MNC. In this embodiment, the eleventh MOSFET MNC is turned on when the third control signal OFFpls is a high-level signal. In other embodiments, the eleventh MOSFET MNC is a P-channel MOSFET or other device or structure, so that the eleventh MOSFET MNC can be turned on when the third control signal OFFpls is a low-level signal.

[0109] The source of the twelfth MOSFET MP5 is connected to the control terminal of the upper-bridge transistor MNH, and the drain of the twelfth MOSFET MP5 is connected to the source of the upper-bridge transistor MNH. The source of the thirteenth MOSFET MP2 is connected to the power supply voltage VCP, and the gate of the thirteenth MOSFET MP2 is connected to the gate of the fourth MOSFET MP0 of the first control unit 30 to receive the first control voltage PGT. The drain of the thirteenth MOSFET MP2 is connected to the first terminal of the first voltage divider resistor R3, the second terminal of the first voltage divider resistor R3 is connected to the gate of the twelfth MOSFET MP5 and the first terminal of the second voltage divider resistor R4, and the second terminal of the second voltage divider resistor R4 is connected to the drain of the twelfth MOSFET MP5.

[0110] In this embodiment, as the first control voltage PGT rapidly rises to be equal to or close to the power supply voltage VCP, the fifth MOSFET MP1 turns off, so that no voltage is generated on the drive resistor R0. At the same time, the eleventh MOSFET MNC turns on under the control of the third control signal OFFpls. The voltage PGT_OFF2 at the gate of the twelfth MOSFET MP5 is pulled down, and the twelfth MOSFET MP5 turns on. This generates a fourth control voltage at the control terminal of the upper bridge transistor MNH, which accelerates the reduction of the difference between the voltage at the gate of the upper bridge transistor MNH and the voltage at the output terminal OUT, thereby accelerating the turn-off of the upper bridge transistor MNH.

[0111] In this embodiment, when the upper-bridge transistor MNH needs to be turned off, the second control unit 40 receives the fourth control signal OFF1, that is, the gate of the seventh MOSFET MNB receives the fourth control signal OFF1. The fourth control signal OFF1 controls the turning on and off of the seventh MOSFET MNB. In this embodiment, when the fourth control signal OFF1 is a high-level signal, the seventh MOSFET MNB is turned on. After the seventh MOSFET MNB is turned on, an updated second control voltage is generated at its drain. That is, after a delay, the original second control signal OFF is used to output the fourth control signal OFF1 to control the turning on of the seventh MOSFET MNB and generate a new second control voltage. The upper-bridge transistor MNH is turned off by the updated second control voltage. In other embodiments, the seventh MOSFET MNB can be a P-channel MOSFET or other devices or structures, so that the seventh MOSFET MNB can be turned on when the fourth control signal OFF1 is a low-level signal.

[0112] When the upper bridge transistor MNH needs to be turned on, it is necessary to ensure that the twelfth MOSFET MP5 is turned off. At this time, by setting the resistance of the first voltage divider resistor R3 to be much smaller than the resistance of the second voltage divider resistor R4, when the third MOSFET MNA is turned on and the thirteenth MOSFET MP2 is also turned on, the voltage at the gate of the twelfth MOSFET MP5 is close to the power supply voltage VCP, thereby turning off the twelfth MOSFET MP5.

[0113] like Figure 5 As shown, the fourth control unit 70 further includes a third diode D1 and a fourth diode D2. The cathode of the third diode D1 is connected to the source of the twelfth MOSFET MP5, and the anode of the third diode D1 is connected to the gate of the twelfth MOSFET MP5. The cathode of the fourth diode D2 is connected to the source of the twelfth MOSFET MP5, and the anode of the fourth diode D2 is connected to the drain of the twelfth MOSFET MP5. The third diode D1 is used to protect the voltage between the source and gate of the twelfth MOSFET MP5 from exceeding its withstand voltage value, and the fourth diode D2 is used to protect the voltage between the gate and drain of the twelfth MOSFET MP5 from exceeding its withstand voltage value. In other embodiments, the third diode D1 and the fourth diode D2 can be replaced with MOSFETs connected in a diode configuration.

[0114] like Figure 7 As shown, the first signal generation circuit 20 also includes a judgment circuit 23. The judgment circuit 23 is used to generate an identification signal HS_isOFF, which characterizes whether the upper bridge transistor MNH is turned off, based on the first control signal ON and the fourth control signal OFF1. In this embodiment, during a period of time when the upper bridge transistor MNH is turned off and not turned on, both the first control signal ON and the fourth control signal OFF1 are at a low level or a high level. The judgment circuit 81 receives the first control signal ON and the fourth control signal OFF1 and outputs the identification signal HS_isOFF. In practical applications, in order to prevent the upper bridge transistor MNH and the lower bridge transistor MNL from being simultaneously turned on, which would cause the upper bridge transistor MNH and the lower bridge transistor MNL to conduct through and burn out, it is necessary to ensure that the lower bridge transistor MNL can only be turned on after the upper bridge transistor MNH is turned off, thus requiring identification of whether the upper bridge transistor MNH is turned off.

[0115] The judgment circuit 81 includes a NAND gate N1. The first input terminal of the NAND gate N1 is used to receive the first control signal ON, the second input terminal of the NAND gate N1 is used to receive the fourth control signal OFF1, and the output terminal of the NAND gate N1 is used to output the identification signal HS_isOFF.

[0116] like Figure 8 As shown, during the period when the first control signal ON flips to a high level signal, i.e. during the turn-on phase of the upper bridge transistor MNH, and during the period when the first control signal ON flips to a low level signal, the third control signal OFFpls, and the fourth control signal OFF1 flip to a high level signal, i.e. during the turn-off phase of the upper bridge transistor MNH, the identification signal HS_isOFF is a low level signal, thus indicating that the upper bridge transistor MNH is not turned off or is in the process of being turned off.

[0117] When the first control signal ON flips to a low level, the third control signal OFFpls and the fourth control signal OFF1 simultaneously flip to high levels. The third control signal OFFpls flips to a low level before the fourth control signal OFF1. During the period when the fourth control signal OFF1 flips to a low level and the first control signal ON remains low, the identification signal HS_isOFF is high, indicating that the upper-bridge transistor MNH is completely turned off. When the lower-bridge drive circuit receives the high-level identification signal HS_isOFF, it can turn on the lower-bridge transistor MNL during this period, thereby preventing the upper-bridge transistor MNH and the lower-bridge transistor MNL from conducting simultaneously.

[0118] Within the same cycle, the duty cycle of the fourth control signal OFF1 is greater than that of the third control signal OFFpls, meaning the turn-on time of the seventh MOSFET MNB is greater than that of the eighth MOSFET MND and the eleventh MOSFET MNC. When the seventh MOSFET MNB is turned on to turn off the upper-bridge transistor MNH, the turn-off of the upper-bridge transistor MNH is accelerated simultaneously by turning on the eighth MOSFET MND and the eleventh MOSFET MNC. During the period when the fourth control signal OFF1 is high, the upper-bridge transistor MNH is completely turned off. When the fourth control signal OFF1 flips to low, the seventh MOSFET MNB turns off and no longer draws current from the output terminal OUT. The gate of the upper-bridge transistor MNH is connected to the output terminal OUT through a drive resistor R0.

[0119] like Figure 9 As shown, this embodiment also discloses a bridge circuit driving method, including:

[0120] The input current Ibias is replicated by the current mirror unit 10 to generate the drive current.

[0121] Under the control of the first control signal ON, the first control unit 30 is turned on to receive the first drive current and the first control voltage PGT is generated through the first control unit 30.

[0122] Under the control of the fourth control signal OFF1, the second control unit 40 is turned on to receive the second drive current and generate an updated second control voltage. The second control voltage generated by the second control unit 40 at the control terminal of the upper bridge transistor MNH is used to turn off the upper bridge transistor MNH.

[0123] Under the control of the third control signal OFFpls, the third control unit 60 is turned on to receive the third drive current, and the third control voltage is generated through the third control unit 60. The rise rate of the first control voltage PGT is increased through the third control unit 60. When the control voltage PGT rises to a preset value, the drive unit 50 is turned off.

[0124] Under the control of the first to fourth control signals, a drive voltage is generated at the control terminal of the upper bridge transistor MNH, which, in conjunction with the rise of the first control voltage PGT, accelerates the turn-off of the upper bridge transistor MNH.

[0125] like Figure 8 and Figure 7 As shown, within the same cycle, the duty cycle of the fourth control signal OFF1 is greater than that of the third control signal OFFpls. An identification signal HS_isOFF is generated based on the first control signal ON and the fourth control signal OFF1 to characterize whether the upper-bridge transistor MNH is turned off. During the period when the upper-bridge transistor MNH is turned off, i.e., when the fourth control signal OFF1 is a low-level signal and the first control signal ON is also a low-level signal, the identification signal HS_isOFF is a high-level signal.

[0126] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A driving circuit, characterized in that, The driving circuit operates in a high-voltage domain and / or a low-voltage domain to drive the upper bridge transistor in the bridge circuit. The driving circuit includes: A current mirror unit is used to generate a drive current by replicating the input current; The first signal generation unit is used to receive the input signal for controlling the upper bridge transistor, and to generate a control signal for controlling the state of the upper bridge transistor. The control signal includes a first control signal and a second control signal. A first control unit is configured to receive a first control signal and a drive current, and generate a first control voltage; The second control unit is used to receive the second control signal and the drive current, and to generate the second control voltage; and The driving unit is used to generate a driving voltage at the control terminal of the upper bridge transistor under the action of the first control voltage and the second control voltage to control the upper bridge transistor to turn on or off. The first signal generating unit further includes a first pulse generating unit and a second pulse generating unit. The input terminal of the first pulse generating unit is used to receive a second control signal, and the output terminal of the first pulse generating unit is used to output a third control signal. The input terminal of the second pulse generating unit is used to receive the second control signal, and the output terminal of the second pulse generating unit is used to output a fourth control signal. The drive circuit also includes a third control unit and a fourth control unit; The third control unit is used to receive the third control signal and drive current, and generate a third control voltage to increase the rise rate of the first control voltage. The fourth control unit is used to receive the third control signal and drive current and generate the fourth control voltage. At the same time, the second control unit receives the fourth control signal to generate an updated second control voltage. The first and fourth control voltages work together to accelerate the turn-off of the upper bridge transistor.

2. The driving circuit as described in claim 1, characterized in that, The current mirror unit includes a first MOSFET and a plurality of second MOSFETs. The first MOSFET and the plurality of second MOSFETs are connected in a common gate configuration. The drain and gate of the first MOSFET are connected to receive the input current. The sources of the first MOSFET and the plurality of second MOSFETs are connected to ground. The plurality of second MOSFETs are used to replicate the input current to generate a corresponding drive current at the drain of the plurality of second MOSFETs.

3. The driving circuit as described in claim 2, characterized in that, The current mirror unit also includes multiple matching resistors, the number of which is the same as the number of MOS transistors in the current mirror unit, and they are connected one-to-one between the source of the MOS transistor and the ground voltage.

4. The driving circuit as described in claim 1, characterized in that, The first signal generating unit includes a first inverter and a second inverter. The input terminal of the first inverter is used to receive the input signal, and the output terminal of the first inverter is used to output the second control signal. The input terminal of the second inverter is used to receive the second control signal, and the output terminal of the second inverter is used to output the first control signal.

5. The driving circuit as described in claim 1, characterized in that, The first control unit includes a third MOS transistor and a bias unit. The source of the third MOS transistor is connected to a current mirror unit, and the gate of the third MOS transistor is used to receive a first control signal. One end of the bias unit is connected to a power supply voltage, and the other end of the bias unit is connected to the drain of the third MOS transistor and a driving unit to generate a first control voltage.

6. The driving circuit as described in claim 5, characterized in that, The bias unit is one or more of a MOSFET, a bias resistor, and a diode.

7. The driving circuit as described in claim 1, characterized in that, The second control unit includes a seventh MOS transistor, the drain of which is connected to the driving unit, the source of which is connected to the current mirror unit, and the gate of which is used to receive a second control signal.

8. The driving circuit as described in claim 1, characterized in that, The driving unit includes a fifth MOS transistor and a differential voltage unit. The gate of the fifth MOS transistor is connected to the first control unit to receive a first control voltage. The source of the fifth MOS transistor is connected to the power supply voltage. The drain of the fifth MOS transistor is connected to the second control unit, the first terminal of the differential voltage unit, and the control terminal of the upper bridge transistor. The second terminal of the differential voltage unit is connected to the source of the upper bridge transistor.

9. The driving circuit as described in claim 8, characterized in that, The differential pressure unit is one or more of the following: a driving resistor, a MOSFET, and a diode.

10. The driving circuit as described in claim 1, characterized in that, The first pulse generation unit includes a first delay unit, a third inverter, and a first AND gate; the second pulse generation unit includes a second delay unit, a fourth inverter, and a second AND gate; the input terminal of the first delay unit is connected to the input terminal of the third inverter to receive a second control signal, the output terminal of the first delay unit and the output terminal of the third inverter are respectively connected to the first input terminal and the second input terminal of the first AND gate, the output terminal of the first AND gate is used to output a third control signal, the input terminal of the second delay unit is connected to the input terminal of the fourth inverter to receive the second control signal, the output terminal of the second delay unit and the output terminal of the fourth inverter are respectively connected to the first input terminal and the second input terminal of the second AND gate, the output terminal of the second AND gate is used to output a fourth control signal.

11. The driving circuit as described in claim 1, characterized in that, The third control unit includes an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, and a second resistor. The source of the eighth MOS transistor is connected to a current mirror unit, and the gate of the eighth MOS transistor is used to receive a third control signal. The drain of the eighth MOS transistor is connected to the drain and gate of the ninth MOS transistor. The source of the ninth MOS transistor is connected to the first terminal of the second resistor, and the second terminal of the second resistor is connected to the power supply voltage. The gate of the ninth MOS transistor is connected to the gate of the tenth MOS transistor, and the source of the tenth MOS transistor is connected to the power supply voltage. The drain of the tenth MOS transistor is connected to the first control unit to improve the rise rate of the first control voltage.

12. The driving circuit as described in claim 1, characterized in that, The fourth control unit includes an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, a first voltage divider resistor, and a second voltage divider resistor. The source of the eleventh MOSFET is connected to a current mirror unit, the gate of the eleventh MOSFET is used to receive a third control signal, the drain of the eleventh MOSFET is connected to the gate of the twelfth MOSFET, the source of the twelfth MOSFET is connected to the control terminal of the upper bridge transistor, the drain of the twelfth MOSFET is connected to the source of the upper bridge transistor, the source of the thirteenth MOSFET is connected to the power supply voltage, the gate of the thirteenth MOSFET is connected to the first control unit to receive a first control voltage, the drain of the thirteenth MOSFET is connected to the first terminal of the first voltage divider resistor, the second terminal of the first voltage divider resistor is connected to the gate of the twelfth MOSFET and the first terminal of the second voltage divider resistor, and the second terminal of the second voltage divider resistor is connected to the drain of the twelfth MOSFET.

13. The driving circuit as described in claim 12, characterized in that, The fourth control unit further includes a third diode and a fourth diode. The cathode of the third diode is connected to the source of the twelfth MOS transistor, and the anode of the third diode is connected to the gate of the twelfth MOS transistor. The cathode of the fourth diode is connected to the source of the twelfth MOS transistor, and the anode of the fourth diode is connected to the drain of the twelfth MOS transistor.

14. The driving circuit as described in claim 1, characterized in that, The driving circuit also includes a Zener diode, the cathode of which is connected to the gate of the upper bridge transistor, and the anode of which is connected to the source of the upper bridge transistor.

15. The driving circuit as described in claim 1, characterized in that, The first signal generation unit further includes a judgment circuit, which is used to generate an identification signal characterizing whether the upper bridge transistor is turned off based on the first control signal and the fourth control signal.

16. The driving circuit as described in claim 15, characterized in that, The judgment circuit includes a NAND gate, the first input terminal of which is used to receive a first control signal, the second input terminal of which is used to receive a fourth control signal, and the output terminal of which is used to output an identification signal.

17. A bridge circuit driving method, characterized in that, include: The input current is copied to generate the drive current; Under the control of the first control signal, the first control unit is turned on to receive the first drive current and the first control voltage is generated through the first control unit; Under the control of the second control signal, the second control unit is turned on to receive the second drive current and the second control voltage is generated through the second control unit; Under the control of the first control voltage and the second control, the upper bridge transistor is turned on and off. The bridge circuit driving method further includes: Under the control of the fourth control signal, the second control unit is turned on to receive the second drive current and generate the updated second control voltage. Under the control of the third control signal, the third control unit is turned on to receive the third drive current and generate the third control voltage. The rise rate of the first control voltage is increased through the third control unit. Under the control of the first to fourth control signals, a drive voltage is generated at the control terminal of the upper bridge transistor, which, in conjunction with the rise of the first control voltage, accelerates the turn-off of the upper bridge transistor.

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